Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | /* |
| 3 | * This file contains work-arounds for x86 and x86_64 platform bugs. |
| 4 | */ |
Lukas Wunner | 630b3af | 2017-08-01 14:10:41 +0200 | [diff] [blame] | 5 | #include <linux/dmi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | #include <linux/pci.h> |
| 7 | #include <linux/irq.h> |
| 8 | |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 9 | #include <asm/hpet.h> |
| 10 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI) |
| 12 | |
Greg Kroah-Hartman | a18e369 | 2012-12-21 14:02:53 -0800 | [diff] [blame] | 13 | static void quirk_intel_irqbalance(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | { |
Sergei Shtylyov | 3817505 | 2011-07-11 19:01:38 +0400 | [diff] [blame] | 15 | u8 config; |
Matthew Wilcox | 9585ca0 | 2008-02-10 23:18:15 -0500 | [diff] [blame] | 16 | u16 word; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | |
| 18 | /* BIOS may enable hardware IRQ balancing for |
| 19 | * E7520/E7320/E7525(revision ID 0x9 and below) |
| 20 | * based platforms. |
| 21 | * Disable SW irqbalance/affinity on those platforms. |
| 22 | */ |
Sergei Shtylyov | 3817505 | 2011-07-11 19:01:38 +0400 | [diff] [blame] | 23 | if (dev->revision > 0x9) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | return; |
| 25 | |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 26 | /* enable access to config space*/ |
| 27 | pci_read_config_byte(dev, 0xf4, &config); |
| 28 | pci_write_config_byte(dev, 0xf4, config|0x2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
Matthew Wilcox | 9585ca0 | 2008-02-10 23:18:15 -0500 | [diff] [blame] | 30 | /* |
| 31 | * read xTPR register. We may not have a pci_dev for device 8 |
| 32 | * because it might be hidden until the above write. |
| 33 | */ |
| 34 | pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | |
| 36 | if (!(word & (1 << 13))) { |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 37 | dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " |
| 38 | "disabling irq balancing and affinity\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | noirqdebug_setup(""); |
| 40 | #ifdef CONFIG_PROC_FS |
| 41 | no_irq_affinity = 1; |
| 42 | #endif |
| 43 | } |
| 44 | |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 45 | /* put back the original value for config space*/ |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 46 | if (!(config & 0x2)) |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 47 | pci_write_config_byte(dev, 0xf4, config); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | } |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 49 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, |
| 50 | quirk_intel_irqbalance); |
| 51 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, |
| 52 | quirk_intel_irqbalance); |
| 53 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, |
| 54 | quirk_intel_irqbalance); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | #endif |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 56 | |
| 57 | #if defined(CONFIG_HPET_TIMER) |
| 58 | unsigned long force_hpet_address; |
| 59 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 60 | static enum { |
| 61 | NONE_FORCE_HPET_RESUME, |
| 62 | OLD_ICH_FORCE_HPET_RESUME, |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 63 | ICH_FORCE_HPET_RESUME, |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 64 | VT8237_FORCE_HPET_RESUME, |
| 65 | NVIDIA_FORCE_HPET_RESUME, |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 66 | ATI_FORCE_HPET_RESUME, |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 67 | } force_hpet_resume_type; |
| 68 | |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 69 | static void __iomem *rcba_base; |
| 70 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 71 | static void ich_force_hpet_resume(void) |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 72 | { |
| 73 | u32 val; |
| 74 | |
| 75 | if (!force_hpet_address) |
| 76 | return; |
| 77 | |
Stoyan Gaydarov | 8c5dfd2 | 2009-03-10 00:10:32 -0500 | [diff] [blame] | 78 | BUG_ON(rcba_base == NULL); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 79 | |
| 80 | /* read the Function Disable register, dword mode only */ |
| 81 | val = readl(rcba_base + 0x3404); |
| 82 | if (!(val & 0x80)) { |
| 83 | /* HPET disabled in HPTC. Trying to enable */ |
| 84 | writel(val | 0x80, rcba_base + 0x3404); |
| 85 | } |
| 86 | |
| 87 | val = readl(rcba_base + 0x3404); |
| 88 | if (!(val & 0x80)) |
| 89 | BUG(); |
| 90 | else |
| 91 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 92 | |
| 93 | return; |
| 94 | } |
| 95 | |
| 96 | static void ich_force_enable_hpet(struct pci_dev *dev) |
| 97 | { |
| 98 | u32 val; |
| 99 | u32 uninitialized_var(rcba); |
| 100 | int err = 0; |
| 101 | |
| 102 | if (hpet_address || force_hpet_address) |
| 103 | return; |
| 104 | |
| 105 | pci_read_config_dword(dev, 0xF0, &rcba); |
| 106 | rcba &= 0xFFFFC000; |
| 107 | if (rcba == 0) { |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 108 | dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; " |
| 109 | "cannot force enable HPET\n"); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 110 | return; |
| 111 | } |
| 112 | |
| 113 | /* use bits 31:14, 16 kB aligned */ |
| 114 | rcba_base = ioremap_nocache(rcba, 0x4000); |
| 115 | if (rcba_base == NULL) { |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 116 | dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " |
| 117 | "cannot force enable HPET\n"); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 118 | return; |
| 119 | } |
| 120 | |
| 121 | /* read the Function Disable register, dword mode only */ |
| 122 | val = readl(rcba_base + 0x3404); |
| 123 | |
| 124 | if (val & 0x80) { |
| 125 | /* HPET is enabled in HPTC. Just not reported by BIOS */ |
| 126 | val = val & 0x3; |
| 127 | force_hpet_address = 0xFED00000 | (val << 12); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 128 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 129 | "0x%lx\n", force_hpet_address); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 130 | iounmap(rcba_base); |
| 131 | return; |
| 132 | } |
| 133 | |
| 134 | /* HPET disabled in HPTC. Trying to enable */ |
| 135 | writel(val | 0x80, rcba_base + 0x3404); |
| 136 | |
| 137 | val = readl(rcba_base + 0x3404); |
| 138 | if (!(val & 0x80)) { |
| 139 | err = 1; |
| 140 | } else { |
| 141 | val = val & 0x3; |
| 142 | force_hpet_address = 0xFED00000 | (val << 12); |
| 143 | } |
| 144 | |
| 145 | if (err) { |
| 146 | force_hpet_address = 0; |
| 147 | iounmap(rcba_base); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 148 | dev_printk(KERN_DEBUG, &dev->dev, |
| 149 | "Failed to force enable HPET\n"); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 150 | } else { |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 151 | force_hpet_resume_type = ICH_FORCE_HPET_RESUME; |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 152 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 153 | "0x%lx\n", force_hpet_address); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | |
| 157 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 158 | ich_force_enable_hpet); |
Krzysztof Oledzki | 74e411c | 2008-06-04 03:40:17 +0200 | [diff] [blame] | 159 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, |
| 160 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 161 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 162 | ich_force_enable_hpet); |
Venki Pallipadi | ed6fb17 | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 163 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 164 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 165 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 166 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 167 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 168 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 170 | ich_force_enable_hpet); |
Janne Kulmala | bacbe99 | 2008-12-16 13:39:57 +0200 | [diff] [blame] | 171 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, |
| 172 | ich_force_enable_hpet); |
Alistair John Strachan | dff244a | 2008-01-30 13:33:39 +0100 | [diff] [blame] | 173 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, |
| 174 | ich_force_enable_hpet); |
Andi Kleen | 42bb8cc | 2009-01-09 12:17:40 -0800 | [diff] [blame] | 175 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */ |
| 176 | ich_force_enable_hpet); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 177 | |
| 178 | static struct pci_dev *cached_dev; |
| 179 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 180 | static void hpet_print_force_info(void) |
| 181 | { |
| 182 | printk(KERN_INFO "HPET not enabled in BIOS. " |
| 183 | "You might try hpet=force boot option\n"); |
| 184 | } |
| 185 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 186 | static void old_ich_force_hpet_resume(void) |
| 187 | { |
| 188 | u32 val; |
| 189 | u32 uninitialized_var(gen_cntl); |
| 190 | |
| 191 | if (!force_hpet_address || !cached_dev) |
| 192 | return; |
| 193 | |
| 194 | pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); |
| 195 | gen_cntl &= (~(0x7 << 15)); |
| 196 | gen_cntl |= (0x4 << 15); |
| 197 | |
| 198 | pci_write_config_dword(cached_dev, 0xD0, gen_cntl); |
| 199 | pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); |
| 200 | val = gen_cntl >> 15; |
| 201 | val &= 0x7; |
| 202 | if (val == 0x4) |
| 203 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 204 | else |
| 205 | BUG(); |
| 206 | } |
| 207 | |
| 208 | static void old_ich_force_enable_hpet(struct pci_dev *dev) |
| 209 | { |
| 210 | u32 val; |
| 211 | u32 uninitialized_var(gen_cntl); |
| 212 | |
| 213 | if (hpet_address || force_hpet_address) |
| 214 | return; |
| 215 | |
| 216 | pci_read_config_dword(dev, 0xD0, &gen_cntl); |
| 217 | /* |
| 218 | * Bit 17 is HPET enable bit. |
| 219 | * Bit 16:15 control the HPET base address. |
| 220 | */ |
| 221 | val = gen_cntl >> 15; |
| 222 | val &= 0x7; |
| 223 | if (val & 0x4) { |
| 224 | val &= 0x3; |
| 225 | force_hpet_address = 0xFED00000 | (val << 12); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 226 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
| 227 | force_hpet_address); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 228 | return; |
| 229 | } |
| 230 | |
| 231 | /* |
| 232 | * HPET is disabled. Trying enabling at FED00000 and check |
| 233 | * whether it sticks |
| 234 | */ |
| 235 | gen_cntl &= (~(0x7 << 15)); |
| 236 | gen_cntl |= (0x4 << 15); |
| 237 | pci_write_config_dword(dev, 0xD0, gen_cntl); |
| 238 | |
| 239 | pci_read_config_dword(dev, 0xD0, &gen_cntl); |
| 240 | |
| 241 | val = gen_cntl >> 15; |
| 242 | val &= 0x7; |
| 243 | if (val & 0x4) { |
| 244 | /* HPET is enabled in HPTC. Just not reported by BIOS */ |
| 245 | val &= 0x3; |
| 246 | force_hpet_address = 0xFED00000 | (val << 12); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 247 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 248 | "0x%lx\n", force_hpet_address); |
Venki Pallipadi | 32a2da6 | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 249 | cached_dev = dev; |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 250 | force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; |
| 251 | return; |
| 252 | } |
| 253 | |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 254 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 255 | } |
| 256 | |
Udo A. Steinberg | 158ad32 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 257 | /* |
| 258 | * Undocumented chipset features. Make sure that the user enforced |
| 259 | * this. |
| 260 | */ |
| 261 | static void old_ich_force_enable_hpet_user(struct pci_dev *dev) |
| 262 | { |
| 263 | if (hpet_force_user) |
| 264 | old_ich_force_enable_hpet(dev); |
| 265 | } |
| 266 | |
Joe Buehler | 4c2a997 | 2008-06-09 08:55:20 -0400 | [diff] [blame] | 267 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, |
| 268 | old_ich_force_enable_hpet_user); |
Udo A. Steinberg | 158ad32 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 269 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, |
| 270 | old_ich_force_enable_hpet_user); |
| 271 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, |
| 272 | old_ich_force_enable_hpet_user); |
| 273 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, |
| 274 | old_ich_force_enable_hpet_user); |
| 275 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, |
| 276 | old_ich_force_enable_hpet_user); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 277 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 278 | old_ich_force_enable_hpet); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 279 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 280 | old_ich_force_enable_hpet); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 281 | |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 282 | |
| 283 | static void vt8237_force_hpet_resume(void) |
| 284 | { |
| 285 | u32 val; |
| 286 | |
| 287 | if (!force_hpet_address || !cached_dev) |
| 288 | return; |
| 289 | |
| 290 | val = 0xfed00000 | 0x80; |
| 291 | pci_write_config_dword(cached_dev, 0x68, val); |
| 292 | |
| 293 | pci_read_config_dword(cached_dev, 0x68, &val); |
| 294 | if (val & 0x80) |
| 295 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 296 | else |
| 297 | BUG(); |
| 298 | } |
| 299 | |
| 300 | static void vt8237_force_enable_hpet(struct pci_dev *dev) |
| 301 | { |
| 302 | u32 uninitialized_var(val); |
| 303 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 304 | if (hpet_address || force_hpet_address) |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 305 | return; |
| 306 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 307 | if (!hpet_force_user) { |
| 308 | hpet_print_force_info(); |
| 309 | return; |
| 310 | } |
| 311 | |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 312 | pci_read_config_dword(dev, 0x68, &val); |
| 313 | /* |
| 314 | * Bit 7 is HPET enable bit. |
| 315 | * Bit 31:10 is HPET base address (contrary to what datasheet claims) |
| 316 | */ |
| 317 | if (val & 0x80) { |
| 318 | force_hpet_address = (val & ~0x3ff); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 319 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
| 320 | force_hpet_address); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 321 | return; |
| 322 | } |
| 323 | |
| 324 | /* |
| 325 | * HPET is disabled. Trying enabling at FED00000 and check |
| 326 | * whether it sticks |
| 327 | */ |
| 328 | val = 0xfed00000 | 0x80; |
| 329 | pci_write_config_dword(dev, 0x68, val); |
| 330 | |
| 331 | pci_read_config_dword(dev, 0x68, &val); |
| 332 | if (val & 0x80) { |
| 333 | force_hpet_address = (val & ~0x3ff); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 334 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 335 | "0x%lx\n", force_hpet_address); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 336 | cached_dev = dev; |
| 337 | force_hpet_resume_type = VT8237_FORCE_HPET_RESUME; |
| 338 | return; |
| 339 | } |
| 340 | |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 341 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, |
| 345 | vt8237_force_enable_hpet); |
| 346 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, |
| 347 | vt8237_force_enable_hpet); |
Udo van den Heuvel | 892df7f | 2010-09-14 07:15:08 +0200 | [diff] [blame] | 348 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700, |
| 349 | vt8237_force_enable_hpet); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 350 | |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 351 | static void ati_force_hpet_resume(void) |
| 352 | { |
| 353 | pci_write_config_dword(cached_dev, 0x14, 0xfed00000); |
| 354 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 355 | } |
| 356 | |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 357 | static u32 ati_ixp4x0_rev(struct pci_dev *dev) |
| 358 | { |
Borislav Petkov | 73f4604 | 2013-03-04 21:16:20 +0100 | [diff] [blame] | 359 | int err = 0; |
| 360 | u32 d = 0; |
| 361 | u8 b = 0; |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 362 | |
Borislav Petkov | 73f4604 | 2013-03-04 21:16:20 +0100 | [diff] [blame] | 363 | err = pci_read_config_byte(dev, 0xac, &b); |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 364 | b &= ~(1<<5); |
Borislav Petkov | 73f4604 | 2013-03-04 21:16:20 +0100 | [diff] [blame] | 365 | err |= pci_write_config_byte(dev, 0xac, b); |
| 366 | err |= pci_read_config_dword(dev, 0x70, &d); |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 367 | d |= 1<<8; |
Borislav Petkov | 73f4604 | 2013-03-04 21:16:20 +0100 | [diff] [blame] | 368 | err |= pci_write_config_dword(dev, 0x70, d); |
| 369 | err |= pci_read_config_dword(dev, 0x8, &d); |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 370 | d &= 0xff; |
| 371 | dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d); |
Borislav Petkov | 73f4604 | 2013-03-04 21:16:20 +0100 | [diff] [blame] | 372 | |
| 373 | WARN_ON_ONCE(err); |
| 374 | |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 375 | return d; |
| 376 | } |
| 377 | |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 378 | static void ati_force_enable_hpet(struct pci_dev *dev) |
| 379 | { |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 380 | u32 d, val; |
| 381 | u8 b; |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 382 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 383 | if (hpet_address || force_hpet_address) |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 384 | return; |
| 385 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 386 | if (!hpet_force_user) { |
| 387 | hpet_print_force_info(); |
| 388 | return; |
| 389 | } |
| 390 | |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 391 | d = ati_ixp4x0_rev(dev); |
| 392 | if (d < 0x82) |
| 393 | return; |
| 394 | |
| 395 | /* base address */ |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 396 | pci_write_config_dword(dev, 0x14, 0xfed00000); |
| 397 | pci_read_config_dword(dev, 0x14, &val); |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 398 | |
| 399 | /* enable interrupt */ |
| 400 | outb(0x72, 0xcd6); b = inb(0xcd7); |
| 401 | b |= 0x1; |
| 402 | outb(0x72, 0xcd6); outb(b, 0xcd7); |
| 403 | outb(0x72, 0xcd6); b = inb(0xcd7); |
| 404 | if (!(b & 0x1)) |
| 405 | return; |
| 406 | pci_read_config_dword(dev, 0x64, &d); |
| 407 | d |= (1<<10); |
| 408 | pci_write_config_dword(dev, 0x64, d); |
| 409 | pci_read_config_dword(dev, 0x64, &d); |
| 410 | if (!(d & (1<<10))) |
| 411 | return; |
| 412 | |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 413 | force_hpet_address = val; |
| 414 | force_hpet_resume_type = ATI_FORCE_HPET_RESUME; |
| 415 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", |
| 416 | force_hpet_address); |
| 417 | cached_dev = dev; |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 418 | } |
| 419 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, |
| 420 | ati_force_enable_hpet); |
| 421 | |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 422 | /* |
| 423 | * Undocumented chipset feature taken from LinuxBIOS. |
| 424 | */ |
| 425 | static void nvidia_force_hpet_resume(void) |
| 426 | { |
| 427 | pci_write_config_dword(cached_dev, 0x44, 0xfed00001); |
| 428 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 429 | } |
| 430 | |
| 431 | static void nvidia_force_enable_hpet(struct pci_dev *dev) |
| 432 | { |
| 433 | u32 uninitialized_var(val); |
| 434 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 435 | if (hpet_address || force_hpet_address) |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 436 | return; |
| 437 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 438 | if (!hpet_force_user) { |
| 439 | hpet_print_force_info(); |
| 440 | return; |
| 441 | } |
| 442 | |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 443 | pci_write_config_dword(dev, 0x44, 0xfed00001); |
| 444 | pci_read_config_dword(dev, 0x44, &val); |
| 445 | force_hpet_address = val & 0xfffffffe; |
| 446 | force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME; |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 447 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 448 | force_hpet_address); |
| 449 | cached_dev = dev; |
| 450 | return; |
| 451 | } |
| 452 | |
| 453 | /* ISA Bridges */ |
| 454 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050, |
| 455 | nvidia_force_enable_hpet); |
| 456 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051, |
| 457 | nvidia_force_enable_hpet); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 458 | |
Carlos Corbacho | 1b82ba6 | 2007-10-19 19:34:15 +0100 | [diff] [blame] | 459 | /* LPC bridges */ |
Zbigniew Luszpinski | 96bcf45 | 2008-03-19 15:51:50 +0100 | [diff] [blame] | 460 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260, |
| 461 | nvidia_force_enable_hpet); |
Carlos Corbacho | 1b82ba6 | 2007-10-19 19:34:15 +0100 | [diff] [blame] | 462 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360, |
| 463 | nvidia_force_enable_hpet); |
| 464 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361, |
| 465 | nvidia_force_enable_hpet); |
| 466 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362, |
| 467 | nvidia_force_enable_hpet); |
| 468 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363, |
| 469 | nvidia_force_enable_hpet); |
| 470 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364, |
| 471 | nvidia_force_enable_hpet); |
| 472 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365, |
| 473 | nvidia_force_enable_hpet); |
| 474 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366, |
| 475 | nvidia_force_enable_hpet); |
| 476 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367, |
| 477 | nvidia_force_enable_hpet); |
| 478 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 479 | void force_hpet_resume(void) |
| 480 | { |
| 481 | switch (force_hpet_resume_type) { |
Harvey Harrison | 4a5a77d | 2008-02-06 22:39:44 +0100 | [diff] [blame] | 482 | case ICH_FORCE_HPET_RESUME: |
| 483 | ich_force_hpet_resume(); |
| 484 | return; |
| 485 | case OLD_ICH_FORCE_HPET_RESUME: |
| 486 | old_ich_force_hpet_resume(); |
| 487 | return; |
| 488 | case VT8237_FORCE_HPET_RESUME: |
| 489 | vt8237_force_hpet_resume(); |
| 490 | return; |
| 491 | case NVIDIA_FORCE_HPET_RESUME: |
| 492 | nvidia_force_hpet_resume(); |
| 493 | return; |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 494 | case ATI_FORCE_HPET_RESUME: |
| 495 | ati_force_hpet_resume(); |
| 496 | return; |
Harvey Harrison | 4a5a77d | 2008-02-06 22:39:44 +0100 | [diff] [blame] | 497 | default: |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 498 | break; |
| 499 | } |
| 500 | } |
Pallipadi, Venkatesh | 73472a4 | 2010-01-21 11:09:52 -0800 | [diff] [blame] | 501 | |
| 502 | /* |
Peter Neubauer | 2e151c7 | 2014-09-12 13:06:13 +0200 | [diff] [blame] | 503 | * According to the datasheet e6xx systems have the HPET hardwired to |
| 504 | * 0xfed00000 |
| 505 | */ |
| 506 | static void e6xx_force_enable_hpet(struct pci_dev *dev) |
| 507 | { |
| 508 | if (hpet_address || force_hpet_address) |
| 509 | return; |
| 510 | |
| 511 | force_hpet_address = 0xFED00000; |
| 512 | force_hpet_resume_type = NONE_FORCE_HPET_RESUME; |
| 513 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 514 | "0x%lx\n", force_hpet_address); |
| 515 | return; |
| 516 | } |
| 517 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU, |
| 518 | e6xx_force_enable_hpet); |
| 519 | |
| 520 | /* |
Pallipadi, Venkatesh | 73472a4 | 2010-01-21 11:09:52 -0800 | [diff] [blame] | 521 | * HPET MSI on some boards (ATI SB700/SB800) has side effect on |
| 522 | * floppy DMA. Disable HPET MSI on such platforms. |
Andreas Herrmann | fec84e3 | 2010-05-17 18:43:24 +0200 | [diff] [blame] | 523 | * See erratum #27 (Misinterpreted MSI Requests May Result in |
| 524 | * Corrupted LPC DMA Data) in AMD Publication #46837, |
| 525 | * "SB700 Family Product Errata", Rev. 1.0, March 2010. |
Pallipadi, Venkatesh | 73472a4 | 2010-01-21 11:09:52 -0800 | [diff] [blame] | 526 | */ |
| 527 | static void force_disable_hpet_msi(struct pci_dev *unused) |
| 528 | { |
Jan Beulich | 3d45ac4 | 2015-10-19 04:35:44 -0600 | [diff] [blame] | 529 | hpet_msi_disable = true; |
Pallipadi, Venkatesh | 73472a4 | 2010-01-21 11:09:52 -0800 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, |
| 533 | force_disable_hpet_msi); |
| 534 | |
Andreas Herrmann | 9b94b3a | 2009-04-17 12:07:46 +0200 | [diff] [blame] | 535 | #endif |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 536 | |
Andreas Herrmann | 9b94b3a | 2009-04-17 12:07:46 +0200 | [diff] [blame] | 537 | #if defined(CONFIG_PCI) && defined(CONFIG_NUMA) |
| 538 | /* Set correct numa_node information for AMD NB functions */ |
Greg Kroah-Hartman | a18e369 | 2012-12-21 14:02:53 -0800 | [diff] [blame] | 539 | static void quirk_amd_nb_node(struct pci_dev *dev) |
Andreas Herrmann | 9b94b3a | 2009-04-17 12:07:46 +0200 | [diff] [blame] | 540 | { |
| 541 | struct pci_dev *nb_ht; |
| 542 | unsigned int devfn; |
Prarit Bhargava | 303fc08 | 2009-11-12 13:09:31 -0500 | [diff] [blame] | 543 | u32 node; |
Andreas Herrmann | 9b94b3a | 2009-04-17 12:07:46 +0200 | [diff] [blame] | 544 | u32 val; |
| 545 | |
| 546 | devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0); |
| 547 | nb_ht = pci_get_slot(dev->bus, devfn); |
| 548 | if (!nb_ht) |
| 549 | return; |
| 550 | |
| 551 | pci_read_config_dword(nb_ht, 0x60, &val); |
Daniel J Blueman | 847d797 | 2014-03-13 19:43:01 +0800 | [diff] [blame] | 552 | node = pcibus_to_node(dev->bus) | (val & 7); |
Prarit Bhargava | 303fc08 | 2009-11-12 13:09:31 -0500 | [diff] [blame] | 553 | /* |
| 554 | * Some hardware may return an invalid node ID, |
| 555 | * so check it first: |
| 556 | */ |
| 557 | if (node_online(node)) |
| 558 | set_dev_node(&dev->dev, node); |
Jiri Slaby | 748df9a | 2009-09-08 12:16:18 +0200 | [diff] [blame] | 559 | pci_dev_put(nb_ht); |
Andreas Herrmann | 9b94b3a | 2009-04-17 12:07:46 +0200 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB, |
| 563 | quirk_amd_nb_node); |
| 564 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, |
| 565 | quirk_amd_nb_node); |
| 566 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, |
| 567 | quirk_amd_nb_node); |
| 568 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC, |
| 569 | quirk_amd_nb_node); |
| 570 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 571 | quirk_amd_nb_node); |
| 572 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP, |
| 573 | quirk_amd_nb_node); |
| 574 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM, |
| 575 | quirk_amd_nb_node); |
| 576 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC, |
| 577 | quirk_amd_nb_node); |
| 578 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK, |
| 579 | quirk_amd_nb_node); |
Andreas Herrmann | f62ef5f | 2011-12-02 08:21:43 +0100 | [diff] [blame] | 580 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F0, |
| 581 | quirk_amd_nb_node); |
| 582 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F1, |
| 583 | quirk_amd_nb_node); |
| 584 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F2, |
| 585 | quirk_amd_nb_node); |
| 586 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3, |
| 587 | quirk_amd_nb_node); |
| 588 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4, |
| 589 | quirk_amd_nb_node); |
| 590 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5, |
| 591 | quirk_amd_nb_node); |
| 592 | |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 593 | #endif |
Aravind Gopalakrishnan | fb53a1a | 2014-01-23 16:13:32 -0600 | [diff] [blame] | 594 | |
| 595 | #ifdef CONFIG_PCI |
| 596 | /* |
| 597 | * Processor does not ensure DRAM scrub read/write sequence |
| 598 | * is atomic wrt accesses to CC6 save state area. Therefore |
| 599 | * if a concurrent scrub read/write access is to same address |
| 600 | * the entry may appear as if it is not written. This quirk |
| 601 | * applies to Fam16h models 00h-0Fh |
| 602 | * |
| 603 | * See "Revision Guide" for AMD F16h models 00h-0fh, |
| 604 | * document 51810 rev. 3.04, Nov 2013 |
| 605 | */ |
| 606 | static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev) |
| 607 | { |
| 608 | u32 val; |
| 609 | |
| 610 | /* |
| 611 | * Suggested workaround: |
| 612 | * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b |
| 613 | */ |
| 614 | pci_read_config_dword(dev, 0x58, &val); |
| 615 | if (val & 0x1F) { |
| 616 | val &= ~(0x1F); |
| 617 | pci_write_config_dword(dev, 0x58, val); |
| 618 | } |
| 619 | |
| 620 | pci_read_config_dword(dev, 0x5C, &val); |
| 621 | if (val & BIT(0)) { |
| 622 | val &= ~BIT(0); |
| 623 | pci_write_config_dword(dev, 0x5c, val); |
| 624 | } |
| 625 | } |
| 626 | |
| 627 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3, |
| 628 | amd_disable_seq_and_redirect_scrub); |
| 629 | |
Tony Luck | 3637efb | 2016-09-01 11:39:33 -0700 | [diff] [blame] | 630 | #if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE) |
| 631 | #include <linux/jump_label.h> |
| 632 | #include <asm/string_64.h> |
| 633 | |
| 634 | /* Ivy Bridge, Haswell, Broadwell */ |
| 635 | static void quirk_intel_brickland_xeon_ras_cap(struct pci_dev *pdev) |
| 636 | { |
| 637 | u32 capid0; |
| 638 | |
| 639 | pci_read_config_dword(pdev, 0x84, &capid0); |
| 640 | |
| 641 | if (capid0 & 0x10) |
| 642 | static_branch_inc(&mcsafe_key); |
| 643 | } |
| 644 | |
| 645 | /* Skylake */ |
| 646 | static void quirk_intel_purley_xeon_ras_cap(struct pci_dev *pdev) |
| 647 | { |
| 648 | u32 capid0; |
| 649 | |
| 650 | pci_read_config_dword(pdev, 0x84, &capid0); |
| 651 | |
| 652 | if ((capid0 & 0xc0) == 0xc0) |
| 653 | static_branch_inc(&mcsafe_key); |
| 654 | } |
| 655 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap); |
| 656 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap); |
| 657 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap); |
| 658 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap); |
| 659 | #endif |
Arnd Bergmann | d320b9a | 2016-10-24 17:33:18 +0200 | [diff] [blame] | 660 | #endif |
Lukas Wunner | 630b3af | 2017-08-01 14:10:41 +0200 | [diff] [blame] | 661 | |
| 662 | bool x86_apple_machine; |
| 663 | EXPORT_SYMBOL(x86_apple_machine); |
| 664 | |
| 665 | void __init early_platform_quirks(void) |
| 666 | { |
| 667 | x86_apple_machine = dmi_match(DMI_SYS_VENDOR, "Apple Inc.") || |
| 668 | dmi_match(DMI_SYS_VENDOR, "Apple Computer, Inc."); |
| 669 | } |