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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001# SPDX-License-Identifier: GPL-2.0
Paul Mundtcad82442006-01-16 22:14:19 -08002menu "Memory management options"
3
4config MMU
5 bool "Support for memory management hardware"
6 depends on !CPU_SH2
7 default y
8 help
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
10 boot on these systems, this option must not be set.
11
12 On other systems (such as the SH-3 and 4) where an MMU exists,
13 turning this off will boot the kernel on these machines with the
14 MMU implicitly switched off.
15
Paul Mundte7f93a32006-09-27 17:19:13 +090016config PAGE_OFFSET
17 hex
Arnd Bergmann37744fe2020-04-20 11:37:12 +020018 default "0x80000000" if MMU
Paul Mundte7f93a32006-09-27 17:19:13 +090019 default "0x00000000"
20
Zi Yan01924452022-08-15 10:39:59 -040021config ARCH_FORCE_MAX_ORDER
Mike Rapoport (IBM)b2a37fb2023-03-24 08:22:30 +030022 int "Order of maximal physically contiguous allocations"
Kirill A. Shutemov23baf832023-03-15 14:31:33 +030023 default "8" if PAGE_SIZE_16KB
Kirill A. Shutemov23baf832023-03-15 14:31:33 +030024 default "6" if PAGE_SIZE_64KB
Kirill A. Shutemov23baf832023-03-15 14:31:33 +030025 default "13" if !MMU
26 default "10"
Paul Mundtad3256e2009-05-14 17:40:08 +090027 help
Mike Rapoport (IBM)b2a37fb2023-03-24 08:22:30 +030028 The kernel page allocator limits the size of maximal physically
29 contiguous allocations. The limit is called MAX_ORDER and it
30 defines the maximal power of two of number of pages that can be
31 allocated as a single contiguous block. This option allows
32 overriding the default setting when ability to allocate very
33 large blocks of physically contiguous memory is required.
Paul Mundtad3256e2009-05-14 17:40:08 +090034
Paul Mundtad3256e2009-05-14 17:40:08 +090035 The page size is not necessarily 4KB. Keep this in mind when
36 choosing a value for this option.
37
Mike Rapoport (IBM)b2a37fb2023-03-24 08:22:30 +030038 Don't change if unsure.
39
Paul Mundte7f93a32006-09-27 17:19:13 +090040config MEMORY_START
41 hex "Physical memory start address"
42 default "0x08000000"
Masahiro Yamadaa7f7f622020-06-14 01:50:22 +090043 help
Paul Mundte7f93a32006-09-27 17:19:13 +090044 Computers built with Hitachi SuperH processors always
45 map the ROM starting at address zero. But the processor
46 does not specify the range that RAM takes.
47
48 The physical memory (RAM) start address will be automatically
49 set to 08000000. Other platforms, such as the Solution Engine
50 boards typically map RAM at 0C000000.
51
52 Tweak this only when porting to a new machine which does not
53 already have a defconfig. Changing it from the known correct
54 value on any of the known systems will only lead to disaster.
55
56config MEMORY_SIZE
57 hex "Physical memory size"
Paul Mundt711fe432007-11-21 15:46:07 +090058 default "0x04000000"
Paul Mundte7f93a32006-09-27 17:19:13 +090059 help
60 This sets the default memory size assumed by your SH kernel. It can
61 be overridden as normal by the 'mem=' argument on the kernel command
62 line. If unsure, consult your board specifications or just leave it
Paul Mundt711fe432007-11-21 15:46:07 +090063 as 0x04000000 which was the default value before this became
Paul Mundte7f93a32006-09-27 17:19:13 +090064 configurable.
65
Paul Mundt36bcd392007-11-10 19:16:55 +090066# Physical addressing modes
67
68config 29BIT
69 def_bool !32BIT
Paul Mundtb0f3ae02010-02-12 15:40:00 +090070 select UNCACHED_MAPPING
Paul Mundt36bcd392007-11-10 19:16:55 +090071
Paul Mundtcad82442006-01-16 22:14:19 -080072config 32BIT
Paul Mundt36bcd392007-11-10 19:16:55 +090073 bool
Arnd Bergmann37744fe2020-04-20 11:37:12 +020074 default !MMU
Paul Mundt36bcd392007-11-10 19:16:55 +090075
Paul Mundta0ab3662010-01-13 18:31:48 +090076config PMB
Paul Mundtcad82442006-01-16 22:14:19 -080077 bool "Support 32-bit physical addressing through PMB"
Kees Cook0d57af12013-01-16 18:53:26 -080078 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
Paul Mundta0ab3662010-01-13 18:31:48 +090079 select 32BIT
Paul Mundtb0f3ae02010-02-12 15:40:00 +090080 select UNCACHED_MAPPING
Paul Mundtcad82442006-01-16 22:14:19 -080081 help
82 If you say Y here, physical addressing will be extended to
83 32-bits through the SH-4A PMB. If this is not set, legacy
84 29-bit physical addressing will be used.
85
Paul Mundt21440cf2006-11-20 14:30:26 +090086config X2TLB
Paul Mundt782bb5a2010-01-13 19:11:14 +090087 def_bool y
88 depends on (CPU_SHX2 || CPU_SHX3) && MMU
Paul Mundt21440cf2006-11-20 14:30:26 +090089
Paul Mundt19f9a34f2006-09-27 18:33:49 +090090config VSYSCALL
91 bool "Support vsyscall page"
Paul Mundta09063d2007-11-08 18:54:16 +090092 depends on MMU && (CPU_SH3 || CPU_SH4)
Paul Mundt19f9a34f2006-09-27 18:33:49 +090093 default y
94 help
95 This will enable support for the kernel mapping a vDSO page
96 in process space, and subsequently handing down the entry point
97 to the libc through the ELF auxiliary vector.
98
99 From the kernel side this is used for the signal trampoline.
100 For systems with an MMU that can afford to give up a page,
101 (the default value) say Y.
102
Paul Mundtb241cb02007-06-06 17:52:19 +0900103config NUMA
Randy Dunlap7fb0a1a2020-09-17 19:14:04 -0700104 bool "Non-Uniform Memory Access (NUMA) Support"
Kees Cook0d57af12013-01-16 18:53:26 -0800105 depends on MMU && SYS_SUPPORTS_NUMA
Peter Zijlstracbee9f82012-10-25 14:16:43 +0200106 select ARCH_WANT_NUMA_VARIABLE_LOCALITY
Paul Mundtb241cb02007-06-06 17:52:19 +0900107 default n
108 help
109 Some SH systems have many various memories scattered around
110 the address space, each with varying latencies. This enables
111 support for these blocks by binding them to nodes and allowing
112 memory policies to be used for prioritizing and controlling
113 allocation behaviour.
114
Paul Mundt01066622007-03-28 16:38:13 +0900115config NODES_SHIFT
116 int
Paul Mundt99044942007-08-08 16:45:07 +0900117 default "3" if CPU_SUBTYPE_SHX3
Paul Mundt01066622007-03-28 16:38:13 +0900118 default "1"
Mike Rapoporta9ee6cf2021-06-28 19:43:01 -0700119 depends on NUMA
Paul Mundt01066622007-03-28 16:38:13 +0900120
121config ARCH_FLATMEM_ENABLE
122 def_bool y
Paul Mundt357d5942007-06-11 15:32:07 +0900123 depends on !NUMA
Paul Mundt01066622007-03-28 16:38:13 +0900124
Paul Mundtdfbb9042007-05-23 17:48:36 +0900125config ARCH_SPARSEMEM_ENABLE
126 def_bool y
127 select SPARSEMEM_STATIC
128
129config ARCH_SPARSEMEM_DEFAULT
130 def_bool y
131
Paul Mundtdfbb9042007-05-23 17:48:36 +0900132config ARCH_SELECT_MEMORY_MODEL
133 def_bool y
134
Paul Mundt33d63bd2007-06-07 11:32:52 +0900135config ARCH_MEMORY_PROBE
136 def_bool y
137 depends on MEMORY_HOTPLUG
138
Matt Fleming4d35b932009-11-05 07:54:17 +0000139config IOREMAP_FIXED
140 def_bool y
Arnd Bergmann37744fe2020-04-20 11:37:12 +0200141 depends on X2TLB
Matt Fleming4d35b932009-11-05 07:54:17 +0000142
Paul Mundtb0f3ae02010-02-12 15:40:00 +0900143config UNCACHED_MAPPING
144 bool
145
Paul Mundtc9934872010-10-15 02:09:00 +0900146config HAVE_SRAM_POOL
147 bool
148 select GENERIC_ALLOCATOR
149
Paul Mundtcad82442006-01-16 22:14:19 -0800150choice
Paul Mundt21440cf2006-11-20 14:30:26 +0900151 prompt "Kernel page size"
152 default PAGE_SIZE_4KB
153
154config PAGE_SIZE_4KB
155 bool "4kB"
156 help
157 This is the default page size used by all SuperH CPUs.
158
159config PAGE_SIZE_8KB
160 bool "8kB"
Matt Fleming3f5ab762009-12-24 20:38:45 +0000161 depends on !MMU || X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900162 help
163 This enables 8kB pages as supported by SH-X2 and later MMUs.
164
Paul Mundt66dfe182008-06-03 18:54:02 +0900165config PAGE_SIZE_16KB
166 bool "16kB"
167 depends on !MMU
168 help
169 This enables 16kB pages on MMU-less SH systems.
170
Paul Mundt21440cf2006-11-20 14:30:26 +0900171config PAGE_SIZE_64KB
172 bool "64kB"
Arnd Bergmann37744fe2020-04-20 11:37:12 +0200173 depends on !MMU || CPU_SH4
Paul Mundt21440cf2006-11-20 14:30:26 +0900174 help
175 This enables support for 64kB pages, possible on all SH-4
Paul Mundt4d2cab72007-09-27 10:47:00 +0900176 CPUs and later.
Paul Mundt21440cf2006-11-20 14:30:26 +0900177
178endchoice
179
180choice
Paul Mundtcad82442006-01-16 22:14:19 -0800181 prompt "HugeTLB page size"
Paul Mundtffb4a732009-10-27 07:22:37 +0900182 depends on HUGETLB_PAGE
Paul Mundt68b7c242008-08-06 15:10:49 +0900183 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
Paul Mundtcad82442006-01-16 22:14:19 -0800184 default HUGETLB_PAGE_SIZE_64K
185
186config HUGETLB_PAGE_SIZE_64K
Paul Mundt21440cf2006-11-20 14:30:26 +0900187 bool "64kB"
Paul Mundt68b7c242008-08-06 15:10:49 +0900188 depends on !PAGE_SIZE_64KB
Paul Mundt21440cf2006-11-20 14:30:26 +0900189
190config HUGETLB_PAGE_SIZE_256K
191 bool "256kB"
192 depends on X2TLB
Paul Mundtcad82442006-01-16 22:14:19 -0800193
194config HUGETLB_PAGE_SIZE_1MB
195 bool "1MB"
196
Paul Mundt21440cf2006-11-20 14:30:26 +0900197config HUGETLB_PAGE_SIZE_4MB
198 bool "4MB"
199 depends on X2TLB
200
201config HUGETLB_PAGE_SIZE_64MB
202 bool "64MB"
203 depends on X2TLB
204
Paul Mundtcad82442006-01-16 22:14:19 -0800205endchoice
206
Paul Mundt896f0c02009-10-16 18:00:02 +0900207config SCHED_MC
208 bool "Multi-core scheduler support"
209 depends on SMP
210 default y
211 help
212 Multi-core scheduler support improves the CPU scheduler's decision
213 making when dealing with multi-core CPU chips at a cost of slightly
214 increased overhead in some places. If unsure say N here.
215
Paul Mundtcad82442006-01-16 22:14:19 -0800216endmenu
217
218menu "Cache configuration"
219
220config SH7705_CACHE_32KB
221 bool "Enable 32KB cache size for SH7705"
222 depends on CPU_SUBTYPE_SH7705
223 default y
224
Paul Mundte7bd34a2007-07-31 17:07:28 +0900225choice
226 prompt "Cache mode"
Arnd Bergmann37744fe2020-04-20 11:37:12 +0200227 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
Paul Mundte7bd34a2007-07-31 17:07:28 +0900228 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
229
230config CACHE_WRITEBACK
231 bool "Write-back"
Paul Mundte7bd34a2007-07-31 17:07:28 +0900232
233config CACHE_WRITETHROUGH
234 bool "Write-through"
Paul Mundtcad82442006-01-16 22:14:19 -0800235 help
236 Selecting this option will configure the caches in write-through
237 mode, as opposed to the default write-back configuration.
238
239 Since there's sill some aliasing issues on SH-4, this option will
240 unfortunately still require the majority of flushing functions to
241 be implemented to deal with aliasing.
242
243 If unsure, say N.
244
Paul Mundte7bd34a2007-07-31 17:07:28 +0900245config CACHE_OFF
246 bool "Off"
247
248endchoice
249
Paul Mundtcad82442006-01-16 22:14:19 -0800250endmenu