Gary Bisson | 3221cee | 2018-07-13 14:49:02 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR X11 |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Boundary Devices, Inc. |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 4 | */ |
| 5 | #include <dt-bindings/gpio/gpio.h> |
| 6 | #include <dt-bindings/input/input.h> |
| 7 | |
| 8 | / { |
| 9 | chosen { |
| 10 | stdout-path = &uart2; |
| 11 | }; |
| 12 | |
Marco Franchi | ad00e08 | 2018-01-24 11:22:14 -0200 | [diff] [blame] | 13 | memory@10000000 { |
Marco Franchi | 404c0c9 | 2018-12-05 16:10:03 -0200 | [diff] [blame] | 14 | device_type = "memory"; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 15 | reg = <0x10000000 0xF0000000>; |
| 16 | }; |
| 17 | |
| 18 | regulators { |
| 19 | compatible = "simple-bus"; |
| 20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; |
| 22 | |
| 23 | reg_1p8v: regulator@0 { |
| 24 | compatible = "regulator-fixed"; |
| 25 | reg = <0>; |
| 26 | regulator-name = "1P8V"; |
| 27 | regulator-min-microvolt = <1800000>; |
| 28 | regulator-max-microvolt = <1800000>; |
| 29 | regulator-always-on; |
| 30 | }; |
| 31 | |
| 32 | reg_2p5v: regulator@1 { |
| 33 | compatible = "regulator-fixed"; |
| 34 | reg = <1>; |
| 35 | regulator-name = "2P5V"; |
| 36 | regulator-min-microvolt = <2500000>; |
| 37 | regulator-max-microvolt = <2500000>; |
| 38 | regulator-always-on; |
| 39 | }; |
| 40 | |
| 41 | reg_3p3v: regulator@2 { |
| 42 | compatible = "regulator-fixed"; |
| 43 | reg = <2>; |
| 44 | regulator-name = "3P3V"; |
| 45 | regulator-min-microvolt = <3300000>; |
| 46 | regulator-max-microvolt = <3300000>; |
| 47 | regulator-always-on; |
| 48 | }; |
| 49 | |
| 50 | reg_usb_otg_vbus: regulator@3 { |
| 51 | compatible = "regulator-fixed"; |
| 52 | reg = <3>; |
| 53 | regulator-name = "usb_otg_vbus"; |
| 54 | regulator-min-microvolt = <5000000>; |
| 55 | regulator-max-microvolt = <5000000>; |
| 56 | gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; |
| 57 | enable-active-high; |
| 58 | }; |
| 59 | |
| 60 | reg_usb_h1_vbus: regulator@4 { |
| 61 | compatible = "regulator-fixed"; |
| 62 | reg = <4>; |
| 63 | pinctrl-names = "default"; |
| 64 | pinctrl-0 = <&pinctrl_usbh1>; |
| 65 | regulator-name = "usb_h1_vbus"; |
| 66 | regulator-min-microvolt = <3300000>; |
| 67 | regulator-max-microvolt = <3300000>; |
| 68 | gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; |
| 69 | enable-active-high; |
| 70 | }; |
| 71 | |
| 72 | reg_wlan_vmmc: regulator@5 { |
| 73 | compatible = "regulator-fixed"; |
| 74 | reg = <5>; |
| 75 | pinctrl-names = "default"; |
| 76 | pinctrl-0 = <&pinctrl_wlan_vmmc>; |
| 77 | regulator-name = "reg_wlan_vmmc"; |
| 78 | regulator-min-microvolt = <3300000>; |
| 79 | regulator-max-microvolt = <3300000>; |
| 80 | gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; |
| 81 | startup-delay-us = <70000>; |
| 82 | enable-active-high; |
| 83 | }; |
| 84 | |
| 85 | reg_can_xcvr: regulator@6 { |
| 86 | compatible = "regulator-fixed"; |
| 87 | reg = <6>; |
| 88 | regulator-name = "CAN XCVR"; |
| 89 | regulator-min-microvolt = <3300000>; |
| 90 | regulator-max-microvolt = <3300000>; |
| 91 | pinctrl-names = "default"; |
| 92 | pinctrl-0 = <&pinctrl_can_xcvr>; |
| 93 | gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | gpio-keys { |
| 98 | compatible = "gpio-keys"; |
| 99 | pinctrl-names = "default"; |
| 100 | pinctrl-0 = <&pinctrl_gpio_keys>; |
| 101 | |
| 102 | power { |
| 103 | label = "Power Button"; |
| 104 | gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; |
| 105 | linux,code = <KEY_POWER>; |
Sudeep Holla | 26cefdd | 2015-10-21 11:10:08 +0100 | [diff] [blame] | 106 | wakeup-source; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 107 | }; |
| 108 | |
| 109 | menu { |
| 110 | label = "Menu"; |
| 111 | gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; |
| 112 | linux,code = <KEY_MENU>; |
| 113 | }; |
| 114 | |
| 115 | home { |
| 116 | label = "Home"; |
| 117 | gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; |
| 118 | linux,code = <KEY_HOME>; |
| 119 | }; |
| 120 | |
| 121 | back { |
| 122 | label = "Back"; |
| 123 | gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; |
| 124 | linux,code = <KEY_BACK>; |
| 125 | }; |
| 126 | |
| 127 | volume-up { |
| 128 | label = "Volume Up"; |
| 129 | gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; |
| 130 | linux,code = <KEY_VOLUMEUP>; |
| 131 | }; |
| 132 | |
| 133 | volume-down { |
| 134 | label = "Volume Down"; |
| 135 | gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; |
| 136 | linux,code = <KEY_VOLUMEDOWN>; |
| 137 | }; |
| 138 | }; |
| 139 | |
Fabio Estevam | d03cd58 | 2017-12-04 10:20:15 -0200 | [diff] [blame] | 140 | i2c2mux { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 141 | compatible = "i2c-mux-gpio"; |
| 142 | pinctrl-names = "default"; |
| 143 | pinctrl-0 = <&pinctrl_i2c2mux>; |
| 144 | #address-cells = <1>; |
| 145 | #size-cells = <0>; |
| 146 | mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH |
| 147 | &gpio4 15 GPIO_ACTIVE_HIGH>; |
| 148 | i2c-parent = <&i2c2>; |
| 149 | idle-state = <0>; |
| 150 | |
Fabio Estevam | d03cd58 | 2017-12-04 10:20:15 -0200 | [diff] [blame] | 151 | i2c2mux@1 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 152 | reg = <1>; |
| 153 | #address-cells = <1>; |
| 154 | #size-cells = <0>; |
| 155 | }; |
| 156 | |
Fabio Estevam | d03cd58 | 2017-12-04 10:20:15 -0200 | [diff] [blame] | 157 | i2c2mux@2 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 158 | reg = <2>; |
| 159 | #address-cells = <1>; |
| 160 | #size-cells = <0>; |
| 161 | }; |
| 162 | }; |
| 163 | |
Fabio Estevam | d03cd58 | 2017-12-04 10:20:15 -0200 | [diff] [blame] | 164 | i2c3mux { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 165 | compatible = "i2c-mux-gpio"; |
| 166 | pinctrl-names = "default"; |
| 167 | pinctrl-0 = <&pinctrl_i2c3mux>; |
| 168 | #address-cells = <1>; |
| 169 | #size-cells = <0>; |
| 170 | mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; |
| 171 | i2c-parent = <&i2c3>; |
| 172 | idle-state = <0>; |
| 173 | |
Fabio Estevam | d03cd58 | 2017-12-04 10:20:15 -0200 | [diff] [blame] | 174 | i2c3mux@1 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 175 | reg = <1>; |
| 176 | #address-cells = <1>; |
| 177 | #size-cells = <0>; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | leds { |
| 182 | compatible = "gpio-leds"; |
| 183 | |
| 184 | speaker-enable { |
| 185 | gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; |
| 186 | retain-state-suspended; |
| 187 | default-state = "off"; |
| 188 | }; |
| 189 | |
| 190 | ttymxc4-rs232 { |
| 191 | gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; |
| 192 | retain-state-suspended; |
| 193 | default-state = "on"; |
| 194 | }; |
| 195 | }; |
| 196 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 197 | backlight_lcd: backlight-lcd { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 198 | compatible = "pwm-backlight"; |
| 199 | pwms = <&pwm1 0 5000000>; |
| 200 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 201 | default-brightness-level = <7>; |
| 202 | power-supply = <®_3p3v>; |
| 203 | status = "okay"; |
| 204 | }; |
| 205 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 206 | backlight_lvds0: backlight-lvds0 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 207 | compatible = "pwm-backlight"; |
| 208 | pwms = <&pwm4 0 5000000>; |
| 209 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 210 | default-brightness-level = <7>; |
| 211 | power-supply = <®_3p3v>; |
| 212 | status = "okay"; |
| 213 | }; |
| 214 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 215 | backlight_lvds1: backlight-lvds1 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 216 | compatible = "pwm-backlight"; |
| 217 | pwms = <&pwm2 0 5000000>; |
| 218 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 219 | default-brightness-level = <7>; |
| 220 | power-supply = <®_3p3v>; |
| 221 | status = "okay"; |
| 222 | }; |
| 223 | |
Marco Franchi | 792d4ed | 2017-10-05 11:31:40 -0300 | [diff] [blame] | 224 | lcd_display: disp0 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 225 | compatible = "fsl,imx-parallel-display"; |
| 226 | #address-cells = <1>; |
| 227 | #size-cells = <0>; |
| 228 | interface-pix-fmt = "bgr666"; |
| 229 | pinctrl-names = "default"; |
| 230 | pinctrl-0 = <&pinctrl_j15>; |
| 231 | status = "okay"; |
| 232 | |
| 233 | port@0 { |
| 234 | reg = <0>; |
| 235 | |
| 236 | lcd_display_in: endpoint { |
| 237 | remote-endpoint = <&ipu1_di0_disp0>; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | port@1 { |
| 242 | reg = <1>; |
| 243 | |
| 244 | lcd_display_out: endpoint { |
| 245 | remote-endpoint = <&lcd_panel_in>; |
| 246 | }; |
| 247 | }; |
| 248 | }; |
| 249 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 250 | panel-lcd { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 251 | compatible = "okaya,rs800480t-7x0gp"; |
| 252 | backlight = <&backlight_lcd>; |
| 253 | |
| 254 | port { |
| 255 | lcd_panel_in: endpoint { |
| 256 | remote-endpoint = <&lcd_display_out>; |
| 257 | }; |
| 258 | }; |
| 259 | }; |
| 260 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 261 | panel-lvds0 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 262 | compatible = "hannstar,hsd100pxn1"; |
| 263 | backlight = <&backlight_lvds0>; |
| 264 | |
| 265 | port { |
| 266 | panel_in_lvds0: endpoint { |
| 267 | remote-endpoint = <&lvds0_out>; |
| 268 | }; |
| 269 | }; |
| 270 | }; |
| 271 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 272 | panel-lvds1 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 273 | compatible = "hannstar,hsd100pxn1"; |
| 274 | backlight = <&backlight_lvds1>; |
| 275 | |
| 276 | port { |
| 277 | panel_in_lvds1: endpoint { |
| 278 | remote-endpoint = <&lvds1_out>; |
| 279 | }; |
| 280 | }; |
| 281 | }; |
| 282 | |
| 283 | sound { |
| 284 | compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", |
| 285 | "fsl,imx-audio-sgtl5000"; |
| 286 | model = "imx6q-nitrogen6_max-sgtl5000"; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 287 | ssi-controller = <&ssi1>; |
| 288 | audio-codec = <&codec>; |
| 289 | audio-routing = |
| 290 | "MIC_IN", "Mic Jack", |
| 291 | "Mic Jack", "Mic Bias", |
| 292 | "Headphone Jack", "HP_OUT"; |
| 293 | mux-int-port = <1>; |
| 294 | mux-ext-port = <3>; |
| 295 | }; |
| 296 | }; |
| 297 | |
| 298 | &audmux { |
| 299 | pinctrl-names = "default"; |
| 300 | pinctrl-0 = <&pinctrl_audmux>; |
| 301 | status = "okay"; |
| 302 | }; |
| 303 | |
| 304 | &can1 { |
| 305 | pinctrl-names = "default"; |
| 306 | pinctrl-0 = <&pinctrl_can1>; |
| 307 | xceiver-supply = <®_can_xcvr>; |
| 308 | status = "okay"; |
| 309 | }; |
| 310 | |
| 311 | &clks { |
| 312 | assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| 313 | <&clks IMX6QDL_CLK_LDB_DI1_SEL>; |
| 314 | assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, |
| 315 | <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
| 316 | }; |
| 317 | |
| 318 | &ecspi1 { |
Fabio Estevam | 2bfdd11 | 2020-08-19 18:04:24 -0300 | [diff] [blame] | 319 | cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 320 | pinctrl-names = "default"; |
| 321 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 322 | status = "okay"; |
| 323 | |
Krzysztof Kozlowski | ba9fe46 | 2022-04-07 16:31:54 +0200 | [diff] [blame] | 324 | flash: flash@0 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 325 | compatible = "microchip,sst25vf016b"; |
| 326 | spi-max-frequency = <20000000>; |
| 327 | reg = <0>; |
| 328 | }; |
| 329 | }; |
| 330 | |
| 331 | &fec { |
| 332 | pinctrl-names = "default"; |
| 333 | pinctrl-0 = <&pinctrl_enet>; |
| 334 | phy-mode = "rgmii"; |
Joakim Zhang | dabb5db | 2021-07-21 18:12:20 +0800 | [diff] [blame] | 335 | phy-handle = <ðphy>; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 336 | phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; |
Alexander Stein | c9d38ff | 2022-07-20 08:41:58 +0200 | [diff] [blame] | 337 | /delete-property/ interrupts; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 338 | interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, |
| 339 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; |
Lucas Stach | a28eeb4 | 2016-06-03 18:31:20 +0200 | [diff] [blame] | 340 | fsl,err006687-workaround-present; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 341 | status = "okay"; |
Joakim Zhang | dabb5db | 2021-07-21 18:12:20 +0800 | [diff] [blame] | 342 | |
| 343 | mdio { |
| 344 | #address-cells = <1>; |
| 345 | #size-cells = <0>; |
| 346 | |
| 347 | ethphy: ethernet-phy { |
| 348 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 349 | txen-skew-ps = <0>; |
| 350 | txc-skew-ps = <3000>; |
| 351 | rxdv-skew-ps = <0>; |
| 352 | rxc-skew-ps = <3000>; |
| 353 | rxd0-skew-ps = <0>; |
| 354 | rxd1-skew-ps = <0>; |
| 355 | rxd2-skew-ps = <0>; |
| 356 | rxd3-skew-ps = <0>; |
| 357 | txd0-skew-ps = <0>; |
| 358 | txd1-skew-ps = <0>; |
| 359 | txd2-skew-ps = <0>; |
| 360 | txd3-skew-ps = <0>; |
| 361 | }; |
| 362 | }; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 363 | }; |
| 364 | |
| 365 | &hdmi { |
| 366 | ddc-i2c-bus = <&i2c2>; |
| 367 | status = "okay"; |
| 368 | }; |
| 369 | |
| 370 | &i2c1 { |
| 371 | clock-frequency = <100000>; |
| 372 | pinctrl-names = "default"; |
| 373 | pinctrl-0 = <&pinctrl_i2c1>; |
| 374 | status = "okay"; |
| 375 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 376 | codec: sgtl5000@a { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 377 | compatible = "fsl,sgtl5000"; |
Gary Bisson | 6ab5c2b | 2017-01-03 12:22:46 +0100 | [diff] [blame] | 378 | pinctrl-names = "default"; |
| 379 | pinctrl-0 = <&pinctrl_sgtl5000>; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 380 | reg = <0x0a>; |
Fabio Estevam | b26a68c | 2016-04-26 22:28:29 -0300 | [diff] [blame] | 381 | clocks = <&clks IMX6QDL_CLK_CKO>; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 382 | VDDA-supply = <®_2p5v>; |
| 383 | VDDIO-supply = <®_3p3v>; |
| 384 | }; |
| 385 | |
| 386 | rtc: rtc@68 { |
Alexandre Belloni | 2b73493 | 2017-04-19 22:22:02 +0200 | [diff] [blame] | 387 | compatible = "microcrystal,rv4162"; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 388 | pinctrl-names = "default"; |
| 389 | pinctrl-0 = <&pinctrl_rv4162>; |
| 390 | reg = <0x68>; |
| 391 | interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; |
| 392 | }; |
| 393 | }; |
| 394 | |
| 395 | &i2c2 { |
| 396 | clock-frequency = <100000>; |
| 397 | pinctrl-names = "default"; |
| 398 | pinctrl-0 = <&pinctrl_i2c2>; |
| 399 | status = "okay"; |
| 400 | }; |
| 401 | |
| 402 | &i2c3 { |
| 403 | clock-frequency = <100000>; |
| 404 | pinctrl-names = "default"; |
| 405 | pinctrl-0 = <&pinctrl_i2c3>; |
| 406 | status = "okay"; |
| 407 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 408 | touchscreen@4 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 409 | compatible = "eeti,egalax_ts"; |
| 410 | reg = <0x04>; |
| 411 | interrupt-parent = <&gpio1>; |
| 412 | interrupts = <9 IRQ_TYPE_EDGE_FALLING>; |
| 413 | wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; |
| 414 | }; |
| 415 | |
| 416 | touchscreen@38 { |
| 417 | compatible = "edt,edt-ft5x06"; |
| 418 | reg = <0x38>; |
| 419 | interrupt-parent = <&gpio1>; |
| 420 | interrupts = <9 IRQ_TYPE_EDGE_FALLING>; |
Daniel Mack | 5ebc384 | 2018-05-23 10:30:12 +0200 | [diff] [blame] | 421 | wakeup-source; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 422 | }; |
| 423 | }; |
| 424 | |
| 425 | &iomuxc { |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 426 | imx6q-nitrogen6-max { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 427 | pinctrl_audmux: audmuxgrp { |
| 428 | fsl,pins = < |
| 429 | MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 |
| 430 | MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 |
| 431 | MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 |
| 432 | MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 |
| 433 | >; |
| 434 | }; |
| 435 | |
| 436 | pinctrl_can1: can1grp { |
| 437 | fsl,pins = < |
| 438 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 |
| 439 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 |
| 440 | >; |
| 441 | }; |
| 442 | |
| 443 | pinctrl_can_xcvr: can-xcvrgrp { |
| 444 | fsl,pins = < |
| 445 | /* Flexcan XCVR enable */ |
| 446 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 |
| 447 | >; |
| 448 | }; |
| 449 | |
| 450 | pinctrl_ecspi1: ecspi1grp { |
| 451 | fsl,pins = < |
| 452 | MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |
| 453 | MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 |
| 454 | MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |
| 455 | MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 |
| 456 | >; |
| 457 | }; |
| 458 | |
| 459 | pinctrl_enet: enetgrp { |
| 460 | fsl,pins = < |
| 461 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 |
| 462 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 |
Uwe Kleine-König | c007b3a | 2016-07-08 23:22:54 +0200 | [diff] [blame] | 463 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 |
| 464 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 |
| 465 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 |
| 466 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 |
| 467 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 |
| 468 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 469 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 |
Uwe Kleine-König | c007b3a | 2016-07-08 23:22:54 +0200 | [diff] [blame] | 470 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 |
| 471 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 |
| 472 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 |
| 473 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 |
| 474 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 |
| 475 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 476 | /* Phy reset */ |
| 477 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 |
| 478 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 |
| 479 | MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 |
| 480 | >; |
| 481 | }; |
| 482 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 483 | pinctrl_gpio_keys: gpio-keysgrp { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 484 | fsl,pins = < |
| 485 | /* Power Button */ |
| 486 | MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 |
| 487 | /* Menu Button */ |
| 488 | MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 |
| 489 | /* Home Button */ |
| 490 | MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 |
| 491 | /* Back Button */ |
| 492 | MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 |
| 493 | /* Volume Up Button */ |
| 494 | MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 |
| 495 | /* Volume Down Button */ |
| 496 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 |
| 497 | >; |
| 498 | }; |
| 499 | |
| 500 | pinctrl_i2c1: i2c1grp { |
| 501 | fsl,pins = < |
| 502 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
| 503 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
| 504 | >; |
| 505 | }; |
| 506 | |
| 507 | pinctrl_i2c2: i2c2grp { |
| 508 | fsl,pins = < |
| 509 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
| 510 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
| 511 | >; |
| 512 | }; |
| 513 | |
| 514 | pinctrl_i2c2mux: i2c2muxgrp { |
| 515 | fsl,pins = < |
| 516 | /* ov5642 camera i2c enable */ |
| 517 | MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 |
| 518 | /* ov5640_mipi camera i2c enable */ |
| 519 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 |
| 520 | >; |
| 521 | }; |
| 522 | |
| 523 | pinctrl_i2c3: i2c3grp { |
| 524 | fsl,pins = < |
| 525 | MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 |
| 526 | MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 |
| 527 | MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 |
| 528 | >; |
| 529 | }; |
| 530 | |
| 531 | pinctrl_i2c3mux: i2c3muxgrp { |
| 532 | fsl,pins = < |
| 533 | /* PCIe I2C enable */ |
| 534 | MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 |
| 535 | >; |
| 536 | }; |
| 537 | |
| 538 | pinctrl_j15: j15grp { |
| 539 | fsl,pins = < |
| 540 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 |
| 541 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 |
| 542 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 |
| 543 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 |
| 544 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 |
| 545 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 |
| 546 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 |
| 547 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 |
| 548 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 |
| 549 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 |
| 550 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 |
| 551 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 |
| 552 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 |
| 553 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 |
| 554 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 |
| 555 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 |
| 556 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 |
| 557 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 |
| 558 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 |
| 559 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 |
| 560 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 |
| 561 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 |
| 562 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 |
| 563 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 |
| 564 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 |
| 565 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 |
| 566 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 |
| 567 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 |
| 568 | >; |
| 569 | }; |
| 570 | |
| 571 | pinctrl_pcie: pciegrp { |
| 572 | fsl,pins = < |
| 573 | /* PCIe reset */ |
| 574 | MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 |
| 575 | >; |
| 576 | }; |
| 577 | |
| 578 | pinctrl_pwm1: pwm1grp { |
| 579 | fsl,pins = < |
| 580 | MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 |
| 581 | >; |
| 582 | }; |
| 583 | |
| 584 | pinctrl_pwm2: pwm2grp { |
| 585 | fsl,pins = < |
| 586 | MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 |
| 587 | >; |
| 588 | }; |
| 589 | |
| 590 | pinctrl_pwm3: pwm3grp { |
| 591 | fsl,pins = < |
| 592 | MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 |
| 593 | >; |
| 594 | }; |
| 595 | |
| 596 | pinctrl_pwm4: pwm4grp { |
| 597 | fsl,pins = < |
| 598 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 |
| 599 | >; |
| 600 | }; |
| 601 | |
| 602 | pinctrl_rv4162: rv4162grp { |
| 603 | fsl,pins = < |
| 604 | MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 |
| 605 | >; |
| 606 | }; |
| 607 | |
| 608 | pinctrl_sgtl5000: sgtl5000grp { |
| 609 | fsl,pins = < |
| 610 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 |
| 611 | MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 |
| 612 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 |
| 613 | >; |
| 614 | }; |
| 615 | |
| 616 | pinctrl_uart1: uart1grp { |
| 617 | fsl,pins = < |
| 618 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 |
| 619 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 |
| 620 | >; |
| 621 | }; |
| 622 | |
| 623 | pinctrl_uart2: uart2grp { |
| 624 | fsl,pins = < |
| 625 | MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 |
| 626 | MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 |
| 627 | >; |
| 628 | }; |
| 629 | |
| 630 | pinctrl_uart5: uart5grp { |
| 631 | fsl,pins = < |
| 632 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 |
| 633 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 |
| 634 | /* RS485 RX Enable: pull up */ |
| 635 | MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 |
| 636 | /* RS485 DEN: pull down */ |
| 637 | MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 |
| 638 | /* RS485/!RS232 Select: pull down (rs232) */ |
| 639 | MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 |
| 640 | /* ON: pull down */ |
| 641 | MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 |
| 642 | >; |
| 643 | }; |
| 644 | |
| 645 | pinctrl_usbh1: usbh1grp { |
| 646 | fsl,pins = < |
| 647 | MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 |
| 648 | >; |
| 649 | }; |
| 650 | |
| 651 | pinctrl_usbotg: usbotggrp { |
| 652 | fsl,pins = < |
| 653 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 |
| 654 | MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 |
| 655 | /* power enable, high active */ |
| 656 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 |
| 657 | >; |
| 658 | }; |
| 659 | |
| 660 | pinctrl_usdhc2: usdhc2grp { |
| 661 | fsl,pins = < |
| 662 | MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| 663 | MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| 664 | MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| 665 | MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| 666 | MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| 667 | MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| 668 | >; |
| 669 | }; |
| 670 | |
| 671 | pinctrl_usdhc3: usdhc3grp { |
| 672 | fsl,pins = < |
| 673 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 674 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 675 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 676 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 677 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 678 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 679 | MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 |
| 680 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 |
| 681 | >; |
| 682 | }; |
| 683 | |
| 684 | pinctrl_usdhc4: usdhc4grp { |
| 685 | fsl,pins = < |
| 686 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 |
| 687 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 |
| 688 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| 689 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| 690 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| 691 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| 692 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 |
| 693 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 |
| 694 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 |
| 695 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 |
| 696 | >; |
| 697 | }; |
| 698 | |
Gary Bisson | a7859df | 2016-11-01 18:10:06 +0100 | [diff] [blame] | 699 | pinctrl_wlan_vmmc: wlan-vmmcgrp { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 700 | fsl,pins = < |
| 701 | MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 |
| 702 | MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 |
| 703 | MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 |
| 704 | MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 |
| 705 | >; |
| 706 | }; |
| 707 | }; |
| 708 | }; |
| 709 | |
| 710 | &ipu1_di0_disp0 { |
| 711 | remote-endpoint = <&lcd_display_in>; |
| 712 | }; |
| 713 | |
| 714 | &ldb { |
| 715 | status = "okay"; |
| 716 | |
| 717 | lvds-channel@0 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 718 | status = "okay"; |
| 719 | |
| 720 | port@4 { |
| 721 | reg = <4>; |
| 722 | |
| 723 | lvds0_out: endpoint { |
| 724 | remote-endpoint = <&panel_in_lvds0>; |
| 725 | }; |
| 726 | }; |
| 727 | }; |
| 728 | |
| 729 | lvds-channel@1 { |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 730 | status = "okay"; |
| 731 | |
| 732 | port@4 { |
| 733 | reg = <4>; |
| 734 | |
| 735 | lvds1_out: endpoint { |
| 736 | remote-endpoint = <&panel_in_lvds1>; |
| 737 | }; |
| 738 | }; |
| 739 | }; |
| 740 | }; |
| 741 | |
| 742 | &pcie { |
| 743 | pinctrl-names = "default"; |
| 744 | pinctrl-0 = <&pinctrl_pcie>; |
| 745 | reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; |
| 746 | status = "okay"; |
| 747 | }; |
| 748 | |
| 749 | &pwm1 { |
Uwe Kleine-König | fa28d82 | 2020-07-10 07:19:37 +0200 | [diff] [blame] | 750 | #pwm-cells = <2>; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 751 | pinctrl-names = "default"; |
| 752 | pinctrl-0 = <&pinctrl_pwm1>; |
| 753 | status = "okay"; |
| 754 | }; |
| 755 | |
| 756 | &pwm2 { |
Uwe Kleine-König | fa28d82 | 2020-07-10 07:19:37 +0200 | [diff] [blame] | 757 | #pwm-cells = <2>; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 758 | pinctrl-names = "default"; |
| 759 | pinctrl-0 = <&pinctrl_pwm2>; |
| 760 | status = "okay"; |
| 761 | }; |
| 762 | |
| 763 | &pwm3 { |
| 764 | pinctrl-names = "default"; |
| 765 | pinctrl-0 = <&pinctrl_pwm3>; |
| 766 | status = "okay"; |
| 767 | }; |
| 768 | |
| 769 | &pwm4 { |
Uwe Kleine-König | fa28d82 | 2020-07-10 07:19:37 +0200 | [diff] [blame] | 770 | #pwm-cells = <2>; |
Gary Bisson | b32e7002 | 2015-09-30 15:46:45 +0200 | [diff] [blame] | 771 | pinctrl-names = "default"; |
| 772 | pinctrl-0 = <&pinctrl_pwm4>; |
| 773 | status = "okay"; |
| 774 | }; |
| 775 | |
| 776 | &ssi1 { |
| 777 | status = "okay"; |
| 778 | }; |
| 779 | |
| 780 | &uart1 { |
| 781 | pinctrl-names = "default"; |
| 782 | pinctrl-0 = <&pinctrl_uart1>; |
| 783 | status = "okay"; |
| 784 | }; |
| 785 | |
| 786 | &uart2 { |
| 787 | pinctrl-names = "default"; |
| 788 | pinctrl-0 = <&pinctrl_uart2>; |
| 789 | status = "okay"; |
| 790 | }; |
| 791 | |
| 792 | &uart5 { |
| 793 | pinctrl-names = "default"; |
| 794 | pinctrl-0 = <&pinctrl_uart5>; |
| 795 | status = "okay"; |
| 796 | }; |
| 797 | |
| 798 | &usbh1 { |
| 799 | vbus-supply = <®_usb_h1_vbus>; |
| 800 | status = "okay"; |
| 801 | }; |
| 802 | |
| 803 | &usbotg { |
| 804 | vbus-supply = <®_usb_otg_vbus>; |
| 805 | pinctrl-names = "default"; |
| 806 | pinctrl-0 = <&pinctrl_usbotg>; |
| 807 | disable-over-current; |
| 808 | status = "okay"; |
| 809 | }; |
| 810 | |
| 811 | &usdhc2 { |
| 812 | pinctrl-names = "default"; |
| 813 | pinctrl-0 = <&pinctrl_usdhc2>; |
| 814 | bus-width = <4>; |
| 815 | non-removable; |
| 816 | vmmc-supply = <®_wlan_vmmc>; |
| 817 | cap-power-off-card; |
| 818 | keep-power-in-suspend; |
| 819 | status = "okay"; |
| 820 | |
| 821 | #address-cells = <1>; |
| 822 | #size-cells = <0>; |
| 823 | wlcore: wlcore@2 { |
| 824 | compatible = "ti,wl1271"; |
| 825 | reg = <2>; |
| 826 | interrupt-parent = <&gpio6>; |
| 827 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; |
| 828 | ref-clock-frequency = <38400000>; |
| 829 | }; |
| 830 | }; |
| 831 | |
| 832 | &usdhc3 { |
| 833 | pinctrl-names = "default"; |
| 834 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 835 | cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; |
| 836 | bus-width = <4>; |
| 837 | vmmc-supply = <®_3p3v>; |
| 838 | status = "okay"; |
| 839 | }; |
| 840 | |
| 841 | &usdhc4 { |
| 842 | pinctrl-names = "default"; |
| 843 | pinctrl-0 = <&pinctrl_usdhc4>; |
| 844 | bus-width = <8>; |
| 845 | non-removable; |
| 846 | vmmc-supply = <®_1p8v>; |
| 847 | keep-power-in-suspend; |
| 848 | status = "okay"; |
| 849 | }; |