Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com) |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/of.h> |
| 13 | #include <linux/irqdomain.h> |
| 14 | #include <linux/irqchip.h> |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 15 | #include <asm/irq.h> |
| 16 | |
Vineet Gupta | 179cf19 | 2017-02-01 09:44:33 -0800 | [diff] [blame] | 17 | #define NR_EXCEPTIONS 16 |
| 18 | |
| 19 | struct bcr_irq_arcv2 { |
| 20 | #ifdef CONFIG_CPU_BIG_ENDIAN |
| 21 | unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; |
| 22 | #else |
| 23 | unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3; |
| 24 | #endif |
| 25 | }; |
Vineet Gupta | fe7b109 | 2017-02-01 10:14:11 -0800 | [diff] [blame] | 26 | |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 27 | /* |
| 28 | * Early Hardware specific Interrupt setup |
| 29 | * -Called very early (start_kernel -> setup_arch -> setup_processor) |
| 30 | * -Platform Independent (must for any ARC Core) |
| 31 | * -Needed for each CPU (hence not foldable into init_IRQ) |
| 32 | */ |
| 33 | void arc_init_IRQ(void) |
| 34 | { |
Yuriy Kolerov | be568e7 | 2017-01-31 14:45:24 +0300 | [diff] [blame] | 35 | unsigned int tmp, irq_prio, i; |
Vineet Gupta | 179cf19 | 2017-02-01 09:44:33 -0800 | [diff] [blame] | 36 | struct bcr_irq_arcv2 irq_bcr; |
Vineet Gupta | dec2b28 | 2016-02-07 12:54:35 +0530 | [diff] [blame] | 37 | |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 38 | struct aux_irq_ctrl { |
| 39 | #ifdef CONFIG_CPU_BIG_ENDIAN |
| 40 | unsigned int res3:18, save_idx_regs:1, res2:1, |
| 41 | save_u_to_u:1, save_lp_regs:1, save_blink:1, |
| 42 | res:4, save_nr_gpr_pairs:5; |
| 43 | #else |
| 44 | unsigned int save_nr_gpr_pairs:5, res:4, |
| 45 | save_blink:1, save_lp_regs:1, save_u_to_u:1, |
| 46 | res2:1, save_idx_regs:1, res3:18; |
| 47 | #endif |
| 48 | } ictrl; |
| 49 | |
| 50 | *(unsigned int *)&ictrl = 0; |
| 51 | |
Vineet Gupta | e494239 | 2018-06-06 10:20:37 -0700 | [diff] [blame] | 52 | #ifndef CONFIG_ARC_IRQ_NO_AUTOSAVE |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 53 | ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ |
| 54 | ictrl.save_blink = 1; |
| 55 | ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ |
| 56 | ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */ |
| 57 | ictrl.save_idx_regs = 1; /* JLI, LDI, EI */ |
Vineet Gupta | e494239 | 2018-06-06 10:20:37 -0700 | [diff] [blame] | 58 | #endif |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 59 | |
| 60 | WRITE_AUX(AUX_IRQ_CTRL, ictrl); |
| 61 | |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 62 | /* |
| 63 | * ARCv2 core intc provides multiple interrupt priorities (upto 16). |
| 64 | * Typical builds though have only two levels (0-high, 1-low) |
| 65 | * Linux by default uses lower prio 1 for most irqs, reserving 0 for |
| 66 | * NMI style interrupts in future (say perf) |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 67 | */ |
Vineet Gupta | dec2b28 | 2016-02-07 12:54:35 +0530 | [diff] [blame] | 68 | |
| 69 | READ_BCR(ARC_REG_IRQ_BCR, irq_bcr); |
| 70 | |
| 71 | irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ |
| 72 | pr_info("archs-intc\t: %d priority levels (default %d)%s\n", |
Vineet Gupta | 107177b1 | 2016-09-30 16:13:28 -0700 | [diff] [blame] | 73 | irq_prio + 1, ARCV2_IRQ_DEF_PRIO, |
Vineet Gupta | dec2b28 | 2016-02-07 12:54:35 +0530 | [diff] [blame] | 74 | irq_bcr.firq ? " FIRQ (not used)":""); |
| 75 | |
Yuriy Kolerov | be568e7 | 2017-01-31 14:45:24 +0300 | [diff] [blame] | 76 | /* |
| 77 | * Set a default priority for all available interrupts to prevent |
| 78 | * switching of register banks if Fast IRQ and multiple register banks |
| 79 | * are supported by CPU. |
Alexey Brodkin | e8206d2 | 2017-08-28 15:03:58 -0700 | [diff] [blame] | 80 | * Also disable private-per-core IRQ lines so faulty external HW won't |
Alexey Brodkin | a8ec3ee | 2017-08-10 18:07:36 +0300 | [diff] [blame] | 81 | * trigger interrupt that kernel is not ready to handle. |
Yuriy Kolerov | be568e7 | 2017-01-31 14:45:24 +0300 | [diff] [blame] | 82 | */ |
| 83 | for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { |
| 84 | write_aux_reg(AUX_IRQ_SELECT, i); |
| 85 | write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); |
Alexey Brodkin | e8206d2 | 2017-08-28 15:03:58 -0700 | [diff] [blame] | 86 | |
| 87 | /* |
| 88 | * Only mask cpu private IRQs here. |
| 89 | * "common" interrupts are masked at IDU, otherwise it would |
| 90 | * need to be unmasked at each cpu, with IPIs |
| 91 | */ |
| 92 | if (i < FIRST_EXT_IRQ) |
| 93 | write_aux_reg(AUX_IRQ_ENABLE, 0); |
Yuriy Kolerov | be568e7 | 2017-01-31 14:45:24 +0300 | [diff] [blame] | 94 | } |
| 95 | |
Vineet Gupta | dec2b28 | 2016-02-07 12:54:35 +0530 | [diff] [blame] | 96 | /* setup status32, don't enable intr yet as kernel doesn't want */ |
Yuriy Kolerov | e98a7bf | 2017-01-31 14:45:21 +0300 | [diff] [blame] | 97 | tmp = read_aux_reg(ARC_REG_STATUS32); |
Vineet Gupta | 107177b1 | 2016-09-30 16:13:28 -0700 | [diff] [blame] | 98 | tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1); |
Vineet Gupta | dec2b28 | 2016-02-07 12:54:35 +0530 | [diff] [blame] | 99 | tmp &= ~STATUS_IE_MASK; |
Yuriy Kolerov | bc0c7ec | 2016-09-12 18:55:03 +0300 | [diff] [blame] | 100 | asm volatile("kflag %0 \n"::"r"(tmp)); |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | static void arcv2_irq_mask(struct irq_data *data) |
| 104 | { |
Yuriy Kolerov | 2163266 | 2016-12-28 11:46:24 +0300 | [diff] [blame] | 105 | write_aux_reg(AUX_IRQ_SELECT, data->hwirq); |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 106 | write_aux_reg(AUX_IRQ_ENABLE, 0); |
| 107 | } |
| 108 | |
| 109 | static void arcv2_irq_unmask(struct irq_data *data) |
| 110 | { |
Yuriy Kolerov | 2163266 | 2016-12-28 11:46:24 +0300 | [diff] [blame] | 111 | write_aux_reg(AUX_IRQ_SELECT, data->hwirq); |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 112 | write_aux_reg(AUX_IRQ_ENABLE, 1); |
| 113 | } |
| 114 | |
| 115 | void arcv2_irq_enable(struct irq_data *data) |
| 116 | { |
| 117 | /* set default priority */ |
Yuriy Kolerov | 2163266 | 2016-12-28 11:46:24 +0300 | [diff] [blame] | 118 | write_aux_reg(AUX_IRQ_SELECT, data->hwirq); |
Vineet Gupta | 107177b1 | 2016-09-30 16:13:28 -0700 | [diff] [blame] | 119 | write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 120 | |
| 121 | /* |
| 122 | * hw auto enables (linux unmask) all by default |
| 123 | * So no need to do IRQ_ENABLE here |
| 124 | * XXX: However OSCI LAN need it |
| 125 | */ |
| 126 | write_aux_reg(AUX_IRQ_ENABLE, 1); |
| 127 | } |
| 128 | |
| 129 | static struct irq_chip arcv2_irq_chip = { |
| 130 | .name = "ARCv2 core Intc", |
| 131 | .irq_mask = arcv2_irq_mask, |
| 132 | .irq_unmask = arcv2_irq_unmask, |
| 133 | .irq_enable = arcv2_irq_enable |
| 134 | }; |
| 135 | |
| 136 | static int arcv2_irq_map(struct irq_domain *d, unsigned int irq, |
| 137 | irq_hw_number_t hw) |
| 138 | { |
Vineet Gupta | 8eb0984 | 2015-12-11 15:54:03 +0530 | [diff] [blame] | 139 | /* |
| 140 | * core intc IRQs [16, 23]: |
| 141 | * Statically assigned always private-per-core (Timers, WDT, IPI, PCT) |
| 142 | */ |
Vineet Gupta | 179cf19 | 2017-02-01 09:44:33 -0800 | [diff] [blame] | 143 | if (hw < FIRST_EXT_IRQ) { |
Vineet Gupta | 8eb0984 | 2015-12-11 15:54:03 +0530 | [diff] [blame] | 144 | /* |
| 145 | * A subsequent request_percpu_irq() fails if percpu_devid is |
| 146 | * not set. That in turns sets NOAUTOEN, meaning each core needs |
| 147 | * to call enable_percpu_irq() |
| 148 | */ |
| 149 | irq_set_percpu_devid(irq); |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 150 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq); |
Vineet Gupta | 8eb0984 | 2015-12-11 15:54:03 +0530 | [diff] [blame] | 151 | } else { |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 152 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq); |
Vineet Gupta | 8eb0984 | 2015-12-11 15:54:03 +0530 | [diff] [blame] | 153 | } |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | static const struct irq_domain_ops arcv2_irq_ops = { |
| 159 | .xlate = irq_domain_xlate_onecell, |
| 160 | .map = arcv2_irq_map, |
| 161 | }; |
| 162 | |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 163 | |
| 164 | static int __init |
| 165 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent) |
| 166 | { |
Vineet Gupta | 1b0ccb8 | 2016-01-01 15:12:54 +0530 | [diff] [blame] | 167 | struct irq_domain *root_domain; |
Vineet Gupta | 179cf19 | 2017-02-01 09:44:33 -0800 | [diff] [blame] | 168 | struct bcr_irq_arcv2 irq_bcr; |
| 169 | unsigned int nr_cpu_irqs; |
| 170 | |
| 171 | READ_BCR(ARC_REG_IRQ_BCR, irq_bcr); |
| 172 | nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS; |
Vineet Gupta | 1b0ccb8 | 2016-01-01 15:12:54 +0530 | [diff] [blame] | 173 | |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 174 | if (parent) |
| 175 | panic("DeviceTree incore intc not a root irq controller\n"); |
| 176 | |
Vineet Gupta | 179cf19 | 2017-02-01 09:44:33 -0800 | [diff] [blame] | 177 | root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL); |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 178 | if (!root_domain) |
| 179 | panic("root irq domain not avail\n"); |
| 180 | |
Vineet Gupta | 1b0ccb8 | 2016-01-01 15:12:54 +0530 | [diff] [blame] | 181 | /* |
| 182 | * Needed for primary domain lookup to succeed |
| 183 | * This is a primary irqchip, and can never have a parent |
| 184 | */ |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 185 | irq_set_default_host(root_domain); |
| 186 | |
Vineet Gupta | d21beff | 2016-01-28 09:40:10 +0530 | [diff] [blame] | 187 | #ifdef CONFIG_SMP |
| 188 | irq_create_mapping(root_domain, IPI_IRQ); |
| 189 | #endif |
| 190 | irq_create_mapping(root_domain, SOFTIRQ_IRQ); |
| 191 | |
Vineet Gupta | 820970a | 2015-03-06 14:08:20 +0530 | [diff] [blame] | 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ); |