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Thomas Gleixner2025cf92019-05-29 07:18:02 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Steffen Trumtrar97259e92014-01-06 10:27:37 -06002/*
3 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
4 *
5 * based on drivers/clk/tegra/clk.h
Steffen Trumtrar97259e92014-01-06 10:27:37 -06006 */
7
8#ifndef __SOCFPGA_CLK_H
9#define __SOCFPGA_CLK_H
10
11#include <linux/clk-provider.h>
Steffen Trumtrar97259e92014-01-06 10:27:37 -060012
13/* Clock Manager offsets */
14#define CLKMGR_CTRL 0x0
15#define CLKMGR_BYPASS 0x4
Dinh Nguyen34d50032015-07-24 22:30:18 -050016#define CLKMGR_DBCTRL 0x10
Steffen Trumtrar97259e92014-01-06 10:27:37 -060017#define CLKMGR_L4SRC 0x70
18#define CLKMGR_PERPLL_SRC 0xAC
19
Dinh Nguyen5611a5b2015-05-19 22:22:41 -050020#define SOCFPGA_MAX_PARENTS 5
Steffen Trumtrar97259e92014-01-06 10:27:37 -060021
Dinh Nguyen5611a5b2015-05-19 22:22:41 -050022#define streq(a, b) (strcmp((a), (b)) == 0)
23#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
24 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
25
Dinh Nguyenb7f81012017-06-08 09:18:39 -050026#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
27 ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
28
Steffen Trumtrar97259e92014-01-06 10:27:37 -060029extern void __iomem *clk_mgr_base_addr;
Dinh Nguyen53433252015-05-19 22:22:42 -050030extern void __iomem *clk_mgr_a10_base_addr;
Steffen Trumtrar97259e92014-01-06 10:27:37 -060031
32void __init socfpga_pll_init(struct device_node *node);
33void __init socfpga_periph_init(struct device_node *node);
34void __init socfpga_gate_init(struct device_node *node);
Dinh Nguyen53433252015-05-19 22:22:42 -050035void socfpga_a10_pll_init(struct device_node *node);
36void socfpga_a10_periph_init(struct device_node *node);
37void socfpga_a10_gate_init(struct device_node *node);
Steffen Trumtrar97259e92014-01-06 10:27:37 -060038
39struct socfpga_pll {
40 struct clk_gate hw;
41};
42
43struct socfpga_gate_clk {
44 struct clk_gate hw;
45 char *parent_name;
46 u32 fixed_div;
47 void __iomem *div_reg;
Dinh Nguyen07afb8d2018-03-21 09:20:12 -050048 void __iomem *bypass_reg;
Dinh Nguyen53433252015-05-19 22:22:42 -050049 struct regmap *sys_mgr_base_addr;
Steffen Trumtrar97259e92014-01-06 10:27:37 -060050 u32 width; /* only valid if div_reg != 0 */
51 u32 shift; /* only valid if div_reg != 0 */
Dinh Nguyen07afb8d2018-03-21 09:20:12 -050052 u32 bypass_shift; /* only valid if bypass_reg != 0 */
Steffen Trumtrar97259e92014-01-06 10:27:37 -060053 u32 clk_phase[2];
54};
55
56struct socfpga_periph_clk {
57 struct clk_gate hw;
58 char *parent_name;
59 u32 fixed_div;
Dinh Nguyen0691bb12014-05-12 12:27:22 -050060 void __iomem *div_reg;
Dinh Nguyen07afb8d2018-03-21 09:20:12 -050061 void __iomem *bypass_reg;
Dinh Nguyen0691bb12014-05-12 12:27:22 -050062 u32 width; /* only valid if div_reg != 0 */
63 u32 shift; /* only valid if div_reg != 0 */
Dinh Nguyen07afb8d2018-03-21 09:20:12 -050064 u32 bypass_shift; /* only valid if bypass_reg != 0 */
Steffen Trumtrar97259e92014-01-06 10:27:37 -060065};
66
67#endif /* SOCFPGA_CLK_H */