blob: 3c9ed412932f6ae87a60794d55f788c70f009dc9 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Romain Perier5762ab72016-12-08 15:58:44 +01002/*
3 * Marvell Armada-3700 SPI controller driver
4 *
5 * Copyright (C) 2016 Marvell Ltd.
6 *
7 * Author: Wilson Ding <dingwei@marvell.com>
8 * Author: Romain Perier <romain.perier@free-electrons.com>
Romain Perier5762ab72016-12-08 15:58:44 +01009 */
10
11#include <linux/clk.h>
12#include <linux/completion.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
Rob Herring749396c2023-07-14 11:49:52 -060020#include <linux/platform_device.h>
Romain Perier5762ab72016-12-08 15:58:44 +010021#include <linux/pinctrl/consumer.h>
22#include <linux/spi/spi.h>
23
24#define DRIVER_NAME "armada_3700_spi"
25
Maxime Chevallierabf3a492018-01-17 17:15:26 +010026#define A3700_SPI_MAX_SPEED_HZ 100000000
27#define A3700_SPI_MAX_PRESCALE 30
Romain Perier5762ab72016-12-08 15:58:44 +010028#define A3700_SPI_TIMEOUT 10
29
30/* SPI Register Offest */
31#define A3700_SPI_IF_CTRL_REG 0x00
32#define A3700_SPI_IF_CFG_REG 0x04
33#define A3700_SPI_DATA_OUT_REG 0x08
34#define A3700_SPI_DATA_IN_REG 0x0C
35#define A3700_SPI_IF_INST_REG 0x10
36#define A3700_SPI_IF_ADDR_REG 0x14
37#define A3700_SPI_IF_RMODE_REG 0x18
38#define A3700_SPI_IF_HDR_CNT_REG 0x1C
39#define A3700_SPI_IF_DIN_CNT_REG 0x20
40#define A3700_SPI_IF_TIME_REG 0x24
41#define A3700_SPI_INT_STAT_REG 0x28
42#define A3700_SPI_INT_MASK_REG 0x2C
43
44/* A3700_SPI_IF_CTRL_REG */
45#define A3700_SPI_EN BIT(16)
46#define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
47#define A3700_SPI_WFIFO_OVERFLOW BIT(11)
48#define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
49#define A3700_SPI_RFIFO_OVERFLOW BIT(9)
50#define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
51#define A3700_SPI_WFIFO_FULL BIT(7)
52#define A3700_SPI_WFIFO_EMPTY BIT(6)
53#define A3700_SPI_RFIFO_FULL BIT(5)
54#define A3700_SPI_RFIFO_EMPTY BIT(4)
55#define A3700_SPI_WFIFO_RDY BIT(3)
56#define A3700_SPI_RFIFO_RDY BIT(2)
57#define A3700_SPI_XFER_RDY BIT(1)
58#define A3700_SPI_XFER_DONE BIT(0)
59
60/* A3700_SPI_IF_CFG_REG */
61#define A3700_SPI_WFIFO_THRS BIT(28)
62#define A3700_SPI_RFIFO_THRS BIT(24)
63#define A3700_SPI_AUTO_CS BIT(20)
64#define A3700_SPI_DMA_RD_EN BIT(18)
65#define A3700_SPI_FIFO_MODE BIT(17)
66#define A3700_SPI_SRST BIT(16)
67#define A3700_SPI_XFER_START BIT(15)
68#define A3700_SPI_XFER_STOP BIT(14)
69#define A3700_SPI_INST_PIN BIT(13)
70#define A3700_SPI_ADDR_PIN BIT(12)
71#define A3700_SPI_DATA_PIN1 BIT(11)
72#define A3700_SPI_DATA_PIN0 BIT(10)
73#define A3700_SPI_FIFO_FLUSH BIT(9)
74#define A3700_SPI_RW_EN BIT(8)
75#define A3700_SPI_CLK_POL BIT(7)
76#define A3700_SPI_CLK_PHA BIT(6)
77#define A3700_SPI_BYTE_LEN BIT(5)
78#define A3700_SPI_CLK_PRESCALE BIT(0)
79#define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
Maxime Chevallier251c2012017-11-27 15:16:32 +010080#define A3700_SPI_CLK_EVEN_OFFS (0x10)
Romain Perier5762ab72016-12-08 15:58:44 +010081
82#define A3700_SPI_WFIFO_THRS_BIT 28
83#define A3700_SPI_RFIFO_THRS_BIT 24
84#define A3700_SPI_FIFO_THRS_MASK 0x7
85
86#define A3700_SPI_DATA_PIN_MASK 0x3
87
88/* A3700_SPI_IF_HDR_CNT_REG */
89#define A3700_SPI_DUMMY_CNT_BIT 12
90#define A3700_SPI_DUMMY_CNT_MASK 0x7
91#define A3700_SPI_RMODE_CNT_BIT 8
92#define A3700_SPI_RMODE_CNT_MASK 0x3
93#define A3700_SPI_ADDR_CNT_BIT 4
94#define A3700_SPI_ADDR_CNT_MASK 0x7
95#define A3700_SPI_INSTR_CNT_BIT 0
96#define A3700_SPI_INSTR_CNT_MASK 0x3
97
98/* A3700_SPI_IF_TIME_REG */
99#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
100
Romain Perier5762ab72016-12-08 15:58:44 +0100101struct a3700_spi {
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800102 struct spi_controller *host;
Romain Perier5762ab72016-12-08 15:58:44 +0100103 void __iomem *base;
104 struct clk *clk;
105 unsigned int irq;
106 unsigned int flags;
107 bool xmit_data;
108 const u8 *tx_buf;
109 u8 *rx_buf;
110 size_t buf_len;
111 u8 byte_len;
112 u32 wait_mask;
113 struct completion done;
Romain Perier5762ab72016-12-08 15:58:44 +0100114};
115
116static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
117{
118 return readl(a3700_spi->base + offset);
119}
120
121static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
122{
123 writel(data, a3700_spi->base + offset);
124}
125
126static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
127{
128 u32 val;
129
130 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
131 val &= ~A3700_SPI_AUTO_CS;
132 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
133}
134
135static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
136{
137 u32 val;
138
139 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
140 val |= (A3700_SPI_EN << cs);
141 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
142}
143
144static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
145 unsigned int cs)
146{
147 u32 val;
148
149 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
150 val &= ~(A3700_SPI_EN << cs);
151 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
152}
153
154static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
Miquel Raynal747e1f62017-09-13 18:21:38 +0200155 unsigned int pin_mode, bool receiving)
Romain Perier5762ab72016-12-08 15:58:44 +0100156{
157 u32 val;
158
159 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
160 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
161 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
162
163 switch (pin_mode) {
Romain Periercfd66932016-12-21 11:10:30 +0100164 case SPI_NBITS_SINGLE:
Romain Perier5762ab72016-12-08 15:58:44 +0100165 break;
Romain Periercfd66932016-12-21 11:10:30 +0100166 case SPI_NBITS_DUAL:
Romain Perier5762ab72016-12-08 15:58:44 +0100167 val |= A3700_SPI_DATA_PIN0;
168 break;
Romain Periercfd66932016-12-21 11:10:30 +0100169 case SPI_NBITS_QUAD:
Romain Perier5762ab72016-12-08 15:58:44 +0100170 val |= A3700_SPI_DATA_PIN1;
Miquel Raynal747e1f62017-09-13 18:21:38 +0200171 /* RX during address reception uses 4-pin */
172 if (receiving)
173 val |= A3700_SPI_ADDR_PIN;
Romain Perier5762ab72016-12-08 15:58:44 +0100174 break;
175 default:
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800176 dev_err(&a3700_spi->host->dev, "wrong pin mode %u", pin_mode);
Romain Perier5762ab72016-12-08 15:58:44 +0100177 return -EINVAL;
178 }
179
180 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
181
182 return 0;
183}
184
Maxime Chevalliera456c932018-01-17 17:15:27 +0100185static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
Romain Perier5762ab72016-12-08 15:58:44 +0100186{
187 u32 val;
188
189 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
Maxime Chevalliera456c932018-01-17 17:15:27 +0100190 if (enable)
191 val |= A3700_SPI_FIFO_MODE;
192 else
193 val &= ~A3700_SPI_FIFO_MODE;
Romain Perier5762ab72016-12-08 15:58:44 +0100194 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
195}
196
197static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
198 unsigned int mode_bits)
199{
200 u32 val;
201
202 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
203
204 if (mode_bits & SPI_CPOL)
205 val |= A3700_SPI_CLK_POL;
206 else
207 val &= ~A3700_SPI_CLK_POL;
208
209 if (mode_bits & SPI_CPHA)
210 val |= A3700_SPI_CLK_PHA;
211 else
212 val &= ~A3700_SPI_CLK_PHA;
213
214 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
215}
216
217static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
Maxime Chevallierdd7aa8d2017-10-10 10:43:18 +0200218 unsigned int speed_hz)
Romain Perier5762ab72016-12-08 15:58:44 +0100219{
220 u32 val;
221 u32 prescale;
222
223 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
224
Maxime Chevallier251c2012017-11-27 15:16:32 +0100225 /* For prescaler values over 15, we can only set it by steps of 2.
226 * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to
227 * 30. We only use this range from 16 to 30.
228 */
229 if (prescale > 15)
230 prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2);
231
Romain Perier5762ab72016-12-08 15:58:44 +0100232 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
233 val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
234
235 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
236 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
237
238 if (prescale <= 2) {
239 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
240 val |= A3700_SPI_CLK_CAPT_EDGE;
241 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
242 }
Romain Perier5762ab72016-12-08 15:58:44 +0100243}
244
245static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
246{
247 u32 val;
248
249 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
250 if (len == 4)
251 val |= A3700_SPI_BYTE_LEN;
252 else
253 val &= ~A3700_SPI_BYTE_LEN;
254 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
255
256 a3700_spi->byte_len = len;
257}
258
259static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
260{
261 int timeout = A3700_SPI_TIMEOUT;
262 u32 val;
263
264 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
265 val |= A3700_SPI_FIFO_FLUSH;
266 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
267
268 while (--timeout) {
269 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
270 if (!(val & A3700_SPI_FIFO_FLUSH))
271 return 0;
272 udelay(1);
273 }
274
275 return -ETIMEDOUT;
276}
277
Jason Yan5b684512020-05-06 14:19:11 +0800278static void a3700_spi_init(struct a3700_spi *a3700_spi)
Romain Perier5762ab72016-12-08 15:58:44 +0100279{
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800280 struct spi_controller *host = a3700_spi->host;
Romain Perier5762ab72016-12-08 15:58:44 +0100281 u32 val;
Jason Yan5b684512020-05-06 14:19:11 +0800282 int i;
Romain Perier5762ab72016-12-08 15:58:44 +0100283
284 /* Reset SPI unit */
285 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
286 val |= A3700_SPI_SRST;
287 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
288
289 udelay(A3700_SPI_TIMEOUT);
290
291 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
292 val &= ~A3700_SPI_SRST;
293 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
294
295 /* Disable AUTO_CS and deactivate all chip-selects */
296 a3700_spi_auto_cs_unset(a3700_spi);
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800297 for (i = 0; i < host->num_chipselect; i++)
Romain Perier5762ab72016-12-08 15:58:44 +0100298 a3700_spi_deactivate_cs(a3700_spi, i);
299
300 /* Enable FIFO mode */
Maxime Chevalliera456c932018-01-17 17:15:27 +0100301 a3700_spi_fifo_mode_set(a3700_spi, true);
Romain Perier5762ab72016-12-08 15:58:44 +0100302
303 /* Set SPI mode */
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800304 a3700_spi_mode_set(a3700_spi, host->mode_bits);
Romain Perier5762ab72016-12-08 15:58:44 +0100305
306 /* Reset counters */
307 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
308 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
309
310 /* Mask the interrupts and clear cause bits */
311 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
312 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
Romain Perier5762ab72016-12-08 15:58:44 +0100313}
314
315static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
316{
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800317 struct spi_controller *host = dev_id;
Romain Perier5762ab72016-12-08 15:58:44 +0100318 struct a3700_spi *a3700_spi;
319 u32 cause;
320
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800321 a3700_spi = spi_controller_get_devdata(host);
Romain Perier5762ab72016-12-08 15:58:44 +0100322
323 /* Get interrupt causes */
324 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
325
326 if (!cause || !(a3700_spi->wait_mask & cause))
327 return IRQ_NONE;
328
329 /* mask and acknowledge the SPI interrupts */
330 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
331 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
332
333 /* Wake up the transfer */
Dan Carpenter0cc059a2016-12-16 12:33:59 +0300334 complete(&a3700_spi->done);
Romain Perier5762ab72016-12-08 15:58:44 +0100335
336 return IRQ_HANDLED;
337}
338
339static bool a3700_spi_wait_completion(struct spi_device *spi)
340{
341 struct a3700_spi *a3700_spi;
342 unsigned int timeout;
343 unsigned int ctrl_reg;
344 unsigned long timeout_jiffies;
345
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800346 a3700_spi = spi_controller_get_devdata(spi->controller);
Romain Perier5762ab72016-12-08 15:58:44 +0100347
348 /* SPI interrupt is edge-triggered, which means an interrupt will
349 * be generated only when detecting a specific status bit changed
350 * from '0' to '1'. So when we start waiting for a interrupt, we
351 * need to check status bit in control reg first, if it is already 1,
352 * then we do not need to wait for interrupt
353 */
354 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
355 if (a3700_spi->wait_mask & ctrl_reg)
356 return true;
357
358 reinit_completion(&a3700_spi->done);
359
360 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
361 a3700_spi->wait_mask);
362
363 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
364 timeout = wait_for_completion_timeout(&a3700_spi->done,
365 timeout_jiffies);
366
367 a3700_spi->wait_mask = 0;
368
369 if (timeout)
370 return true;
371
372 /* there might be the case that right after we checked the
373 * status bits in this routine and before start to wait for
374 * interrupt by wait_for_completion_timeout, the interrupt
375 * happens, to avoid missing it we need to double check
376 * status bits in control reg, if it is already 1, then
377 * consider that we have the interrupt successfully and
378 * return true.
379 */
380 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
381 if (a3700_spi->wait_mask & ctrl_reg)
382 return true;
383
384 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
385
Maxime Chevallier5a866ec2017-10-10 10:43:17 +0200386 /* Timeout was reached */
387 return false;
Romain Perier5762ab72016-12-08 15:58:44 +0100388}
389
390static bool a3700_spi_transfer_wait(struct spi_device *spi,
391 unsigned int bit_mask)
392{
393 struct a3700_spi *a3700_spi;
394
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800395 a3700_spi = spi_controller_get_devdata(spi->controller);
Romain Perier5762ab72016-12-08 15:58:44 +0100396 a3700_spi->wait_mask = bit_mask;
397
398 return a3700_spi_wait_completion(spi);
399}
400
401static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
402 unsigned int bytes)
403{
404 u32 val;
405
406 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
407 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
408 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
409 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
410 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
411 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
412}
413
414static void a3700_spi_transfer_setup(struct spi_device *spi,
Romain Perier85798e152016-12-21 11:10:29 +0100415 struct spi_transfer *xfer)
Romain Perier5762ab72016-12-08 15:58:44 +0100416{
417 struct a3700_spi *a3700_spi;
Romain Perier5762ab72016-12-08 15:58:44 +0100418
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800419 a3700_spi = spi_controller_get_devdata(spi->controller);
Romain Perier5762ab72016-12-08 15:58:44 +0100420
Maxime Chevallierdd7aa8d2017-10-10 10:43:18 +0200421 a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
Romain Perier5762ab72016-12-08 15:58:44 +0100422
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100423 /* Use 4 bytes long transfers. Each transfer method has its way to deal
424 * with the remaining bytes for non 4-bytes aligned transfers.
425 */
426 a3700_spi_bytelen_set(a3700_spi, 4);
Romain Perier5762ab72016-12-08 15:58:44 +0100427
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100428 /* Initialize the working buffers */
429 a3700_spi->tx_buf = xfer->tx_buf;
430 a3700_spi->rx_buf = xfer->rx_buf;
431 a3700_spi->buf_len = xfer->len;
Romain Perier5762ab72016-12-08 15:58:44 +0100432}
433
434static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
435{
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800436 struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller);
Romain Perier5762ab72016-12-08 15:58:44 +0100437
438 if (!enable)
Amit Kumar Mahapatra via Alsa-devel9e264f3f2023-03-10 23:02:03 +0530439 a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0));
Romain Perier5762ab72016-12-08 15:58:44 +0100440 else
Amit Kumar Mahapatra via Alsa-devel9e264f3f2023-03-10 23:02:03 +0530441 a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0));
Romain Perier5762ab72016-12-08 15:58:44 +0100442}
443
444static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
445{
Zachary Zhang6fd6fd62017-09-13 18:21:39 +0200446 unsigned int addr_cnt;
Romain Perier5762ab72016-12-08 15:58:44 +0100447 u32 val = 0;
448
449 /* Clear the header registers */
450 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
451 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
452 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
Zachary Zhang6fd6fd62017-09-13 18:21:39 +0200453 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
Romain Perier5762ab72016-12-08 15:58:44 +0100454
455 /* Set header counters */
456 if (a3700_spi->tx_buf) {
Zachary Zhang6fd6fd62017-09-13 18:21:39 +0200457 /*
458 * when tx data is not 4 bytes aligned, there will be unexpected
459 * bytes out of SPI output register, since it always shifts out
460 * as whole 4 bytes. This might cause incorrect transaction with
461 * some devices. To avoid that, use SPI header count feature to
462 * transfer up to 3 bytes of data first, and then make the rest
463 * of data 4-byte aligned.
464 */
465 addr_cnt = a3700_spi->buf_len % 4;
466 if (addr_cnt) {
467 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK)
468 << A3700_SPI_ADDR_CNT_BIT;
469 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
470
471 /* Update the buffer length to be transferred */
472 a3700_spi->buf_len -= addr_cnt;
473
474 /* transfer 1~3 bytes through address count */
475 val = 0;
476 while (addr_cnt--) {
477 val = (val << 8) | a3700_spi->tx_buf[0];
478 a3700_spi->tx_buf++;
479 }
480 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
Romain Perier5762ab72016-12-08 15:58:44 +0100481 }
Romain Perier5762ab72016-12-08 15:58:44 +0100482 }
Romain Perier5762ab72016-12-08 15:58:44 +0100483}
484
485static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
486{
487 u32 val;
488
489 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
490 return (val & A3700_SPI_WFIFO_FULL);
491}
492
493static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
494{
495 u32 val;
Romain Perier5762ab72016-12-08 15:58:44 +0100496
497 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
Maxime Chevallier162f8de2018-01-24 15:10:47 +0100498 val = *(u32 *)a3700_spi->tx_buf;
Noam66bbf142022-07-26 16:00:37 +0300499 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val));
Zachary Zhang6fd6fd62017-09-13 18:21:39 +0200500 a3700_spi->buf_len -= 4;
501 a3700_spi->tx_buf += 4;
Romain Perier5762ab72016-12-08 15:58:44 +0100502 }
503
504 return 0;
505}
506
507static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
508{
509 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
510
511 return (val & A3700_SPI_RFIFO_EMPTY);
512}
513
514static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
515{
516 u32 val;
517
518 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
519 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
520 if (a3700_spi->buf_len >= 4) {
Noam66bbf142022-07-26 16:00:37 +0300521 val = le32_to_cpu(val);
Maxime Chevallier162f8de2018-01-24 15:10:47 +0100522 memcpy(a3700_spi->rx_buf, &val, 4);
Romain Perier5762ab72016-12-08 15:58:44 +0100523
524 a3700_spi->buf_len -= 4;
525 a3700_spi->rx_buf += 4;
526 } else {
527 /*
528 * When remain bytes is not larger than 4, we should
529 * avoid memory overwriting and just write the left rx
530 * buffer bytes.
531 */
532 while (a3700_spi->buf_len) {
533 *a3700_spi->rx_buf = val & 0xff;
534 val >>= 8;
535
536 a3700_spi->buf_len--;
537 a3700_spi->rx_buf++;
538 }
539 }
540 }
541
542 return 0;
543}
544
545static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
546{
547 int timeout = A3700_SPI_TIMEOUT;
548 u32 val;
549
550 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
551 val |= A3700_SPI_XFER_STOP;
552 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
553
554 while (--timeout) {
555 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
556 if (!(val & A3700_SPI_XFER_START))
557 break;
558 udelay(1);
559 }
560
561 a3700_spi_fifo_flush(a3700_spi);
562
563 val &= ~A3700_SPI_XFER_STOP;
564 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
565}
566
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800567static int a3700_spi_prepare_message(struct spi_controller *host,
Romain Perier5762ab72016-12-08 15:58:44 +0100568 struct spi_message *message)
569{
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800570 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
Romain Perier5762ab72016-12-08 15:58:44 +0100571 struct spi_device *spi = message->spi;
572 int ret;
573
574 ret = clk_enable(a3700_spi->clk);
575 if (ret) {
576 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret);
577 return ret;
578 }
579
580 /* Flush the FIFOs */
581 ret = a3700_spi_fifo_flush(a3700_spi);
582 if (ret)
583 return ret;
584
Maxime Chevallierdd7aa8d2017-10-10 10:43:18 +0200585 a3700_spi_mode_set(a3700_spi, spi->mode);
586
Romain Perier5762ab72016-12-08 15:58:44 +0100587 return 0;
588}
589
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800590static int a3700_spi_transfer_one_fifo(struct spi_controller *host,
Romain Perier5762ab72016-12-08 15:58:44 +0100591 struct spi_device *spi,
592 struct spi_transfer *xfer)
593{
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800594 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
Romain Perier5762ab72016-12-08 15:58:44 +0100595 int ret = 0, timeout = A3700_SPI_TIMEOUT;
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100596 unsigned int nbits = 0, byte_len;
Romain Perier5762ab72016-12-08 15:58:44 +0100597 u32 val;
598
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100599 /* Make sure we use FIFO mode */
600 a3700_spi_fifo_mode_set(a3700_spi, true);
Romain Perier5762ab72016-12-08 15:58:44 +0100601
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100602 /* Configure FIFO thresholds */
603 byte_len = xfer->bits_per_word >> 3;
604 a3700_spi_fifo_thres_set(a3700_spi, byte_len);
Romain Perier5762ab72016-12-08 15:58:44 +0100605
Romain Perier5762ab72016-12-08 15:58:44 +0100606 if (xfer->tx_buf)
607 nbits = xfer->tx_nbits;
608 else if (xfer->rx_buf)
609 nbits = xfer->rx_nbits;
610
Miquel Raynal747e1f62017-09-13 18:21:38 +0200611 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
Romain Perier5762ab72016-12-08 15:58:44 +0100612
Zachary Zhang6fd6fd62017-09-13 18:21:39 +0200613 /* Flush the FIFOs */
614 a3700_spi_fifo_flush(a3700_spi);
615
616 /* Transfer first bytes of data when buffer is not 4-byte aligned */
617 a3700_spi_header_set(a3700_spi);
618
Romain Perier5762ab72016-12-08 15:58:44 +0100619 if (xfer->rx_buf) {
Maxime Chevallier44a5f422018-01-17 17:15:25 +0100620 /* Clear WFIFO, since it's last 2 bytes are shifted out during
621 * a read operation
622 */
623 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
624
Romain Perier5762ab72016-12-08 15:58:44 +0100625 /* Set read data length */
626 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
627 a3700_spi->buf_len);
628 /* Start READ transfer */
629 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
630 val &= ~A3700_SPI_RW_EN;
631 val |= A3700_SPI_XFER_START;
632 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
633 } else if (xfer->tx_buf) {
634 /* Start Write transfer */
635 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
636 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
637 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
638
639 /*
640 * If there are data to be written to the SPI device, xmit_data
641 * flag is set true; otherwise the instruction in SPI_INSTR does
642 * not require data to be written to the SPI device, then
643 * xmit_data flag is set false.
644 */
645 a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
646 }
647
648 while (a3700_spi->buf_len) {
649 if (a3700_spi->tx_buf) {
650 /* Wait wfifo ready */
651 if (!a3700_spi_transfer_wait(spi,
652 A3700_SPI_WFIFO_RDY)) {
653 dev_err(&spi->dev,
654 "wait wfifo ready timed out\n");
655 ret = -ETIMEDOUT;
656 goto error;
657 }
658 /* Fill up the wfifo */
659 ret = a3700_spi_fifo_write(a3700_spi);
660 if (ret)
661 goto error;
662 } else if (a3700_spi->rx_buf) {
663 /* Wait rfifo ready */
664 if (!a3700_spi_transfer_wait(spi,
665 A3700_SPI_RFIFO_RDY)) {
666 dev_err(&spi->dev,
667 "wait rfifo ready timed out\n");
668 ret = -ETIMEDOUT;
669 goto error;
670 }
671 /* Drain out the rfifo */
672 ret = a3700_spi_fifo_read(a3700_spi);
673 if (ret)
674 goto error;
675 }
676 }
677
678 /*
679 * Stop a write transfer in fifo mode:
680 * - wait all the bytes in wfifo to be shifted out
681 * - set XFER_STOP bit
682 * - wait XFER_START bit clear
683 * - clear XFER_STOP bit
684 * Stop a read transfer in fifo mode:
685 * - the hardware is to reset the XFER_START bit
686 * after the number of bytes indicated in DIN_CNT
687 * register
688 * - just wait XFER_START bit clear
689 */
690 if (a3700_spi->tx_buf) {
691 if (a3700_spi->xmit_data) {
692 /*
693 * If there are data written to the SPI device, wait
694 * until SPI_WFIFO_EMPTY is 1 to wait for all data to
695 * transfer out of write FIFO.
696 */
697 if (!a3700_spi_transfer_wait(spi,
698 A3700_SPI_WFIFO_EMPTY)) {
699 dev_err(&spi->dev, "wait wfifo empty timed out\n");
700 return -ETIMEDOUT;
701 }
Zachary Zhang6fd6fd62017-09-13 18:21:39 +0200702 }
703
704 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
705 dev_err(&spi->dev, "wait xfer ready timed out\n");
706 return -ETIMEDOUT;
Romain Perier5762ab72016-12-08 15:58:44 +0100707 }
708
709 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
710 val |= A3700_SPI_XFER_STOP;
711 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
712 }
713
714 while (--timeout) {
715 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
716 if (!(val & A3700_SPI_XFER_START))
717 break;
718 udelay(1);
719 }
720
721 if (timeout == 0) {
722 dev_err(&spi->dev, "wait transfer start clear timed out\n");
723 ret = -ETIMEDOUT;
724 goto error;
725 }
726
727 val &= ~A3700_SPI_XFER_STOP;
728 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
729 goto out;
730
731error:
732 a3700_spi_transfer_abort_fifo(a3700_spi);
733out:
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800734 spi_finalize_current_transfer(host);
Romain Perier5762ab72016-12-08 15:58:44 +0100735
736 return ret;
737}
738
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800739static int a3700_spi_transfer_one_full_duplex(struct spi_controller *host,
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100740 struct spi_device *spi,
741 struct spi_transfer *xfer)
742{
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800743 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
Maxime Chevallier34b1fca2018-01-24 15:10:48 +0100744 u32 val;
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100745
746 /* Disable FIFO mode */
747 a3700_spi_fifo_mode_set(a3700_spi, false);
748
749 while (a3700_spi->buf_len) {
750
751 /* When we have less than 4 bytes to transfer, switch to 1 byte
752 * mode. This is reset after each transfer
753 */
754 if (a3700_spi->buf_len < 4)
755 a3700_spi_bytelen_set(a3700_spi, 1);
756
757 if (a3700_spi->byte_len == 1)
Maxime Chevallier34b1fca2018-01-24 15:10:48 +0100758 val = *a3700_spi->tx_buf;
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100759 else
Maxime Chevallier34b1fca2018-01-24 15:10:48 +0100760 val = *(u32 *)a3700_spi->tx_buf;
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100761
Maxime Chevallier34b1fca2018-01-24 15:10:48 +0100762 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100763
764 /* Wait for all the data to be shifted in / out */
765 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
766 A3700_SPI_XFER_DONE))
767 cpu_relax();
768
Maxime Chevallier34b1fca2018-01-24 15:10:48 +0100769 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100770
Maxime Chevallier34b1fca2018-01-24 15:10:48 +0100771 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100772
773 a3700_spi->buf_len -= a3700_spi->byte_len;
774 a3700_spi->tx_buf += a3700_spi->byte_len;
775 a3700_spi->rx_buf += a3700_spi->byte_len;
776
777 }
778
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800779 spi_finalize_current_transfer(host);
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100780
781 return 0;
782}
783
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800784static int a3700_spi_transfer_one(struct spi_controller *host,
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100785 struct spi_device *spi,
786 struct spi_transfer *xfer)
787{
788 a3700_spi_transfer_setup(spi, xfer);
789
790 if (xfer->tx_buf && xfer->rx_buf)
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800791 return a3700_spi_transfer_one_full_duplex(host, spi, xfer);
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100792
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800793 return a3700_spi_transfer_one_fifo(host, spi, xfer);
Maxime Chevallierf68a7dc2018-01-17 17:15:28 +0100794}
795
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800796static int a3700_spi_unprepare_message(struct spi_controller *host,
Romain Perier5762ab72016-12-08 15:58:44 +0100797 struct spi_message *message)
798{
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800799 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
Romain Perier5762ab72016-12-08 15:58:44 +0100800
801 clk_disable(a3700_spi->clk);
802
803 return 0;
804}
805
806static const struct of_device_id a3700_spi_dt_ids[] = {
807 { .compatible = "marvell,armada-3700-spi", .data = NULL },
808 {},
809};
810
811MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids);
812
813static int a3700_spi_probe(struct platform_device *pdev)
814{
815 struct device *dev = &pdev->dev;
816 struct device_node *of_node = dev->of_node;
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800817 struct spi_controller *host;
Romain Perier5762ab72016-12-08 15:58:44 +0100818 struct a3700_spi *spi;
819 u32 num_cs = 0;
Colin Ian Kingf6f00832016-12-13 10:28:12 +0000820 int irq, ret = 0;
Romain Perier5762ab72016-12-08 15:58:44 +0100821
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800822 host = spi_alloc_host(dev, sizeof(*spi));
823 if (!host) {
824 dev_err(dev, "host allocation failed\n");
Romain Perier5762ab72016-12-08 15:58:44 +0100825 ret = -ENOMEM;
826 goto out;
827 }
828
829 if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
830 dev_err(dev, "could not find num-cs\n");
831 ret = -ENXIO;
832 goto error;
833 }
834
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800835 host->bus_num = pdev->id;
836 host->dev.of_node = of_node;
837 host->mode_bits = SPI_MODE_3;
838 host->num_chipselect = num_cs;
839 host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
840 host->prepare_message = a3700_spi_prepare_message;
841 host->transfer_one = a3700_spi_transfer_one;
842 host->unprepare_message = a3700_spi_unprepare_message;
843 host->set_cs = a3700_spi_set_cs;
844 host->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL |
Romain Perier5762ab72016-12-08 15:58:44 +0100845 SPI_RX_QUAD | SPI_TX_QUAD);
846
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800847 platform_set_drvdata(pdev, host);
Romain Perier5762ab72016-12-08 15:58:44 +0100848
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800849 spi = spi_controller_get_devdata(host);
Romain Perier5762ab72016-12-08 15:58:44 +0100850
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800851 spi->host = host;
Romain Perier5762ab72016-12-08 15:58:44 +0100852
YueHaibing084fae22019-09-04 21:58:44 +0800853 spi->base = devm_platform_ioremap_resource(pdev, 0);
Romain Perier5762ab72016-12-08 15:58:44 +0100854 if (IS_ERR(spi->base)) {
855 ret = PTR_ERR(spi->base);
856 goto error;
857 }
858
Colin Ian Kingf6f00832016-12-13 10:28:12 +0000859 irq = platform_get_irq(pdev, 0);
860 if (irq < 0) {
Romain Perier5762ab72016-12-08 15:58:44 +0100861 ret = -ENXIO;
862 goto error;
863 }
Colin Ian Kingf6f00832016-12-13 10:28:12 +0000864 spi->irq = irq;
Romain Perier5762ab72016-12-08 15:58:44 +0100865
866 init_completion(&spi->done);
867
Li Zetaof918b3a2023-08-23 21:39:15 +0800868 spi->clk = devm_clk_get_prepared(dev, NULL);
Romain Perier5762ab72016-12-08 15:58:44 +0100869 if (IS_ERR(spi->clk)) {
870 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
871 goto error;
872 }
873
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800874 host->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ,
Maxime Chevallierabf3a492018-01-17 17:15:26 +0100875 clk_get_rate(spi->clk));
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800876 host->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk),
Maxime Chevallierabf3a492018-01-17 17:15:26 +0100877 A3700_SPI_MAX_PRESCALE);
878
Jason Yan5b684512020-05-06 14:19:11 +0800879 a3700_spi_init(spi);
Romain Perier5762ab72016-12-08 15:58:44 +0100880
881 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800882 dev_name(dev), host);
Romain Perier5762ab72016-12-08 15:58:44 +0100883 if (ret) {
884 dev_err(dev, "could not request IRQ: %d\n", ret);
Li Zetaof918b3a2023-08-23 21:39:15 +0800885 goto error;
Romain Perier5762ab72016-12-08 15:58:44 +0100886 }
887
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800888 ret = devm_spi_register_controller(dev, host);
Romain Perier5762ab72016-12-08 15:58:44 +0100889 if (ret) {
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800890 dev_err(dev, "Failed to register host\n");
Li Zetaof918b3a2023-08-23 21:39:15 +0800891 goto error;
Romain Perier5762ab72016-12-08 15:58:44 +0100892 }
893
894 return 0;
895
Romain Perier5762ab72016-12-08 15:58:44 +0100896error:
Yang Yingliang90ce7e72022-12-30 17:28:05 +0800897 spi_controller_put(host);
Romain Perier5762ab72016-12-08 15:58:44 +0100898out:
899 return ret;
900}
901
Romain Perier5762ab72016-12-08 15:58:44 +0100902static struct platform_driver a3700_spi_driver = {
903 .driver = {
904 .name = DRIVER_NAME,
Romain Perier5762ab72016-12-08 15:58:44 +0100905 .of_match_table = of_match_ptr(a3700_spi_dt_ids),
906 },
907 .probe = a3700_spi_probe,
Romain Perier5762ab72016-12-08 15:58:44 +0100908};
909
910module_platform_driver(a3700_spi_driver);
911
912MODULE_DESCRIPTION("Armada-3700 SPI driver");
913MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
914MODULE_LICENSE("GPL");
915MODULE_ALIAS("platform:" DRIVER_NAME);