blob: acb99eff99394f406ae013cc860f5048ac496df1 [file] [log] [blame]
Thomas Gleixner9c92ab62019-05-29 07:17:56 -07001// SPDX-License-Identifier: GPL-2.0-only
Erik Gilling3c92db92010-03-15 19:40:06 -07002/*
3 * arch/arm/mach-tegra/gpio.c
4 *
5 * Copyright (c) 2010 Google, Inc
Linus Walleij11da9052019-02-19 21:32:02 +01006 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
Erik Gilling3c92db92010-03-15 19:40:06 -07007 *
8 * Author:
9 * Erik Gilling <konkers@google.com>
Erik Gilling3c92db92010-03-15 19:40:06 -070010 */
11
Thierry Reding641d0342013-01-21 11:09:01 +010012#include <linux/err.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070013#include <linux/init.h>
14#include <linux/irq.h>
Colin Cross2e47b8b2010-04-07 12:59:42 -070015#include <linux/interrupt.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070016#include <linux/io.h>
Linus Walleij21041da2018-08-06 17:38:33 +020017#include <linux/gpio/driver.h>
Stephen Warren5c1e2c92012-03-16 17:35:08 -060018#include <linux/of_device.h>
Stephen Warren88d89512011-10-11 16:16:14 -060019#include <linux/platform_device.h>
20#include <linux/module.h>
Stephen Warren6f74dc92012-01-04 08:39:37 +000021#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000022#include <linux/irqchip/chained_irq.h>
Stephen Warren3e215d02012-02-18 01:04:55 -070023#include <linux/pinctrl/consumer.h>
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053024#include <linux/pm.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070025
Erik Gilling3c92db92010-03-15 19:40:06 -070026#define GPIO_BANK(x) ((x) >> 5)
27#define GPIO_PORT(x) (((x) >> 3) & 0x3)
28#define GPIO_BIT(x) ((x) & 0x7)
29
Laxman Dewanganb546be02016-04-25 16:08:33 +053030#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
Stephen Warren5c1e2c92012-03-16 17:35:08 -060031 GPIO_PORT(x) * 4)
Erik Gilling3c92db92010-03-15 19:40:06 -070032
Laxman Dewanganb546be02016-04-25 16:08:33 +053033#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
34#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
35#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
36#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
37#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
38#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
39#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
40#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
Laxman Dewangan3737de422016-04-25 16:08:34 +053041#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
42
Erik Gilling3c92db92010-03-15 19:40:06 -070043
Laxman Dewanganb546be02016-04-25 16:08:33 +053044#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
45#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
46#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
Laxman Dewangan3737de422016-04-25 16:08:34 +053047#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
Laxman Dewanganb546be02016-04-25 16:08:33 +053048#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
49#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
50#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
Erik Gilling3c92db92010-03-15 19:40:06 -070051
52#define GPIO_INT_LVL_MASK 0x010101
53#define GPIO_INT_LVL_EDGE_RISING 0x000101
54#define GPIO_INT_LVL_EDGE_FALLING 0x000100
55#define GPIO_INT_LVL_EDGE_BOTH 0x010100
56#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
57#define GPIO_INT_LVL_LEVEL_LOW 0x000000
58
Laxman Dewanganb546be02016-04-25 16:08:33 +053059struct tegra_gpio_info;
60
Erik Gilling3c92db92010-03-15 19:40:06 -070061struct tegra_gpio_bank {
Thierry Reding539b7a32017-07-24 16:55:08 +020062 unsigned int bank;
63 unsigned int irq;
Erik Gilling3c92db92010-03-15 19:40:06 -070064 spinlock_t lvl_lock[4];
Laxman Dewangan3737de422016-04-25 16:08:34 +053065 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053066#ifdef CONFIG_PM_SLEEP
Colin Cross2e47b8b2010-04-07 12:59:42 -070067 u32 cnf[4];
68 u32 out[4];
69 u32 oe[4];
70 u32 int_enb[4];
71 u32 int_lvl[4];
Joseph Lo203f31c2013-04-03 19:31:44 +080072 u32 wake_enb[4];
Laxman Dewangan3737de422016-04-25 16:08:34 +053073 u32 dbc_enb[4];
Colin Cross2e47b8b2010-04-07 12:59:42 -070074#endif
Laxman Dewangan3737de422016-04-25 16:08:34 +053075 u32 dbc_cnt[4];
Laxman Dewanganb546be02016-04-25 16:08:33 +053076 struct tegra_gpio_info *tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -070077};
78
Laxman Dewangan171b92c2016-04-25 16:08:31 +053079struct tegra_gpio_soc_config {
Laxman Dewangan3737de422016-04-25 16:08:34 +053080 bool debounce_supported;
Laxman Dewangan171b92c2016-04-25 16:08:31 +053081 u32 bank_stride;
82 u32 upper_offset;
83};
84
Laxman Dewanganb546be02016-04-25 16:08:33 +053085struct tegra_gpio_info {
86 struct device *dev;
87 void __iomem *regs;
88 struct irq_domain *irq_domain;
89 struct tegra_gpio_bank *bank_info;
90 const struct tegra_gpio_soc_config *soc;
91 struct gpio_chip gc;
92 struct irq_chip ic;
Laxman Dewanganb546be02016-04-25 16:08:33 +053093 u32 bank_count;
94};
Stephen Warren88d89512011-10-11 16:16:14 -060095
Laxman Dewanganb546be02016-04-25 16:08:33 +053096static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
97 u32 val, u32 reg)
Stephen Warren88d89512011-10-11 16:16:14 -060098{
Dmitry Osipenkofc782e42019-12-15 21:30:45 +030099 writel_relaxed(val, tgi->regs + reg);
Stephen Warren88d89512011-10-11 16:16:14 -0600100}
101
Laxman Dewanganb546be02016-04-25 16:08:33 +0530102static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
Stephen Warren88d89512011-10-11 16:16:14 -0600103{
Dmitry Osipenkofc782e42019-12-15 21:30:45 +0300104 return readl_relaxed(tgi->regs + reg);
Stephen Warren88d89512011-10-11 16:16:14 -0600105}
Erik Gilling3c92db92010-03-15 19:40:06 -0700106
Thierry Reding539b7a32017-07-24 16:55:08 +0200107static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
108 unsigned int bit)
Erik Gilling3c92db92010-03-15 19:40:06 -0700109{
110 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
111}
112
Laxman Dewanganb546be02016-04-25 16:08:33 +0530113static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
Thierry Reding539b7a32017-07-24 16:55:08 +0200114 unsigned int gpio, u32 value)
Erik Gilling3c92db92010-03-15 19:40:06 -0700115{
116 u32 val;
117
118 val = 0x100 << GPIO_BIT(gpio);
119 if (value)
120 val |= 1 << GPIO_BIT(gpio);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530121 tegra_gpio_writel(tgi, val, reg);
Erik Gilling3c92db92010-03-15 19:40:06 -0700122}
123
Thierry Reding539b7a32017-07-24 16:55:08 +0200124static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700125{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530126 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
Erik Gilling3c92db92010-03-15 19:40:06 -0700127}
128
Thierry Reding539b7a32017-07-24 16:55:08 +0200129static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700130{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530131 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
Erik Gilling3c92db92010-03-15 19:40:06 -0700132}
133
Thierry Reding4bc17862017-07-24 16:55:07 +0200134static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700135{
Linus Walleij11da9052019-02-19 21:32:02 +0100136 return pinctrl_gpio_request(chip->base + offset);
Stephen Warren3e215d02012-02-18 01:04:55 -0700137}
138
Thierry Reding4bc17862017-07-24 16:55:07 +0200139static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700140{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530141 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
142
Linus Walleij11da9052019-02-19 21:32:02 +0100143 pinctrl_gpio_free(chip->base + offset);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530144 tegra_gpio_disable(tgi, offset);
Stephen Warren3e215d02012-02-18 01:04:55 -0700145}
146
Thierry Reding4bc17862017-07-24 16:55:07 +0200147static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
148 int value)
Erik Gilling3c92db92010-03-15 19:40:06 -0700149{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530150 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
151
152 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
Erik Gilling3c92db92010-03-15 19:40:06 -0700153}
154
Thierry Reding4bc17862017-07-24 16:55:07 +0200155static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
Erik Gilling3c92db92010-03-15 19:40:06 -0700156{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530157 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Thierry Reding539b7a32017-07-24 16:55:08 +0200158 unsigned int bval = BIT(GPIO_BIT(offset));
Laxman Dewangan195812e2012-11-09 11:34:20 +0530159
Laxman Dewanganb546be02016-04-25 16:08:33 +0530160 /* If gpio is in output mode then read from the out value */
161 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
162 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
163
164 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
Erik Gilling3c92db92010-03-15 19:40:06 -0700165}
166
Thierry Reding4bc17862017-07-24 16:55:07 +0200167static int tegra_gpio_direction_input(struct gpio_chip *chip,
168 unsigned int offset)
Erik Gilling3c92db92010-03-15 19:40:06 -0700169{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530170 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Linus Walleij11da9052019-02-19 21:32:02 +0100171 int ret;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530172
173 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
174 tegra_gpio_enable(tgi, offset);
Linus Walleij11da9052019-02-19 21:32:02 +0100175
176 ret = pinctrl_gpio_direction_input(chip->base + offset);
177 if (ret < 0)
178 dev_err(tgi->dev,
179 "Failed to set pinctrl input direction of GPIO %d: %d",
180 chip->base + offset, ret);
181
182 return ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700183}
184
Thierry Reding4bc17862017-07-24 16:55:07 +0200185static int tegra_gpio_direction_output(struct gpio_chip *chip,
186 unsigned int offset,
187 int value)
Erik Gilling3c92db92010-03-15 19:40:06 -0700188{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Linus Walleij11da9052019-02-19 21:32:02 +0100190 int ret;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530191
Erik Gilling3c92db92010-03-15 19:40:06 -0700192 tegra_gpio_set(chip, offset, value);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530193 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
194 tegra_gpio_enable(tgi, offset);
Linus Walleij11da9052019-02-19 21:32:02 +0100195
196 ret = pinctrl_gpio_direction_output(chip->base + offset);
197 if (ret < 0)
198 dev_err(tgi->dev,
199 "Failed to set pinctrl output direction of GPIO %d: %d",
200 chip->base + offset, ret);
201
202 return ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700203}
204
Thierry Reding4bc17862017-07-24 16:55:07 +0200205static int tegra_gpio_get_direction(struct gpio_chip *chip,
206 unsigned int offset)
Laxman Dewanganf002d072016-04-29 21:55:23 +0530207{
208 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
209 u32 pin_mask = BIT(GPIO_BIT(offset));
210 u32 cnf, oe;
211
212 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
213 if (!(cnf & pin_mask))
214 return -EINVAL;
215
216 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
217
Matti Vaittinene42615e2019-11-06 10:54:12 +0200218 if (oe & pin_mask)
219 return GPIO_LINE_DIRECTION_OUT;
220
221 return GPIO_LINE_DIRECTION_IN;
Laxman Dewanganf002d072016-04-29 21:55:23 +0530222}
223
Laxman Dewangan3737de422016-04-25 16:08:34 +0530224static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
225 unsigned int debounce)
226{
227 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
228 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
229 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
230 unsigned long flags;
Thierry Reding539b7a32017-07-24 16:55:08 +0200231 unsigned int port;
Laxman Dewangan3737de422016-04-25 16:08:34 +0530232
233 if (!debounce_ms) {
234 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
235 offset, 0);
236 return 0;
237 }
238
239 debounce_ms = min(debounce_ms, 255U);
240 port = GPIO_PORT(offset);
241
242 /* There is only one debounce count register per port and hence
243 * set the maximum of current and requested debounce time.
244 */
245 spin_lock_irqsave(&bank->dbc_lock[port], flags);
246 if (bank->dbc_cnt[port] < debounce_ms) {
247 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
248 bank->dbc_cnt[port] = debounce_ms;
249 }
250 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
251
252 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
253
254 return 0;
255}
256
Mika Westerberg2956b5d2017-01-23 15:34:34 +0300257static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
258 unsigned long config)
259{
260 u32 debounce;
261
262 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
263 return -ENOTSUPP;
264
265 debounce = pinconf_to_config_argument(config);
266 return tegra_gpio_set_debounce(chip, offset, debounce);
267}
268
Thierry Reding4bc17862017-07-24 16:55:07 +0200269static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
Stephen Warren438a99c2011-08-23 00:39:56 +0100270{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530271 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Erik Gilling3c92db92010-03-15 19:40:06 -0700272
Laxman Dewanganb546be02016-04-25 16:08:33 +0530273 return irq_find_mapping(tgi->irq_domain, offset);
274}
Erik Gilling3c92db92010-03-15 19:40:06 -0700275
Lennert Buytenhek37337a8d2010-11-29 11:14:46 +0100276static void tegra_gpio_irq_ack(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700277{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530278 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
279 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200280 unsigned int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700281
Laxman Dewanganb546be02016-04-25 16:08:33 +0530282 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700283}
284
Lennert Buytenhek37337a8d2010-11-29 11:14:46 +0100285static void tegra_gpio_irq_mask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700286{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530287 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
288 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200289 unsigned int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700290
Laxman Dewanganb546be02016-04-25 16:08:33 +0530291 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
Erik Gilling3c92db92010-03-15 19:40:06 -0700292}
293
Lennert Buytenhek37337a8d2010-11-29 11:14:46 +0100294static void tegra_gpio_irq_unmask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700295{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530296 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
297 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200298 unsigned int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700299
Laxman Dewanganb546be02016-04-25 16:08:33 +0530300 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
Erik Gilling3c92db92010-03-15 19:40:06 -0700301}
302
Lennert Buytenhek37337a8d2010-11-29 11:14:46 +0100303static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
Erik Gilling3c92db92010-03-15 19:40:06 -0700304{
Thierry Reding539b7a32017-07-24 16:55:08 +0200305 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
Lennert Buytenhek37337a8d2010-11-29 11:14:46 +0100306 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530307 struct tegra_gpio_info *tgi = bank->tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700308 unsigned long flags;
Thierry Reding539b7a32017-07-24 16:55:08 +0200309 u32 val;
Stephen Warrendf231f22013-10-16 13:25:33 -0600310 int ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700311
312 switch (type & IRQ_TYPE_SENSE_MASK) {
313 case IRQ_TYPE_EDGE_RISING:
314 lvl_type = GPIO_INT_LVL_EDGE_RISING;
315 break;
316
317 case IRQ_TYPE_EDGE_FALLING:
318 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
319 break;
320
321 case IRQ_TYPE_EDGE_BOTH:
322 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
323 break;
324
325 case IRQ_TYPE_LEVEL_HIGH:
326 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
327 break;
328
329 case IRQ_TYPE_LEVEL_LOW:
330 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
331 break;
332
333 default:
334 return -EINVAL;
335 }
336
337 spin_lock_irqsave(&bank->lvl_lock[port], flags);
338
Laxman Dewanganb546be02016-04-25 16:08:33 +0530339 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700340 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
341 val |= lvl_type << GPIO_BIT(gpio);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530342 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700343
344 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
345
Laxman Dewanganb546be02016-04-25 16:08:33 +0530346 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
347 tegra_gpio_enable(tgi, gpio);
Stephen Warrend9411362012-03-19 10:31:58 -0600348
Dmitry Osipenkof78709a2018-07-17 19:10:38 +0300349 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
350 if (ret) {
351 dev_err(tgi->dev,
352 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
353 tegra_gpio_disable(tgi, gpio);
354 return ret;
355 }
356
Erik Gilling3c92db92010-03-15 19:40:06 -0700357 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200358 irq_set_handler_locked(d, handle_level_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700359 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200360 irq_set_handler_locked(d, handle_edge_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700361
362 return 0;
363}
364
Stephen Warrendf231f22013-10-16 13:25:33 -0600365static void tegra_gpio_irq_shutdown(struct irq_data *d)
366{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530367 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
368 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200369 unsigned int gpio = d->hwirq;
Stephen Warrendf231f22013-10-16 13:25:33 -0600370
Laxman Dewanganb546be02016-04-25 16:08:33 +0530371 gpiochip_unlock_as_irq(&tgi->gc, gpio);
Stephen Warrendf231f22013-10-16 13:25:33 -0600372}
373
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200374static void tegra_gpio_irq_handler(struct irq_desc *desc)
Erik Gilling3c92db92010-03-15 19:40:06 -0700375{
Thierry Reding539b7a32017-07-24 16:55:08 +0200376 unsigned int port, pin, gpio;
Michał Mirosław9e9509e2017-07-18 14:35:45 +0200377 bool unmasked = false;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530378 u32 lvl;
379 unsigned long sta;
Will Deacon98022942011-02-21 13:58:10 +0000380 struct irq_chip *chip = irq_desc_get_chip(desc);
Jiang Liu476f8b42015-06-04 12:13:15 +0800381 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530382 struct tegra_gpio_info *tgi = bank->tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700383
Will Deacon98022942011-02-21 13:58:10 +0000384 chained_irq_enter(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700385
Erik Gilling3c92db92010-03-15 19:40:06 -0700386 for (port = 0; port < 4; port++) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530387 gpio = tegra_gpio_compose(bank->bank, port, 0);
388 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
389 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
390 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700391
392 for_each_set_bit(pin, &sta, 8) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530393 tegra_gpio_writel(tgi, 1 << pin,
394 GPIO_INT_CLR(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700395
396 /* if gpio is edge triggered, clear condition
Colin Cronin20a8a962015-05-18 11:41:43 -0700397 * before executing the handler so that we don't
Erik Gilling3c92db92010-03-15 19:40:06 -0700398 * miss edges
399 */
Michał Mirosław9e9509e2017-07-18 14:35:45 +0200400 if (!unmasked && lvl & (0x100 << pin)) {
401 unmasked = true;
Will Deacon98022942011-02-21 13:58:10 +0000402 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700403 }
404
Grygorii Strashkoc0debb32017-07-08 17:44:11 -0500405 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
406 gpio + pin));
Erik Gilling3c92db92010-03-15 19:40:06 -0700407 }
408 }
409
410 if (!unmasked)
Will Deacon98022942011-02-21 13:58:10 +0000411 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700412
413}
414
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530415#ifdef CONFIG_PM_SLEEP
416static int tegra_gpio_resume(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700417{
Wolfram Sang7ddb7dce2018-10-21 22:00:00 +0200418 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
Thierry Reding539b7a32017-07-24 16:55:08 +0200419 unsigned int b, p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700420
Laxman Dewanganb546be02016-04-25 16:08:33 +0530421 for (b = 0; b < tgi->bank_count; b++) {
422 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
Colin Cross2e47b8b2010-04-07 12:59:42 -0700423
424 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
Thierry Reding4bc17862017-07-24 16:55:07 +0200425 unsigned int gpio = (b << 5) | (p << 3);
426
Laxman Dewanganb546be02016-04-25 16:08:33 +0530427 tegra_gpio_writel(tgi, bank->cnf[p],
428 GPIO_CNF(tgi, gpio));
Laxman Dewangan3737de422016-04-25 16:08:34 +0530429
430 if (tgi->soc->debounce_supported) {
431 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
432 GPIO_DBC_CNT(tgi, gpio));
433 tegra_gpio_writel(tgi, bank->dbc_enb[p],
434 GPIO_MSK_DBC_EN(tgi, gpio));
435 }
436
Laxman Dewanganb546be02016-04-25 16:08:33 +0530437 tegra_gpio_writel(tgi, bank->out[p],
438 GPIO_OUT(tgi, gpio));
439 tegra_gpio_writel(tgi, bank->oe[p],
440 GPIO_OE(tgi, gpio));
441 tegra_gpio_writel(tgi, bank->int_lvl[p],
442 GPIO_INT_LVL(tgi, gpio));
443 tegra_gpio_writel(tgi, bank->int_enb[p],
444 GPIO_INT_ENB(tgi, gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700445 }
446 }
447
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530448 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700449}
450
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530451static int tegra_gpio_suspend(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700452{
Wolfram Sang7ddb7dce2018-10-21 22:00:00 +0200453 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
Thierry Reding539b7a32017-07-24 16:55:08 +0200454 unsigned int b, p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700455
Laxman Dewanganb546be02016-04-25 16:08:33 +0530456 for (b = 0; b < tgi->bank_count; b++) {
457 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
Colin Cross2e47b8b2010-04-07 12:59:42 -0700458
459 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
Thierry Reding4bc17862017-07-24 16:55:07 +0200460 unsigned int gpio = (b << 5) | (p << 3);
461
Laxman Dewanganb546be02016-04-25 16:08:33 +0530462 bank->cnf[p] = tegra_gpio_readl(tgi,
463 GPIO_CNF(tgi, gpio));
464 bank->out[p] = tegra_gpio_readl(tgi,
465 GPIO_OUT(tgi, gpio));
466 bank->oe[p] = tegra_gpio_readl(tgi,
467 GPIO_OE(tgi, gpio));
Laxman Dewangan3737de422016-04-25 16:08:34 +0530468 if (tgi->soc->debounce_supported) {
469 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
470 GPIO_MSK_DBC_EN(tgi, gpio));
471 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
472 bank->dbc_enb[p];
473 }
474
Laxman Dewanganb546be02016-04-25 16:08:33 +0530475 bank->int_enb[p] = tegra_gpio_readl(tgi,
476 GPIO_INT_ENB(tgi, gpio));
477 bank->int_lvl[p] = tegra_gpio_readl(tgi,
478 GPIO_INT_LVL(tgi, gpio));
Joseph Lo203f31c2013-04-03 19:31:44 +0800479
480 /* Enable gpio irq for wake up source */
Laxman Dewanganb546be02016-04-25 16:08:33 +0530481 tegra_gpio_writel(tgi, bank->wake_enb[p],
482 GPIO_INT_ENB(tgi, gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700483 }
484 }
Dmitry Osipenko9ccaf102019-12-15 21:30:47 +0300485
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530486 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700487}
488
Joseph Lo203f31c2013-04-03 19:31:44 +0800489static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700490{
Lennert Buytenhek37337a8d2010-11-29 11:14:46 +0100491 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Thierry Reding539b7a32017-07-24 16:55:08 +0200492 unsigned int gpio = d->hwirq;
Joseph Lo203f31c2013-04-03 19:31:44 +0800493 u32 port, bit, mask;
Dmitry Osipenkof56d9792019-12-15 21:30:46 +0300494 int err;
495
496 err = irq_set_irq_wake(bank->irq, enable);
497 if (err)
498 return err;
Joseph Lo203f31c2013-04-03 19:31:44 +0800499
500 port = GPIO_PORT(gpio);
501 bit = GPIO_BIT(gpio);
502 mask = BIT(bit);
503
504 if (enable)
505 bank->wake_enb[port] |= mask;
506 else
507 bank->wake_enb[port] &= ~mask;
508
Dmitry Osipenkof56d9792019-12-15 21:30:46 +0300509 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700510}
511#endif
Erik Gilling3c92db92010-03-15 19:40:06 -0700512
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000513#ifdef CONFIG_DEBUG_FS
514
515#include <linux/debugfs.h>
516#include <linux/seq_file.h>
517
Axel Lin2773eb22018-02-12 22:01:57 +0800518static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000519{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530520 struct tegra_gpio_info *tgi = s->private;
Thierry Reding539b7a32017-07-24 16:55:08 +0200521 unsigned int i, j;
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000522
Laxman Dewanganb546be02016-04-25 16:08:33 +0530523 for (i = 0; i < tgi->bank_count; i++) {
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000524 for (j = 0; j < 4; j++) {
Thierry Reding539b7a32017-07-24 16:55:08 +0200525 unsigned int gpio = tegra_gpio_compose(i, j, 0);
Thierry Reding4bc17862017-07-24 16:55:07 +0200526
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000527 seq_printf(s,
Thierry Reding539b7a32017-07-24 16:55:08 +0200528 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000529 i, j,
Laxman Dewanganb546be02016-04-25 16:08:33 +0530530 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
531 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
532 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
533 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
534 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
535 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
536 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000537 }
538 }
539 return 0;
540}
541
Axel Lin2773eb22018-02-12 22:01:57 +0800542DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000543
Laxman Dewanganb546be02016-04-25 16:08:33 +0530544static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000545{
Linus Walleij9b3b6232019-07-06 20:15:54 +0200546 debugfs_create_file("tegra_gpio", 0444, NULL, tgi,
547 &tegra_dbg_gpio_fops);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000548}
549
550#else
551
Laxman Dewanganb546be02016-04-25 16:08:33 +0530552static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000553{
554}
555
556#endif
557
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530558static const struct dev_pm_ops tegra_gpio_pm_ops = {
Dmitry Osipenko9ccaf102019-12-15 21:30:47 +0300559 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530560};
561
Bill Pemberton38363092012-11-19 13:22:34 -0500562static int tegra_gpio_probe(struct platform_device *pdev)
Erik Gilling3c92db92010-03-15 19:40:06 -0700563{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530564 struct tegra_gpio_info *tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700565 struct tegra_gpio_bank *bank;
Thierry Reding539b7a32017-07-24 16:55:08 +0200566 unsigned int gpio, i, j;
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700567 int ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700568
Laxman Dewanganb546be02016-04-25 16:08:33 +0530569 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
570 if (!tgi)
571 return -ENODEV;
572
Thierry Reding20133bd2017-07-24 16:55:05 +0200573 tgi->soc = of_device_get_match_data(&pdev->dev);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530574 tgi->dev = &pdev->dev;
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600575
Thierry Reding56420902017-07-20 18:00:56 +0200576 ret = platform_irq_count(pdev);
577 if (ret < 0)
578 return ret;
579
580 tgi->bank_count = ret;
581
Laxman Dewanganb546be02016-04-25 16:08:33 +0530582 if (!tgi->bank_count) {
Stephen Warren33918112012-01-19 08:16:35 +0000583 dev_err(&pdev->dev, "Missing IRQ resource\n");
584 return -ENODEV;
585 }
586
Laxman Dewanganb546be02016-04-25 16:08:33 +0530587 tgi->gc.label = "tegra-gpio";
588 tgi->gc.request = tegra_gpio_request;
589 tgi->gc.free = tegra_gpio_free;
590 tgi->gc.direction_input = tegra_gpio_direction_input;
591 tgi->gc.get = tegra_gpio_get;
592 tgi->gc.direction_output = tegra_gpio_direction_output;
593 tgi->gc.set = tegra_gpio_set;
Laxman Dewanganf002d072016-04-29 21:55:23 +0530594 tgi->gc.get_direction = tegra_gpio_get_direction;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530595 tgi->gc.to_irq = tegra_gpio_to_irq;
596 tgi->gc.base = 0;
597 tgi->gc.ngpio = tgi->bank_count * 32;
598 tgi->gc.parent = &pdev->dev;
599 tgi->gc.of_node = pdev->dev.of_node;
Stephen Warren33918112012-01-19 08:16:35 +0000600
Laxman Dewanganb546be02016-04-25 16:08:33 +0530601 tgi->ic.name = "GPIO";
602 tgi->ic.irq_ack = tegra_gpio_irq_ack;
603 tgi->ic.irq_mask = tegra_gpio_irq_mask;
604 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
605 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
606 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
607#ifdef CONFIG_PM_SLEEP
608 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
609#endif
610
611 platform_set_drvdata(pdev, tgi);
612
Thierry Reding20133bd2017-07-24 16:55:05 +0200613 if (tgi->soc->debounce_supported)
Mika Westerberg2956b5d2017-01-23 15:34:34 +0300614 tgi->gc.set_config = tegra_gpio_set_config;
Laxman Dewangan3737de422016-04-25 16:08:34 +0530615
Thierry Reding9b882262017-07-24 16:55:06 +0200616 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
Laxman Dewanganb546be02016-04-25 16:08:33 +0530617 sizeof(*tgi->bank_info), GFP_KERNEL);
618 if (!tgi->bank_info)
Thierry Reding9b882262017-07-24 16:55:06 +0200619 return -ENOMEM;
Stephen Warren33918112012-01-19 08:16:35 +0000620
Laxman Dewanganb546be02016-04-25 16:08:33 +0530621 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
622 tgi->gc.ngpio,
623 &irq_domain_simple_ops, NULL);
624 if (!tgi->irq_domain)
Linus Walleijd0235672012-10-16 21:00:09 +0200625 return -ENODEV;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000626
Laxman Dewanganb546be02016-04-25 16:08:33 +0530627 for (i = 0; i < tgi->bank_count; i++) {
Thierry Reding9c074092017-07-20 18:00:57 +0200628 ret = platform_get_irq(pdev, i);
Stephen Boyd15bddb72019-07-30 11:15:15 -0700629 if (ret < 0)
Thierry Reding9c074092017-07-20 18:00:57 +0200630 return ret;
Stephen Warren88d89512011-10-11 16:16:14 -0600631
Laxman Dewanganb546be02016-04-25 16:08:33 +0530632 bank = &tgi->bank_info[i];
Stephen Warren88d89512011-10-11 16:16:14 -0600633 bank->bank = i;
Thierry Reding9c074092017-07-20 18:00:57 +0200634 bank->irq = ret;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530635 bank->tgi = tgi;
Stephen Warren88d89512011-10-11 16:16:14 -0600636 }
637
Enrico Weigelt, metux IT consulta0b81f12019-03-11 19:55:12 +0100638 tgi->regs = devm_platform_ioremap_resource(pdev, 0);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530639 if (IS_ERR(tgi->regs))
640 return PTR_ERR(tgi->regs);
Stephen Warren88d89512011-10-11 16:16:14 -0600641
Laxman Dewanganb546be02016-04-25 16:08:33 +0530642 for (i = 0; i < tgi->bank_count; i++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700643 for (j = 0; j < 4; j++) {
644 int gpio = tegra_gpio_compose(i, j, 0);
Thierry Reding4bc17862017-07-24 16:55:07 +0200645
Laxman Dewanganb546be02016-04-25 16:08:33 +0530646 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700647 }
648 }
649
Laxman Dewanganb546be02016-04-25 16:08:33 +0530650 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700651 if (ret < 0) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530652 irq_domain_remove(tgi->irq_domain);
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700653 return ret;
654 }
Erik Gilling3c92db92010-03-15 19:40:06 -0700655
Laxman Dewanganb546be02016-04-25 16:08:33 +0530656 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
657 int irq = irq_create_mapping(tgi->irq_domain, gpio);
Stephen Warren47008002011-08-23 00:39:55 +0100658 /* No validity check; all Tegra GPIOs are valid IRQs */
Erik Gilling3c92db92010-03-15 19:40:06 -0700659
Laxman Dewanganb546be02016-04-25 16:08:33 +0530660 bank = &tgi->bank_info[GPIO_BANK(gpio)];
Stephen Warren47008002011-08-23 00:39:55 +0100661
Stephen Warren47008002011-08-23 00:39:55 +0100662 irq_set_chip_data(irq, bank);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530663 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700664 }
665
Laxman Dewanganb546be02016-04-25 16:08:33 +0530666 for (i = 0; i < tgi->bank_count; i++) {
667 bank = &tgi->bank_info[i];
Erik Gilling3c92db92010-03-15 19:40:06 -0700668
Russell Kinge88d2512015-06-16 23:06:50 +0100669 irq_set_chained_handler_and_data(bank->irq,
670 tegra_gpio_irq_handler, bank);
Erik Gilling3c92db92010-03-15 19:40:06 -0700671
Laxman Dewangan3737de422016-04-25 16:08:34 +0530672 for (j = 0; j < 4; j++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700673 spin_lock_init(&bank->lvl_lock[j]);
Laxman Dewangan3737de422016-04-25 16:08:34 +0530674 spin_lock_init(&bank->dbc_lock[j]);
675 }
Erik Gilling3c92db92010-03-15 19:40:06 -0700676 }
677
Laxman Dewanganb546be02016-04-25 16:08:33 +0530678 tegra_gpio_debuginit(tgi);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000679
Erik Gilling3c92db92010-03-15 19:40:06 -0700680 return 0;
681}
682
Laxman Dewangan804f5682016-04-25 16:08:32 +0530683static const struct tegra_gpio_soc_config tegra20_gpio_config = {
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530684 .bank_stride = 0x80,
685 .upper_offset = 0x800,
686};
687
Laxman Dewangan804f5682016-04-25 16:08:32 +0530688static const struct tegra_gpio_soc_config tegra30_gpio_config = {
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530689 .bank_stride = 0x100,
690 .upper_offset = 0x80,
691};
692
Laxman Dewangan3737de422016-04-25 16:08:34 +0530693static const struct tegra_gpio_soc_config tegra210_gpio_config = {
694 .debounce_supported = true,
695 .bank_stride = 0x100,
696 .upper_offset = 0x80,
697};
698
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530699static const struct of_device_id tegra_gpio_of_match[] = {
Laxman Dewangan3737de422016-04-25 16:08:34 +0530700 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530701 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
702 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
703 { },
704};
705
Stephen Warren88d89512011-10-11 16:16:14 -0600706static struct platform_driver tegra_gpio_driver = {
707 .driver = {
708 .name = "tegra-gpio",
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530709 .pm = &tegra_gpio_pm_ops,
Stephen Warren88d89512011-10-11 16:16:14 -0600710 .of_match_table = tegra_gpio_of_match,
711 },
712 .probe = tegra_gpio_probe,
713};
714
715static int __init tegra_gpio_init(void)
716{
717 return platform_driver_register(&tegra_gpio_driver);
718}
Dmitry Osipenko40b25bc2018-08-02 14:11:44 +0300719subsys_initcall(tegra_gpio_init);