Bean Huo | 6735111 | 2020-06-05 22:05:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Universal Flash Storage Host controller driver |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 4 | * Copyright (C) 2011-2013 Samsung India Software Operations |
Yaniv Gardi | dc3c8d3 | 2016-02-01 15:02:46 +0200 | [diff] [blame] | 5 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 6 | * |
| 7 | * Authors: |
| 8 | * Santosh Yaraganavi <santosh.sy@samsung.com> |
| 9 | * Vinayak Holikatti <h.vinayak@samsung.com> |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #ifndef _UFSHCD_H |
| 13 | #define _UFSHCD_H |
| 14 | |
Stanley Chu | 5a244e0 | 2020-01-29 18:52:50 +0800 | [diff] [blame] | 15 | #include <linux/bitfield.h> |
Eric Biggers | 1e8d44b | 2021-10-18 11:04:51 -0700 | [diff] [blame] | 16 | #include <linux/blk-crypto-profile.h> |
Bart Van Assche | 3f06f78 | 2022-04-19 15:58:08 -0700 | [diff] [blame] | 17 | #include <linux/blk-mq.h> |
| 18 | #include <linux/devfreq.h> |
Akinobu Mita | 045da30 | 2023-11-18 21:44:43 +0900 | [diff] [blame] | 19 | #include <linux/fault-inject.h> |
Can Guo | e02288e | 2022-12-14 19:06:21 -0800 | [diff] [blame] | 20 | #include <linux/msi.h> |
Bart Van Assche | 3f06f78 | 2022-04-19 15:58:08 -0700 | [diff] [blame] | 21 | #include <linux/pm_runtime.h> |
Bean Huo | f3e57da | 2023-01-08 23:40:56 +0100 | [diff] [blame] | 22 | #include <linux/dma-direction.h> |
Bart Van Assche | 3f06f78 | 2022-04-19 15:58:08 -0700 | [diff] [blame] | 23 | #include <scsi/scsi_device.h> |
Bart Van Assche | cce9fd6 | 2023-07-27 12:41:17 -0700 | [diff] [blame] | 24 | #include <scsi/scsi_host.h> |
Bart Van Assche | dd11376 | 2022-05-11 14:25:52 -0700 | [diff] [blame] | 25 | #include <ufs/unipro.h> |
| 26 | #include <ufs/ufs.h> |
| 27 | #include <ufs/ufs_quirks.h> |
| 28 | #include <ufs/ufshci.h> |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 29 | |
| 30 | #define UFSHCD "ufshcd" |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 31 | |
Bart Van Assche | 858231b | 2023-09-21 12:22:47 -0700 | [diff] [blame] | 32 | struct scsi_device; |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 33 | struct ufs_hba; |
| 34 | |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 35 | enum dev_cmd_type { |
| 36 | DEV_CMD_TYPE_NOP = 0x0, |
Dolev Raviv | 68078d5 | 2013-07-30 00:35:58 +0530 | [diff] [blame] | 37 | DEV_CMD_TYPE_QUERY = 0x1, |
Bean Huo | 6ff265fc | 2022-12-01 15:04:37 +0100 | [diff] [blame] | 38 | DEV_CMD_TYPE_RPMB = 0x2, |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 39 | }; |
| 40 | |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 41 | enum ufs_event_type { |
| 42 | /* uic specific errors */ |
| 43 | UFS_EVT_PA_ERR = 0, |
| 44 | UFS_EVT_DL_ERR, |
| 45 | UFS_EVT_NL_ERR, |
| 46 | UFS_EVT_TL_ERR, |
| 47 | UFS_EVT_DME_ERR, |
| 48 | |
| 49 | /* fatal errors */ |
| 50 | UFS_EVT_AUTO_HIBERN8_ERR, |
| 51 | UFS_EVT_FATAL_ERR, |
| 52 | UFS_EVT_LINK_STARTUP_FAIL, |
| 53 | UFS_EVT_RESUME_ERR, |
| 54 | UFS_EVT_SUSPEND_ERR, |
Asutosh Das | b294ff3 | 2021-04-23 17:20:16 -0700 | [diff] [blame] | 55 | UFS_EVT_WL_SUSP_ERR, |
| 56 | UFS_EVT_WL_RES_ERR, |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 57 | |
| 58 | /* abnormal events */ |
| 59 | UFS_EVT_DEV_RESET, |
| 60 | UFS_EVT_HOST_RESET, |
| 61 | UFS_EVT_ABORT, |
| 62 | |
| 63 | UFS_EVT_CNT, |
| 64 | }; |
| 65 | |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 66 | /** |
| 67 | * struct uic_command - UIC command structure |
| 68 | * @command: UIC command |
| 69 | * @argument1: UIC command argument 1 |
| 70 | * @argument2: UIC command argument 2 |
| 71 | * @argument3: UIC command argument 3 |
Can Guo | 0f52fcb9 | 2020-11-02 22:24:40 -0800 | [diff] [blame] | 72 | * @cmd_active: Indicate if UIC command is outstanding |
Seungwon Jeon | 6ccf44fe | 2013-06-26 22:39:29 +0530 | [diff] [blame] | 73 | * @done: UIC command completion |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 74 | */ |
| 75 | struct uic_command { |
| 76 | u32 command; |
| 77 | u32 argument1; |
| 78 | u32 argument2; |
| 79 | u32 argument3; |
Can Guo | 0f52fcb9 | 2020-11-02 22:24:40 -0800 | [diff] [blame] | 80 | int cmd_active; |
Seungwon Jeon | 6ccf44fe | 2013-06-26 22:39:29 +0530 | [diff] [blame] | 81 | struct completion done; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 82 | }; |
| 83 | |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 84 | /* Used to differentiate the power management options */ |
| 85 | enum ufs_pm_op { |
| 86 | UFS_RUNTIME_PM, |
| 87 | UFS_SYSTEM_PM, |
| 88 | UFS_SHUTDOWN_PM, |
| 89 | }; |
| 90 | |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 91 | /* Host <-> Device UniPro Link state */ |
| 92 | enum uic_link_state { |
| 93 | UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ |
| 94 | UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ |
| 95 | UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ |
Can Guo | 4db7a23 | 2020-08-09 05:15:51 -0700 | [diff] [blame] | 96 | UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) |
| 100 | #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ |
| 101 | UIC_LINK_ACTIVE_STATE) |
| 102 | #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ |
| 103 | UIC_LINK_HIBERN8_STATE) |
Can Guo | 4db7a23 | 2020-08-09 05:15:51 -0700 | [diff] [blame] | 104 | #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ |
| 105 | UIC_LINK_BROKEN_STATE) |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 106 | #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) |
| 107 | #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ |
| 108 | UIC_LINK_ACTIVE_STATE) |
| 109 | #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ |
| 110 | UIC_LINK_HIBERN8_STATE) |
Can Guo | 4db7a23 | 2020-08-09 05:15:51 -0700 | [diff] [blame] | 111 | #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ |
| 112 | UIC_LINK_BROKEN_STATE) |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 113 | |
Stanley Chu | 1764fa2 | 2020-03-27 17:58:35 +0800 | [diff] [blame] | 114 | #define ufshcd_set_ufs_dev_active(h) \ |
| 115 | ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) |
| 116 | #define ufshcd_set_ufs_dev_sleep(h) \ |
| 117 | ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) |
| 118 | #define ufshcd_set_ufs_dev_poweroff(h) \ |
| 119 | ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) |
Adrian Hunter | fe1d4c2 | 2020-11-03 16:14:02 +0200 | [diff] [blame] | 120 | #define ufshcd_set_ufs_dev_deepsleep(h) \ |
| 121 | ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) |
Stanley Chu | 1764fa2 | 2020-03-27 17:58:35 +0800 | [diff] [blame] | 122 | #define ufshcd_is_ufs_dev_active(h) \ |
| 123 | ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) |
| 124 | #define ufshcd_is_ufs_dev_sleep(h) \ |
| 125 | ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) |
| 126 | #define ufshcd_is_ufs_dev_poweroff(h) \ |
| 127 | ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) |
Adrian Hunter | fe1d4c2 | 2020-11-03 16:14:02 +0200 | [diff] [blame] | 128 | #define ufshcd_is_ufs_dev_deepsleep(h) \ |
| 129 | ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) |
Stanley Chu | 1764fa2 | 2020-03-27 17:58:35 +0800 | [diff] [blame] | 130 | |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 131 | /* |
| 132 | * UFS Power management levels. |
Adrian Hunter | fe1d4c2 | 2020-11-03 16:14:02 +0200 | [diff] [blame] | 133 | * Each level is in increasing order of power savings, except DeepSleep |
| 134 | * which is lower than PowerDown with power on but not PowerDown with |
| 135 | * power off. |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 136 | */ |
| 137 | enum ufs_pm_level { |
Bart Van Assche | e2ac7ab | 2021-05-19 13:20:58 -0700 | [diff] [blame] | 138 | UFS_PM_LVL_0, |
| 139 | UFS_PM_LVL_1, |
| 140 | UFS_PM_LVL_2, |
| 141 | UFS_PM_LVL_3, |
| 142 | UFS_PM_LVL_4, |
| 143 | UFS_PM_LVL_5, |
| 144 | UFS_PM_LVL_6, |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 145 | UFS_PM_LVL_MAX |
| 146 | }; |
| 147 | |
| 148 | struct ufs_pm_lvl_states { |
| 149 | enum ufs_dev_pwr_mode dev_state; |
| 150 | enum uic_link_state link_state; |
| 151 | }; |
| 152 | |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 153 | /** |
| 154 | * struct ufshcd_lrb - local reference block |
| 155 | * @utr_descriptor_ptr: UTRD address of the command |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 156 | * @ucd_req_ptr: UCD address of the command |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 157 | * @ucd_rsp_ptr: Response UPIU address for this command |
| 158 | * @ucd_prdt_ptr: PRDT address of the command |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 159 | * @utrd_dma_addr: UTRD dma address for debug |
| 160 | * @ucd_prdt_dma_addr: PRDT dma address for debug |
| 161 | * @ucd_rsp_dma_addr: UPIU response dma address for debug |
| 162 | * @ucd_req_dma_addr: UPIU request dma address for debug |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 163 | * @cmd: pointer to SCSI command |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 164 | * @scsi_status: SCSI status of the command |
| 165 | * @command_type: SCSI, UFS, Query. |
| 166 | * @task_tag: Task tag of the command |
| 167 | * @lun: LUN of the command |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 168 | * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) |
Daniil Lunev | 0f85e74 | 2022-08-04 06:50:34 +1000 | [diff] [blame] | 169 | * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) |
| 170 | * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) |
| 171 | * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) |
| 172 | * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) |
Satya Tangirala | df043c74 | 2020-07-06 20:04:14 +0000 | [diff] [blame] | 173 | * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) |
| 174 | * @data_unit_num: the data unit number for the first block for inline crypto |
Gilad Broner | e0b299e | 2017-02-03 16:56:40 -0800 | [diff] [blame] | 175 | * @req_abort_skip: skip request abort task flag |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 176 | */ |
| 177 | struct ufshcd_lrb { |
| 178 | struct utp_transfer_req_desc *utr_descriptor_ptr; |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 179 | struct utp_upiu_req *ucd_req_ptr; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 180 | struct utp_upiu_rsp *ucd_rsp_ptr; |
| 181 | struct ufshcd_sg_entry *ucd_prdt_ptr; |
| 182 | |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 183 | dma_addr_t utrd_dma_addr; |
| 184 | dma_addr_t ucd_req_dma_addr; |
| 185 | dma_addr_t ucd_rsp_dma_addr; |
| 186 | dma_addr_t ucd_prdt_dma_addr; |
| 187 | |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 188 | struct scsi_cmnd *cmd; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 189 | int scsi_status; |
| 190 | |
| 191 | int command_type; |
| 192 | int task_tag; |
Subhash Jadavani | 0ce147d | 2014-09-25 15:32:29 +0300 | [diff] [blame] | 193 | u8 lun; /* UPIU LUN id field is only 8-bit wide */ |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 194 | bool intr_cmd; |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 195 | ktime_t issue_time_stamp; |
Daniil Lunev | 0f85e74 | 2022-08-04 06:50:34 +1000 | [diff] [blame] | 196 | u64 issue_time_stamp_local_clock; |
Zang Leigang | 0901718 | 2017-09-27 10:06:06 +0800 | [diff] [blame] | 197 | ktime_t compl_time_stamp; |
Daniil Lunev | 0f85e74 | 2022-08-04 06:50:34 +1000 | [diff] [blame] | 198 | u64 compl_time_stamp_local_clock; |
Satya Tangirala | df043c74 | 2020-07-06 20:04:14 +0000 | [diff] [blame] | 199 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
| 200 | int crypto_key_slot; |
| 201 | u64 data_unit_num; |
| 202 | #endif |
Gilad Broner | e0b299e | 2017-02-03 16:56:40 -0800 | [diff] [blame] | 203 | |
| 204 | bool req_abort_skip; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 205 | }; |
| 206 | |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 207 | /** |
Bart Van Assche | e2566e0 | 2023-07-27 12:41:22 -0700 | [diff] [blame] | 208 | * struct ufs_query_req - parameters for building a query request |
| 209 | * @query_func: UPIU header query function |
| 210 | * @upiu_req: the query request data |
| 211 | */ |
| 212 | struct ufs_query_req { |
| 213 | u8 query_func; |
| 214 | struct utp_upiu_query upiu_req; |
| 215 | }; |
| 216 | |
| 217 | /** |
| 218 | * struct ufs_query_resp - UPIU QUERY |
| 219 | * @response: device response code |
| 220 | * @upiu_res: query response data |
| 221 | */ |
| 222 | struct ufs_query_res { |
| 223 | struct utp_upiu_query upiu_res; |
| 224 | }; |
| 225 | |
| 226 | /** |
Tomas Winkler | a230c2f | 2016-02-09 10:25:41 +0200 | [diff] [blame] | 227 | * struct ufs_query - holds relevant data structures for query request |
Dolev Raviv | 68078d5 | 2013-07-30 00:35:58 +0530 | [diff] [blame] | 228 | * @request: request upiu and function |
| 229 | * @descriptor: buffer for sending/receiving descriptor |
| 230 | * @response: response upiu and response |
| 231 | */ |
| 232 | struct ufs_query { |
| 233 | struct ufs_query_req request; |
| 234 | u8 *descriptor; |
| 235 | struct ufs_query_res response; |
| 236 | }; |
| 237 | |
| 238 | /** |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 239 | * struct ufs_dev_cmd - all assosiated fields with device management commands |
| 240 | * @type: device management command type - Query, NOP OUT |
| 241 | * @lock: lock to allow one command at a time |
| 242 | * @complete: internal commands completion |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 243 | * @query: Device management query information |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 244 | */ |
| 245 | struct ufs_dev_cmd { |
| 246 | enum dev_cmd_type type; |
| 247 | struct mutex lock; |
| 248 | struct completion *complete; |
Dolev Raviv | 68078d5 | 2013-07-30 00:35:58 +0530 | [diff] [blame] | 249 | struct ufs_query query; |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 250 | }; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 251 | |
Sujit Reddy Thumma | c6e79da | 2014-09-25 15:32:23 +0300 | [diff] [blame] | 252 | /** |
| 253 | * struct ufs_clk_info - UFS clock related info |
| 254 | * @list: list headed by hba->clk_list_head |
| 255 | * @clk: clock node |
| 256 | * @name: clock name |
| 257 | * @max_freq: maximum frequency supported by the clock |
Sahitya Tummala | 4cff6d99 | 2014-09-25 15:32:33 +0300 | [diff] [blame] | 258 | * @min_freq: min frequency that can be used for clock scaling |
Sahitya Tummala | 856b348 | 2014-09-25 15:32:34 +0300 | [diff] [blame] | 259 | * @curr_freq: indicates the current frequency that it is set to |
Can Guo | 81309c2 | 2020-11-25 18:01:00 -0800 | [diff] [blame] | 260 | * @keep_link_active: indicates that the clk should not be disabled if |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 261 | * link is active |
Sujit Reddy Thumma | c6e79da | 2014-09-25 15:32:23 +0300 | [diff] [blame] | 262 | * @enabled: variable to check against multiple enable/disable |
| 263 | */ |
| 264 | struct ufs_clk_info { |
| 265 | struct list_head list; |
| 266 | struct clk *clk; |
| 267 | const char *name; |
| 268 | u32 max_freq; |
Sahitya Tummala | 4cff6d99 | 2014-09-25 15:32:33 +0300 | [diff] [blame] | 269 | u32 min_freq; |
Sahitya Tummala | 856b348 | 2014-09-25 15:32:34 +0300 | [diff] [blame] | 270 | u32 curr_freq; |
Can Guo | 81309c2 | 2020-11-25 18:01:00 -0800 | [diff] [blame] | 271 | bool keep_link_active; |
Sujit Reddy Thumma | c6e79da | 2014-09-25 15:32:23 +0300 | [diff] [blame] | 272 | bool enabled; |
| 273 | }; |
| 274 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 275 | enum ufs_notify_change_status { |
| 276 | PRE_CHANGE, |
| 277 | POST_CHANGE, |
| 278 | }; |
Dolev Raviv | 7eb584d | 2014-09-25 15:32:31 +0300 | [diff] [blame] | 279 | |
| 280 | struct ufs_pa_layer_attr { |
| 281 | u32 gear_rx; |
| 282 | u32 gear_tx; |
| 283 | u32 lane_rx; |
| 284 | u32 lane_tx; |
| 285 | u32 pwr_rx; |
| 286 | u32 pwr_tx; |
| 287 | u32 hs_rate; |
| 288 | }; |
| 289 | |
| 290 | struct ufs_pwr_mode_info { |
| 291 | bool is_valid; |
| 292 | struct ufs_pa_layer_attr info; |
| 293 | }; |
| 294 | |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 295 | /** |
| 296 | * struct ufs_hba_variant_ops - variant specific callbacks |
| 297 | * @name: variant name |
| 298 | * @init: called when the driver is initialized |
| 299 | * @exit: called to cleanup everything done in init |
Yaniv Gardi | 9949e70 | 2015-05-17 18:55:05 +0300 | [diff] [blame] | 300 | * @get_ufs_hci_version: called to get UFS HCI version |
Sahitya Tummala | 856b348 | 2014-09-25 15:32:34 +0300 | [diff] [blame] | 301 | * @clk_scale_notify: notifies that clks are scaled up/down |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 302 | * @setup_clocks: called before touching any of the controller registers |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 303 | * @hce_enable_notify: called before and after HCE enable bit is set to allow |
| 304 | * variant specific Uni-Pro initialization. |
| 305 | * @link_startup_notify: called before and after Link startup is carried out |
| 306 | * to allow variant specific Uni-Pro initialization. |
Dolev Raviv | 7eb584d | 2014-09-25 15:32:31 +0300 | [diff] [blame] | 307 | * @pwr_change_notify: called before and after a power mode change |
| 308 | * is carried out to allow vendor spesific capabilities |
| 309 | * to be set. |
Kiwoong Kim | 0e675ef | 2016-11-10 21:14:36 +0900 | [diff] [blame] | 310 | * @setup_xfer_req: called before any transfer request is issued |
| 311 | * to set some things |
Kiwoong Kim | d2877be | 2016-11-10 21:16:15 +0900 | [diff] [blame] | 312 | * @setup_task_mgmt: called before any task management request is issued |
| 313 | * to set some things |
Kiwoong Kim | ee32c90 | 2016-11-10 21:17:43 +0900 | [diff] [blame] | 314 | * @hibern8_notify: called around hibern8 enter/exit |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 315 | * @apply_dev_quirks: called to apply device specific quirks |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 316 | * @fixup_dev_quirks: called to modify device specific quirks |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 317 | * @suspend: called during host controller PM callback |
| 318 | * @resume: called during host controller PM callback |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 319 | * @dbg_register_dump: used to dump controller debug information |
Joao Pinto | 4b9ffb5 | 2016-05-11 12:21:30 +0100 | [diff] [blame] | 320 | * @phy_initialization: used to initialize phys |
Bjorn Andersson | d8d9f79 | 2019-08-28 12:17:54 -0700 | [diff] [blame] | 321 | * @device_reset: called to issue a reset pulse on the UFS device |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 322 | * @config_scaling_param: called to configure clock scaling parameters |
Eric Biggers | 1bc726e | 2020-07-10 00:20:11 -0700 | [diff] [blame] | 323 | * @program_key: program or evict an inline encryption key |
Stanley Chu | 172614a | 2020-12-05 19:59:00 +0800 | [diff] [blame] | 324 | * @event_notify: called to notify important events |
Manivannan Sadhasivam | c2c38c5 | 2022-12-22 19:39:56 +0530 | [diff] [blame] | 325 | * @reinit_notify: called to notify reinit of UFSHCD during max gear switch |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 326 | * @mcq_config_resource: called to configure MCQ platform resources |
Asutosh Das | 7224c80 | 2023-01-13 12:48:43 -0800 | [diff] [blame] | 327 | * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 328 | * @op_runtime_config: called to config Operation and runtime regs Pointers |
Asutosh Das | f87b2c4 | 2023-01-13 12:48:50 -0800 | [diff] [blame] | 329 | * @get_outstanding_cqs: called to get outstanding completion queues |
Can Guo | edb0db0 | 2022-12-14 19:06:20 -0800 | [diff] [blame] | 330 | * @config_esi: called to config Event Specific Interrupt |
Peter Wang | db06ae7 | 2024-03-01 11:46:10 +0800 | [diff] [blame] | 331 | * @config_scsi_dev: called to configure SCSI device parameters |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 332 | */ |
| 333 | struct ufs_hba_variant_ops { |
| 334 | const char *name; |
| 335 | int (*init)(struct ufs_hba *); |
| 336 | void (*exit)(struct ufs_hba *); |
Yaniv Gardi | 9949e70 | 2015-05-17 18:55:05 +0300 | [diff] [blame] | 337 | u32 (*get_ufs_hci_version)(struct ufs_hba *); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 338 | int (*clk_scale_notify)(struct ufs_hba *, bool, |
| 339 | enum ufs_notify_change_status); |
Subhash Jadavani | 1e879e8 | 2016-10-06 21:48:22 -0700 | [diff] [blame] | 340 | int (*setup_clocks)(struct ufs_hba *, bool, |
| 341 | enum ufs_notify_change_status); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 342 | int (*hce_enable_notify)(struct ufs_hba *, |
| 343 | enum ufs_notify_change_status); |
| 344 | int (*link_startup_notify)(struct ufs_hba *, |
| 345 | enum ufs_notify_change_status); |
Dolev Raviv | 7eb584d | 2014-09-25 15:32:31 +0300 | [diff] [blame] | 346 | int (*pwr_change_notify)(struct ufs_hba *, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 347 | enum ufs_notify_change_status status, |
| 348 | struct ufs_pa_layer_attr *, |
Dolev Raviv | 7eb584d | 2014-09-25 15:32:31 +0300 | [diff] [blame] | 349 | struct ufs_pa_layer_attr *); |
Bart Van Assche | b427609 | 2021-12-03 15:19:35 -0800 | [diff] [blame] | 350 | void (*setup_xfer_req)(struct ufs_hba *hba, int tag, |
| 351 | bool is_scsi_cmd); |
Kiwoong Kim | d2877be | 2016-11-10 21:16:15 +0900 | [diff] [blame] | 352 | void (*setup_task_mgmt)(struct ufs_hba *, int, u8); |
Kiwoong Kim | ee32c90 | 2016-11-10 21:17:43 +0900 | [diff] [blame] | 353 | void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 354 | enum ufs_notify_change_status); |
Bean Huo | 0975006 | 2020-01-20 14:08:14 +0100 | [diff] [blame] | 355 | int (*apply_dev_quirks)(struct ufs_hba *hba); |
Stanley Chu | c28c00b | 2020-05-08 16:01:09 +0800 | [diff] [blame] | 356 | void (*fixup_dev_quirks)(struct ufs_hba *hba); |
Peter Wang | 9561f58 | 2021-10-06 13:47:05 +0800 | [diff] [blame] | 357 | int (*suspend)(struct ufs_hba *, enum ufs_pm_op, |
| 358 | enum ufs_notify_change_status); |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 359 | int (*resume)(struct ufs_hba *, enum ufs_pm_op); |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 360 | void (*dbg_register_dump)(struct ufs_hba *hba); |
Joao Pinto | 4b9ffb5 | 2016-05-11 12:21:30 +0100 | [diff] [blame] | 361 | int (*phy_initialization)(struct ufs_hba *); |
Adrian Hunter | 151f1b6 | 2020-11-03 16:14:03 +0200 | [diff] [blame] | 362 | int (*device_reset)(struct ufs_hba *hba); |
Asutosh Das | 2c75f9a5 | 2020-03-25 11:29:01 -0700 | [diff] [blame] | 363 | void (*config_scaling_param)(struct ufs_hba *hba, |
Bart Van Assche | c906e83 | 2022-04-19 15:57:57 -0700 | [diff] [blame] | 364 | struct devfreq_dev_profile *profile, |
| 365 | struct devfreq_simple_ondemand_data *data); |
Eric Biggers | 1bc726e | 2020-07-10 00:20:11 -0700 | [diff] [blame] | 366 | int (*program_key)(struct ufs_hba *hba, |
| 367 | const union ufs_crypto_cfg_entry *cfg, int slot); |
Stanley Chu | 172614a | 2020-12-05 19:59:00 +0800 | [diff] [blame] | 368 | void (*event_notify)(struct ufs_hba *hba, |
| 369 | enum ufs_event_type evt, void *data); |
Manivannan Sadhasivam | c2c38c5 | 2022-12-22 19:39:56 +0530 | [diff] [blame] | 370 | void (*reinit_notify)(struct ufs_hba *); |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 371 | int (*mcq_config_resource)(struct ufs_hba *hba); |
Asutosh Das | 7224c80 | 2023-01-13 12:48:43 -0800 | [diff] [blame] | 372 | int (*get_hba_mac)(struct ufs_hba *hba); |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 373 | int (*op_runtime_config)(struct ufs_hba *hba); |
Asutosh Das | f87b2c4 | 2023-01-13 12:48:50 -0800 | [diff] [blame] | 374 | int (*get_outstanding_cqs)(struct ufs_hba *hba, |
| 375 | unsigned long *ocqs); |
Can Guo | edb0db0 | 2022-12-14 19:06:20 -0800 | [diff] [blame] | 376 | int (*config_esi)(struct ufs_hba *hba); |
Bart Van Assche | 858231b | 2023-09-21 12:22:47 -0700 | [diff] [blame] | 377 | void (*config_scsi_dev)(struct scsi_device *sdev); |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 378 | }; |
| 379 | |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 380 | /* clock gating state */ |
| 381 | enum clk_gating_state { |
| 382 | CLKS_OFF, |
| 383 | CLKS_ON, |
| 384 | REQ_CLKS_OFF, |
| 385 | REQ_CLKS_ON, |
| 386 | }; |
| 387 | |
| 388 | /** |
| 389 | * struct ufs_clk_gating - UFS clock gating related info |
| 390 | * @gate_work: worker to turn off clocks after some delay as specified in |
| 391 | * delay_ms |
| 392 | * @ungate_work: worker to turn on clocks that will be used in case of |
| 393 | * interrupt context |
| 394 | * @state: the current clocks state |
| 395 | * @delay_ms: gating delay in ms |
| 396 | * @is_suspended: clk gating is suspended when set to 1 which can be used |
| 397 | * during suspend/resume |
| 398 | * @delay_attr: sysfs attribute to control delay_attr |
Sahitya Tummala | b427411 | 2016-12-22 18:40:39 -0800 | [diff] [blame] | 399 | * @enable_attr: sysfs attribute to enable/disable clock gating |
| 400 | * @is_enabled: Indicates the current status of clock gating |
Can Guo | 4543d9d | 2021-01-20 02:04:22 -0800 | [diff] [blame] | 401 | * @is_initialized: Indicates whether clock gating is initialized or not |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 402 | * @active_reqs: number of requests that are pending and should be waited for |
| 403 | * completion before gating clocks. |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 404 | * @clk_gating_workq: workqueue for clock gating work. |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 405 | */ |
| 406 | struct ufs_clk_gating { |
| 407 | struct delayed_work gate_work; |
| 408 | struct work_struct ungate_work; |
| 409 | enum clk_gating_state state; |
| 410 | unsigned long delay_ms; |
| 411 | bool is_suspended; |
| 412 | struct device_attribute delay_attr; |
Sahitya Tummala | b427411 | 2016-12-22 18:40:39 -0800 | [diff] [blame] | 413 | struct device_attribute enable_attr; |
| 414 | bool is_enabled; |
Can Guo | 4543d9d | 2021-01-20 02:04:22 -0800 | [diff] [blame] | 415 | bool is_initialized; |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 416 | int active_reqs; |
Vijay Viswanath | 10e5e37 | 2018-05-03 16:37:22 +0530 | [diff] [blame] | 417 | struct workqueue_struct *clk_gating_workq; |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 418 | }; |
| 419 | |
subhashj@codeaurora.org | 401f1e4 | 2017-02-03 16:57:39 -0800 | [diff] [blame] | 420 | /** |
| 421 | * struct ufs_clk_scaling - UFS clock scaling related data |
| 422 | * @active_reqs: number of requests that are pending. If this is zero when |
| 423 | * devfreq ->target() function is called then schedule "suspend_work" to |
| 424 | * suspend devfreq. |
| 425 | * @tot_busy_t: Total busy time in current polling window |
| 426 | * @window_start_t: Start time (in jiffies) of the current polling window |
| 427 | * @busy_start_t: Start time of current busy period |
| 428 | * @enable_attr: sysfs attribute to enable/disable clock scaling |
| 429 | * @saved_pwr_info: UFS power mode may also be changed during scaling and this |
| 430 | * one keeps track of previous power mode. |
| 431 | * @workq: workqueue to schedule devfreq suspend/resume work |
| 432 | * @suspend_work: worker to suspend devfreq |
| 433 | * @resume_work: worker to resume devfreq |
Manivannan Sadhasivam | 930bd77 | 2023-10-12 22:51:26 +0530 | [diff] [blame] | 434 | * @target_freq: frequency requested by devfreq framework |
Can Guo | 29b87e9 | 2020-11-26 17:58:48 -0800 | [diff] [blame] | 435 | * @min_gear: lowest HS gear to scale down to |
Can Guo | 0e9d4ca | 2021-01-20 02:04:21 -0800 | [diff] [blame] | 436 | * @is_enabled: tracks if scaling is currently enabled or not, controlled by |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 437 | * clkscale_enable sysfs node |
Can Guo | 0e9d4ca | 2021-01-20 02:04:21 -0800 | [diff] [blame] | 438 | * @is_allowed: tracks if scaling is currently allowed or not, used to block |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 439 | * clock scaling which is not invoked from devfreq governor |
Can Guo | 4543d9d | 2021-01-20 02:04:22 -0800 | [diff] [blame] | 440 | * @is_initialized: Indicates whether clock scaling is initialized or not |
subhashj@codeaurora.org | 401f1e4 | 2017-02-03 16:57:39 -0800 | [diff] [blame] | 441 | * @is_busy_started: tracks if busy period has started or not |
| 442 | * @is_suspended: tracks if devfreq is suspended or not |
| 443 | */ |
Sahitya Tummala | 856b348 | 2014-09-25 15:32:34 +0300 | [diff] [blame] | 444 | struct ufs_clk_scaling { |
subhashj@codeaurora.org | 401f1e4 | 2017-02-03 16:57:39 -0800 | [diff] [blame] | 445 | int active_reqs; |
| 446 | unsigned long tot_busy_t; |
Stanley Chu | b1bf66d | 2020-06-11 18:10:43 +0800 | [diff] [blame] | 447 | ktime_t window_start_t; |
subhashj@codeaurora.org | 401f1e4 | 2017-02-03 16:57:39 -0800 | [diff] [blame] | 448 | ktime_t busy_start_t; |
Sahitya Tummala | fcb0c4b | 2016-12-22 18:40:50 -0800 | [diff] [blame] | 449 | struct device_attribute enable_attr; |
Stanley Chu | 543a827b | 2023-03-30 09:29:18 +0800 | [diff] [blame] | 450 | struct ufs_pa_layer_attr saved_pwr_info; |
subhashj@codeaurora.org | 401f1e4 | 2017-02-03 16:57:39 -0800 | [diff] [blame] | 451 | struct workqueue_struct *workq; |
| 452 | struct work_struct suspend_work; |
| 453 | struct work_struct resume_work; |
Manivannan Sadhasivam | 930bd77 | 2023-10-12 22:51:26 +0530 | [diff] [blame] | 454 | unsigned long target_freq; |
Can Guo | 29b87e9 | 2020-11-26 17:58:48 -0800 | [diff] [blame] | 455 | u32 min_gear; |
Can Guo | 0e9d4ca | 2021-01-20 02:04:21 -0800 | [diff] [blame] | 456 | bool is_enabled; |
subhashj@codeaurora.org | 401f1e4 | 2017-02-03 16:57:39 -0800 | [diff] [blame] | 457 | bool is_allowed; |
Can Guo | 4543d9d | 2021-01-20 02:04:22 -0800 | [diff] [blame] | 458 | bool is_initialized; |
subhashj@codeaurora.org | 401f1e4 | 2017-02-03 16:57:39 -0800 | [diff] [blame] | 459 | bool is_busy_started; |
| 460 | bool is_suspended; |
Sahitya Tummala | 856b348 | 2014-09-25 15:32:34 +0300 | [diff] [blame] | 461 | }; |
| 462 | |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 463 | #define UFS_EVENT_HIST_LENGTH 8 |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 464 | /** |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 465 | * struct ufs_event_hist - keeps history of errors |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 466 | * @pos: index to indicate cyclic buffer position |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 467 | * @val: cyclic buffer for registers value |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 468 | * @tstamp: cyclic buffer for time stamp |
Adrian Hunter | b6cacaf | 2021-01-07 09:25:38 +0200 | [diff] [blame] | 469 | * @cnt: error counter |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 470 | */ |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 471 | struct ufs_event_hist { |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 472 | int pos; |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 473 | u32 val[UFS_EVENT_HIST_LENGTH]; |
Daniil Lunev | 0f85e74 | 2022-08-04 06:50:34 +1000 | [diff] [blame] | 474 | u64 tstamp[UFS_EVENT_HIST_LENGTH]; |
Adrian Hunter | b6cacaf | 2021-01-07 09:25:38 +0200 | [diff] [blame] | 475 | unsigned long long cnt; |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 476 | }; |
| 477 | |
| 478 | /** |
| 479 | * struct ufs_stats - keeps usage/err statistics |
Can Guo | 3f8af60 | 2020-08-09 05:15:50 -0700 | [diff] [blame] | 480 | * @last_intr_status: record the last interrupt status. |
| 481 | * @last_intr_ts: record the last interrupt timestamp. |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 482 | * @hibern8_exit_cnt: Counter to keep track of number of exits, |
| 483 | * reset this after link-startup. |
| 484 | * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. |
| 485 | * Clear after the first successful command completion. |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 486 | * @event: array with event history. |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 487 | */ |
| 488 | struct ufs_stats { |
Can Guo | 3f8af60 | 2020-08-09 05:15:50 -0700 | [diff] [blame] | 489 | u32 last_intr_status; |
Daniil Lunev | 0f85e74 | 2022-08-04 06:50:34 +1000 | [diff] [blame] | 490 | u64 last_intr_ts; |
Can Guo | 3f8af60 | 2020-08-09 05:15:50 -0700 | [diff] [blame] | 491 | |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 492 | u32 hibern8_exit_cnt; |
Daniil Lunev | 0f85e74 | 2022-08-04 06:50:34 +1000 | [diff] [blame] | 493 | u64 last_hibern8_exit_tstamp; |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 494 | struct ufs_event_hist event[UFS_EVT_CNT]; |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 495 | }; |
| 496 | |
Bart Van Assche | 9c20209 | 2021-07-21 20:34:29 -0700 | [diff] [blame] | 497 | /** |
| 498 | * enum ufshcd_state - UFS host controller state |
| 499 | * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command |
| 500 | * processing. |
| 501 | * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process |
| 502 | * SCSI commands. |
| 503 | * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. |
| 504 | * SCSI commands may be submitted to the controller. |
| 505 | * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail |
| 506 | * newly submitted SCSI commands with error code DID_BAD_TARGET. |
| 507 | * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery |
| 508 | * failed. Fail all SCSI commands with error code DID_ERROR. |
| 509 | */ |
| 510 | enum ufshcd_state { |
| 511 | UFSHCD_STATE_RESET, |
| 512 | UFSHCD_STATE_OPERATIONAL, |
| 513 | UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, |
| 514 | UFSHCD_STATE_EH_SCHEDULED_FATAL, |
| 515 | UFSHCD_STATE_ERROR, |
| 516 | }; |
| 517 | |
Christoph Hellwig | c3f7d1f | 2020-02-21 06:08:12 -0800 | [diff] [blame] | 518 | enum ufshcd_quirks { |
| 519 | /* Interrupt aggregation support is broken */ |
| 520 | UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, |
| 521 | |
| 522 | /* |
| 523 | * delay before each dme command is required as the unipro |
| 524 | * layer has shown instabilities |
| 525 | */ |
| 526 | UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, |
| 527 | |
| 528 | /* |
| 529 | * If UFS host controller is having issue in processing LCC (Line |
| 530 | * Control Command) coming from device then enable this quirk. |
| 531 | * When this quirk is enabled, host controller driver should disable |
| 532 | * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE |
| 533 | * attribute of device to 0). |
| 534 | */ |
| 535 | UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, |
| 536 | |
| 537 | /* |
| 538 | * The attribute PA_RXHSUNTERMCAP specifies whether or not the |
| 539 | * inbound Link supports unterminated line in HS mode. Setting this |
| 540 | * attribute to 1 fixes moving to HS gear. |
| 541 | */ |
| 542 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, |
| 543 | |
| 544 | /* |
| 545 | * This quirk needs to be enabled if the host controller only allows |
| 546 | * accessing the peer dme attributes in AUTO mode (FAST AUTO or |
| 547 | * SLOW AUTO). |
| 548 | */ |
| 549 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, |
| 550 | |
| 551 | /* |
| 552 | * This quirk needs to be enabled if the host controller doesn't |
| 553 | * advertise the correct version in UFS_VER register. If this quirk |
| 554 | * is enabled, standard UFS host driver will call the vendor specific |
| 555 | * ops (get_ufs_hci_version) to get the correct version. |
| 556 | */ |
| 557 | UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, |
Alim Akhtar | 8718384 | 2020-05-28 06:46:49 +0530 | [diff] [blame] | 558 | |
| 559 | /* |
| 560 | * Clear handling for transfer/task request list is just opposite. |
| 561 | */ |
| 562 | UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, |
Alim Akhtar | b638b5e | 2020-05-28 06:46:50 +0530 | [diff] [blame] | 563 | |
| 564 | /* |
| 565 | * This quirk needs to be enabled if host controller doesn't allow |
| 566 | * that the interrupt aggregation timer and counter are reset by s/w. |
| 567 | */ |
| 568 | UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, |
Alim Akhtar | 39bf2d8 | 2020-05-28 06:46:51 +0530 | [diff] [blame] | 569 | |
| 570 | /* |
| 571 | * This quirks needs to be enabled if host controller cannot be |
| 572 | * enabled via HCE register. |
| 573 | */ |
| 574 | UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, |
Alim Akhtar | 26f968d | 2020-05-28 06:46:52 +0530 | [diff] [blame] | 575 | |
| 576 | /* |
| 577 | * This quirk needs to be enabled if the host controller regards |
| 578 | * resolution of the values of PRDTO and PRDTL in UTRD as byte. |
| 579 | */ |
| 580 | UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, |
Kiwoong Kim | d779a6e | 2020-05-28 06:46:53 +0530 | [diff] [blame] | 581 | |
| 582 | /* |
| 583 | * This quirk needs to be enabled if the host controller reports |
| 584 | * OCS FATAL ERROR with device error through sense data |
| 585 | */ |
| 586 | UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, |
Kiwoong Kim | 5df6f2d | 2020-08-25 10:43:15 +0900 | [diff] [blame] | 587 | |
| 588 | /* |
Adrian Hunter | 8da76f7 | 2020-08-10 17:10:24 +0300 | [diff] [blame] | 589 | * This quirk needs to be enabled if the host controller has |
| 590 | * auto-hibernate capability but it doesn't work. |
| 591 | */ |
| 592 | UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, |
Martin K. Petersen | 02f7415 | 2020-09-15 11:24:32 -0400 | [diff] [blame] | 593 | |
| 594 | /* |
Kiwoong Kim | 5df6f2d | 2020-08-25 10:43:15 +0900 | [diff] [blame] | 595 | * This quirk needs to disable manual flush for write booster |
| 596 | */ |
Martin K. Petersen | 02f7415 | 2020-09-15 11:24:32 -0400 | [diff] [blame] | 597 | UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, |
| 598 | |
Kiwoong Kim | b1d0d2e | 2020-12-21 10:24:40 +0900 | [diff] [blame] | 599 | /* |
| 600 | * This quirk needs to disable unipro timeout values |
| 601 | * before power mode change |
| 602 | */ |
| 603 | UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, |
| 604 | |
Kiwoong Kim | 2b2bfc8a | 2021-01-19 12:33:41 +0900 | [diff] [blame] | 605 | /* |
jongmin jeong | a22bcfd | 2021-10-18 21:42:02 +0900 | [diff] [blame] | 606 | * This quirk needs to be enabled if the host controller does not |
| 607 | * support UIC command |
| 608 | */ |
| 609 | UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, |
jongmin jeong | 10fb4f8 | 2021-10-18 21:42:03 +0900 | [diff] [blame] | 610 | |
| 611 | /* |
| 612 | * This quirk needs to be enabled if the host controller cannot |
| 613 | * support physical host configuration. |
| 614 | */ |
| 615 | UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, |
Yoshihiro Shimoda | 6554400 | 2022-06-03 20:05:19 +0900 | [diff] [blame] | 616 | |
| 617 | /* |
| 618 | * This quirk needs to be enabled if the host controller has |
| 619 | * 64-bit addressing supported capability but it doesn't work. |
| 620 | */ |
| 621 | UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, |
Yoshihiro Shimoda | 2f11bbc | 2022-06-03 20:05:20 +0900 | [diff] [blame] | 622 | |
| 623 | /* |
| 624 | * This quirk needs to be enabled if the host controller has |
| 625 | * auto-hibernate capability but it's FASTAUTO only. |
| 626 | */ |
| 627 | UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, |
Manivannan Sadhasivam | 96a7141 | 2022-12-22 19:39:57 +0530 | [diff] [blame] | 628 | |
| 629 | /* |
| 630 | * This quirk needs to be enabled if the host controller needs |
| 631 | * to reinit the device after switching to maximum gear. |
| 632 | */ |
| 633 | UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, |
Po-Wen Kao | c4ad4f2 | 2023-06-12 16:58:09 +0800 | [diff] [blame] | 634 | |
| 635 | /* |
| 636 | * Some host raises interrupt (per queue) in addition to |
| 637 | * CQES (traditional) when ESI is disabled. |
| 638 | * Enable this quirk will disable CQES and use per queue interrupt. |
| 639 | */ |
| 640 | UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, |
Po-Wen Kao | aa9d5d0 | 2023-06-12 16:58:10 +0800 | [diff] [blame] | 641 | |
| 642 | /* |
| 643 | * Some host does not implement SQ Run Time Command (SQRTC) register |
| 644 | * thus need this quirk to skip related flow. |
| 645 | */ |
| 646 | UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, |
Christoph Hellwig | c3f7d1f | 2020-02-21 06:08:12 -0800 | [diff] [blame] | 647 | }; |
| 648 | |
Stanley Chu | c201468 | 2020-03-18 18:40:11 +0800 | [diff] [blame] | 649 | enum ufshcd_caps { |
| 650 | /* Allow dynamic clk gating */ |
| 651 | UFSHCD_CAP_CLK_GATING = 1 << 0, |
| 652 | |
| 653 | /* Allow hiberb8 with clk gating */ |
| 654 | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, |
| 655 | |
| 656 | /* Allow dynamic clk scaling */ |
| 657 | UFSHCD_CAP_CLK_SCALING = 1 << 2, |
| 658 | |
| 659 | /* Allow auto bkops to enabled during runtime suspend */ |
| 660 | UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, |
| 661 | |
| 662 | /* |
| 663 | * This capability allows host controller driver to use the UFS HCI's |
| 664 | * interrupt aggregation capability. |
| 665 | * CAUTION: Enabling this might reduce overall UFS throughput. |
| 666 | */ |
| 667 | UFSHCD_CAP_INTR_AGGR = 1 << 4, |
| 668 | |
| 669 | /* |
| 670 | * This capability allows the device auto-bkops to be always enabled |
| 671 | * except during suspend (both runtime and suspend). |
| 672 | * Enabling this capability means that device will always be allowed |
| 673 | * to do background operation when it's active but it might degrade |
| 674 | * the performance of ongoing read/write operations. |
| 675 | */ |
| 676 | UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, |
| 677 | |
| 678 | /* |
| 679 | * This capability allows host controller driver to automatically |
| 680 | * enable runtime power management by itself instead of waiting |
| 681 | * for userspace to control the power management. |
| 682 | */ |
| 683 | UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, |
Asutosh Das | 3d17b9b | 2020-04-22 14:41:42 -0700 | [diff] [blame] | 684 | |
| 685 | /* |
| 686 | * This capability allows the host controller driver to turn-on |
| 687 | * WriteBooster, if the underlying device supports it and is |
| 688 | * provisioned to be used. This would increase the write performance. |
| 689 | */ |
| 690 | UFSHCD_CAP_WB_EN = 1 << 7, |
Satya Tangirala | 5e7341e | 2020-07-06 20:04:12 +0000 | [diff] [blame] | 691 | |
| 692 | /* |
| 693 | * This capability allows the host controller driver to use the |
| 694 | * inline crypto engine, if it is present |
| 695 | */ |
| 696 | UFSHCD_CAP_CRYPTO = 1 << 8, |
Can Guo | dd7143e | 2020-10-27 12:10:36 -0700 | [diff] [blame] | 697 | |
| 698 | /* |
| 699 | * This capability allows the controller regulators to be put into |
| 700 | * lpm mode aggressively during clock gating. |
| 701 | * This would increase power savings. |
| 702 | */ |
| 703 | UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, |
Adrian Hunter | fe1d4c2 | 2020-11-03 16:14:02 +0200 | [diff] [blame] | 704 | |
| 705 | /* |
| 706 | * This capability allows the host controller driver to use DeepSleep, |
| 707 | * if it is supported by the UFS device. The host controller driver must |
| 708 | * support device hardware reset via the hba->device_reset() callback, |
| 709 | * in order to exit DeepSleep state. |
| 710 | */ |
| 711 | UFSHCD_CAP_DEEPSLEEP = 1 << 10, |
Avri Altman | e88e2d3 | 2021-09-15 09:04:06 +0300 | [diff] [blame] | 712 | |
| 713 | /* |
| 714 | * This capability allows the host controller driver to use temperature |
| 715 | * notification if it is supported by the UFS device. |
| 716 | */ |
| 717 | UFSHCD_CAP_TEMP_NOTIF = 1 << 11, |
Peter Wang | 87bd050 | 2022-08-04 10:54:22 +0800 | [diff] [blame] | 718 | |
| 719 | /* |
| 720 | * Enable WriteBooster when scaling up the clock and disable |
| 721 | * WriteBooster when scaling the clock down. |
| 722 | */ |
| 723 | UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, |
Stanley Chu | c201468 | 2020-03-18 18:40:11 +0800 | [diff] [blame] | 724 | }; |
| 725 | |
Stanley Chu | 90b8491 | 2020-05-09 17:37:13 +0800 | [diff] [blame] | 726 | struct ufs_hba_variant_params { |
| 727 | struct devfreq_dev_profile devfreq_profile; |
| 728 | struct devfreq_simple_ondemand_data ondemand_data; |
| 729 | u16 hba_enable_delay_us; |
Stanley Chu | d14734ae | 2020-05-09 17:37:15 +0800 | [diff] [blame] | 730 | u32 wb_flush_threshold; |
Stanley Chu | 90b8491 | 2020-05-09 17:37:13 +0800 | [diff] [blame] | 731 | }; |
| 732 | |
Can Guo | 1d8613a | 2021-04-21 19:28:39 -0700 | [diff] [blame] | 733 | struct ufs_hba_monitor { |
| 734 | unsigned long chunk_size; |
| 735 | |
| 736 | unsigned long nr_sec_rw[2]; |
| 737 | ktime_t total_busy[2]; |
| 738 | |
| 739 | unsigned long nr_req[2]; |
| 740 | /* latencies*/ |
| 741 | ktime_t lat_sum[2]; |
| 742 | ktime_t lat_max[2]; |
| 743 | ktime_t lat_min[2]; |
| 744 | |
| 745 | u32 nr_queued[2]; |
| 746 | ktime_t busy_start_ts[2]; |
| 747 | |
| 748 | ktime_t enabled_ts; |
| 749 | bool enabled; |
| 750 | }; |
| 751 | |
Yaniv Gardi | 3a4bf06 | 2014-09-25 15:32:27 +0300 | [diff] [blame] | 752 | /** |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 753 | * struct ufshcd_res_info_t - MCQ related resource regions |
| 754 | * |
| 755 | * @name: resource name |
| 756 | * @resource: pointer to resource region |
| 757 | * @base: register base address |
| 758 | */ |
| 759 | struct ufshcd_res_info { |
| 760 | const char *name; |
| 761 | struct resource *resource; |
| 762 | void __iomem *base; |
| 763 | }; |
| 764 | |
| 765 | enum ufshcd_res { |
| 766 | RES_UFS, |
| 767 | RES_MCQ, |
| 768 | RES_MCQ_SQD, |
| 769 | RES_MCQ_SQIS, |
| 770 | RES_MCQ_CQD, |
| 771 | RES_MCQ_CQIS, |
| 772 | RES_MCQ_VS, |
| 773 | RES_MAX, |
| 774 | }; |
| 775 | |
| 776 | /** |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 777 | * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers |
| 778 | * |
| 779 | * @offset: Doorbell Address Offset |
| 780 | * @stride: Steps proportional to queue [0...31] |
| 781 | * @base: base address |
| 782 | */ |
| 783 | struct ufshcd_mcq_opr_info_t { |
| 784 | unsigned long offset; |
| 785 | unsigned long stride; |
| 786 | void __iomem *base; |
| 787 | }; |
| 788 | |
| 789 | enum ufshcd_mcq_opr { |
| 790 | OPR_SQD, |
| 791 | OPR_SQIS, |
| 792 | OPR_CQD, |
| 793 | OPR_CQIS, |
| 794 | OPR_MAX, |
| 795 | }; |
| 796 | |
| 797 | /** |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 798 | * struct ufs_hba - per adapter private structure |
| 799 | * @mmio_base: UFSHCI base register address |
| 800 | * @ucdl_base_addr: UFS Command Descriptor base address |
| 801 | * @utrdl_base_addr: UTP Transfer Request Descriptor base address |
| 802 | * @utmrdl_base_addr: UTP Task Management Descriptor base address |
| 803 | * @ucdl_dma_addr: UFS Command Descriptor DMA address |
| 804 | * @utrdl_dma_addr: UTRDL DMA address |
| 805 | * @utmrdl_dma_addr: UTMRDL DMA address |
| 806 | * @host: Scsi_Host instance of the driver |
| 807 | * @dev: device handle |
Bart Van Assche | e210658 | 2022-04-19 15:57:59 -0700 | [diff] [blame] | 808 | * @ufs_device_wlun: WLUN that controls the entire UFS device. |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 809 | * @hwmon_device: device instance registered with the hwmon core. |
| 810 | * @curr_dev_pwr_mode: active UFS device power mode. |
| 811 | * @uic_link_state: active state of the link to the UFS device. |
| 812 | * @rpm_lvl: desired UFS power management level during runtime PM. |
| 813 | * @spm_lvl: desired UFS power management level during system PM. |
| 814 | * @pm_op_in_progress: whether or not a PM operation is in progress. |
| 815 | * @ahit: value of Auto-Hibernate Idle Timer register. |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 816 | * @lrb: local reference block |
| 817 | * @outstanding_tasks: Bits representing outstanding task requests |
Bart Van Assche | 169f5eb | 2021-07-21 20:34:34 -0700 | [diff] [blame] | 818 | * @outstanding_lock: Protects @outstanding_reqs. |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 819 | * @outstanding_reqs: Bits representing outstanding transfer requests |
| 820 | * @capabilities: UFS Controller Capabilities |
Asutosh Das | 6e1d850 | 2023-01-13 12:48:38 -0800 | [diff] [blame] | 821 | * @mcq_capabilities: UFS Multi Circular Queue capabilities |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 822 | * @nutrs: Transfer Request Queue depth supported by controller |
| 823 | * @nutmrs: Task Management Queue depth supported by controller |
Bart Van Assche | 945c3cc | 2021-12-03 15:19:42 -0800 | [diff] [blame] | 824 | * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 825 | * @ufs_version: UFS Version to which controller complies |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 826 | * @vops: pointer to variant specific operations |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 827 | * @vps: pointer to variant specific parameters |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 828 | * @priv: pointer to variant specific private data |
Eric Biggers | ada1e65 | 2022-12-08 15:43:58 -0800 | [diff] [blame] | 829 | * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 830 | * @irq: Irq number of the controller |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 831 | * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. |
| 832 | * @dev_ref_clk_freq: reference clock frequency |
| 833 | * @quirks: bitmask with information about deviations from the UFSHCI standard. |
| 834 | * @dev_quirks: bitmask with information about deviations from the UFS standard. |
Bart Van Assche | 69a6c26 | 2019-12-09 10:13:09 -0800 | [diff] [blame] | 835 | * @tmf_tag_set: TMF tag set. |
| 836 | * @tmf_queue: Used to allocate TMF tags. |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 837 | * @tmf_rqs: array with pointers to TMF requests while these are in progress. |
| 838 | * @active_uic_cmd: handle of active UIC command |
| 839 | * @uic_cmd_mutex: mutex for UIC command |
| 840 | * @uic_async_done: completion used during UIC processing |
Bart Van Assche | 9c20209 | 2021-07-21 20:34:29 -0700 | [diff] [blame] | 841 | * @ufshcd_state: UFSHCD state |
Sujit Reddy Thumma | 3441da7 | 2014-05-26 10:59:14 +0530 | [diff] [blame] | 842 | * @eh_flags: Error handling flags |
Seungwon Jeon | 2fbd009 | 2013-06-26 22:39:27 +0530 | [diff] [blame] | 843 | * @intr_mask: Interrupt Mask Bits |
Sujit Reddy Thumma | 66ec6d5 | 2013-07-30 00:35:59 +0530 | [diff] [blame] | 844 | * @ee_ctrl_mask: Exception event control mask |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 845 | * @ee_drv_mask: Exception event mask for driver |
| 846 | * @ee_usr_mask: Exception event mask for user (set via debugfs) |
| 847 | * @ee_ctrl_mutex: Used to serialize exception event information. |
Sujit Reddy Thumma | 1d337ec | 2014-09-25 15:32:26 +0300 | [diff] [blame] | 848 | * @is_powered: flag to check if HBA is powered |
Can Guo | 9cd20d3 | 2021-01-13 19:13:28 -0800 | [diff] [blame] | 849 | * @shutting_down: flag to check if shutdown has been invoked |
| 850 | * @host_sem: semaphore used to serialize concurrent contexts |
Adrian Hunter | 88b09900 | 2021-09-17 17:43:49 +0300 | [diff] [blame] | 851 | * @eh_wq: Workqueue that eh_work works on |
| 852 | * @eh_work: Worker to handle UFS errors that require s/w attention |
Sujit Reddy Thumma | 66ec6d5 | 2013-07-30 00:35:59 +0530 | [diff] [blame] | 853 | * @eeh_work: Worker to handle exception events |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 854 | * @errors: HBA errors |
Sujit Reddy Thumma | e8e7f27 | 2014-05-26 10:59:15 +0530 | [diff] [blame] | 855 | * @uic_error: UFS interconnect layer error status |
| 856 | * @saved_err: sticky error mask |
| 857 | * @saved_uic_err: sticky UIC error mask |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 858 | * @ufs_stats: various error counters |
Can Guo | 4db7a23 | 2020-08-09 05:15:51 -0700 | [diff] [blame] | 859 | * @force_reset: flag to force eh_work perform a full reset |
Can Guo | 2355b66 | 2020-08-24 19:07:06 -0700 | [diff] [blame] | 860 | * @force_pmc: flag to force a power mode change |
Can Guo | 2df74b6 | 2019-11-25 22:53:33 -0800 | [diff] [blame] | 861 | * @silence_err_logs: flag to silence error logs |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 862 | * @dev_cmd: ufs device management command information |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 863 | * @last_dme_cmd_tstamp: time stamp of the last completed DME command |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 864 | * @nop_out_timeout: NOP OUT timeout value |
| 865 | * @dev_info: information about the UFS device |
Sujit Reddy Thumma | 66ec6d5 | 2013-07-30 00:35:59 +0530 | [diff] [blame] | 866 | * @auto_bkops_enabled: to track whether bkops is enabled in device |
Sujit Reddy Thumma | aa49761 | 2014-09-25 15:32:22 +0300 | [diff] [blame] | 867 | * @vreg_info: UFS device voltage regulator information |
Sujit Reddy Thumma | c6e79da | 2014-09-25 15:32:23 +0300 | [diff] [blame] | 868 | * @clk_list_head: UFS host controller clocks list node head |
Manivannan Sadhasivam | 930bd77 | 2023-10-12 22:51:26 +0530 | [diff] [blame] | 869 | * @use_pm_opp: Indicates whether OPP based scaling is used or not |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 870 | * @req_abort_count: number of times ufshcd_abort() has been called |
| 871 | * @lanes_per_direction: number of lanes per data direction between the UFS |
| 872 | * controller and the UFS device. |
Dolev Raviv | 7eb584d | 2014-09-25 15:32:31 +0300 | [diff] [blame] | 873 | * @pwr_info: holds current power mode |
| 874 | * @max_pwr_info: keeps the device max valid pwm |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 875 | * @clk_gating: information related to clock gating |
| 876 | * @caps: bitmask with information about UFS controller capabilities |
| 877 | * @devfreq: frequency scaling information owned by the devfreq core |
| 878 | * @clk_scaling: frequency scaling information owned by the UFS driver |
Bart Van Assche | 1a547cb | 2022-10-18 13:29:56 -0700 | [diff] [blame] | 879 | * @system_suspending: system suspend has been started and system resume has |
| 880 | * not yet finished. |
| 881 | * @is_sys_suspended: UFS device has been suspended because of system suspend |
Yaniv Gardi | afdfff5 | 2016-03-10 17:37:15 +0200 | [diff] [blame] | 882 | * @urgent_bkops_lvl: keeps track of urgent bkops level for device |
| 883 | * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for |
| 884 | * device is known or not. |
Johan Hovold | ba81043 | 2023-01-16 17:12:01 +0100 | [diff] [blame] | 885 | * @wb_mutex: used to serialize devfreq and sysfs write booster toggling |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 886 | * @clk_scaling_lock: used to serialize device commands and clock scaling |
| 887 | * @desc_size: descriptor sizes reported by device |
Subhash Jadavani | 3813553 | 2018-05-03 16:37:18 +0530 | [diff] [blame] | 888 | * @scsi_block_reqs_cnt: reference counting for scsi block requests |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 889 | * @bsg_dev: struct device associated with the BSG queue |
| 890 | * @bsg_queue: BSG queue associated with the UFS controller |
| 891 | * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power |
| 892 | * management) after the UFS device has finished a WriteBooster buffer |
| 893 | * flush or auto BKOP. |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 894 | * @monitor: statistics about UFS commands |
Satya Tangirala | 70297a8 | 2020-07-06 20:04:13 +0000 | [diff] [blame] | 895 | * @crypto_capabilities: Content of crypto capabilities register (0x100) |
| 896 | * @crypto_cap_array: Array of crypto capabilities |
| 897 | * @crypto_cfg_register: Start of the crypto cfg array |
Eric Biggers | cb77cb5 | 2021-10-18 11:04:52 -0700 | [diff] [blame] | 898 | * @crypto_profile: the crypto profile of this hba (if applicable) |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 899 | * @debugfs_root: UFS controller debugfs root directory |
| 900 | * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay |
| 901 | * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore |
| 902 | * ee_ctrl_mask |
| 903 | * @luns_avail: number of regular and well known LUNs supported by the UFS |
| 904 | * device |
Asutosh Das | 57b1c0e | 2023-01-13 12:48:41 -0800 | [diff] [blame] | 905 | * @nr_hw_queues: number of hardware queues configured |
| 906 | * @nr_queues: number of Queues of different queue types |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 907 | * @complete_put: whether or not to call ufshcd_rpm_put() from inside |
| 908 | * ufshcd_resume_complete() |
Asutosh Das | 6e1d850 | 2023-01-13 12:48:38 -0800 | [diff] [blame] | 909 | * @ext_iid_sup: is EXT_IID is supported by UFSHC |
Asutosh Das | 305a357 | 2023-01-13 12:48:39 -0800 | [diff] [blame] | 910 | * @mcq_sup: is mcq supported by UFSHC |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 911 | * @mcq_enabled: is mcq ready to accept requests |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 912 | * @res: array of resource info of MCQ registers |
| 913 | * @mcq_base: Multi circular queue registers base address |
Asutosh Das | 4682abf | 2023-01-13 12:48:44 -0800 | [diff] [blame] | 914 | * @uhq: array of supported hardware queues |
| 915 | * @dev_cmd_queue: Queue for issuing device management commands |
Bean Huo | 6bf999e | 2023-12-12 23:08:24 +0100 | [diff] [blame] | 916 | * @mcq_opr: MCQ operation and runtime registers |
| 917 | * @ufs_rtc_update_work: A work for UFS RTC periodic update |
Maramaina Naresh | 2777e73 | 2023-12-19 18:07:05 +0530 | [diff] [blame] | 918 | * @pm_qos_req: PM QoS request handle |
| 919 | * @pm_qos_enabled: flag to check if pm qos is enabled |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 920 | */ |
| 921 | struct ufs_hba { |
| 922 | void __iomem *mmio_base; |
| 923 | |
| 924 | /* Virtual memory reference */ |
| 925 | struct utp_transfer_cmd_desc *ucdl_base_addr; |
| 926 | struct utp_transfer_req_desc *utrdl_base_addr; |
| 927 | struct utp_task_req_desc *utmrdl_base_addr; |
| 928 | |
| 929 | /* DMA memory reference */ |
| 930 | dma_addr_t ucdl_dma_addr; |
| 931 | dma_addr_t utrdl_dma_addr; |
| 932 | dma_addr_t utmrdl_dma_addr; |
| 933 | |
| 934 | struct Scsi_Host *host; |
| 935 | struct device *dev; |
Bart Van Assche | e210658 | 2022-04-19 15:57:59 -0700 | [diff] [blame] | 936 | struct scsi_device *ufs_device_wlun; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 937 | |
Avri Altman | e88e2d3 | 2021-09-15 09:04:06 +0300 | [diff] [blame] | 938 | #ifdef CONFIG_SCSI_UFS_HWMON |
| 939 | struct device *hwmon_device; |
| 940 | #endif |
| 941 | |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 942 | enum ufs_dev_pwr_mode curr_dev_pwr_mode; |
| 943 | enum uic_link_state uic_link_state; |
| 944 | /* Desired UFS power management level during runtime PM */ |
| 945 | enum ufs_pm_level rpm_lvl; |
| 946 | /* Desired UFS power management level during system PM */ |
| 947 | enum ufs_pm_level spm_lvl; |
| 948 | int pm_op_in_progress; |
| 949 | |
Adrian Hunter | ad44837 | 2018-03-20 15:07:38 +0200 | [diff] [blame] | 950 | /* Auto-Hibernate Idle Timer register value */ |
| 951 | u32 ahit; |
| 952 | |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 953 | struct ufshcd_lrb *lrb; |
| 954 | |
| 955 | unsigned long outstanding_tasks; |
Bart Van Assche | 169f5eb | 2021-07-21 20:34:34 -0700 | [diff] [blame] | 956 | spinlock_t outstanding_lock; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 957 | unsigned long outstanding_reqs; |
| 958 | |
| 959 | u32 capabilities; |
| 960 | int nutrs; |
Asutosh Das | 6e1d850 | 2023-01-13 12:48:38 -0800 | [diff] [blame] | 961 | u32 mcq_capabilities; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 962 | int nutmrs; |
Bart Van Assche | 945c3cc | 2021-12-03 15:19:42 -0800 | [diff] [blame] | 963 | u32 reserved_slot; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 964 | u32 ufs_version; |
Arnd Bergmann | 176eb92 | 2019-03-04 20:39:11 +0100 | [diff] [blame] | 965 | const struct ufs_hba_variant_ops *vops; |
Stanley Chu | 90b8491 | 2020-05-09 17:37:13 +0800 | [diff] [blame] | 966 | struct ufs_hba_variant_params *vps; |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 967 | void *priv; |
Eric Biggers | ada1e65 | 2022-12-08 15:43:58 -0800 | [diff] [blame] | 968 | #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE |
| 969 | size_t sg_entry_size; |
| 970 | #endif |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 971 | unsigned int irq; |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 972 | bool is_irq_enabled; |
Subhash Jadavani | 9e1e8a75 | 2018-10-16 14:29:41 +0530 | [diff] [blame] | 973 | enum ufs_ref_clk_freq dev_ref_clk_freq; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 974 | |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 975 | unsigned int quirks; /* Deviations from standard UFSHCI spec. */ |
Seungwon Jeon | 6ccf44fe | 2013-06-26 22:39:29 +0530 | [diff] [blame] | 976 | |
Yaniv Gardi | c58ab7a | 2016-03-10 17:37:10 +0200 | [diff] [blame] | 977 | /* Device deviations from standard UFS device spec. */ |
| 978 | unsigned int dev_quirks; |
| 979 | |
Bart Van Assche | 69a6c26 | 2019-12-09 10:13:09 -0800 | [diff] [blame] | 980 | struct blk_mq_tag_set tmf_tag_set; |
| 981 | struct request_queue *tmf_queue; |
Adrian Hunter | f5ef336 | 2021-09-22 12:10:59 +0300 | [diff] [blame] | 982 | struct request **tmf_rqs; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 983 | |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 984 | struct uic_command *active_uic_cmd; |
| 985 | struct mutex uic_cmd_mutex; |
| 986 | struct completion *uic_async_done; |
Seungwon Jeon | 53b3d9c | 2013-08-31 21:40:22 +0530 | [diff] [blame] | 987 | |
Bart Van Assche | 9c20209 | 2021-07-21 20:34:29 -0700 | [diff] [blame] | 988 | enum ufshcd_state ufshcd_state; |
Sujit Reddy Thumma | 3441da7 | 2014-05-26 10:59:14 +0530 | [diff] [blame] | 989 | u32 eh_flags; |
Seungwon Jeon | 2fbd009 | 2013-06-26 22:39:27 +0530 | [diff] [blame] | 990 | u32 intr_mask; |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 991 | u16 ee_ctrl_mask; |
| 992 | u16 ee_drv_mask; |
| 993 | u16 ee_usr_mask; |
Adrian Hunter | cd46947 | 2021-02-09 08:24:36 +0200 | [diff] [blame] | 994 | struct mutex ee_ctrl_mutex; |
Sujit Reddy Thumma | 1d337ec | 2014-09-25 15:32:26 +0300 | [diff] [blame] | 995 | bool is_powered; |
Can Guo | 9cd20d3 | 2021-01-13 19:13:28 -0800 | [diff] [blame] | 996 | bool shutting_down; |
| 997 | struct semaphore host_sem; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 998 | |
| 999 | /* Work Queues */ |
Adrian Hunter | 88b09900 | 2021-09-17 17:43:49 +0300 | [diff] [blame] | 1000 | struct workqueue_struct *eh_wq; |
| 1001 | struct work_struct eh_work; |
Sujit Reddy Thumma | 66ec6d5 | 2013-07-30 00:35:59 +0530 | [diff] [blame] | 1002 | struct work_struct eeh_work; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 1003 | |
| 1004 | /* HBA Errors */ |
| 1005 | u32 errors; |
Sujit Reddy Thumma | e8e7f27 | 2014-05-26 10:59:15 +0530 | [diff] [blame] | 1006 | u32 uic_error; |
| 1007 | u32 saved_err; |
| 1008 | u32 saved_uic_err; |
Dolev Raviv | ff8e20c | 2016-12-22 18:42:18 -0800 | [diff] [blame] | 1009 | struct ufs_stats ufs_stats; |
Can Guo | 4db7a23 | 2020-08-09 05:15:51 -0700 | [diff] [blame] | 1010 | bool force_reset; |
Can Guo | 2355b66 | 2020-08-24 19:07:06 -0700 | [diff] [blame] | 1011 | bool force_pmc; |
Can Guo | 2df74b6 | 2019-11-25 22:53:33 -0800 | [diff] [blame] | 1012 | bool silence_err_logs; |
Sujit Reddy Thumma | 5a0b0cb | 2013-07-30 00:35:57 +0530 | [diff] [blame] | 1013 | |
| 1014 | /* Device management request data */ |
| 1015 | struct ufs_dev_cmd dev_cmd; |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 1016 | ktime_t last_dme_cmd_tstamp; |
Adrian Hunter | 1cbc9ad | 2021-08-31 17:53:17 +0300 | [diff] [blame] | 1017 | int nop_out_timeout; |
Sujit Reddy Thumma | 66ec6d5 | 2013-07-30 00:35:59 +0530 | [diff] [blame] | 1018 | |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 1019 | /* Keeps information of the UFS device connected to this host */ |
| 1020 | struct ufs_dev_info dev_info; |
Sujit Reddy Thumma | 66ec6d5 | 2013-07-30 00:35:59 +0530 | [diff] [blame] | 1021 | bool auto_bkops_enabled; |
Sujit Reddy Thumma | aa49761 | 2014-09-25 15:32:22 +0300 | [diff] [blame] | 1022 | struct ufs_vreg_info vreg_info; |
Sujit Reddy Thumma | c6e79da | 2014-09-25 15:32:23 +0300 | [diff] [blame] | 1023 | struct list_head clk_list_head; |
Manivannan Sadhasivam | 930bd77 | 2023-10-12 22:51:26 +0530 | [diff] [blame] | 1024 | bool use_pm_opp; |
Subhash Jadavani | 57d104c | 2014-09-25 15:32:30 +0300 | [diff] [blame] | 1025 | |
Gilad Broner | 7fabb77 | 2017-02-03 16:56:50 -0800 | [diff] [blame] | 1026 | /* Number of requests aborts */ |
| 1027 | int req_abort_count; |
| 1028 | |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 1029 | /* Number of lanes available (1 or 2) for Rx/Tx */ |
| 1030 | u32 lanes_per_direction; |
Dolev Raviv | 7eb584d | 2014-09-25 15:32:31 +0300 | [diff] [blame] | 1031 | struct ufs_pa_layer_attr pwr_info; |
| 1032 | struct ufs_pwr_mode_info max_pwr_info; |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 1033 | |
| 1034 | struct ufs_clk_gating clk_gating; |
| 1035 | /* Control to enable/disable host capabilities */ |
| 1036 | u32 caps; |
Sahitya Tummala | 856b348 | 2014-09-25 15:32:34 +0300 | [diff] [blame] | 1037 | |
| 1038 | struct devfreq *devfreq; |
| 1039 | struct ufs_clk_scaling clk_scaling; |
Bart Van Assche | 1a547cb | 2022-10-18 13:29:56 -0700 | [diff] [blame] | 1040 | bool system_suspending; |
Dolev Raviv | e785060 | 2014-09-25 15:32:36 +0300 | [diff] [blame] | 1041 | bool is_sys_suspended; |
Yaniv Gardi | afdfff5 | 2016-03-10 17:37:15 +0200 | [diff] [blame] | 1042 | |
| 1043 | enum bkops_status urgent_bkops_lvl; |
| 1044 | bool is_urgent_bkops_lvl_checked; |
subhashj@codeaurora.org | a3cd5ec | 2017-02-03 16:57:02 -0800 | [diff] [blame] | 1045 | |
Johan Hovold | ba81043 | 2023-01-16 17:12:01 +0100 | [diff] [blame] | 1046 | struct mutex wb_mutex; |
subhashj@codeaurora.org | a3cd5ec | 2017-02-03 16:57:02 -0800 | [diff] [blame] | 1047 | struct rw_semaphore clk_scaling_lock; |
Subhash Jadavani | 3813553 | 2018-05-03 16:37:18 +0530 | [diff] [blame] | 1048 | atomic_t scsi_block_reqs_cnt; |
Avri Altman | df032bf | 2018-10-07 17:30:35 +0300 | [diff] [blame] | 1049 | |
| 1050 | struct device bsg_dev; |
| 1051 | struct request_queue *bsg_queue; |
Stanley Chu | 51dd905 | 2020-05-22 16:32:12 +0800 | [diff] [blame] | 1052 | struct delayed_work rpm_dev_flush_recheck_work; |
Satya Tangirala | 70297a8 | 2020-07-06 20:04:13 +0000 | [diff] [blame] | 1053 | |
Can Guo | 1d8613a | 2021-04-21 19:28:39 -0700 | [diff] [blame] | 1054 | struct ufs_hba_monitor monitor; |
| 1055 | |
Satya Tangirala | 70297a8 | 2020-07-06 20:04:13 +0000 | [diff] [blame] | 1056 | #ifdef CONFIG_SCSI_UFS_CRYPTO |
| 1057 | union ufs_crypto_capabilities crypto_capabilities; |
| 1058 | union ufs_crypto_cap_entry *crypto_cap_array; |
| 1059 | u32 crypto_cfg_register; |
Eric Biggers | cb77cb5 | 2021-10-18 11:04:52 -0700 | [diff] [blame] | 1060 | struct blk_crypto_profile crypto_profile; |
Satya Tangirala | 70297a8 | 2020-07-06 20:04:13 +0000 | [diff] [blame] | 1061 | #endif |
Adrian Hunter | b6cacaf | 2021-01-07 09:25:38 +0200 | [diff] [blame] | 1062 | #ifdef CONFIG_DEBUG_FS |
| 1063 | struct dentry *debugfs_root; |
Adrian Hunter | 7deedfd | 2021-02-09 08:24:37 +0200 | [diff] [blame] | 1064 | struct delayed_work debugfs_ee_work; |
| 1065 | u32 debugfs_ee_rate_limit_ms; |
Adrian Hunter | b6cacaf | 2021-01-07 09:25:38 +0200 | [diff] [blame] | 1066 | #endif |
Akinobu Mita | 045da30 | 2023-11-18 21:44:43 +0900 | [diff] [blame] | 1067 | #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION |
| 1068 | struct fault_attr trigger_eh_attr; |
| 1069 | struct fault_attr timeout_attr; |
| 1070 | #endif |
Asutosh Das | b294ff3 | 2021-04-23 17:20:16 -0700 | [diff] [blame] | 1071 | u32 luns_avail; |
Asutosh Das | 57b1c0e | 2023-01-13 12:48:41 -0800 | [diff] [blame] | 1072 | unsigned int nr_hw_queues; |
| 1073 | unsigned int nr_queues[HCTX_MAX_TYPES]; |
Asutosh Das | b294ff3 | 2021-04-23 17:20:16 -0700 | [diff] [blame] | 1074 | bool complete_put; |
Asutosh Das | 6e1d850 | 2023-01-13 12:48:38 -0800 | [diff] [blame] | 1075 | bool ext_iid_sup; |
Asutosh Das | 0cab402 | 2023-01-13 12:48:40 -0800 | [diff] [blame] | 1076 | bool scsi_host_added; |
Asutosh Das | 305a357 | 2023-01-13 12:48:39 -0800 | [diff] [blame] | 1077 | bool mcq_sup; |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1078 | bool mcq_enabled; |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1079 | struct ufshcd_res_info res[RES_MAX]; |
| 1080 | void __iomem *mcq_base; |
Asutosh Das | 4682abf | 2023-01-13 12:48:44 -0800 | [diff] [blame] | 1081 | struct ufs_hw_queue *uhq; |
| 1082 | struct ufs_hw_queue *dev_cmd_queue; |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1083 | struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; |
Bean Huo | 6bf999e | 2023-12-12 23:08:24 +0100 | [diff] [blame] | 1084 | |
| 1085 | struct delayed_work ufs_rtc_update_work; |
Maramaina Naresh | 2777e73 | 2023-12-19 18:07:05 +0530 | [diff] [blame] | 1086 | struct pm_qos_request pm_qos_req; |
| 1087 | bool pm_qos_enabled; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 1088 | }; |
| 1089 | |
Asutosh Das | 4682abf | 2023-01-13 12:48:44 -0800 | [diff] [blame] | 1090 | /** |
| 1091 | * struct ufs_hw_queue - per hardware queue structure |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1092 | * @mcq_sq_head: base address of submission queue head pointer |
| 1093 | * @mcq_sq_tail: base address of submission queue tail pointer |
| 1094 | * @mcq_cq_head: base address of completion queue head pointer |
| 1095 | * @mcq_cq_tail: base address of completion queue tail pointer |
Asutosh Das | 4682abf | 2023-01-13 12:48:44 -0800 | [diff] [blame] | 1096 | * @sqe_base_addr: submission queue entry base address |
| 1097 | * @sqe_dma_addr: submission queue dma address |
| 1098 | * @cqe_base_addr: completion queue base address |
| 1099 | * @cqe_dma_addr: completion queue dma address |
| 1100 | * @max_entries: max number of slots in this hardware queue |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1101 | * @id: hardware queue ID |
Asutosh Das | 22a2d56 | 2023-01-13 12:48:47 -0800 | [diff] [blame] | 1102 | * @sq_tp_slot: current slot to which SQ tail pointer is pointing |
| 1103 | * @sq_lock: serialize submission queue access |
Asutosh Das | f87b2c4 | 2023-01-13 12:48:50 -0800 | [diff] [blame] | 1104 | * @cq_tail_slot: current slot to which CQ tail pointer is pointing |
| 1105 | * @cq_head_slot: current slot to which CQ head pointer is pointing |
Asutosh Das | ed97506 | 2023-01-13 12:48:51 -0800 | [diff] [blame] | 1106 | * @cq_lock: Synchronize between multiple polling instances |
Bao D. Nguyen | 8d72903 | 2023-05-29 15:12:22 -0700 | [diff] [blame] | 1107 | * @sq_mutex: prevent submission queue concurrent access |
Asutosh Das | 4682abf | 2023-01-13 12:48:44 -0800 | [diff] [blame] | 1108 | */ |
| 1109 | struct ufs_hw_queue { |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1110 | void __iomem *mcq_sq_head; |
| 1111 | void __iomem *mcq_sq_tail; |
| 1112 | void __iomem *mcq_cq_head; |
| 1113 | void __iomem *mcq_cq_tail; |
| 1114 | |
Avri Altman | 3c85f08 | 2023-03-29 13:13:03 +0300 | [diff] [blame] | 1115 | struct utp_transfer_req_desc *sqe_base_addr; |
Asutosh Das | 4682abf | 2023-01-13 12:48:44 -0800 | [diff] [blame] | 1116 | dma_addr_t sqe_dma_addr; |
| 1117 | struct cq_entry *cqe_base_addr; |
| 1118 | dma_addr_t cqe_dma_addr; |
| 1119 | u32 max_entries; |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1120 | u32 id; |
Asutosh Das | 22a2d56 | 2023-01-13 12:48:47 -0800 | [diff] [blame] | 1121 | u32 sq_tail_slot; |
| 1122 | spinlock_t sq_lock; |
Asutosh Das | f87b2c4 | 2023-01-13 12:48:50 -0800 | [diff] [blame] | 1123 | u32 cq_tail_slot; |
| 1124 | u32 cq_head_slot; |
Asutosh Das | ed97506 | 2023-01-13 12:48:51 -0800 | [diff] [blame] | 1125 | spinlock_t cq_lock; |
Bao D. Nguyen | 8d72903 | 2023-05-29 15:12:22 -0700 | [diff] [blame] | 1126 | /* prevent concurrent access to submission queue */ |
| 1127 | struct mutex sq_mutex; |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 1128 | }; |
| 1129 | |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1130 | static inline bool is_mcq_enabled(struct ufs_hba *hba) |
| 1131 | { |
| 1132 | return hba->mcq_enabled; |
| 1133 | } |
| 1134 | |
Eric Biggers | ada1e65 | 2022-12-08 15:43:58 -0800 | [diff] [blame] | 1135 | #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE |
| 1136 | static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) |
| 1137 | { |
| 1138 | return hba->sg_entry_size; |
| 1139 | } |
| 1140 | |
| 1141 | static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) |
| 1142 | { |
| 1143 | WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); |
| 1144 | hba->sg_entry_size = sg_entry_size; |
| 1145 | } |
| 1146 | #else |
| 1147 | static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) |
| 1148 | { |
| 1149 | return sizeof(struct ufshcd_sg_entry); |
| 1150 | } |
| 1151 | |
| 1152 | #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ |
| 1153 | ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) |
| 1154 | #endif |
| 1155 | |
Po-Wen Kao | 06caeb5 | 2023-05-04 23:44:50 +0800 | [diff] [blame] | 1156 | static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) |
Eric Biggers | ada1e65 | 2022-12-08 15:43:58 -0800 | [diff] [blame] | 1157 | { |
| 1158 | return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); |
| 1159 | } |
| 1160 | |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 1161 | /* Returns true if clocks can be gated. Otherwise false */ |
| 1162 | static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) |
| 1163 | { |
| 1164 | return hba->caps & UFSHCD_CAP_CLK_GATING; |
| 1165 | } |
| 1166 | static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) |
| 1167 | { |
| 1168 | return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; |
| 1169 | } |
Sahitya Tummala | fcb0c4b | 2016-12-22 18:40:50 -0800 | [diff] [blame] | 1170 | static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) |
Sahitya Tummala | 856b348 | 2014-09-25 15:32:34 +0300 | [diff] [blame] | 1171 | { |
| 1172 | return hba->caps & UFSHCD_CAP_CLK_SCALING; |
| 1173 | } |
Subhash Jadavani | 374a246 | 2014-09-25 15:32:35 +0300 | [diff] [blame] | 1174 | static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) |
| 1175 | { |
| 1176 | return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; |
| 1177 | } |
Stanley Chu | 49615ba | 2019-09-16 23:56:50 +0800 | [diff] [blame] | 1178 | static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) |
| 1179 | { |
| 1180 | return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; |
| 1181 | } |
Subhash Jadavani | 374a246 | 2014-09-25 15:32:35 +0300 | [diff] [blame] | 1182 | |
Yaniv Gardi | b852190 | 2015-05-17 18:54:57 +0300 | [diff] [blame] | 1183 | static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) |
| 1184 | { |
Keoseong Park | 1c0810e | 2021-06-28 14:58:01 +0900 | [diff] [blame] | 1185 | return (hba->caps & UFSHCD_CAP_INTR_AGGR) && |
| 1186 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); |
Yaniv Gardi | b852190 | 2015-05-17 18:54:57 +0300 | [diff] [blame] | 1187 | } |
| 1188 | |
Can Guo | dd7143e | 2020-10-27 12:10:36 -0700 | [diff] [blame] | 1189 | static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) |
| 1190 | { |
| 1191 | return !!(ufshcd_is_link_hibern8(hba) && |
| 1192 | (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); |
| 1193 | } |
| 1194 | |
Stanley Chu | ee5f104 | 2019-05-21 14:44:52 +0800 | [diff] [blame] | 1195 | static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) |
| 1196 | { |
Adrian Hunter | 8da76f7 | 2020-08-10 17:10:24 +0300 | [diff] [blame] | 1197 | return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && |
| 1198 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); |
Stanley Chu | ee5f104 | 2019-05-21 14:44:52 +0800 | [diff] [blame] | 1199 | } |
| 1200 | |
Stanley Chu | 5a244e0 | 2020-01-29 18:52:50 +0800 | [diff] [blame] | 1201 | static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) |
| 1202 | { |
Bart Van Assche | 51d1628 | 2022-04-19 15:57:46 -0700 | [diff] [blame] | 1203 | return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); |
Stanley Chu | 5a244e0 | 2020-01-29 18:52:50 +0800 | [diff] [blame] | 1204 | } |
| 1205 | |
Asutosh Das | 3d17b9b | 2020-04-22 14:41:42 -0700 | [diff] [blame] | 1206 | static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) |
| 1207 | { |
| 1208 | return hba->caps & UFSHCD_CAP_WB_EN; |
| 1209 | } |
| 1210 | |
Peter Wang | 87bd050 | 2022-08-04 10:54:22 +0800 | [diff] [blame] | 1211 | static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) |
| 1212 | { |
| 1213 | return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; |
| 1214 | } |
| 1215 | |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1216 | #define ufsmcq_writel(hba, val, reg) \ |
| 1217 | writel((val), (hba)->mcq_base + (reg)) |
| 1218 | #define ufsmcq_readl(hba, reg) \ |
| 1219 | readl((hba)->mcq_base + (reg)) |
| 1220 | |
| 1221 | #define ufsmcq_writelx(hba, val, reg) \ |
| 1222 | writel_relaxed((val), (hba)->mcq_base + (reg)) |
| 1223 | #define ufsmcq_readlx(hba, reg) \ |
| 1224 | readl_relaxed((hba)->mcq_base + (reg)) |
| 1225 | |
Seungwon Jeon | b873a275 | 2013-06-26 22:39:26 +0530 | [diff] [blame] | 1226 | #define ufshcd_writel(hba, val, reg) \ |
| 1227 | writel((val), (hba)->mmio_base + (reg)) |
| 1228 | #define ufshcd_readl(hba, reg) \ |
| 1229 | readl((hba)->mmio_base + (reg)) |
| 1230 | |
Dolev Raviv | e785060 | 2014-09-25 15:32:36 +0300 | [diff] [blame] | 1231 | /** |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 1232 | * ufshcd_rmwl - perform read/modify/write for a controller register |
| 1233 | * @hba: per adapter instance |
| 1234 | * @mask: mask to apply on read value |
| 1235 | * @val: actual value to write |
| 1236 | * @reg: register address |
Dolev Raviv | e785060 | 2014-09-25 15:32:36 +0300 | [diff] [blame] | 1237 | */ |
| 1238 | static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) |
| 1239 | { |
| 1240 | u32 tmp; |
| 1241 | |
| 1242 | tmp = ufshcd_readl(hba, reg); |
| 1243 | tmp &= ~mask; |
| 1244 | tmp |= (val & mask); |
| 1245 | ufshcd_writel(hba, tmp, reg); |
| 1246 | } |
| 1247 | |
Manivannan Sadhasivam | 0ae7a02 | 2023-12-08 12:28:51 +0530 | [diff] [blame] | 1248 | void ufshcd_enable_irq(struct ufs_hba *hba); |
| 1249 | void ufshcd_disable_irq(struct ufs_hba *hba); |
Sujit Reddy Thumma | 5c0c28a | 2014-09-25 15:32:21 +0300 | [diff] [blame] | 1250 | int ufshcd_alloc_host(struct device *, struct ufs_hba **); |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1251 | void ufshcd_dealloc_host(struct ufs_hba *); |
Stanley Chu | 9d19bf7a | 2020-01-17 11:51:07 +0800 | [diff] [blame] | 1252 | int ufshcd_hba_enable(struct ufs_hba *hba); |
Keoseong Park | ecd7beb | 2021-05-18 21:12:17 +0900 | [diff] [blame] | 1253 | int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); |
Stanley Chu | 087c5ef | 2020-03-27 17:53:28 +0800 | [diff] [blame] | 1254 | int ufshcd_link_recovery(struct ufs_hba *hba); |
Stanley Chu | 9d19bf7a | 2020-01-17 11:51:07 +0800 | [diff] [blame] | 1255 | int ufshcd_make_hba_operational(struct ufs_hba *hba); |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 1256 | void ufshcd_remove(struct ufs_hba *); |
Asutosh Das | 525943a | 2021-09-28 02:06:12 -0700 | [diff] [blame] | 1257 | int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); |
Stanley Chu | 9d19bf7a | 2020-01-17 11:51:07 +0800 | [diff] [blame] | 1258 | int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); |
Stanley Chu | 5c955c1 | 2020-03-18 18:40:12 +0800 | [diff] [blame] | 1259 | void ufshcd_delay_us(unsigned long us, unsigned long tolerance); |
Subhash Jadavani | 9e1e8a75 | 2018-10-16 14:29:41 +0530 | [diff] [blame] | 1260 | void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); |
Stanley Chu | e965e5e | 2020-12-05 19:58:59 +0800 | [diff] [blame] | 1261 | void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); |
Alice.Chao | 3a95f5b | 2021-05-28 11:36:21 +0800 | [diff] [blame] | 1262 | void ufshcd_hba_stop(struct ufs_hba *hba); |
Bart Van Assche | 267a59f | 2021-10-20 14:40:19 -0700 | [diff] [blame] | 1263 | void ufshcd_schedule_eh_work(struct ufs_hba *hba); |
Po-Wen Kao | 11afb65 | 2023-07-01 20:44:40 +0800 | [diff] [blame] | 1264 | void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); |
| 1265 | u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); |
Can Guo | e02288e | 2022-12-14 19:06:21 -0800 | [diff] [blame] | 1266 | void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); |
Bao D. Nguyen | 57d6ef4 | 2023-05-29 15:12:25 -0700 | [diff] [blame] | 1267 | unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, |
Can Guo | e02288e | 2022-12-14 19:06:21 -0800 | [diff] [blame] | 1268 | struct ufs_hw_queue *hwq); |
Po-Wen Kao | 11afb65 | 2023-07-01 20:44:40 +0800 | [diff] [blame] | 1269 | void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); |
Can Guo | e02288e | 2022-12-14 19:06:21 -0800 | [diff] [blame] | 1270 | void ufshcd_mcq_enable_esi(struct ufs_hba *hba); |
ChanWoo Lee | ab3e6c4 | 2024-01-02 10:42:22 +0900 | [diff] [blame] | 1271 | void ufshcd_mcq_enable(struct ufs_hba *hba); |
Can Guo | e02288e | 2022-12-14 19:06:21 -0800 | [diff] [blame] | 1272 | void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 1273 | |
Manivannan Sadhasivam | 72208eb | 2023-10-12 22:51:27 +0530 | [diff] [blame] | 1274 | int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, |
| 1275 | struct dev_pm_opp *opp, void *data, |
| 1276 | bool scaling_down); |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 1277 | /** |
| 1278 | * ufshcd_set_variant - set variant specific data to the hba |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 1279 | * @hba: per adapter instance |
| 1280 | * @variant: pointer to variant specific data |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 1281 | */ |
| 1282 | static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) |
| 1283 | { |
| 1284 | BUG_ON(!hba); |
| 1285 | hba->priv = variant; |
| 1286 | } |
| 1287 | |
| 1288 | /** |
| 1289 | * ufshcd_get_variant - get variant specific data from the hba |
Bart Van Assche | cff91da | 2022-04-19 15:58:07 -0700 | [diff] [blame] | 1290 | * @hba: per adapter instance |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 1291 | */ |
| 1292 | static inline void *ufshcd_get_variant(struct ufs_hba *hba) |
| 1293 | { |
| 1294 | BUG_ON(!hba); |
| 1295 | return hba->priv; |
| 1296 | } |
Avri Altman | e88e2d3 | 2021-09-15 09:04:06 +0300 | [diff] [blame] | 1297 | |
Bart Van Assche | 9bb25e5 | 2021-07-21 20:34:24 -0700 | [diff] [blame] | 1298 | #ifdef CONFIG_PM |
Bart Van Assche | f1ecbe1 | 2021-07-21 20:34:23 -0700 | [diff] [blame] | 1299 | extern int ufshcd_runtime_suspend(struct device *dev); |
| 1300 | extern int ufshcd_runtime_resume(struct device *dev); |
Bart Van Assche | 9bb25e5 | 2021-07-21 20:34:24 -0700 | [diff] [blame] | 1301 | #endif |
| 1302 | #ifdef CONFIG_PM_SLEEP |
Bart Van Assche | f1ecbe1 | 2021-07-21 20:34:23 -0700 | [diff] [blame] | 1303 | extern int ufshcd_system_suspend(struct device *dev); |
| 1304 | extern int ufshcd_system_resume(struct device *dev); |
Anjana Hari | 88441a8 | 2023-02-02 21:40:45 +0530 | [diff] [blame] | 1305 | extern int ufshcd_system_freeze(struct device *dev); |
| 1306 | extern int ufshcd_system_thaw(struct device *dev); |
| 1307 | extern int ufshcd_system_restore(struct device *dev); |
Bart Van Assche | 9bb25e5 | 2021-07-21 20:34:24 -0700 | [diff] [blame] | 1308 | #endif |
Anjana Hari | 88441a8 | 2023-02-02 21:40:45 +0530 | [diff] [blame] | 1309 | |
Stanley Chu | fc85a74e | 2020-11-16 14:50:52 +0800 | [diff] [blame] | 1310 | extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, |
| 1311 | int agreed_gear, |
| 1312 | int adapt_val); |
Seungwon Jeon | 12b4fdb | 2013-08-31 21:40:21 +0530 | [diff] [blame] | 1313 | extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, |
| 1314 | u8 attr_set, u32 mib_val, u8 peer); |
| 1315 | extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, |
| 1316 | u32 *mib_val, u8 peer); |
Alim Akhtar | 0d846e7 | 2018-05-06 15:44:18 +0530 | [diff] [blame] | 1317 | extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, |
| 1318 | struct ufs_pa_layer_attr *desired_pwr_mode); |
Stanley Chu | fc53683b | 2022-06-16 13:37:15 +0800 | [diff] [blame] | 1319 | extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); |
Seungwon Jeon | 12b4fdb | 2013-08-31 21:40:21 +0530 | [diff] [blame] | 1320 | |
| 1321 | /* UIC command interfaces for DME primitives */ |
| 1322 | #define DME_LOCAL 0 |
| 1323 | #define DME_PEER 1 |
| 1324 | #define ATTR_SET_NOR 0 /* NORMAL */ |
| 1325 | #define ATTR_SET_ST 1 /* STATIC */ |
| 1326 | |
| 1327 | static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, |
| 1328 | u32 mib_val) |
| 1329 | { |
| 1330 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, |
| 1331 | mib_val, DME_LOCAL); |
| 1332 | } |
| 1333 | |
| 1334 | static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, |
| 1335 | u32 mib_val) |
| 1336 | { |
| 1337 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, |
| 1338 | mib_val, DME_LOCAL); |
| 1339 | } |
| 1340 | |
| 1341 | static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, |
| 1342 | u32 mib_val) |
| 1343 | { |
| 1344 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, |
| 1345 | mib_val, DME_PEER); |
| 1346 | } |
| 1347 | |
| 1348 | static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, |
| 1349 | u32 mib_val) |
| 1350 | { |
| 1351 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, |
| 1352 | mib_val, DME_PEER); |
| 1353 | } |
| 1354 | |
| 1355 | static inline int ufshcd_dme_get(struct ufs_hba *hba, |
| 1356 | u32 attr_sel, u32 *mib_val) |
| 1357 | { |
| 1358 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); |
| 1359 | } |
| 1360 | |
| 1361 | static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, |
| 1362 | u32 attr_sel, u32 *mib_val) |
| 1363 | { |
| 1364 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); |
| 1365 | } |
| 1366 | |
Yaniv Gardi | f37aabc | 2016-03-10 17:37:20 +0200 | [diff] [blame] | 1367 | static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) |
| 1368 | { |
| 1369 | return (pwr_info->pwr_rx == FAST_MODE || |
| 1370 | pwr_info->pwr_rx == FASTAUTO_MODE) && |
| 1371 | (pwr_info->pwr_tx == FAST_MODE || |
| 1372 | pwr_info->pwr_tx == FASTAUTO_MODE); |
| 1373 | } |
| 1374 | |
Stanley Chu | 984eaac | 2020-02-07 15:03:57 +0800 | [diff] [blame] | 1375 | static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) |
| 1376 | { |
| 1377 | return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); |
| 1378 | } |
| 1379 | |
Stanley Chu | ba7af5e | 2019-12-30 13:32:28 +0800 | [diff] [blame] | 1380 | void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); |
Bart Van Assche | aead21f | 2022-04-19 15:57:53 -0700 | [diff] [blame] | 1381 | void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, |
| 1382 | const struct ufs_dev_quirk *fixups); |
Tomas Winkler | 4b828fe | 2019-07-30 08:55:17 +0300 | [diff] [blame] | 1383 | #define SD_ASCII_STD true |
| 1384 | #define SD_RAW false |
| 1385 | int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, |
| 1386 | u8 **buf, bool ascii); |
Stanislav Nijnikov | 2238d31 | 2018-02-15 14:14:07 +0200 | [diff] [blame] | 1387 | |
Bart Van Assche | 078f4f4 | 2023-05-29 13:26:40 -0700 | [diff] [blame] | 1388 | void ufshcd_hold(struct ufs_hba *hba); |
Sahitya Tummala | 1ab27c9 | 2014-09-25 15:32:32 +0300 | [diff] [blame] | 1389 | void ufshcd_release(struct ufs_hba *hba); |
Potomski, MichalX | a4b0e8a | 2017-02-23 09:05:30 +0000 | [diff] [blame] | 1390 | |
Bart Van Assche | ad8a647 | 2022-04-19 15:58:04 -0700 | [diff] [blame] | 1391 | void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); |
| 1392 | |
Yaniv Gardi | 3711310 | 2016-03-10 17:37:16 +0200 | [diff] [blame] | 1393 | u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); |
Yaniv Gardi | 0263bcd | 2015-10-28 13:15:48 +0200 | [diff] [blame] | 1394 | |
Stanley Chu | 1d6f9de | 2022-06-16 13:37:23 +0800 | [diff] [blame] | 1395 | int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); |
| 1396 | |
Avri Altman | e77044c5 | 2018-10-07 17:30:39 +0300 | [diff] [blame] | 1397 | int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); |
| 1398 | |
Bean Huo | 6ff265fc | 2022-12-01 15:04:37 +0100 | [diff] [blame] | 1399 | int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, |
| 1400 | struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, |
| 1401 | struct ufs_ehs *ehs_rsp, int sg_cnt, |
| 1402 | struct scatterlist *sg_list, enum dma_data_direction dir); |
Yue Hu | 3b5f3c0 | 2021-03-18 17:55:36 +0800 | [diff] [blame] | 1403 | int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); |
Jinyoung Choi | 6c4148c | 2022-08-04 16:53:54 +0900 | [diff] [blame] | 1404 | int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); |
Asutosh Das | b294ff3 | 2021-04-23 17:20:16 -0700 | [diff] [blame] | 1405 | int ufshcd_suspend_prepare(struct device *dev); |
Adrian Hunter | ddba1cf | 2021-10-27 16:06:14 +0300 | [diff] [blame] | 1406 | int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); |
Asutosh Das | b294ff3 | 2021-04-23 17:20:16 -0700 | [diff] [blame] | 1407 | void ufshcd_resume_complete(struct device *dev); |
Nitin Rawat | 548fdf7 | 2023-07-26 19:11:39 +0530 | [diff] [blame] | 1408 | bool ufshcd_is_hba_active(struct ufs_hba *hba); |
Maramaina Naresh | 2777e73 | 2023-12-19 18:07:05 +0530 | [diff] [blame] | 1409 | void ufshcd_pm_qos_init(struct ufs_hba *hba); |
| 1410 | void ufshcd_pm_qos_exit(struct ufs_hba *hba); |
Bean Huo | 8e834ca | 2021-01-19 17:38:42 +0100 | [diff] [blame] | 1411 | |
Yaniv Gardi | 0263bcd | 2015-10-28 13:15:48 +0200 | [diff] [blame] | 1412 | /* Wrapper functions for safely calling variant operations */ |
Yaniv Gardi | 0263bcd | 2015-10-28 13:15:48 +0200 | [diff] [blame] | 1413 | static inline int ufshcd_vops_init(struct ufs_hba *hba) |
| 1414 | { |
| 1415 | if (hba->vops && hba->vops->init) |
| 1416 | return hba->vops->init(hba); |
| 1417 | |
| 1418 | return 0; |
| 1419 | } |
| 1420 | |
Stanley Chu | 92bcebe | 2020-12-05 20:00:39 +0800 | [diff] [blame] | 1421 | static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) |
| 1422 | { |
| 1423 | if (hba->vops && hba->vops->phy_initialization) |
| 1424 | return hba->vops->phy_initialization(hba); |
| 1425 | |
| 1426 | return 0; |
| 1427 | } |
| 1428 | |
Krzysztof Kozlowski | 35d11ec | 2022-06-23 12:24:32 +0200 | [diff] [blame] | 1429 | extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; |
Stanislav Nijnikov | cbb6813 | 2018-02-15 14:14:01 +0200 | [diff] [blame] | 1430 | |
Tomas Winkler | ba80917 | 2018-06-14 11:14:09 +0300 | [diff] [blame] | 1431 | int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, |
| 1432 | const char *prefix); |
| 1433 | |
Adrian Hunter | 7deedfd | 2021-02-09 08:24:37 +0200 | [diff] [blame] | 1434 | int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); |
| 1435 | int ufshcd_write_ee_control(struct ufs_hba *hba); |
Krzysztof Kozlowski | 35d11ec | 2022-06-23 12:24:32 +0200 | [diff] [blame] | 1436 | int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, |
| 1437 | const u16 *other_mask, u16 set, u16 clr); |
Adrian Hunter | cd46947 | 2021-02-09 08:24:36 +0200 | [diff] [blame] | 1438 | |
Vinayak Holikatti | e0eca63 | 2013-02-25 21:44:33 +0530 | [diff] [blame] | 1439 | #endif /* End of Header */ |