blob: 70fa18b04ad2bed52efa0be5e72dc416b637364a [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Daniel Ribeiro13a09f92009-05-28 15:43:37 -03002/*
3 * Driver for Motorola PCAP2 as present in EZX phones
4 *
5 * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
6 * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
Daniel Ribeiro13a09f92009-05-28 15:43:37 -03007 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/mfd/ezx-pcap.h>
15#include <linux/spi/spi.h>
Daniel Ribeirob1148fd2009-06-23 12:34:13 -030016#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090017#include <linux/slab.h>
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030018
19#define PCAP_ADC_MAXQ 8
20struct pcap_adc_request {
21 u8 bank;
22 u8 ch[2];
23 u32 flags;
24 void (*callback)(void *, u16[]);
25 void *data;
26};
27
28struct pcap_adc_sync_request {
29 u16 res[2];
30 struct completion completion;
31};
32
33struct pcap_chip {
34 struct spi_device *spi;
35
36 /* IO */
37 u32 buf;
Fuqian Huangb65dc4f2019-08-13 18:31:33 +080038 spinlock_t io_lock;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030039
40 /* IRQ */
41 unsigned int irq_base;
42 u32 msr;
43 struct work_struct isr_work;
44 struct work_struct msr_work;
45 struct workqueue_struct *workqueue;
46
47 /* ADC */
48 struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
49 u8 adc_head;
50 u8 adc_tail;
Fuqian Huangb65dc4f2019-08-13 18:31:33 +080051 spinlock_t adc_lock;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030052};
53
54/* IO */
55static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
56{
57 struct spi_transfer t;
58 struct spi_message m;
59 int status;
60
Lee Jones03095282014-07-25 15:31:02 +010061 memset(&t, 0, sizeof(t));
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030062 spi_message_init(&m);
63 t.len = sizeof(u32);
64 spi_message_add_tail(&t, &m);
65
66 pcap->buf = *data;
67 t.tx_buf = (u8 *) &pcap->buf;
68 t.rx_buf = (u8 *) &pcap->buf;
69 status = spi_sync(pcap->spi, &m);
70
71 if (status == 0)
72 *data = pcap->buf;
73
74 return status;
75}
76
77int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
78{
Fuqian Huangb65dc4f2019-08-13 18:31:33 +080079 unsigned long flags;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030080 int ret;
81
Fuqian Huangb65dc4f2019-08-13 18:31:33 +080082 spin_lock_irqsave(&pcap->io_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030083 value &= PCAP_REGISTER_VALUE_MASK;
84 value |= PCAP_REGISTER_WRITE_OP_BIT
85 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
86 ret = ezx_pcap_putget(pcap, &value);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +080087 spin_unlock_irqrestore(&pcap->io_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030088
89 return ret;
90}
91EXPORT_SYMBOL_GPL(ezx_pcap_write);
92
93int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
94{
Fuqian Huangb65dc4f2019-08-13 18:31:33 +080095 unsigned long flags;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030096 int ret;
97
Fuqian Huangb65dc4f2019-08-13 18:31:33 +080098 spin_lock_irqsave(&pcap->io_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -030099 *value = PCAP_REGISTER_READ_OP_BIT
100 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
101
102 ret = ezx_pcap_putget(pcap, value);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800103 spin_unlock_irqrestore(&pcap->io_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300104
105 return ret;
106}
107EXPORT_SYMBOL_GPL(ezx_pcap_read);
108
Daniel Ribeiroe9a22632009-06-27 00:17:20 -0300109int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
110{
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800111 unsigned long flags;
Daniel Ribeiroe9a22632009-06-27 00:17:20 -0300112 int ret;
113 u32 tmp = PCAP_REGISTER_READ_OP_BIT |
114 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
115
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800116 spin_lock_irqsave(&pcap->io_lock, flags);
Daniel Ribeiroe9a22632009-06-27 00:17:20 -0300117 ret = ezx_pcap_putget(pcap, &tmp);
118 if (ret)
119 goto out_unlock;
120
121 tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
122 tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
123 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
124
125 ret = ezx_pcap_putget(pcap, &tmp);
126out_unlock:
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800127 spin_unlock_irqrestore(&pcap->io_lock, flags);
Daniel Ribeiroe9a22632009-06-27 00:17:20 -0300128
129 return ret;
130}
131EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
132
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300133/* IRQ */
Daniel Ribeiro9f7b07d2009-06-23 12:32:11 -0300134int irq_to_pcap(struct pcap_chip *pcap, int irq)
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300135{
Daniel Ribeiro9f7b07d2009-06-23 12:32:11 -0300136 return irq - pcap->irq_base;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300137}
Daniel Ribeiro9f7b07d2009-06-23 12:32:11 -0300138EXPORT_SYMBOL_GPL(irq_to_pcap);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300139
140int pcap_to_irq(struct pcap_chip *pcap, int irq)
141{
142 return pcap->irq_base + irq;
143}
144EXPORT_SYMBOL_GPL(pcap_to_irq);
145
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100146static void pcap_mask_irq(struct irq_data *d)
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300147{
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100148 struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300149
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100150 pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300151 queue_work(pcap->workqueue, &pcap->msr_work);
152}
153
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100154static void pcap_unmask_irq(struct irq_data *d)
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300155{
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100156 struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300157
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100158 pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300159 queue_work(pcap->workqueue, &pcap->msr_work);
160}
161
162static struct irq_chip pcap_irq_chip = {
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100163 .name = "pcap",
Thomas Gleixner73a68392011-03-25 11:12:27 +0000164 .irq_disable = pcap_mask_irq,
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100165 .irq_mask = pcap_mask_irq,
166 .irq_unmask = pcap_unmask_irq,
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300167};
168
169static void pcap_msr_work(struct work_struct *work)
170{
171 struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
172
173 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
174}
175
176static void pcap_isr_work(struct work_struct *work)
177{
178 struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
Jingoo Han334a41ce2013-07-30 17:10:05 +0900179 struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300180 u32 msr, isr, int_sel, service;
181 int irq;
182
Daniel Ribeirob1148fd2009-06-23 12:34:13 -0300183 do {
184 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
185 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300186
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300187 /* We can't service/ack irqs that are assigned to port 2 */
Daniel Ribeirob1148fd2009-06-23 12:34:13 -0300188 if (!(pdata->config & PCAP_SECOND_PORT)) {
189 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
190 isr &= ~int_sel;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300191 }
Daniel Ribeirob1148fd2009-06-23 12:34:13 -0300192
193 ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
194 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
195
196 local_irq_disable();
197 service = isr & ~msr;
198 for (irq = pcap->irq_base; service; service >>= 1, irq++) {
Thomas Gleixner73a68392011-03-25 11:12:27 +0000199 if (service & 1)
200 generic_handle_irq(irq);
Daniel Ribeirob1148fd2009-06-23 12:34:13 -0300201 }
202 local_irq_enable();
203 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
Arnd Bergmann59ee93a2012-08-05 14:58:37 +0000204 } while (gpio_get_value(pdata->gpio));
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300205}
206
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200207static void pcap_irq_handler(struct irq_desc *desc)
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300208{
Jiang Liu1e84aa42015-07-13 20:44:56 +0000209 struct pcap_chip *pcap = irq_desc_get_handler_data(desc);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300210
Lennert Buytenhekc232f222010-12-13 13:30:09 +0100211 desc->irq_data.chip->irq_ack(&desc->irq_data);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300212 queue_work(pcap->workqueue, &pcap->isr_work);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300213}
214
215/* ADC */
Daniel Ribeiroecd78cb2009-06-23 12:33:10 -0300216void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
217{
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800218 unsigned long flags;
Daniel Ribeiroecd78cb2009-06-23 12:33:10 -0300219 u32 tmp;
220
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800221 spin_lock_irqsave(&pcap->adc_lock, flags);
Daniel Ribeiroecd78cb2009-06-23 12:33:10 -0300222 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
223 tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
224 tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
225 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800226 spin_unlock_irqrestore(&pcap->adc_lock, flags);
Daniel Ribeiroecd78cb2009-06-23 12:33:10 -0300227}
228EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
229
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300230static void pcap_disable_adc(struct pcap_chip *pcap)
231{
232 u32 tmp;
233
234 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
235 tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
236 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
237}
238
239static void pcap_adc_trigger(struct pcap_chip *pcap)
240{
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800241 unsigned long flags;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300242 u32 tmp;
243 u8 head;
244
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800245 spin_lock_irqsave(&pcap->adc_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300246 head = pcap->adc_head;
247 if (!pcap->adc_queue[head]) {
248 /* queue is empty, save power */
249 pcap_disable_adc(pcap);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800250 spin_unlock_irqrestore(&pcap->adc_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300251 return;
252 }
Daniel Ribeiroecd78cb2009-06-23 12:33:10 -0300253 /* start conversion on requested bank, save TS_M bits */
254 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
255 tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
256 tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300257
258 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
259 tmp |= PCAP_ADC_AD_SEL1;
260
261 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800262 spin_unlock_irqrestore(&pcap->adc_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300263 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
264}
265
266static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
267{
268 struct pcap_chip *pcap = _pcap;
269 struct pcap_adc_request *req;
270 u16 res[2];
271 u32 tmp;
272
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800273 spin_lock(&pcap->adc_lock);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300274 req = pcap->adc_queue[pcap->adc_head];
275
Joe Perchese0084aa2010-10-30 14:08:32 -0700276 if (WARN(!req, "adc irq without pending request\n")) {
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800277 spin_unlock(&pcap->adc_lock);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300278 return IRQ_HANDLED;
Daniel Ribeiro1c90ea22009-06-23 12:30:58 -0300279 }
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300280
281 /* read requested channels results */
282 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
283 tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
284 tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
285 tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
286 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
287 ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
288 res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
289 res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
290
291 pcap->adc_queue[pcap->adc_head] = NULL;
292 pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800293 spin_unlock(&pcap->adc_lock);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300294
295 /* pass the results and release memory */
296 req->callback(req->data, res);
297 kfree(req);
298
299 /* trigger next conversion (if any) on queue */
300 pcap_adc_trigger(pcap);
301
302 return IRQ_HANDLED;
303}
304
305int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
306 void *callback, void *data)
307{
308 struct pcap_adc_request *req;
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800309 unsigned long irq_flags;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300310
311 /* This will be freed after we have a result */
312 req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
313 if (!req)
314 return -ENOMEM;
315
316 req->bank = bank;
317 req->flags = flags;
318 req->ch[0] = ch[0];
319 req->ch[1] = ch[1];
320 req->callback = callback;
321 req->data = data;
322
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800323 spin_lock_irqsave(&pcap->adc_lock, irq_flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300324 if (pcap->adc_queue[pcap->adc_tail]) {
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800325 spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300326 kfree(req);
327 return -EBUSY;
328 }
329 pcap->adc_queue[pcap->adc_tail] = req;
330 pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800331 spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300332
333 /* start conversion */
334 pcap_adc_trigger(pcap);
335
336 return 0;
337}
338EXPORT_SYMBOL_GPL(pcap_adc_async);
339
340static void pcap_adc_sync_cb(void *param, u16 res[])
341{
342 struct pcap_adc_sync_request *req = param;
343
344 req->res[0] = res[0];
345 req->res[1] = res[1];
346 complete(&req->completion);
347}
348
349int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
350 u16 res[])
351{
352 struct pcap_adc_sync_request sync_data;
353 int ret;
354
355 init_completion(&sync_data.completion);
356 ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
357 &sync_data);
358 if (ret)
359 return ret;
360 wait_for_completion(&sync_data.completion);
361 res[0] = sync_data.res[0];
362 res[1] = sync_data.res[1];
363
364 return 0;
365}
366EXPORT_SYMBOL_GPL(pcap_adc_sync);
367
368/* subdevs */
369static int pcap_remove_subdev(struct device *dev, void *unused)
370{
371 platform_device_unregister(to_platform_device(dev));
372 return 0;
373}
374
Bill Pembertonf791be42012-11-19 13:23:04 -0500375static int pcap_add_subdev(struct pcap_chip *pcap,
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300376 struct pcap_subdev *subdev)
377{
378 struct platform_device *pdev;
Axel Lin09ff21e2010-08-24 13:45:49 +0800379 int ret;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300380
381 pdev = platform_device_alloc(subdev->name, subdev->id);
Axel Lin09ff21e2010-08-24 13:45:49 +0800382 if (!pdev)
383 return -ENOMEM;
384
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300385 pdev->dev.parent = &pcap->spi->dev;
386 pdev->dev.platform_data = subdev->platform_data;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300387
Axel Lin09ff21e2010-08-24 13:45:49 +0800388 ret = platform_device_add(pdev);
389 if (ret)
390 platform_device_put(pdev);
391
392 return ret;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300393}
394
Bill Pemberton4740f732012-11-19 13:26:01 -0500395static int ezx_pcap_remove(struct spi_device *spi)
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300396{
Jingoo Han7c478b42013-04-06 15:43:48 +0900397 struct pcap_chip *pcap = spi_get_drvdata(spi);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800398 unsigned long flags;
Wei Yongjun89720262013-09-25 15:37:45 +0800399 int i;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300400
401 /* remove all registered subdevs */
402 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
403
404 /* cleanup ADC */
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800405 spin_lock_irqsave(&pcap->adc_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300406 for (i = 0; i < PCAP_ADC_MAXQ; i++)
407 kfree(pcap->adc_queue[i]);
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800408 spin_unlock_irqrestore(&pcap->adc_lock, flags);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300409
410 /* cleanup irqchip */
411 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000412 irq_set_chip_and_handler(i, NULL, NULL);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300413
414 destroy_workqueue(pcap->workqueue);
415
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300416 return 0;
417}
418
Bill Pembertonf791be42012-11-19 13:23:04 -0500419static int ezx_pcap_probe(struct spi_device *spi)
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300420{
Jingoo Han334a41ce2013-07-30 17:10:05 +0900421 struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300422 struct pcap_chip *pcap;
423 int i, adc_irq;
424 int ret = -ENODEV;
425
426 /* platform data is required */
427 if (!pdata)
428 goto ret;
429
Jingoo Han1ba895e2013-02-20 18:30:55 +0900430 pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300431 if (!pcap) {
432 ret = -ENOMEM;
433 goto ret;
434 }
435
Fuqian Huangb65dc4f2019-08-13 18:31:33 +0800436 spin_lock_init(&pcap->io_lock);
437 spin_lock_init(&pcap->adc_lock);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300438 INIT_WORK(&pcap->isr_work, pcap_isr_work);
439 INIT_WORK(&pcap->msr_work, pcap_msr_work);
Jingoo Han7c478b42013-04-06 15:43:48 +0900440 spi_set_drvdata(spi, pcap);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300441
442 /* setup spi */
443 spi->bits_per_word = 32;
444 spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
445 ret = spi_setup(spi);
446 if (ret)
Jingoo Han1ba895e2013-02-20 18:30:55 +0900447 goto ret;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300448
449 pcap->spi = spi;
450
451 /* setup irq */
452 pcap->irq_base = pdata->irq_base;
453 pcap->workqueue = create_singlethread_workqueue("pcapd");
454 if (!pcap->workqueue) {
Axel Lin47dabae2010-10-19 20:28:24 +0800455 ret = -ENOMEM;
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300456 dev_err(&spi->dev, "can't create pcap thread\n");
Jingoo Han1ba895e2013-02-20 18:30:55 +0900457 goto ret;
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300458 }
459
460 /* redirect interrupts to AP, except adcdone2 */
461 if (!(pdata->config & PCAP_SECOND_PORT))
462 ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
463 (1 << PCAP_IRQ_ADCDONE2));
464
465 /* setup irq chip */
466 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000467 irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
468 irq_set_chip_data(i, pcap);
Rob Herring9bd09f32015-07-27 15:55:20 -0500469 irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300470 }
471
472 /* mask/ack all PCAP interrupts */
473 ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
474 ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
475 pcap->msr = PCAP_MASK_ALL_INTERRUPT;
476
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000477 irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
Thomas Gleixnerc89fc9a2015-07-13 20:44:46 +0000478 irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000479 irq_set_irq_wake(spi->irq, 1);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300480
481 /* ADC */
482 adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
483 PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
484
Jingoo Han1ba895e2013-02-20 18:30:55 +0900485 ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
486 pcap);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300487 if (ret)
488 goto free_irqchip;
489
490 /* setup subdevs */
491 for (i = 0; i < pdata->num_subdevs; i++) {
492 ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
493 if (ret)
494 goto remove_subdevs;
495 }
496
497 /* board specific quirks */
498 if (pdata->init)
499 pdata->init(pcap);
500
501 return 0;
502
503remove_subdevs:
504 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300505free_irqchip:
506 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000507 irq_set_chip_and_handler(i, NULL, NULL);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300508/* destroy_workqueue: */
509 destroy_workqueue(pcap->workqueue);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300510ret:
511 return ret;
512}
513
514static struct spi_driver ezxpcap_driver = {
515 .probe = ezx_pcap_probe,
Bill Pemberton84449212012-11-19 13:20:24 -0500516 .remove = ezx_pcap_remove,
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300517 .driver = {
518 .name = "ezx-pcap",
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300519 },
520};
521
522static int __init ezx_pcap_init(void)
523{
524 return spi_register_driver(&ezxpcap_driver);
525}
526
527static void __exit ezx_pcap_exit(void)
528{
529 spi_unregister_driver(&ezxpcap_driver);
530}
531
Antonio Ospitef0782372009-07-31 15:55:45 -0700532subsys_initcall(ezx_pcap_init);
Daniel Ribeiro13a09f92009-05-28 15:43:37 -0300533module_exit(ezx_pcap_exit);
534
535MODULE_LICENSE("GPL");
536MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
537MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
Anton Vorontsove0626e32009-09-22 16:46:08 -0700538MODULE_ALIAS("spi:ezx-pcap");