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Cyrill Gorcunov47a486c2008-06-24 22:52:03 +02001/*
2 * local apic based NMI watchdog for various CPUs.
3 *
4 * This file also handles reservation of performance counters for coordination
5 * with other users (like oprofile).
6 *
7 * Note that these events normally don't tick when the CPU idles. This means
8 * the frequency varies with CPU load.
9 *
10 * Original code for K7/P6 written by Keith Owens
11 *
12 */
Andi Kleen09198e62007-05-02 19:27:20 +020013
14#include <linux/percpu.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/bitops.h>
18#include <linux/smp.h>
Don Zickus4a7863c2010-12-22 14:00:03 -050019#include <asm/nmi.h>
Ingo Molnar8b1fa1d2008-07-29 12:36:02 +020020#include <linux/kprobes.h>
21
Andi Kleen09198e62007-05-02 19:27:20 +020022#include <asm/apic.h>
Ingo Molnarcdd6c482009-09-21 12:02:48 +020023#include <asm/perf_event.h>
Andi Kleen09198e62007-05-02 19:27:20 +020024
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +020025/*
26 * this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
27 * offset from MSR_P4_BSU_ESCR0.
28 *
29 * It will be the max for all platforms (for now)
Andi Kleen09198e62007-05-02 19:27:20 +020030 */
31#define NMI_MAX_COUNTER_BITS 66
32
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +020033/*
34 * perfctr_nmi_owner tracks the ownership of the perfctr registers:
Andi Kleen09198e62007-05-02 19:27:20 +020035 * evtsel_nmi_owner tracks the ownership of the event selection
36 * - different performance counters/ event selection may be reserved for
37 * different subsystems this reservation system just tries to coordinate
38 * things a little
39 */
40static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
41static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
42
Andi Kleen09198e62007-05-02 19:27:20 +020043/* converts an msr to an appropriate reservation bit */
44static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
45{
Andi Kleen5dcccd82007-07-04 01:38:13 +020046 /* returns the bit offset of the performance counter register */
47 switch (boot_cpu_data.x86_vendor) {
48 case X86_VENDOR_AMD:
Robert Richter69d8e1e2011-02-02 17:40:58 +010049 if (msr >= MSR_F15H_PERF_CTR)
50 return (msr - MSR_F15H_PERF_CTR) >> 1;
Alan Cox8bdbd962009-07-04 00:35:45 +010051 return msr - MSR_K7_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020052 case X86_VENDOR_INTEL:
53 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
Alan Cox8bdbd962009-07-04 00:35:45 +010054 return msr - MSR_ARCH_PERFMON_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020055
56 switch (boot_cpu_data.x86) {
57 case 6:
Alan Cox8bdbd962009-07-04 00:35:45 +010058 return msr - MSR_P6_PERFCTR0;
Vince Weavere717bf42012-09-26 14:12:52 -040059 case 11:
60 return msr - MSR_KNC_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020061 case 15:
Alan Cox8bdbd962009-07-04 00:35:45 +010062 return msr - MSR_P4_BPU_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020063 }
64 }
65 return 0;
Andi Kleen09198e62007-05-02 19:27:20 +020066}
67
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +020068/*
69 * converts an msr to an appropriate reservation bit
70 * returns the bit offset of the event selection register
71 */
Andi Kleen09198e62007-05-02 19:27:20 +020072static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
73{
Andi Kleen5dcccd82007-07-04 01:38:13 +020074 /* returns the bit offset of the event selection register */
75 switch (boot_cpu_data.x86_vendor) {
76 case X86_VENDOR_AMD:
Robert Richter69d8e1e2011-02-02 17:40:58 +010077 if (msr >= MSR_F15H_PERF_CTL)
78 return (msr - MSR_F15H_PERF_CTL) >> 1;
Alan Cox8bdbd962009-07-04 00:35:45 +010079 return msr - MSR_K7_EVNTSEL0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020080 case X86_VENDOR_INTEL:
81 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
Alan Cox8bdbd962009-07-04 00:35:45 +010082 return msr - MSR_ARCH_PERFMON_EVENTSEL0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020083
84 switch (boot_cpu_data.x86) {
85 case 6:
Alan Cox8bdbd962009-07-04 00:35:45 +010086 return msr - MSR_P6_EVNTSEL0;
Vince Weavere717bf42012-09-26 14:12:52 -040087 case 11:
88 return msr - MSR_KNC_EVNTSEL0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020089 case 15:
Alan Cox8bdbd962009-07-04 00:35:45 +010090 return msr - MSR_P4_BSU_ESCR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020091 }
92 }
93 return 0;
94
Andi Kleen09198e62007-05-02 19:27:20 +020095}
96
97/* checks for a bit availability (hack for oprofile) */
98int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
99{
100 BUG_ON(counter > NMI_MAX_COUNTER_BITS);
101
Alan Cox8bdbd962009-07-04 00:35:45 +0100102 return !test_bit(counter, perfctr_nmi_owner);
Andi Kleen09198e62007-05-02 19:27:20 +0200103}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200104EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
Andi Kleen09198e62007-05-02 19:27:20 +0200105
106int reserve_perfctr_nmi(unsigned int msr)
107{
108 unsigned int counter;
109
110 counter = nmi_perfctr_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200111 /* register not managed by the allocator? */
112 if (counter > NMI_MAX_COUNTER_BITS)
113 return 1;
Andi Kleen09198e62007-05-02 19:27:20 +0200114
115 if (!test_and_set_bit(counter, perfctr_nmi_owner))
116 return 1;
117 return 0;
118}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200119EXPORT_SYMBOL(reserve_perfctr_nmi);
Andi Kleen09198e62007-05-02 19:27:20 +0200120
121void release_perfctr_nmi(unsigned int msr)
122{
123 unsigned int counter;
124
125 counter = nmi_perfctr_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200126 /* register not managed by the allocator? */
127 if (counter > NMI_MAX_COUNTER_BITS)
128 return;
Andi Kleen09198e62007-05-02 19:27:20 +0200129
130 clear_bit(counter, perfctr_nmi_owner);
131}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200132EXPORT_SYMBOL(release_perfctr_nmi);
Andi Kleen09198e62007-05-02 19:27:20 +0200133
134int reserve_evntsel_nmi(unsigned int msr)
135{
136 unsigned int counter;
137
138 counter = nmi_evntsel_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200139 /* register not managed by the allocator? */
140 if (counter > NMI_MAX_COUNTER_BITS)
141 return 1;
Andi Kleen09198e62007-05-02 19:27:20 +0200142
143 if (!test_and_set_bit(counter, evntsel_nmi_owner))
144 return 1;
145 return 0;
146}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200147EXPORT_SYMBOL(reserve_evntsel_nmi);
Andi Kleen09198e62007-05-02 19:27:20 +0200148
149void release_evntsel_nmi(unsigned int msr)
150{
151 unsigned int counter;
152
153 counter = nmi_evntsel_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200154 /* register not managed by the allocator? */
155 if (counter > NMI_MAX_COUNTER_BITS)
156 return;
Andi Kleen09198e62007-05-02 19:27:20 +0200157
158 clear_bit(counter, evntsel_nmi_owner);
159}
Andi Kleen09198e62007-05-02 19:27:20 +0200160EXPORT_SYMBOL(release_evntsel_nmi);