Matthew Hagan | d291fbb | 2021-10-14 00:39:21 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/net/dsa/qca8k.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Atheros QCA83xx switch family |
| 8 | |
| 9 | maintainers: |
| 10 | - John Crispin <john@phrozen.org> |
| 11 | |
| 12 | description: |
| 13 | If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode |
| 14 | describing a port needs to have a valid phandle referencing the internal PHY |
| 15 | it is connected to. This is because there is no N:N mapping of port and PHY |
| 16 | ID. To declare the internal mdio-bus configuration, declare an MDIO node in |
| 17 | the switch node and declare the phandle for the port, referencing the internal |
| 18 | PHY it is connected to. In this config, an internal mdio-bus is registered and |
| 19 | the MDIO master is used for communication. Mixed external and internal |
| 20 | mdio-bus configurations are not supported by the hardware. |
| 21 | |
| 22 | properties: |
| 23 | compatible: |
| 24 | oneOf: |
| 25 | - enum: |
| 26 | - qca,qca8327 |
| 27 | - qca,qca8328 |
| 28 | - qca,qca8334 |
| 29 | - qca,qca8337 |
| 30 | description: | |
| 31 | qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package |
| 32 | qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package |
| 33 | qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package |
| 34 | qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package |
| 35 | |
| 36 | reg: |
| 37 | maxItems: 1 |
| 38 | |
| 39 | reset-gpios: |
| 40 | description: |
| 41 | GPIO to be used to reset the whole device |
| 42 | maxItems: 1 |
| 43 | |
| 44 | qca,ignore-power-on-sel: |
| 45 | $ref: /schemas/types.yaml#/definitions/flag |
| 46 | description: |
| 47 | Ignore power-on pin strapping to configure LED open-drain or EEPROM |
| 48 | presence. This is needed for devices with incorrect configuration or when |
| 49 | the OEM has decided not to use pin strapping and falls back to SW regs. |
| 50 | |
| 51 | qca,led-open-drain: |
| 52 | $ref: /schemas/types.yaml#/definitions/flag |
| 53 | description: |
| 54 | Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to |
| 55 | be set, otherwise the driver will fail at probe. This is required if the |
| 56 | OEM does not use pin strapping to set this mode and prefers to set it |
| 57 | using SW regs. The pin strappings related to LED open-drain mode are |
| 58 | B68 on the QCA832x and B49 on the QCA833x. |
| 59 | |
| 60 | mdio: |
| 61 | type: object |
| 62 | description: Qca8k switch have an internal mdio to access switch port. |
| 63 | If this is not present, the legacy mapping is used and the |
| 64 | internal mdio access is used. |
| 65 | With the legacy mapping the reg corresponding to the internal |
| 66 | mdio is the switch reg with an offset of -1. |
| 67 | |
| 68 | properties: |
| 69 | '#address-cells': |
| 70 | const: 1 |
| 71 | '#size-cells': |
| 72 | const: 0 |
| 73 | |
| 74 | patternProperties: |
| 75 | "^(ethernet-)?phy@[0-4]$": |
| 76 | type: object |
| 77 | |
| 78 | allOf: |
| 79 | - $ref: "http://devicetree.org/schemas/net/mdio.yaml#" |
| 80 | |
| 81 | properties: |
| 82 | reg: |
| 83 | maxItems: 1 |
| 84 | |
| 85 | required: |
| 86 | - reg |
| 87 | |
| 88 | patternProperties: |
| 89 | "^(ethernet-)?ports$": |
| 90 | type: object |
| 91 | properties: |
| 92 | '#address-cells': |
| 93 | const: 1 |
| 94 | '#size-cells': |
| 95 | const: 0 |
| 96 | |
| 97 | patternProperties: |
| 98 | "^(ethernet-)?port@[0-6]$": |
| 99 | type: object |
| 100 | description: Ethernet switch ports |
| 101 | |
Ansuel Smith | dfb40cb | 2021-11-30 22:16:25 +0100 | [diff] [blame] | 102 | $ref: dsa-port.yaml# |
| 103 | |
Matthew Hagan | d291fbb | 2021-10-14 00:39:21 +0200 | [diff] [blame] | 104 | properties: |
Matthew Hagan | d291fbb | 2021-10-14 00:39:21 +0200 | [diff] [blame] | 105 | qca,sgmii-rxclk-falling-edge: |
| 106 | $ref: /schemas/types.yaml#/definitions/flag |
| 107 | description: |
| 108 | Set the receive clock phase to falling edge. Mostly commonly used on |
| 109 | the QCA8327 with CPU port 0 set to SGMII. |
| 110 | |
| 111 | qca,sgmii-txclk-falling-edge: |
| 112 | $ref: /schemas/types.yaml#/definitions/flag |
| 113 | description: |
| 114 | Set the transmit clock phase to falling edge. |
| 115 | |
| 116 | qca,sgmii-enable-pll: |
| 117 | $ref: /schemas/types.yaml#/definitions/flag |
| 118 | description: |
| 119 | For SGMII CPU port, explicitly enable PLL, TX and RX chain along with |
| 120 | Signal Detection. On the QCA8327 this should not be enabled, otherwise |
| 121 | the SGMII port will not initialize. When used on the QCA8337, revision 3 |
| 122 | or greater, a warning will be displayed. When the CPU port is set to |
| 123 | SGMII on the QCA8337, it is advised to set this unless a communication |
| 124 | issue is observed. |
| 125 | |
Ansuel Smith | dfb40cb | 2021-11-30 22:16:25 +0100 | [diff] [blame] | 126 | unevaluatedProperties: false |
Matthew Hagan | d291fbb | 2021-10-14 00:39:21 +0200 | [diff] [blame] | 127 | |
| 128 | oneOf: |
| 129 | - required: |
| 130 | - ports |
| 131 | - required: |
| 132 | - ethernet-ports |
| 133 | |
| 134 | required: |
| 135 | - compatible |
| 136 | - reg |
| 137 | |
| 138 | additionalProperties: true |
| 139 | |
| 140 | examples: |
| 141 | - | |
| 142 | #include <dt-bindings/gpio/gpio.h> |
| 143 | |
| 144 | mdio { |
| 145 | #address-cells = <1>; |
| 146 | #size-cells = <0>; |
| 147 | |
| 148 | external_phy_port1: ethernet-phy@0 { |
| 149 | reg = <0>; |
| 150 | }; |
| 151 | |
| 152 | external_phy_port2: ethernet-phy@1 { |
| 153 | reg = <1>; |
| 154 | }; |
| 155 | |
| 156 | external_phy_port3: ethernet-phy@2 { |
| 157 | reg = <2>; |
| 158 | }; |
| 159 | |
| 160 | external_phy_port4: ethernet-phy@3 { |
| 161 | reg = <3>; |
| 162 | }; |
| 163 | |
| 164 | external_phy_port5: ethernet-phy@4 { |
| 165 | reg = <4>; |
| 166 | }; |
| 167 | |
| 168 | switch@10 { |
| 169 | compatible = "qca,qca8337"; |
| 170 | #address-cells = <1>; |
| 171 | #size-cells = <0>; |
| 172 | reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; |
| 173 | reg = <0x10>; |
| 174 | |
| 175 | ports { |
| 176 | #address-cells = <1>; |
| 177 | #size-cells = <0>; |
| 178 | |
| 179 | port@0 { |
| 180 | reg = <0>; |
| 181 | label = "cpu"; |
| 182 | ethernet = <&gmac1>; |
| 183 | phy-mode = "rgmii"; |
| 184 | |
| 185 | fixed-link { |
| 186 | speed = <1000>; |
| 187 | full-duplex; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | port@1 { |
| 192 | reg = <1>; |
| 193 | label = "lan1"; |
| 194 | phy-handle = <&external_phy_port1>; |
| 195 | }; |
| 196 | |
| 197 | port@2 { |
| 198 | reg = <2>; |
| 199 | label = "lan2"; |
| 200 | phy-handle = <&external_phy_port2>; |
| 201 | }; |
| 202 | |
| 203 | port@3 { |
| 204 | reg = <3>; |
| 205 | label = "lan3"; |
| 206 | phy-handle = <&external_phy_port3>; |
| 207 | }; |
| 208 | |
| 209 | port@4 { |
| 210 | reg = <4>; |
| 211 | label = "lan4"; |
| 212 | phy-handle = <&external_phy_port4>; |
| 213 | }; |
| 214 | |
| 215 | port@5 { |
| 216 | reg = <5>; |
| 217 | label = "wan"; |
| 218 | phy-handle = <&external_phy_port5>; |
| 219 | }; |
| 220 | }; |
| 221 | }; |
| 222 | }; |
| 223 | - | |
| 224 | #include <dt-bindings/gpio/gpio.h> |
| 225 | |
| 226 | mdio { |
| 227 | #address-cells = <1>; |
| 228 | #size-cells = <0>; |
| 229 | |
| 230 | switch@10 { |
| 231 | compatible = "qca,qca8337"; |
| 232 | #address-cells = <1>; |
| 233 | #size-cells = <0>; |
| 234 | reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; |
| 235 | reg = <0x10>; |
| 236 | |
| 237 | ports { |
| 238 | #address-cells = <1>; |
| 239 | #size-cells = <0>; |
| 240 | |
| 241 | port@0 { |
| 242 | reg = <0>; |
| 243 | label = "cpu"; |
| 244 | ethernet = <&gmac1>; |
| 245 | phy-mode = "rgmii"; |
| 246 | |
| 247 | fixed-link { |
| 248 | speed = <1000>; |
| 249 | full-duplex; |
| 250 | }; |
| 251 | }; |
| 252 | |
| 253 | port@1 { |
| 254 | reg = <1>; |
| 255 | label = "lan1"; |
| 256 | phy-mode = "internal"; |
| 257 | phy-handle = <&internal_phy_port1>; |
| 258 | }; |
| 259 | |
| 260 | port@2 { |
| 261 | reg = <2>; |
| 262 | label = "lan2"; |
| 263 | phy-mode = "internal"; |
| 264 | phy-handle = <&internal_phy_port2>; |
| 265 | }; |
| 266 | |
| 267 | port@3 { |
| 268 | reg = <3>; |
| 269 | label = "lan3"; |
| 270 | phy-mode = "internal"; |
| 271 | phy-handle = <&internal_phy_port3>; |
| 272 | }; |
| 273 | |
| 274 | port@4 { |
| 275 | reg = <4>; |
| 276 | label = "lan4"; |
| 277 | phy-mode = "internal"; |
| 278 | phy-handle = <&internal_phy_port4>; |
| 279 | }; |
| 280 | |
| 281 | port@5 { |
| 282 | reg = <5>; |
| 283 | label = "wan"; |
| 284 | phy-mode = "internal"; |
| 285 | phy-handle = <&internal_phy_port5>; |
| 286 | }; |
| 287 | |
| 288 | port@6 { |
| 289 | reg = <0>; |
| 290 | label = "cpu"; |
| 291 | ethernet = <&gmac1>; |
| 292 | phy-mode = "sgmii"; |
| 293 | |
| 294 | qca,sgmii-rxclk-falling-edge; |
| 295 | |
| 296 | fixed-link { |
| 297 | speed = <1000>; |
| 298 | full-duplex; |
| 299 | }; |
| 300 | }; |
| 301 | }; |
| 302 | |
| 303 | mdio { |
| 304 | #address-cells = <1>; |
| 305 | #size-cells = <0>; |
| 306 | |
| 307 | internal_phy_port1: ethernet-phy@0 { |
| 308 | reg = <0>; |
| 309 | }; |
| 310 | |
| 311 | internal_phy_port2: ethernet-phy@1 { |
| 312 | reg = <1>; |
| 313 | }; |
| 314 | |
| 315 | internal_phy_port3: ethernet-phy@2 { |
| 316 | reg = <2>; |
| 317 | }; |
| 318 | |
| 319 | internal_phy_port4: ethernet-phy@3 { |
| 320 | reg = <3>; |
| 321 | }; |
| 322 | |
| 323 | internal_phy_port5: ethernet-phy@4 { |
| 324 | reg = <4>; |
| 325 | }; |
| 326 | }; |
| 327 | }; |
| 328 | }; |