Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: AMD |
| 23 | * |
| 24 | */ |
| 25 | |
David Francis | 0cf5eb7 | 2018-11-30 09:57:06 -0500 | [diff] [blame] | 26 | /* The caprices of the preprocessor require that this be declared right here */ |
| 27 | #define CREATE_TRACE_POINTS |
| 28 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 29 | #include "dm_services_types.h" |
| 30 | #include "dc.h" |
Jude Shih | f6e03f8 | 2021-09-13 14:41:34 +0800 | [diff] [blame] | 31 | #include "link_enc_cfg.h" |
Andrey Grodzovsky | 1dc9049 | 2017-07-31 11:29:25 -0400 | [diff] [blame] | 32 | #include "dc/inc/core_types.h" |
Harry Wentland | a7669af | 2019-04-29 09:39:15 -0400 | [diff] [blame] | 33 | #include "dal_asic_id.h" |
Anthony Koo | cdca3f2 | 2020-04-21 22:01:58 -0400 | [diff] [blame] | 34 | #include "dmub/dmub_srv.h" |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 35 | #include "dc/inc/hw/dmcu.h" |
| 36 | #include "dc/inc/hw/abm.h" |
Nicholas Kazlauskas | 9a71c7d | 2019-10-28 09:07:30 -0400 | [diff] [blame] | 37 | #include "dc/dc_dmub_srv.h" |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 38 | #include "dc/dc_edid_parser.h" |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 39 | #include "dc/dc_stat.h" |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 40 | #include "dc/dc_state.h" |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 41 | #include "amdgpu_dm_trace.h" |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 42 | #include "dpcd_defs.h" |
Wenjing Liu | bc33f5e | 2022-12-16 17:16:19 -0500 | [diff] [blame] | 43 | #include "link/protocols/link_dpcd.h" |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 44 | #include "link_service_types.h" |
Ryan Lin | 1e5d4d8 | 2023-02-07 23:03:48 +0800 | [diff] [blame] | 45 | #include "link/protocols/link_dp_capability.h" |
| 46 | #include "link/protocols/link_ddc.h" |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 47 | |
| 48 | #include "vid.h" |
| 49 | #include "amdgpu.h" |
Harry Wentland | a49dcb8 | 2017-01-12 09:09:08 -0500 | [diff] [blame] | 50 | #include "amdgpu_display.h" |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 51 | #include "amdgpu_ucode.h" |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 52 | #include "atom.h" |
| 53 | #include "amdgpu_dm.h" |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 54 | #include "amdgpu_dm_plane.h" |
Rodrigo Siqueira | 473683a | 2022-07-20 15:43:21 -0400 | [diff] [blame] | 55 | #include "amdgpu_dm_crtc.h" |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 56 | #include "amdgpu_dm_hdcp.h" |
Thomas Zimmermann | 6a99099 | 2022-04-21 09:31:06 +0200 | [diff] [blame] | 57 | #include <drm/display/drm_hdcp_helper.h> |
Alex Hung | dfc0358 | 2023-12-01 06:25:24 -0700 | [diff] [blame] | 58 | #include "amdgpu_dm_wb.h" |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 59 | #include "amdgpu_pm.h" |
Alex Deucher | 1f57925 | 2021-11-23 10:44:48 -0500 | [diff] [blame] | 60 | #include "amdgpu_atombios.h" |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 61 | |
| 62 | #include "amd_shared.h" |
| 63 | #include "amdgpu_dm_irq.h" |
| 64 | #include "dm_helpers.h" |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 65 | #include "amdgpu_dm_mst_types.h" |
David Francis | dc38fd9 | 2018-06-01 09:49:06 -0400 | [diff] [blame] | 66 | #if defined(CONFIG_DEBUG_FS) |
| 67 | #include "amdgpu_dm_debugfs.h" |
| 68 | #endif |
Roman Li | f4594cd | 2021-06-04 14:34:24 -0400 | [diff] [blame] | 69 | #include "amdgpu_dm_psr.h" |
Tom Chung | 5950efe | 2023-12-06 22:07:51 +0800 | [diff] [blame] | 70 | #include "amdgpu_dm_replay.h" |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 71 | |
| 72 | #include "ivsrcid/ivsrcid_vislands30.h" |
| 73 | |
Thomas Zimmermann | a6276e9 | 2023-01-11 14:01:57 +0100 | [diff] [blame] | 74 | #include <linux/backlight.h> |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 75 | #include <linux/module.h> |
| 76 | #include <linux/moduleparam.h> |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 77 | #include <linux/types.h> |
Lyude Paul | 9702803 | 2018-06-04 15:35:03 -0400 | [diff] [blame] | 78 | #include <linux/pm_runtime.h> |
Sam Ravnborg | 09d2185 | 2019-06-10 00:07:55 +0200 | [diff] [blame] | 79 | #include <linux/pci.h> |
Mario Limonciello | 2fe87f5 | 2024-06-07 01:02:28 -0500 | [diff] [blame] | 80 | #include <linux/power_supply.h> |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 81 | #include <linux/firmware.h> |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 82 | #include <linux/component.h> |
Fangzhi Zuo | 57b9f33 | 2022-07-06 15:52:46 -0400 | [diff] [blame] | 83 | #include <linux/dmi.h> |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 84 | #include <linux/sort.h> |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 85 | |
Thomas Zimmermann | da68386 | 2022-04-21 09:31:02 +0200 | [diff] [blame] | 86 | #include <drm/display/drm_dp_mst_helper.h> |
Thomas Zimmermann | 4fc8cb4 | 2022-04-21 09:31:07 +0200 | [diff] [blame] | 87 | #include <drm/display/drm_hdmi_helper.h> |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 88 | #include <drm/drm_atomic.h> |
Nicholas Kazlauskas | 674e78a | 2018-12-05 14:59:07 -0500 | [diff] [blame] | 89 | #include <drm/drm_atomic_uapi.h> |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 90 | #include <drm/drm_atomic_helper.h> |
Ville Syrjälä | 90bb087 | 2022-06-13 23:03:12 +0300 | [diff] [blame] | 91 | #include <drm/drm_blend.h> |
Imre Deak | 191dc43 | 2023-11-16 15:18:31 +0200 | [diff] [blame] | 92 | #include <drm/drm_fixed.h> |
Sam Ravnborg | 09d2185 | 2019-06-10 00:07:55 +0200 | [diff] [blame] | 93 | #include <drm/drm_fourcc.h> |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 94 | #include <drm/drm_edid.h> |
Jani Nikula | 439590a | 2023-10-31 12:16:40 +0200 | [diff] [blame] | 95 | #include <drm/drm_eld.h> |
Sam Ravnborg | 09d2185 | 2019-06-10 00:07:55 +0200 | [diff] [blame] | 96 | #include <drm/drm_vblank.h> |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 97 | #include <drm/drm_audio_component.h> |
Christian König | 047de3f | 2022-05-09 09:47:12 +0200 | [diff] [blame] | 98 | #include <drm/drm_gem_atomic_helper.h> |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 99 | |
Hans de Goede | da11ef8 | 2022-04-15 22:22:41 +0200 | [diff] [blame] | 100 | #include <acpi/video.h> |
| 101 | |
Hawking Zhang | 5527cd0 | 2019-03-05 19:52:22 +0800 | [diff] [blame] | 102 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 103 | |
Feifei Xu | ad941f7a | 2017-11-27 18:59:10 +0800 | [diff] [blame] | 104 | #include "dcn/dcn_1_0_offset.h" |
| 105 | #include "dcn/dcn_1_0_sh_mask.h" |
Hawking Zhang | 407e751 | 2018-01-15 15:43:23 +0800 | [diff] [blame] | 106 | #include "soc15_hw_ip.h" |
Aurabindo Pillai | 543036a | 2022-02-21 15:33:05 -0500 | [diff] [blame] | 107 | #include "soc15_common.h" |
Hawking Zhang | 407e751 | 2018-01-15 15:43:23 +0800 | [diff] [blame] | 108 | #include "vega10_ip_offset.h" |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 109 | |
Aurabindo Pillai | 543036a | 2022-02-21 15:33:05 -0500 | [diff] [blame] | 110 | #include "gc/gc_11_0_0_offset.h" |
| 111 | #include "gc/gc_11_0_0_sh_mask.h" |
| 112 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 113 | #include "modules/inc/mod_freesync.h" |
David Francis | bbf854d | 2018-11-26 11:38:33 -0500 | [diff] [blame] | 114 | #include "modules/power/power_helpers.h" |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 115 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 116 | #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" |
| 117 | MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); |
Bhawanpreet Lakha | 7903732 | 2020-05-21 12:48:41 -0400 | [diff] [blame] | 118 | #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" |
| 119 | MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); |
Bhawanpreet Lakha | 5ce868fc | 2020-07-21 13:59:52 -0400 | [diff] [blame] | 120 | #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" |
| 121 | MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); |
Roman Li | 71c0fd9 | 2020-10-08 13:32:47 -0400 | [diff] [blame] | 122 | #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" |
| 123 | MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); |
Roman Li | 469989c | 2020-09-23 17:02:12 -0400 | [diff] [blame] | 124 | #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" |
| 125 | MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); |
Bhawanpreet Lakha | 2a41120 | 2020-09-25 14:00:24 -0400 | [diff] [blame] | 126 | #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" |
| 127 | MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); |
Aurabindo Pillai | 656fe9b | 2021-03-10 15:53:11 -0500 | [diff] [blame] | 128 | #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" |
| 129 | MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); |
Nicholas Kazlauskas | 1ebcaeb | 2021-05-19 12:55:44 -0400 | [diff] [blame] | 130 | #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" |
| 131 | MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); |
Roman Li | e850f6b | 2022-06-28 18:41:37 -0400 | [diff] [blame] | 132 | #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" |
| 133 | MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 134 | #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" |
| 135 | MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 136 | #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" |
| 137 | MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); |
Nicholas Kazlauskas | 2200eb9 | 2019-10-28 09:22:34 -0400 | [diff] [blame] | 138 | |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 139 | #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" |
| 140 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); |
| 141 | #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" |
| 142 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); |
| 143 | |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 144 | #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" |
| 145 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 146 | |
Roman Li | 5ea2393 | 2020-02-05 09:39:41 -0500 | [diff] [blame] | 147 | #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" |
| 148 | MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); |
| 149 | |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 150 | #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" |
| 151 | MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); |
| 152 | |
Li Ma | 2dbe9c2 | 2024-03-28 10:55:10 +0800 | [diff] [blame] | 153 | #define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" |
| 154 | MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); |
| 155 | |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 156 | #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" |
| 157 | MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); |
| 158 | |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 159 | /* Number of bytes in PSP header for firmware. */ |
| 160 | #define PSP_HEADER_BYTES 0x100 |
| 161 | |
| 162 | /* Number of bytes in PSP footer for firmware. */ |
| 163 | #define PSP_FOOTER_BYTES 0x100 |
| 164 | |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 165 | /** |
| 166 | * DOC: overview |
| 167 | * |
| 168 | * The AMDgpu display manager, **amdgpu_dm** (or even simpler, |
Diego Viola | ec5c0ff | 2021-03-28 02:35:04 -0300 | [diff] [blame] | 169 | * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 170 | * requests into DC requests, and DC responses into DRM responses. |
| 171 | * |
| 172 | * The root control structure is &struct amdgpu_display_manager. |
| 173 | */ |
| 174 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 175 | /* basic init/fini API */ |
| 176 | static int amdgpu_dm_init(struct amdgpu_device *adev); |
| 177 | static void amdgpu_dm_fini(struct amdgpu_device *adev); |
Nikola Cornij | fe8858b | 2021-03-26 19:13:52 -0400 | [diff] [blame] | 178 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); |
Tom Chung | df18a4d | 2024-07-12 17:29:07 +0800 | [diff] [blame] | 179 | static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state); |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 180 | |
Oleg Vasilev | 0f87789 | 2020-04-24 18:20:55 +0530 | [diff] [blame] | 181 | static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) |
| 182 | { |
| 183 | switch (link->dpcd_caps.dongle_type) { |
| 184 | case DISPLAY_DONGLE_NONE: |
| 185 | return DRM_MODE_SUBCONNECTOR_Native; |
| 186 | case DISPLAY_DONGLE_DP_VGA_CONVERTER: |
| 187 | return DRM_MODE_SUBCONNECTOR_VGA; |
| 188 | case DISPLAY_DONGLE_DP_DVI_CONVERTER: |
| 189 | case DISPLAY_DONGLE_DP_DVI_DONGLE: |
| 190 | return DRM_MODE_SUBCONNECTOR_DVID; |
| 191 | case DISPLAY_DONGLE_DP_HDMI_CONVERTER: |
| 192 | case DISPLAY_DONGLE_DP_HDMI_DONGLE: |
| 193 | return DRM_MODE_SUBCONNECTOR_HDMIA; |
| 194 | case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: |
| 195 | default: |
| 196 | return DRM_MODE_SUBCONNECTOR_Unknown; |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) |
| 201 | { |
| 202 | struct dc_link *link = aconnector->dc_link; |
| 203 | struct drm_connector *connector = &aconnector->base; |
| 204 | enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; |
| 205 | |
| 206 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
| 207 | return; |
| 208 | |
| 209 | if (aconnector->dc_sink) |
| 210 | subconnector = get_subconnector_type(link); |
| 211 | |
| 212 | drm_object_property_set_value(&connector->base, |
| 213 | connector->dev->mode_config.dp_subconnector_property, |
| 214 | subconnector); |
| 215 | } |
| 216 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 217 | /* |
| 218 | * initializes drm_device display related structures, based on the information |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 219 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
| 220 | * drm_encoder, drm_mode_config |
| 221 | * |
| 222 | * Returns 0 on success |
| 223 | */ |
| 224 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); |
| 225 | /* removes and deallocates the drm structures, created by the above function */ |
| 226 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); |
| 227 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 228 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
| 229 | struct amdgpu_dm_connector *amdgpu_dm_connector, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 230 | u32 link_index, |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 231 | struct amdgpu_encoder *amdgpu_encoder); |
| 232 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
| 233 | struct amdgpu_encoder *aencoder, |
| 234 | uint32_t link_index); |
| 235 | |
| 236 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); |
| 237 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 238 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); |
| 239 | |
| 240 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
| 241 | struct drm_atomic_state *state); |
| 242 | |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 243 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); |
Nicholas Kazlauskas | c40a09e | 2021-11-04 16:52:07 -0400 | [diff] [blame] | 244 | static void handle_hpd_rx_irq(void *param); |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 245 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 246 | static bool |
| 247 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, |
| 248 | struct drm_crtc_state *new_crtc_state); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 249 | /* |
| 250 | * dm_vblank_get_counter |
| 251 | * |
| 252 | * @brief |
| 253 | * Get counter for number of vertical blanks |
| 254 | * |
| 255 | * @param |
| 256 | * struct amdgpu_device *adev - [in] desired amdgpu device |
| 257 | * int disp_idx - [in] which CRTC to get the counter from |
| 258 | * |
| 259 | * @return |
| 260 | * Counter for vertical blanks |
| 261 | */ |
| 262 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) |
| 263 | { |
Srinivasan Shanmugam | 53e1db0 | 2023-07-23 14:52:09 +0530 | [diff] [blame] | 264 | struct amdgpu_crtc *acrtc = NULL; |
| 265 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 266 | if (crtc >= adev->mode_info.num_crtc) |
| 267 | return 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 268 | |
Srinivasan Shanmugam | 53e1db0 | 2023-07-23 14:52:09 +0530 | [diff] [blame] | 269 | acrtc = adev->mode_info.crtcs[crtc]; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 270 | |
Srinivasan Shanmugam | 53e1db0 | 2023-07-23 14:52:09 +0530 | [diff] [blame] | 271 | if (!acrtc->dm_irq_params.stream) { |
| 272 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
| 273 | crtc); |
| 274 | return 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 275 | } |
Srinivasan Shanmugam | 53e1db0 | 2023-07-23 14:52:09 +0530 | [diff] [blame] | 276 | |
| 277 | return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 281 | u32 *vbl, u32 *position) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 282 | { |
Alex Hung | f95bcb0 | 2024-04-15 19:02:56 -0600 | [diff] [blame] | 283 | u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; |
Srinivasan Shanmugam | 0c2d77b | 2023-06-19 17:19:29 +0530 | [diff] [blame] | 284 | struct amdgpu_crtc *acrtc = NULL; |
Roman Li | 196107e | 2024-01-09 17:31:33 -0500 | [diff] [blame] | 285 | struct dc *dc = adev->dm.dc; |
Sylvia Tsai | 81c5096 | 2017-04-11 15:15:28 -0400 | [diff] [blame] | 286 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 287 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
| 288 | return -EINVAL; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 289 | |
Srinivasan Shanmugam | 0c2d77b | 2023-06-19 17:19:29 +0530 | [diff] [blame] | 290 | acrtc = adev->mode_info.crtcs[crtc]; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 291 | |
Srinivasan Shanmugam | 0c2d77b | 2023-06-19 17:19:29 +0530 | [diff] [blame] | 292 | if (!acrtc->dm_irq_params.stream) { |
| 293 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
| 294 | crtc); |
| 295 | return 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 296 | } |
| 297 | |
Roman Li | 196107e | 2024-01-09 17:31:33 -0500 | [diff] [blame] | 298 | if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) |
| 299 | dc_allow_idle_optimizations(dc, false); |
| 300 | |
Srinivasan Shanmugam | 0c2d77b | 2023-06-19 17:19:29 +0530 | [diff] [blame] | 301 | /* |
| 302 | * TODO rework base driver to use values directly. |
| 303 | * for now parse it back into reg-format |
| 304 | */ |
| 305 | dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, |
| 306 | &v_blank_start, |
| 307 | &v_blank_end, |
| 308 | &h_position, |
| 309 | &v_position); |
| 310 | |
| 311 | *position = v_position | (h_position << 16); |
| 312 | *vbl = v_blank_start | (v_blank_end << 16); |
| 313 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | static bool dm_is_idle(void *handle) |
| 318 | { |
| 319 | /* XXX todo */ |
| 320 | return true; |
| 321 | } |
| 322 | |
| 323 | static int dm_wait_for_idle(void *handle) |
| 324 | { |
| 325 | /* XXX todo */ |
| 326 | return 0; |
| 327 | } |
| 328 | |
| 329 | static bool dm_check_soft_reset(void *handle) |
| 330 | { |
| 331 | return false; |
| 332 | } |
| 333 | |
| 334 | static int dm_soft_reset(void *handle) |
| 335 | { |
| 336 | /* XXX todo */ |
| 337 | return 0; |
| 338 | } |
| 339 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 340 | static struct amdgpu_crtc * |
| 341 | get_crtc_by_otg_inst(struct amdgpu_device *adev, |
| 342 | int otg_inst) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 343 | { |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 344 | struct drm_device *dev = adev_to_drm(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 345 | struct drm_crtc *crtc; |
| 346 | struct amdgpu_crtc *amdgpu_crtc; |
| 347 | |
Nirmoy Das | bcd7437 | 2021-05-27 14:13:04 +0200 | [diff] [blame] | 348 | if (WARN_ON(otg_inst == -1)) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 349 | return adev->mode_info.crtcs[0]; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 350 | |
| 351 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 352 | amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 353 | |
| 354 | if (amdgpu_crtc->otg_inst == otg_inst) |
| 355 | return amdgpu_crtc; |
| 356 | } |
| 357 | |
| 358 | return NULL; |
| 359 | } |
| 360 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 361 | static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, |
| 362 | struct dm_crtc_state *new_state) |
| 363 | { |
| 364 | if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) |
| 365 | return true; |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 366 | else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 367 | return true; |
| 368 | else |
| 369 | return false; |
| 370 | } |
| 371 | |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 372 | /* |
| 373 | * DC will program planes with their z-order determined by their ordering |
| 374 | * in the dc_surface_updates array. This comparator is used to sort them |
| 375 | * by descending zpos. |
| 376 | */ |
| 377 | static int dm_plane_layer_index_cmp(const void *a, const void *b) |
| 378 | { |
| 379 | const struct dc_surface_update *sa = (struct dc_surface_update *)a; |
| 380 | const struct dc_surface_update *sb = (struct dc_surface_update *)b; |
| 381 | |
| 382 | /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ |
| 383 | return sb->surface->layer_index - sa->surface->layer_index; |
| 384 | } |
| 385 | |
Harry Wentland | b8e8c93 | 2019-09-18 11:42:59 -0400 | [diff] [blame] | 386 | /** |
Rodrigo Siqueira | 81f743a | 2023-02-23 11:36:08 -0700 | [diff] [blame] | 387 | * update_planes_and_stream_adapter() - Send planes to be updated in DC |
| 388 | * |
| 389 | * DC has a generic way to update planes and stream via |
| 390 | * dc_update_planes_and_stream function; however, DM might need some |
| 391 | * adjustments and preparation before calling it. This function is a wrapper |
| 392 | * for the dc_update_planes_and_stream that does any required configuration |
| 393 | * before passing control to DC. |
Srinivasan Shanmugam | 21d8168 | 2023-05-27 19:45:52 +0530 | [diff] [blame] | 394 | * |
| 395 | * @dc: Display Core control structure |
| 396 | * @update_type: specify whether it is FULL/MEDIUM/FAST update |
| 397 | * @planes_count: planes count to update |
| 398 | * @stream: stream state |
| 399 | * @stream_update: stream update |
| 400 | * @array_of_surface_update: dc surface update pointer |
| 401 | * |
Rodrigo Siqueira | 81f743a | 2023-02-23 11:36:08 -0700 | [diff] [blame] | 402 | */ |
| 403 | static inline bool update_planes_and_stream_adapter(struct dc *dc, |
| 404 | int update_type, |
| 405 | int planes_count, |
| 406 | struct dc_stream_state *stream, |
| 407 | struct dc_stream_update *stream_update, |
| 408 | struct dc_surface_update *array_of_surface_update) |
| 409 | { |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 410 | sort(array_of_surface_update, planes_count, |
| 411 | sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); |
Rodrigo Siqueira | bb46a6a9 | 2023-02-16 09:49:22 -0700 | [diff] [blame] | 412 | |
Rodrigo Siqueira | 81f743a | 2023-02-23 11:36:08 -0700 | [diff] [blame] | 413 | /* |
| 414 | * Previous frame finished and HW is ready for optimization. |
| 415 | */ |
| 416 | if (update_type == UPDATE_TYPE_FAST) |
| 417 | dc_post_update_surfaces_to_stream(dc); |
| 418 | |
| 419 | return dc_update_planes_and_stream(dc, |
| 420 | array_of_surface_update, |
| 421 | planes_count, |
| 422 | stream, |
| 423 | stream_update); |
| 424 | } |
| 425 | |
| 426 | /** |
Harry Wentland | b8e8c93 | 2019-09-18 11:42:59 -0400 | [diff] [blame] | 427 | * dm_pflip_high_irq() - Handle pageflip interrupt |
| 428 | * @interrupt_params: ignored |
| 429 | * |
| 430 | * Handles the pageflip interrupt by notifying all interested parties |
| 431 | * that the pageflip has been completed. |
| 432 | */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 433 | static void dm_pflip_high_irq(void *interrupt_params) |
| 434 | { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 435 | struct amdgpu_crtc *amdgpu_crtc; |
| 436 | struct common_irq_params *irq_params = interrupt_params; |
| 437 | struct amdgpu_device *adev = irq_params->adev; |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 438 | struct drm_device *dev = adev_to_drm(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 439 | unsigned long flags; |
Mario Kleiner | 71bbe51 | 2019-03-29 13:00:57 +0100 | [diff] [blame] | 440 | struct drm_pending_vblank_event *e; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 441 | u32 vpos, hpos, v_blank_start, v_blank_end; |
Mario Kleiner | 71bbe51 | 2019-03-29 13:00:57 +0100 | [diff] [blame] | 442 | bool vrr_active; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 443 | |
| 444 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); |
| 445 | |
| 446 | /* IRQ could occur when in initial stage */ |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 447 | /* TODO work and BO cleanup */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 448 | if (amdgpu_crtc == NULL) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 449 | drm_dbg_state(dev, "CRTC is null, returning.\n"); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 450 | return; |
| 451 | } |
| 452 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 453 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 454 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 455 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 456 | drm_dbg_state(dev, |
| 457 | "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", |
| 458 | amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, |
| 459 | amdgpu_crtc->crtc_id, amdgpu_crtc); |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 460 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 461 | return; |
| 462 | } |
| 463 | |
Mario Kleiner | 71bbe51 | 2019-03-29 13:00:57 +0100 | [diff] [blame] | 464 | /* page flip completed. */ |
| 465 | e = amdgpu_crtc->event; |
| 466 | amdgpu_crtc->event = NULL; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 467 | |
Nirmoy Das | bcd7437 | 2021-05-27 14:13:04 +0200 | [diff] [blame] | 468 | WARN_ON(!e); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 469 | |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 470 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); |
Mario Kleiner | 71bbe51 | 2019-03-29 13:00:57 +0100 | [diff] [blame] | 471 | |
| 472 | /* Fixed refresh rate, or VRR scanout position outside front-porch? */ |
| 473 | if (!vrr_active || |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 474 | !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, |
Mario Kleiner | 71bbe51 | 2019-03-29 13:00:57 +0100 | [diff] [blame] | 475 | &v_blank_end, &hpos, &vpos) || |
| 476 | (vpos < v_blank_start)) { |
| 477 | /* Update to correct count and vblank timestamp if racing with |
| 478 | * vblank irq. This also updates to the correct vblank timestamp |
| 479 | * even in VRR mode, as scanout is past the front-porch atm. |
| 480 | */ |
| 481 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); |
| 482 | |
| 483 | /* Wake up userspace by sending the pageflip event with proper |
| 484 | * count and timestamp of vblank of flip completion. |
| 485 | */ |
| 486 | if (e) { |
| 487 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); |
| 488 | |
| 489 | /* Event sent, so done with vblank for this flip */ |
| 490 | drm_crtc_vblank_put(&amdgpu_crtc->base); |
| 491 | } |
| 492 | } else if (e) { |
| 493 | /* VRR active and inside front-porch: vblank count and |
| 494 | * timestamp for pageflip event will only be up to date after |
| 495 | * drm_crtc_handle_vblank() has been executed from late vblank |
| 496 | * irq handler after start of back-porch (vline 0). We queue the |
| 497 | * pageflip event for send-out by drm_crtc_handle_vblank() with |
| 498 | * updated timestamp and count, once it runs after us. |
| 499 | * |
| 500 | * We need to open-code this instead of using the helper |
| 501 | * drm_crtc_arm_vblank_event(), as that helper would |
| 502 | * call drm_crtc_accurate_vblank_count(), which we must |
| 503 | * not call in VRR mode while we are in front-porch! |
| 504 | */ |
| 505 | |
| 506 | /* sequence will be replaced by real count during send-out. */ |
| 507 | e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); |
| 508 | e->pipe = amdgpu_crtc->crtc_id; |
| 509 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 510 | list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); |
Mario Kleiner | 71bbe51 | 2019-03-29 13:00:57 +0100 | [diff] [blame] | 511 | e = NULL; |
| 512 | } |
| 513 | |
Mario Kleiner | fdd1fe5 | 2019-04-02 17:00:06 -0500 | [diff] [blame] | 514 | /* Keep track of vblank of this flip for flip throttling. We use the |
| 515 | * cooked hw counter, as that one incremented at start of this vblank |
| 516 | * of pageflip completion, so last_flip_vblank is the forbidden count |
| 517 | * for queueing new pageflips if vsync + VRR is enabled. |
| 518 | */ |
Aurabindo Pillai | 5d1c59c | 2020-08-12 12:40:34 -0400 | [diff] [blame] | 519 | amdgpu_crtc->dm_irq_params.last_flip_vblank = |
Thomas Zimmermann | e3eff4b | 2020-01-23 14:59:26 +0100 | [diff] [blame] | 520 | amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); |
Mario Kleiner | fdd1fe5 | 2019-04-02 17:00:06 -0500 | [diff] [blame] | 521 | |
Andrey Grodzovsky | 54f5499 | 2017-04-20 15:57:05 -0400 | [diff] [blame] | 522 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 523 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 524 | |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 525 | drm_dbg_state(dev, |
| 526 | "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", |
| 527 | amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 528 | } |
| 529 | |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 530 | static void dm_vupdate_high_irq(void *interrupt_params) |
| 531 | { |
| 532 | struct common_irq_params *irq_params = interrupt_params; |
| 533 | struct amdgpu_device *adev = irq_params->adev; |
| 534 | struct amdgpu_crtc *acrtc; |
Rodrigo Siqueira | 4758823 | 2021-03-10 10:04:56 -0500 | [diff] [blame] | 535 | struct drm_device *drm_dev; |
| 536 | struct drm_vblank_crtc *vblank; |
| 537 | ktime_t frame_duration_ns, previous_timestamp; |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 538 | unsigned long flags; |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 539 | int vrr_active; |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 540 | |
| 541 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); |
| 542 | |
| 543 | if (acrtc) { |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 544 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
Rodrigo Siqueira | 4758823 | 2021-03-10 10:04:56 -0500 | [diff] [blame] | 545 | drm_dev = acrtc->base.dev; |
Ville Syrjälä | d26238c | 2024-04-08 22:06:08 +0300 | [diff] [blame] | 546 | vblank = drm_crtc_vblank_crtc(&acrtc->base); |
Rodrigo Siqueira | 4758823 | 2021-03-10 10:04:56 -0500 | [diff] [blame] | 547 | previous_timestamp = atomic64_read(&irq_params->previous_timestamp); |
| 548 | frame_duration_ns = vblank->time - previous_timestamp; |
| 549 | |
| 550 | if (frame_duration_ns > 0) { |
| 551 | trace_amdgpu_refresh_rate_track(acrtc->base.index, |
| 552 | frame_duration_ns, |
| 553 | ktime_divns(NSEC_PER_SEC, frame_duration_ns)); |
| 554 | atomic64_set(&irq_params->previous_timestamp, vblank->time); |
| 555 | } |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 556 | |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 557 | drm_dbg_vbl(drm_dev, |
| 558 | "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, |
| 559 | vrr_active); |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 560 | |
| 561 | /* Core vblank handling is done here after end of front-porch in |
| 562 | * vrr mode, as vblank timestamping will give valid results |
| 563 | * while now done after front-porch. This will also deliver |
| 564 | * page-flip completion events that have been queued to us |
| 565 | * if a pageflip happened inside front-porch. |
| 566 | */ |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 567 | if (vrr_active) { |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 568 | amdgpu_dm_crtc_handle_vblank(acrtc); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 569 | |
| 570 | /* BTR processing for pre-DCE12 ASICs */ |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 571 | if (acrtc->dm_irq_params.stream && |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 572 | adev->family < AMDGPU_FAMILY_AI) { |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 573 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 574 | mod_freesync_handle_v_update( |
| 575 | adev->dm.freesync_module, |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 576 | acrtc->dm_irq_params.stream, |
| 577 | &acrtc->dm_irq_params.vrr_params); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 578 | |
| 579 | dc_stream_adjust_vmin_vmax( |
| 580 | adev->dm.dc, |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 581 | acrtc->dm_irq_params.stream, |
| 582 | &acrtc->dm_irq_params.vrr_params.adjust); |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 583 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 584 | } |
| 585 | } |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 586 | } |
| 587 | } |
| 588 | |
Harry Wentland | b8e8c93 | 2019-09-18 11:42:59 -0400 | [diff] [blame] | 589 | /** |
| 590 | * dm_crtc_high_irq() - Handles CRTC interrupt |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 591 | * @interrupt_params: used for determining the CRTC instance |
Harry Wentland | b8e8c93 | 2019-09-18 11:42:59 -0400 | [diff] [blame] | 592 | * |
| 593 | * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK |
| 594 | * event handler. |
| 595 | */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 596 | static void dm_crtc_high_irq(void *interrupt_params) |
| 597 | { |
| 598 | struct common_irq_params *irq_params = interrupt_params; |
| 599 | struct amdgpu_device *adev = irq_params->adev; |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 600 | struct drm_writeback_job *job; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 601 | struct amdgpu_crtc *acrtc; |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 602 | unsigned long flags; |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 603 | int vrr_active; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 604 | |
Andrey Grodzovsky | b57de80 | 2017-04-19 13:29:11 -0400 | [diff] [blame] | 605 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 606 | if (!acrtc) |
| 607 | return; |
| 608 | |
Hersen Wu | 922c287 | 2024-04-30 14:24:17 -0400 | [diff] [blame] | 609 | if (acrtc->wb_conn) { |
| 610 | spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); |
| 611 | |
| 612 | if (acrtc->wb_pending) { |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 613 | job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, |
| 614 | struct drm_writeback_job, |
| 615 | list_entry); |
Hersen Wu | 922c287 | 2024-04-30 14:24:17 -0400 | [diff] [blame] | 616 | acrtc->wb_pending = false; |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 617 | spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); |
| 618 | |
Alex Hung | 87ce0e6 | 2023-12-01 06:25:39 -0700 | [diff] [blame] | 619 | if (job) { |
| 620 | unsigned int v_total, refresh_hz; |
| 621 | struct dc_stream_state *stream = acrtc->dm_irq_params.stream; |
| 622 | |
| 623 | v_total = stream->adjust.v_total_max ? |
| 624 | stream->adjust.v_total_max : stream->timing.v_total; |
| 625 | refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz * |
| 626 | 100LL, (v_total * stream->timing.h_total)); |
| 627 | mdelay(1000 / refresh_hz); |
| 628 | |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 629 | drm_writeback_signal_completion(acrtc->wb_conn, 0); |
Alex Hung | 87ce0e6 | 2023-12-01 06:25:39 -0700 | [diff] [blame] | 630 | dc_stream_fc_disable_writeback(adev->dm.dc, |
| 631 | acrtc->dm_irq_params.stream, 0); |
| 632 | } |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 633 | } else |
Hersen Wu | 922c287 | 2024-04-30 14:24:17 -0400 | [diff] [blame] | 634 | spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 635 | } |
| 636 | |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 637 | vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 638 | |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 639 | drm_dbg_vbl(adev_to_drm(adev), |
| 640 | "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, |
| 641 | vrr_active, acrtc->dm_irq_params.active_planes); |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 642 | |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 643 | /** |
| 644 | * Core vblank handling at start of front-porch is only possible |
| 645 | * in non-vrr mode, as only there vblank timestamping will give |
| 646 | * valid results while done in front-porch. Otherwise defer it |
| 647 | * to dm_vupdate_high_irq after end of front-porch. |
| 648 | */ |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 649 | if (!vrr_active) |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 650 | amdgpu_dm_crtc_handle_vblank(acrtc); |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 651 | |
| 652 | /** |
| 653 | * Following stuff must happen at start of vblank, for crc |
| 654 | * computation and below-the-range btr support in vrr mode. |
| 655 | */ |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 656 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 657 | |
| 658 | /* BTR updates need to happen before VUPDATE on Vega and above. */ |
| 659 | if (adev->family < AMDGPU_FAMILY_AI) |
| 660 | return; |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 661 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 662 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 663 | |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 664 | if (acrtc->dm_irq_params.stream && |
| 665 | acrtc->dm_irq_params.vrr_params.supported && |
| 666 | acrtc->dm_irq_params.freesync_config.state == |
| 667 | VRR_STATE_ACTIVE_VARIABLE) { |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 668 | mod_freesync_handle_v_update(adev->dm.freesync_module, |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 669 | acrtc->dm_irq_params.stream, |
| 670 | &acrtc->dm_irq_params.vrr_params); |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 671 | |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 672 | dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, |
| 673 | &acrtc->dm_irq_params.vrr_params.adjust); |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 674 | } |
| 675 | |
Mario Kleiner | 2b5aed9 | 2020-03-02 07:17:32 +0100 | [diff] [blame] | 676 | /* |
| 677 | * If there aren't any active_planes then DCH HUBP may be clock-gated. |
| 678 | * In that case, pageflip completion interrupts won't fire and pageflip |
| 679 | * completion events won't get delivered. Prevent this by sending |
| 680 | * pending pageflip events from here if a flip is still pending. |
| 681 | * |
| 682 | * If any planes are enabled, use dm_pflip_high_irq() instead, to |
| 683 | * avoid race conditions between flip programming and completion, |
| 684 | * which could cause too early flip completion events. |
| 685 | */ |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 686 | if (adev->family >= AMDGPU_FAMILY_RV && |
| 687 | acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 688 | acrtc->dm_irq_params.active_planes == 0) { |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 689 | if (acrtc->event) { |
| 690 | drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); |
| 691 | acrtc->event = NULL; |
| 692 | drm_crtc_vblank_put(&acrtc->base); |
| 693 | } |
| 694 | acrtc->pflip_status = AMDGPU_FLIP_NONE; |
| 695 | } |
| 696 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 697 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Leo Li | 16f17ed | 2019-11-04 09:22:23 -0500 | [diff] [blame] | 698 | } |
| 699 | |
Lee Jones | 9e1178e | 2021-05-26 09:47:04 +0100 | [diff] [blame] | 700 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 701 | /** |
| 702 | * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for |
| 703 | * DCN generation ASICs |
Lee Jones | 48e01bf | 2021-05-26 09:47:12 +0100 | [diff] [blame] | 704 | * @interrupt_params: interrupt parameters |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 705 | * |
| 706 | * Used to set crc window/read out crc value at vertical line 0 position |
| 707 | */ |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 708 | static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) |
| 709 | { |
| 710 | struct common_irq_params *irq_params = interrupt_params; |
| 711 | struct amdgpu_device *adev = irq_params->adev; |
| 712 | struct amdgpu_crtc *acrtc; |
| 713 | |
| 714 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); |
| 715 | |
| 716 | if (!acrtc) |
| 717 | return; |
| 718 | |
| 719 | amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); |
| 720 | } |
Anson Jacob | 433e5de | 2021-11-04 16:51:57 -0400 | [diff] [blame] | 721 | #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 722 | |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 723 | /** |
Yann Dirson | 03f2abb | 2021-12-14 00:30:29 +0100 | [diff] [blame] | 724 | * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 725 | * @adev: amdgpu_device pointer |
| 726 | * @notify: dmub notification structure |
| 727 | * |
| 728 | * Dmub AUX or SET_CONFIG command completion processing callback |
| 729 | * Copies dmub notification to DM which is to be read by AUX command. |
| 730 | * issuing thread and also signals the event to wake up the thread. |
| 731 | */ |
Isabella Basso | 240e6d2 | 2021-12-08 14:46:51 -0300 | [diff] [blame] | 732 | static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, |
| 733 | struct dmub_notification *notify) |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 734 | { |
| 735 | if (adev->dm.dmub_notify) |
| 736 | memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); |
| 737 | if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) |
| 738 | complete(&adev->dm.dmub_aux_transfer_done); |
| 739 | } |
| 740 | |
| 741 | /** |
| 742 | * dmub_hpd_callback - DMUB HPD interrupt processing callback. |
| 743 | * @adev: amdgpu_device pointer |
| 744 | * @notify: dmub notification structure |
| 745 | * |
| 746 | * Dmub Hpd interrupt processing callback. Gets displayindex through the |
| 747 | * ink index and calls helper to do the processing. |
| 748 | */ |
Isabella Basso | 240e6d2 | 2021-12-08 14:46:51 -0300 | [diff] [blame] | 749 | static void dmub_hpd_callback(struct amdgpu_device *adev, |
| 750 | struct dmub_notification *notify) |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 751 | { |
| 752 | struct amdgpu_dm_connector *aconnector; |
Jude Shih | f6e03f8 | 2021-09-13 14:41:34 +0800 | [diff] [blame] | 753 | struct amdgpu_dm_connector *hpd_aconnector = NULL; |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 754 | struct drm_connector *connector; |
| 755 | struct drm_connector_list_iter iter; |
| 756 | struct dc_link *link; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 757 | u8 link_index = 0; |
José Expósito | 978ffac8 | 2022-01-09 19:42:45 +0100 | [diff] [blame] | 758 | struct drm_device *dev; |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 759 | |
| 760 | if (adev == NULL) |
| 761 | return; |
| 762 | |
| 763 | if (notify == NULL) { |
| 764 | DRM_ERROR("DMUB HPD callback notification was NULL"); |
| 765 | return; |
| 766 | } |
| 767 | |
| 768 | if (notify->link_index > adev->dm.dc->link_count) { |
| 769 | DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); |
| 770 | return; |
| 771 | } |
| 772 | |
Tom Chung | 52d4e3f | 2024-09-13 15:44:40 +0800 | [diff] [blame] | 773 | /* Skip DMUB HPD IRQ in suspend/resume. We will probe them later. */ |
| 774 | if (notify->type == DMUB_NOTIFICATION_HPD && adev->in_suspend) { |
| 775 | DRM_INFO("Skip DMUB HPD IRQ callback in suspend/resume\n"); |
| 776 | return; |
| 777 | } |
| 778 | |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 779 | link_index = notify->link_index; |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 780 | link = adev->dm.dc->links[link_index]; |
José Expósito | 978ffac8 | 2022-01-09 19:42:45 +0100 | [diff] [blame] | 781 | dev = adev->dm.ddev; |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 782 | |
| 783 | drm_connector_list_iter_begin(dev, &iter); |
| 784 | drm_for_each_connector_iter(connector, &iter) { |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 785 | |
| 786 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 787 | continue; |
| 788 | |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 789 | aconnector = to_amdgpu_dm_connector(connector); |
| 790 | if (link && aconnector->dc_link == link) { |
Stylon Wang | c416a9e | 2023-03-01 23:56:51 +0800 | [diff] [blame] | 791 | if (notify->type == DMUB_NOTIFICATION_HPD) |
Stylon Wang | c416a9e | 2023-03-01 23:56:51 +0800 | [diff] [blame] | 792 | DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); |
Wayne Lin | e32e15d | 2024-05-27 15:04:31 +0800 | [diff] [blame] | 793 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) |
| 794 | DRM_INFO("DMUB HPD RX IRQ callback: link_index=%u\n", link_index); |
Stylon Wang | c416a9e | 2023-03-01 23:56:51 +0800 | [diff] [blame] | 795 | else |
| 796 | DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", |
| 797 | notify->type, link_index); |
| 798 | |
Jude Shih | f6e03f8 | 2021-09-13 14:41:34 +0800 | [diff] [blame] | 799 | hpd_aconnector = aconnector; |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 800 | break; |
| 801 | } |
| 802 | } |
| 803 | drm_connector_list_iter_end(&iter); |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 804 | |
Nicholas Kazlauskas | c40a09e | 2021-11-04 16:52:07 -0400 | [diff] [blame] | 805 | if (hpd_aconnector) { |
Wayne Lin | e32e15d | 2024-05-27 15:04:31 +0800 | [diff] [blame] | 806 | if (notify->type == DMUB_NOTIFICATION_HPD) { |
| 807 | if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG)) |
| 808 | DRM_WARN("DMUB reported hpd status unchanged. link_index=%u\n", link_index); |
Nicholas Kazlauskas | c40a09e | 2021-11-04 16:52:07 -0400 | [diff] [blame] | 809 | handle_hpd_irq_helper(hpd_aconnector); |
Wayne Lin | e32e15d | 2024-05-27 15:04:31 +0800 | [diff] [blame] | 810 | } else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) { |
Nicholas Kazlauskas | c40a09e | 2021-11-04 16:52:07 -0400 | [diff] [blame] | 811 | handle_hpd_rx_irq(hpd_aconnector); |
Wayne Lin | e32e15d | 2024-05-27 15:04:31 +0800 | [diff] [blame] | 812 | } |
Nicholas Kazlauskas | c40a09e | 2021-11-04 16:52:07 -0400 | [diff] [blame] | 813 | } |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 814 | } |
| 815 | |
| 816 | /** |
Roman Li | 5a3d3e1 | 2024-08-21 10:53:15 -0400 | [diff] [blame] | 817 | * dmub_hpd_sense_callback - DMUB HPD sense processing callback. |
| 818 | * @adev: amdgpu_device pointer |
| 819 | * @notify: dmub notification structure |
| 820 | * |
| 821 | * HPD sense changes can occur during low power states and need to be |
| 822 | * notified from firmware to driver. |
| 823 | */ |
| 824 | static void dmub_hpd_sense_callback(struct amdgpu_device *adev, |
| 825 | struct dmub_notification *notify) |
| 826 | { |
| 827 | DRM_DEBUG_DRIVER("DMUB HPD SENSE callback.\n"); |
| 828 | } |
| 829 | |
| 830 | /** |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 831 | * register_dmub_notify_callback - Sets callback for DMUB notify |
| 832 | * @adev: amdgpu_device pointer |
| 833 | * @type: Type of dmub notification |
| 834 | * @callback: Dmub interrupt callback function |
| 835 | * @dmub_int_thread_offload: offload indicator |
| 836 | * |
| 837 | * API to register a dmub callback handler for a dmub notification |
| 838 | * Also sets indicator whether callback processing to be offloaded. |
| 839 | * to dmub interrupt handling thread |
| 840 | * Return: true if successfully registered, false if there is existing registration |
| 841 | */ |
Isabella Basso | 240e6d2 | 2021-12-08 14:46:51 -0300 | [diff] [blame] | 842 | static bool register_dmub_notify_callback(struct amdgpu_device *adev, |
| 843 | enum dmub_notification_type type, |
| 844 | dmub_notify_interrupt_callback_t callback, |
| 845 | bool dmub_int_thread_offload) |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 846 | { |
| 847 | if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { |
| 848 | adev->dm.dmub_callback[type] = callback; |
| 849 | adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; |
| 850 | } else |
| 851 | return false; |
| 852 | |
| 853 | return true; |
| 854 | } |
| 855 | |
| 856 | static void dm_handle_hpd_work(struct work_struct *work) |
| 857 | { |
| 858 | struct dmub_hpd_work *dmub_hpd_wrk; |
| 859 | |
| 860 | dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); |
| 861 | |
| 862 | if (!dmub_hpd_wrk->dmub_notify) { |
| 863 | DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); |
| 864 | return; |
| 865 | } |
| 866 | |
| 867 | if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { |
| 868 | dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, |
| 869 | dmub_hpd_wrk->dmub_notify); |
| 870 | } |
Jude Shih | 094b21c | 2021-10-18 12:04:23 +0800 | [diff] [blame] | 871 | |
| 872 | kfree(dmub_hpd_wrk->dmub_notify); |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 873 | kfree(dmub_hpd_wrk); |
| 874 | |
| 875 | } |
| 876 | |
Anson Jacob | e25515e | 2021-07-19 13:46:09 -0400 | [diff] [blame] | 877 | #define DMUB_TRACE_MAX_READ 64 |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 878 | /** |
| 879 | * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt |
| 880 | * @interrupt_params: used for determining the Outbox instance |
| 881 | * |
| 882 | * Handles the Outbox Interrupt |
| 883 | * event handler. |
| 884 | */ |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 885 | static void dm_dmub_outbox1_low_irq(void *interrupt_params) |
| 886 | { |
Alex Hung | f95bcb0 | 2024-04-15 19:02:56 -0600 | [diff] [blame] | 887 | struct dmub_notification notify = {0}; |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 888 | struct common_irq_params *irq_params = interrupt_params; |
| 889 | struct amdgpu_device *adev = irq_params->adev; |
| 890 | struct amdgpu_display_manager *dm = &adev->dm; |
| 891 | struct dmcub_trace_buf_entry entry = { 0 }; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 892 | u32 count = 0; |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 893 | struct dmub_hpd_work *dmub_hpd_wrk; |
Wayne Lin | e32e15d | 2024-05-27 15:04:31 +0800 | [diff] [blame] | 894 | static const char *const event_type[] = { |
| 895 | "NO_DATA", |
| 896 | "AUX_REPLY", |
| 897 | "HPD", |
| 898 | "HPD_IRQ", |
| 899 | "SET_CONFIGC_REPLY", |
| 900 | "DPIA_NOTIFICATION", |
Charlene Liu | 093b79d | 2024-07-16 15:58:35 -0400 | [diff] [blame] | 901 | "HPD_SENSE_NOTIFY", |
Wayne Lin | e32e15d | 2024-05-27 15:04:31 +0800 | [diff] [blame] | 902 | }; |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 903 | |
| 904 | do { |
| 905 | if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { |
| 906 | trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, |
| 907 | entry.param0, entry.param1); |
| 908 | |
| 909 | DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", |
| 910 | entry.trace_code, entry.tick_count, entry.param0, entry.param1); |
| 911 | } else |
| 912 | break; |
| 913 | |
| 914 | count++; |
| 915 | |
| 916 | } while (count <= DMUB_TRACE_MAX_READ); |
| 917 | |
Jude Shih | f6e03f8 | 2021-09-13 14:41:34 +0800 | [diff] [blame] | 918 | if (count > DMUB_TRACE_MAX_READ) |
| 919 | DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); |
Leo (Sunpeng) Li | e5d0170 | 2018-08-13 17:45:05 -0400 | [diff] [blame] | 920 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 921 | if (dc_enable_dmub_notifications(adev->dm.dc) && |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 922 | irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { |
| 923 | |
| 924 | do { |
| 925 | dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); |
| 926 | if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { |
| 927 | DRM_ERROR("DM: notify type %d invalid!", notify.type); |
| 928 | continue; |
| 929 | } |
| 930 | if (!dm->dmub_callback[notify.type]) { |
Wayne Lin | e32e15d | 2024-05-27 15:04:31 +0800 | [diff] [blame] | 931 | DRM_WARN("DMUB notification skipped due to no handler: type=%s\n", |
| 932 | event_type[notify.type]); |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 933 | continue; |
| 934 | } |
| 935 | if (dm->dmub_thread_offload[notify.type] == true) { |
| 936 | dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); |
| 937 | if (!dmub_hpd_wrk) { |
| 938 | DRM_ERROR("Failed to allocate dmub_hpd_wrk"); |
| 939 | return; |
| 940 | } |
| 941 | dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), |
| 942 | GFP_ATOMIC); |
| 943 | if (!dmub_hpd_wrk->dmub_notify) { |
| 944 | kfree(dmub_hpd_wrk); |
| 945 | DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); |
| 946 | return; |
| 947 | } |
| 948 | INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); |
| 949 | dmub_hpd_wrk->adev = adev; |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 950 | queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); |
| 951 | } else { |
| 952 | dm->dmub_callback[notify.type](adev, ¬ify); |
| 953 | } |
| 954 | } while (notify.pending_notification); |
| 955 | } |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 956 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 957 | |
| 958 | static int dm_set_clockgating_state(void *handle, |
| 959 | enum amd_clockgating_state state) |
| 960 | { |
| 961 | return 0; |
| 962 | } |
| 963 | |
| 964 | static int dm_set_powergating_state(void *handle, |
| 965 | enum amd_powergating_state state) |
| 966 | { |
| 967 | return 0; |
| 968 | } |
| 969 | |
| 970 | /* Prototypes of private functions */ |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 971 | static int dm_early_init(void *handle); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 972 | |
Roman Li | a32e24b | 2017-07-27 19:53:55 -0400 | [diff] [blame] | 973 | /* Allocate memory for FBC compressed data */ |
Roman Li | 3e332d3 | 2018-02-06 18:47:26 -0500 | [diff] [blame] | 974 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
Roman Li | a32e24b | 2017-07-27 19:53:55 -0400 | [diff] [blame] | 975 | { |
Srinivasan Shanmugam | 534eee8 | 2023-11-12 09:30:51 +0530 | [diff] [blame] | 976 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
Mauro Carvalho Chehab | 4d154b8 | 2020-10-23 18:32:49 +0200 | [diff] [blame] | 977 | struct dm_compressor_info *compressor = &adev->dm.compressor; |
Roman Li | 3e332d3 | 2018-02-06 18:47:26 -0500 | [diff] [blame] | 978 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); |
| 979 | struct drm_display_mode *mode; |
Roman Li | 42e67c3 | 2017-12-13 17:25:02 -0500 | [diff] [blame] | 980 | unsigned long max_size = 0; |
Roman Li | a32e24b | 2017-07-27 19:53:55 -0400 | [diff] [blame] | 981 | |
Roman Li | 42e67c3 | 2017-12-13 17:25:02 -0500 | [diff] [blame] | 982 | if (adev->dm.dc->fbc_compressor == NULL) |
| 983 | return; |
Roman Li | a32e24b | 2017-07-27 19:53:55 -0400 | [diff] [blame] | 984 | |
Roman Li | 3e332d3 | 2018-02-06 18:47:26 -0500 | [diff] [blame] | 985 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
| 986 | return; |
| 987 | |
Roman Li | 42e67c3 | 2017-12-13 17:25:02 -0500 | [diff] [blame] | 988 | if (compressor->bo_ptr) |
| 989 | return; |
| 990 | |
Roman Li | 42e67c3 | 2017-12-13 17:25:02 -0500 | [diff] [blame] | 991 | |
Roman Li | 3e332d3 | 2018-02-06 18:47:26 -0500 | [diff] [blame] | 992 | list_for_each_entry(mode, &connector->modes, head) { |
Alex Hung | 143818f | 2024-06-05 12:37:18 -0600 | [diff] [blame] | 993 | if (max_size < (unsigned long) mode->htotal * mode->vtotal) |
| 994 | max_size = (unsigned long) mode->htotal * mode->vtotal; |
Roman Li | a32e24b | 2017-07-27 19:53:55 -0400 | [diff] [blame] | 995 | } |
| 996 | |
Roman Li | 42e67c3 | 2017-12-13 17:25:02 -0500 | [diff] [blame] | 997 | if (max_size) { |
| 998 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, |
Shirish S | 0e5916f | 2018-02-20 14:34:16 +0530 | [diff] [blame] | 999 | AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, |
Roman Li | 42e67c3 | 2017-12-13 17:25:02 -0500 | [diff] [blame] | 1000 | &compressor->gpu_addr, &compressor->cpu_addr); |
| 1001 | |
| 1002 | if (r) |
| 1003 | DRM_ERROR("DM: Failed to initialize FBC\n"); |
| 1004 | else { |
| 1005 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; |
| 1006 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4); |
| 1007 | } |
| 1008 | |
| 1009 | } |
| 1010 | |
Roman Li | a32e24b | 2017-07-27 19:53:55 -0400 | [diff] [blame] | 1011 | } |
Roman Li | a32e24b | 2017-07-27 19:53:55 -0400 | [diff] [blame] | 1012 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 1013 | static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, |
| 1014 | int pipe, bool *enabled, |
| 1015 | unsigned char *buf, int max_bytes) |
| 1016 | { |
| 1017 | struct drm_device *dev = dev_get_drvdata(kdev); |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 1018 | struct amdgpu_device *adev = drm_to_adev(dev); |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 1019 | struct drm_connector *connector; |
| 1020 | struct drm_connector_list_iter conn_iter; |
| 1021 | struct amdgpu_dm_connector *aconnector; |
| 1022 | int ret = 0; |
| 1023 | |
| 1024 | *enabled = false; |
| 1025 | |
| 1026 | mutex_lock(&adev->dm.audio_lock); |
| 1027 | |
| 1028 | drm_connector_list_iter_begin(dev, &conn_iter); |
| 1029 | drm_for_each_connector_iter(connector, &conn_iter) { |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 1030 | |
| 1031 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 1032 | continue; |
| 1033 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 1034 | aconnector = to_amdgpu_dm_connector(connector); |
| 1035 | if (aconnector->audio_inst != port) |
| 1036 | continue; |
| 1037 | |
| 1038 | *enabled = true; |
| 1039 | ret = drm_eld_size(connector->eld); |
| 1040 | memcpy(buf, connector->eld, min(max_bytes, ret)); |
| 1041 | |
| 1042 | break; |
| 1043 | } |
| 1044 | drm_connector_list_iter_end(&conn_iter); |
| 1045 | |
| 1046 | mutex_unlock(&adev->dm.audio_lock); |
| 1047 | |
| 1048 | DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); |
| 1049 | |
| 1050 | return ret; |
| 1051 | } |
| 1052 | |
| 1053 | static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { |
| 1054 | .get_eld = amdgpu_dm_audio_component_get_eld, |
| 1055 | }; |
| 1056 | |
| 1057 | static int amdgpu_dm_audio_component_bind(struct device *kdev, |
| 1058 | struct device *hda_kdev, void *data) |
| 1059 | { |
| 1060 | struct drm_device *dev = dev_get_drvdata(kdev); |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 1061 | struct amdgpu_device *adev = drm_to_adev(dev); |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 1062 | struct drm_audio_component *acomp = data; |
| 1063 | |
| 1064 | acomp->ops = &amdgpu_dm_audio_component_ops; |
| 1065 | acomp->dev = kdev; |
| 1066 | adev->dm.audio_component = acomp; |
| 1067 | |
| 1068 | return 0; |
| 1069 | } |
| 1070 | |
| 1071 | static void amdgpu_dm_audio_component_unbind(struct device *kdev, |
| 1072 | struct device *hda_kdev, void *data) |
| 1073 | { |
Srinivasan Shanmugam | 534eee8 | 2023-11-12 09:30:51 +0530 | [diff] [blame] | 1074 | struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev)); |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 1075 | struct drm_audio_component *acomp = data; |
| 1076 | |
| 1077 | acomp->ops = NULL; |
| 1078 | acomp->dev = NULL; |
| 1079 | adev->dm.audio_component = NULL; |
| 1080 | } |
| 1081 | |
| 1082 | static const struct component_ops amdgpu_dm_audio_component_bind_ops = { |
| 1083 | .bind = amdgpu_dm_audio_component_bind, |
| 1084 | .unbind = amdgpu_dm_audio_component_unbind, |
| 1085 | }; |
| 1086 | |
| 1087 | static int amdgpu_dm_audio_init(struct amdgpu_device *adev) |
| 1088 | { |
| 1089 | int i, ret; |
| 1090 | |
| 1091 | if (!amdgpu_audio) |
| 1092 | return 0; |
| 1093 | |
| 1094 | adev->mode_info.audio.enabled = true; |
| 1095 | |
| 1096 | adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; |
| 1097 | |
| 1098 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1099 | adev->mode_info.audio.pin[i].channels = -1; |
| 1100 | adev->mode_info.audio.pin[i].rate = -1; |
| 1101 | adev->mode_info.audio.pin[i].bits_per_sample = -1; |
| 1102 | adev->mode_info.audio.pin[i].status_bits = 0; |
| 1103 | adev->mode_info.audio.pin[i].category_code = 0; |
| 1104 | adev->mode_info.audio.pin[i].connected = false; |
| 1105 | adev->mode_info.audio.pin[i].id = |
| 1106 | adev->dm.dc->res_pool->audios[i]->inst; |
| 1107 | adev->mode_info.audio.pin[i].offset = 0; |
| 1108 | } |
| 1109 | |
| 1110 | ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); |
| 1111 | if (ret < 0) |
| 1112 | return ret; |
| 1113 | |
| 1114 | adev->dm.audio_registered = true; |
| 1115 | |
| 1116 | return 0; |
| 1117 | } |
| 1118 | |
| 1119 | static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) |
| 1120 | { |
| 1121 | if (!amdgpu_audio) |
| 1122 | return; |
| 1123 | |
| 1124 | if (!adev->mode_info.audio.enabled) |
| 1125 | return; |
| 1126 | |
| 1127 | if (adev->dm.audio_registered) { |
| 1128 | component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); |
| 1129 | adev->dm.audio_registered = false; |
| 1130 | } |
| 1131 | |
| 1132 | /* TODO: Disable audio? */ |
| 1133 | |
| 1134 | adev->mode_info.audio.enabled = false; |
| 1135 | } |
| 1136 | |
Nirmoy Das | dfd84d9 | 2020-06-18 15:07:13 +0200 | [diff] [blame] | 1137 | static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 1138 | { |
| 1139 | struct drm_audio_component *acomp = adev->dm.audio_component; |
| 1140 | |
| 1141 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { |
| 1142 | DRM_DEBUG_KMS("Notify ELD: %d\n", pin); |
| 1143 | |
| 1144 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
| 1145 | pin, -1); |
| 1146 | } |
| 1147 | } |
| 1148 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1149 | static int dm_dmub_hw_init(struct amdgpu_device *adev) |
| 1150 | { |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1151 | const struct dmcub_firmware_header_v1_0 *hdr; |
| 1152 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 1153 | struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1154 | const struct firmware *dmub_fw = adev->dm.dmub_fw; |
| 1155 | struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; |
| 1156 | struct abm *abm = adev->dm.dc->res_pool->abm; |
Aurabindo Pillai | 96182df | 2023-08-08 16:25:59 -0400 | [diff] [blame] | 1157 | struct dc_context *ctx = adev->dm.dc->ctx; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1158 | struct dmub_srv_hw_params hw_params; |
| 1159 | enum dmub_status status; |
| 1160 | const unsigned char *fw_inst_const, *fw_bss_data; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 1161 | u32 i, fw_inst_const_size, fw_bss_data_size; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1162 | bool has_hw_support; |
| 1163 | |
| 1164 | if (!dmub_srv) |
| 1165 | /* DMUB isn't supported on the ASIC. */ |
| 1166 | return 0; |
| 1167 | |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 1168 | if (!fb_info) { |
| 1169 | DRM_ERROR("No framebuffer info for DMUB service.\n"); |
| 1170 | return -EINVAL; |
| 1171 | } |
| 1172 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1173 | if (!dmub_fw) { |
| 1174 | /* Firmware required for DMUB support. */ |
| 1175 | DRM_ERROR("No firmware provided for DMUB.\n"); |
| 1176 | return -EINVAL; |
| 1177 | } |
| 1178 | |
Aurabindo Pillai | 96182df | 2023-08-08 16:25:59 -0400 | [diff] [blame] | 1179 | /* initialize register offsets for ASICs with runtime initialization available */ |
| 1180 | if (dmub_srv->hw_funcs.init_reg_offsets) |
| 1181 | dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); |
| 1182 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1183 | status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); |
| 1184 | if (status != DMUB_STATUS_OK) { |
| 1185 | DRM_ERROR("Error checking HW support for DMUB: %d\n", status); |
| 1186 | return -EINVAL; |
| 1187 | } |
| 1188 | |
| 1189 | if (!has_hw_support) { |
| 1190 | DRM_INFO("DMUB unsupported on ASIC\n"); |
| 1191 | return 0; |
| 1192 | } |
| 1193 | |
Nicholas Kazlauskas | 47e62db | 2021-12-10 15:04:05 -0800 | [diff] [blame] | 1194 | /* Reset DMCUB if it was previously running - before we overwrite its memory. */ |
| 1195 | status = dmub_srv_hw_reset(dmub_srv); |
| 1196 | if (status != DMUB_STATUS_OK) |
| 1197 | DRM_WARN("Error resetting DMUB HW: %d\n", status); |
| 1198 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1199 | hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; |
| 1200 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1201 | fw_inst_const = dmub_fw->data + |
| 1202 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 1203 | PSP_HEADER_BYTES; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1204 | |
| 1205 | fw_bss_data = dmub_fw->data + |
| 1206 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + |
| 1207 | le32_to_cpu(hdr->inst_const_bytes); |
| 1208 | |
| 1209 | /* Copy firmware and bios info into FB memory. */ |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 1210 | fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - |
| 1211 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; |
| 1212 | |
| 1213 | fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); |
| 1214 | |
Hersen Wu | ddde28a | 2020-02-05 17:48:39 -0500 | [diff] [blame] | 1215 | /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, |
| 1216 | * amdgpu_ucode_init_single_fw will load dmub firmware |
| 1217 | * fw_inst_const part to cw0; otherwise, the firmware back door load |
| 1218 | * will be done by dm_dmub_hw_init |
| 1219 | */ |
| 1220 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 1221 | memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, |
| 1222 | fw_inst_const_size); |
| 1223 | } |
| 1224 | |
Nicholas Kazlauskas | a576b34 | 2020-04-05 16:41:14 -0400 | [diff] [blame] | 1225 | if (fw_bss_data_size) |
| 1226 | memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, |
| 1227 | fw_bss_data, fw_bss_data_size); |
Hersen Wu | ddde28a | 2020-02-05 17:48:39 -0500 | [diff] [blame] | 1228 | |
| 1229 | /* Copy firmware bios info into FB memory. */ |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 1230 | memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, |
| 1231 | adev->bios_size); |
| 1232 | |
| 1233 | /* Reset regions that need to be reset. */ |
| 1234 | memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, |
| 1235 | fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); |
| 1236 | |
| 1237 | memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, |
| 1238 | fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); |
| 1239 | |
| 1240 | memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, |
| 1241 | fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1242 | |
Roman Li | a329598 | 2024-05-06 15:34:55 -0400 | [diff] [blame] | 1243 | memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0, |
| 1244 | fb_info->fb[DMUB_WINDOW_SHARED_STATE].size); |
| 1245 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1246 | /* Initialize hardware. */ |
| 1247 | memset(&hw_params, 0, sizeof(hw_params)); |
| 1248 | hw_params.fb_base = adev->gmc.fb_start; |
Alex Deucher | 949933b | 2022-11-28 10:38:53 -0500 | [diff] [blame] | 1249 | hw_params.fb_offset = adev->vm_manager.vram_base_offset; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1250 | |
Hersen Wu | 31a7f4b | 2020-02-05 14:58:53 -0500 | [diff] [blame] | 1251 | /* backdoor load firmware and trigger dmub running */ |
| 1252 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) |
| 1253 | hw_params.load_inst_const = true; |
| 1254 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1255 | if (dmcu) |
| 1256 | hw_params.psp_version = dmcu->psp_version; |
| 1257 | |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 1258 | for (i = 0; i < fb_info->num_fb; ++i) |
| 1259 | hw_params.fb[i] = &fb_info->fb[i]; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1260 | |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 1261 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Roman Li | f6aa84b | 2022-09-29 14:37:00 -0400 | [diff] [blame] | 1262 | case IP_VERSION(3, 1, 3): |
| 1263 | case IP_VERSION(3, 1, 4): |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 1264 | case IP_VERSION(3, 5, 0): |
Hamza Mahfooz | 10740e4 | 2024-02-26 09:11:00 -0500 | [diff] [blame] | 1265 | case IP_VERSION(3, 5, 1): |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 1266 | case IP_VERSION(4, 0, 1): |
Tim Huang | 3b36f50 | 2022-01-25 11:14:46 +0800 | [diff] [blame] | 1267 | hw_params.dpia_supported = true; |
Tim Huang | 7367540 | 2022-01-27 10:48:41 +0800 | [diff] [blame] | 1268 | hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; |
Jude Shih | 5b10939 | 2021-10-21 22:00:13 +0800 | [diff] [blame] | 1269 | break; |
| 1270 | default: |
| 1271 | break; |
| 1272 | } |
| 1273 | |
Nicholas Kazlauskas | e730c58 | 2024-04-03 10:41:29 -0400 | [diff] [blame] | 1274 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
| 1275 | case IP_VERSION(3, 5, 0): |
| 1276 | case IP_VERSION(3, 5, 1): |
| 1277 | hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; |
| 1278 | break; |
| 1279 | default: |
| 1280 | break; |
| 1281 | } |
| 1282 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1283 | status = dmub_srv_hw_init(dmub_srv, &hw_params); |
| 1284 | if (status != DMUB_STATUS_OK) { |
| 1285 | DRM_ERROR("Error initializing DMUB HW: %d\n", status); |
| 1286 | return -EINVAL; |
| 1287 | } |
| 1288 | |
| 1289 | /* Wait for firmware load to finish. */ |
| 1290 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); |
| 1291 | if (status != DMUB_STATUS_OK) |
| 1292 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); |
| 1293 | |
| 1294 | /* Init DMCU and ABM if available. */ |
| 1295 | if (dmcu && abm) { |
| 1296 | dmcu->funcs->dmcu_init(dmcu); |
| 1297 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); |
| 1298 | } |
| 1299 | |
Roman Li | 051b788 | 2021-05-10 11:58:54 -0400 | [diff] [blame] | 1300 | if (!adev->dm.dc->ctx->dmub_srv) |
| 1301 | adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); |
Nicholas Kazlauskas | 9a71c7d | 2019-10-28 09:07:30 -0400 | [diff] [blame] | 1302 | if (!adev->dm.dc->ctx->dmub_srv) { |
| 1303 | DRM_ERROR("Couldn't allocate DC DMUB server!\n"); |
| 1304 | return -ENOMEM; |
| 1305 | } |
| 1306 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1307 | DRM_INFO("DMUB hardware initialized: version=0x%08X\n", |
| 1308 | adev->dm.dmcub_fw_version); |
| 1309 | |
| 1310 | return 0; |
| 1311 | } |
| 1312 | |
Nicholas Kazlauskas | 79d6b93 | 2021-12-15 18:18:41 -0500 | [diff] [blame] | 1313 | static void dm_dmub_hw_resume(struct amdgpu_device *adev) |
| 1314 | { |
| 1315 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; |
| 1316 | enum dmub_status status; |
| 1317 | bool init; |
Alex Hung | 2c2ee1d | 2024-06-11 10:51:31 -0600 | [diff] [blame] | 1318 | int r; |
Nicholas Kazlauskas | 79d6b93 | 2021-12-15 18:18:41 -0500 | [diff] [blame] | 1319 | |
| 1320 | if (!dmub_srv) { |
| 1321 | /* DMUB isn't supported on the ASIC. */ |
| 1322 | return; |
| 1323 | } |
| 1324 | |
| 1325 | status = dmub_srv_is_hw_init(dmub_srv, &init); |
| 1326 | if (status != DMUB_STATUS_OK) |
| 1327 | DRM_WARN("DMUB hardware init check failed: %d\n", status); |
| 1328 | |
| 1329 | if (status == DMUB_STATUS_OK && init) { |
| 1330 | /* Wait for firmware load to finish. */ |
| 1331 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); |
| 1332 | if (status != DMUB_STATUS_OK) |
| 1333 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); |
| 1334 | } else { |
| 1335 | /* Perform the full hardware initialization. */ |
Alex Hung | 2c2ee1d | 2024-06-11 10:51:31 -0600 | [diff] [blame] | 1336 | r = dm_dmub_hw_init(adev); |
| 1337 | if (r) |
| 1338 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); |
Nicholas Kazlauskas | 79d6b93 | 2021-12-15 18:18:41 -0500 | [diff] [blame] | 1339 | } |
| 1340 | } |
| 1341 | |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1342 | static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 1343 | { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 1344 | u64 pt_base; |
| 1345 | u32 logical_addr_low; |
| 1346 | u32 logical_addr_high; |
| 1347 | u32 agp_base, agp_bot, agp_top; |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1348 | PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 1349 | |
Nicholas Kazlauskas | a0f884f | 2021-09-13 14:56:44 -0400 | [diff] [blame] | 1350 | memset(pa_config, 0, sizeof(*pa_config)); |
| 1351 | |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1352 | agp_base = 0; |
| 1353 | agp_bot = adev->gmc.agp_start >> 24; |
| 1354 | agp_top = adev->gmc.agp_end >> 24; |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 1355 | |
Alex Deucher | 0294868f | 2023-01-31 09:56:46 -0500 | [diff] [blame] | 1356 | /* AGP aperture is disabled */ |
Alex Deucher | de59b69 | 2023-09-20 13:27:58 -0400 | [diff] [blame] | 1357 | if (agp_bot > agp_top) { |
Alex Deucher | 4d2c6e8 | 2023-02-08 23:38:01 -0500 | [diff] [blame] | 1358 | logical_addr_low = adev->gmc.fb_start >> 18; |
Alex Deucher | 16783d8 | 2024-01-03 11:55:53 -0500 | [diff] [blame] | 1359 | if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | |
| 1360 | AMD_APU_IS_RENOIR | |
| 1361 | AMD_APU_IS_GREEN_SARDINE)) |
Alex Deucher | 0294868f | 2023-01-31 09:56:46 -0500 | [diff] [blame] | 1362 | /* |
| 1363 | * Raven2 has a HW issue that it is unable to use the vram which |
| 1364 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the |
| 1365 | * workaround that increase system aperture high address (add 1) |
| 1366 | * to get rid of the VM fault and hardware hang. |
| 1367 | */ |
| 1368 | logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; |
| 1369 | else |
Alex Deucher | 4d2c6e8 | 2023-02-08 23:38:01 -0500 | [diff] [blame] | 1370 | logical_addr_high = adev->gmc.fb_end >> 18; |
Alex Deucher | 0294868f | 2023-01-31 09:56:46 -0500 | [diff] [blame] | 1371 | } else { |
Alex Deucher | 4d2c6e8 | 2023-02-08 23:38:01 -0500 | [diff] [blame] | 1372 | logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; |
Alex Deucher | 16783d8 | 2024-01-03 11:55:53 -0500 | [diff] [blame] | 1373 | if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | |
| 1374 | AMD_APU_IS_RENOIR | |
| 1375 | AMD_APU_IS_GREEN_SARDINE)) |
Alex Deucher | 0294868f | 2023-01-31 09:56:46 -0500 | [diff] [blame] | 1376 | /* |
| 1377 | * Raven2 has a HW issue that it is unable to use the vram which |
| 1378 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the |
| 1379 | * workaround that increase system aperture high address (add 1) |
| 1380 | * to get rid of the VM fault and hardware hang. |
| 1381 | */ |
| 1382 | logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); |
| 1383 | else |
| 1384 | logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; |
| 1385 | } |
| 1386 | |
| 1387 | pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 1388 | |
Yifan Zhang | ef06418 | 2023-09-08 16:46:39 +0800 | [diff] [blame] | 1389 | page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> |
| 1390 | AMDGPU_GPU_PAGE_SHIFT); |
| 1391 | page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> |
| 1392 | AMDGPU_GPU_PAGE_SHIFT); |
| 1393 | page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> |
| 1394 | AMDGPU_GPU_PAGE_SHIFT); |
| 1395 | page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> |
| 1396 | AMDGPU_GPU_PAGE_SHIFT); |
| 1397 | page_table_base.high_part = upper_32_bits(pt_base); |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1398 | page_table_base.low_part = lower_32_bits(pt_base); |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 1399 | |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1400 | pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; |
| 1401 | pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 1402 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 1403 | pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1404 | pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; |
| 1405 | pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; |
| 1406 | |
| 1407 | pa_config->system_aperture.fb_base = adev->gmc.fb_start; |
Alex Deucher | 949933b | 2022-11-28 10:38:53 -0500 | [diff] [blame] | 1408 | pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1409 | pa_config->system_aperture.fb_top = adev->gmc.fb_end; |
| 1410 | |
| 1411 | pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; |
| 1412 | pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; |
| 1413 | pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; |
| 1414 | |
Roman Li | 40e9f3f | 2023-01-05 17:44:10 -0500 | [diff] [blame] | 1415 | pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 1416 | |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 1417 | } |
Alex Hung | cae5c1a | 2022-04-25 15:12:02 -0600 | [diff] [blame] | 1418 | |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 1419 | static void force_connector_state( |
| 1420 | struct amdgpu_dm_connector *aconnector, |
| 1421 | enum drm_connector_force force_state) |
| 1422 | { |
| 1423 | struct drm_connector *connector = &aconnector->base; |
| 1424 | |
| 1425 | mutex_lock(&connector->dev->mode_config.mutex); |
| 1426 | aconnector->base.force = force_state; |
| 1427 | mutex_unlock(&connector->dev->mode_config.mutex); |
| 1428 | |
| 1429 | mutex_lock(&aconnector->hpd_lock); |
| 1430 | drm_kms_helper_connector_hotplug_event(connector); |
| 1431 | mutex_unlock(&aconnector->hpd_lock); |
| 1432 | } |
| 1433 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1434 | static void dm_handle_hpd_rx_offload_work(struct work_struct *work) |
| 1435 | { |
| 1436 | struct hpd_rx_irq_offload_work *offload_work; |
| 1437 | struct amdgpu_dm_connector *aconnector; |
| 1438 | struct dc_link *dc_link; |
| 1439 | struct amdgpu_device *adev; |
| 1440 | enum dc_connection_type new_connection_type = dc_connection_none; |
| 1441 | unsigned long flags; |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 1442 | union test_response test_response; |
| 1443 | |
| 1444 | memset(&test_response, 0, sizeof(test_response)); |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1445 | |
| 1446 | offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); |
| 1447 | aconnector = offload_work->offload_wq->aconnector; |
| 1448 | |
| 1449 | if (!aconnector) { |
| 1450 | DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); |
| 1451 | goto skip; |
| 1452 | } |
| 1453 | |
| 1454 | adev = drm_to_adev(aconnector->base.dev); |
| 1455 | dc_link = aconnector->dc_link; |
| 1456 | |
| 1457 | mutex_lock(&aconnector->hpd_lock); |
Wenjing Liu | 5461888 | 2023-01-18 17:31:24 -0500 | [diff] [blame] | 1458 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1459 | DRM_ERROR("KMS: Failed to detect connector\n"); |
| 1460 | mutex_unlock(&aconnector->hpd_lock); |
| 1461 | |
| 1462 | if (new_connection_type == dc_connection_none) |
| 1463 | goto skip; |
| 1464 | |
| 1465 | if (amdgpu_in_reset(adev)) |
| 1466 | goto skip; |
| 1467 | |
Wayne Lin | bb4fa52 | 2022-03-09 17:05:05 +0800 | [diff] [blame] | 1468 | if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || |
| 1469 | offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { |
| 1470 | dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); |
| 1471 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); |
| 1472 | offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; |
| 1473 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); |
| 1474 | goto skip; |
| 1475 | } |
| 1476 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1477 | mutex_lock(&adev->dm.dc_lock); |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 1478 | if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1479 | dc_link_dp_handle_automated_test(dc_link); |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 1480 | |
| 1481 | if (aconnector->timing_changed) { |
| 1482 | /* force connector disconnect and reconnect */ |
| 1483 | force_connector_state(aconnector, DRM_FORCE_OFF); |
| 1484 | msleep(100); |
| 1485 | force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); |
| 1486 | } |
| 1487 | |
| 1488 | test_response.bits.ACK = 1; |
| 1489 | |
| 1490 | core_link_write_dpcd( |
| 1491 | dc_link, |
| 1492 | DP_TEST_RESPONSE, |
| 1493 | &test_response.raw, |
| 1494 | sizeof(test_response)); |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 1495 | } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && |
Wenjing Liu | c5a31f1 | 2023-01-09 14:38:35 -0500 | [diff] [blame] | 1496 | dc_link_check_link_loss_status(dc_link, &offload_work->data) && |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1497 | dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
Hersen Wu | e322843 | 2023-01-17 10:58:34 -0500 | [diff] [blame] | 1498 | /* offload_work->data is from handle_hpd_rx_irq-> |
| 1499 | * schedule_hpd_rx_offload_work.this is defer handle |
| 1500 | * for hpd short pulse. upon here, link status may be |
| 1501 | * changed, need get latest link status from dpcd |
| 1502 | * registers. if link status is good, skip run link |
| 1503 | * training again. |
| 1504 | */ |
| 1505 | union hpd_irq_data irq_data; |
| 1506 | |
| 1507 | memset(&irq_data, 0, sizeof(irq_data)); |
| 1508 | |
| 1509 | /* before dc_link_dp_handle_link_loss, allow new link lost handle |
| 1510 | * request be added to work queue if link lost at end of dc_link_ |
| 1511 | * dp_handle_link_loss |
| 1512 | */ |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1513 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); |
| 1514 | offload_work->offload_wq->is_handling_link_loss = false; |
| 1515 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); |
Hersen Wu | e322843 | 2023-01-17 10:58:34 -0500 | [diff] [blame] | 1516 | |
Wenjing Liu | 5461888 | 2023-01-18 17:31:24 -0500 | [diff] [blame] | 1517 | if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && |
Hersen Wu | e322843 | 2023-01-17 10:58:34 -0500 | [diff] [blame] | 1518 | dc_link_check_link_loss_status(dc_link, &irq_data)) |
| 1519 | dc_link_dp_handle_link_loss(dc_link); |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1520 | } |
| 1521 | mutex_unlock(&adev->dm.dc_lock); |
| 1522 | |
| 1523 | skip: |
| 1524 | kfree(offload_work); |
| 1525 | |
| 1526 | } |
| 1527 | |
| 1528 | static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) |
| 1529 | { |
| 1530 | int max_caps = dc->caps.max_links; |
| 1531 | int i = 0; |
| 1532 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; |
| 1533 | |
| 1534 | hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); |
| 1535 | |
| 1536 | if (!hpd_rx_offload_wq) |
| 1537 | return NULL; |
| 1538 | |
| 1539 | |
| 1540 | for (i = 0; i < max_caps; i++) { |
| 1541 | hpd_rx_offload_wq[i].wq = |
| 1542 | create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); |
| 1543 | |
| 1544 | if (hpd_rx_offload_wq[i].wq == NULL) { |
| 1545 | DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); |
Rafael Mendonca | 7136f95 | 2022-09-12 19:34:32 -0300 | [diff] [blame] | 1546 | goto out_err; |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1547 | } |
| 1548 | |
| 1549 | spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); |
| 1550 | } |
| 1551 | |
| 1552 | return hpd_rx_offload_wq; |
Rafael Mendonca | 7136f95 | 2022-09-12 19:34:32 -0300 | [diff] [blame] | 1553 | |
| 1554 | out_err: |
| 1555 | for (i = 0; i < max_caps; i++) { |
| 1556 | if (hpd_rx_offload_wq[i].wq) |
| 1557 | destroy_workqueue(hpd_rx_offload_wq[i].wq); |
| 1558 | } |
| 1559 | kfree(hpd_rx_offload_wq); |
| 1560 | return NULL; |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 1561 | } |
| 1562 | |
Alex Deucher | 3ce5164 | 2021-10-20 16:45:00 -0400 | [diff] [blame] | 1563 | struct amdgpu_stutter_quirk { |
| 1564 | u16 chip_vendor; |
| 1565 | u16 chip_device; |
| 1566 | u16 subsys_vendor; |
| 1567 | u16 subsys_device; |
| 1568 | u8 revision; |
| 1569 | }; |
| 1570 | |
| 1571 | static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { |
| 1572 | /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ |
| 1573 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, |
| 1574 | { 0, 0, 0, 0, 0 }, |
| 1575 | }; |
| 1576 | |
| 1577 | static bool dm_should_disable_stutter(struct pci_dev *pdev) |
| 1578 | { |
| 1579 | const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; |
| 1580 | |
| 1581 | while (p && p->chip_device != 0) { |
| 1582 | if (pdev->vendor == p->chip_vendor && |
| 1583 | pdev->device == p->chip_device && |
| 1584 | pdev->subsystem_vendor == p->subsys_vendor && |
| 1585 | pdev->subsystem_device == p->subsys_device && |
| 1586 | pdev->revision == p->revision) { |
| 1587 | return true; |
| 1588 | } |
| 1589 | ++p; |
| 1590 | } |
| 1591 | return false; |
| 1592 | } |
| 1593 | |
Fangzhi Zuo | 57b9f33 | 2022-07-06 15:52:46 -0400 | [diff] [blame] | 1594 | static const struct dmi_system_id hpd_disconnect_quirk_table[] = { |
| 1595 | { |
| 1596 | .matches = { |
| 1597 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1598 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), |
| 1599 | }, |
| 1600 | }, |
| 1601 | { |
| 1602 | .matches = { |
| 1603 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1604 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), |
| 1605 | }, |
| 1606 | }, |
| 1607 | { |
| 1608 | .matches = { |
| 1609 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1610 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), |
| 1611 | }, |
| 1612 | }, |
Tsung-hua Lin | 503dc81 | 2022-11-09 12:54:22 +0800 | [diff] [blame] | 1613 | { |
| 1614 | .matches = { |
| 1615 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1616 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), |
| 1617 | }, |
| 1618 | }, |
| 1619 | { |
| 1620 | .matches = { |
| 1621 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1622 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), |
| 1623 | }, |
| 1624 | }, |
| 1625 | { |
| 1626 | .matches = { |
| 1627 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1628 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), |
| 1629 | }, |
| 1630 | }, |
| 1631 | { |
| 1632 | .matches = { |
| 1633 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1634 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), |
| 1635 | }, |
| 1636 | }, |
| 1637 | { |
| 1638 | .matches = { |
| 1639 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1640 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), |
| 1641 | }, |
| 1642 | }, |
| 1643 | { |
| 1644 | .matches = { |
| 1645 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 1646 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), |
| 1647 | }, |
| 1648 | }, |
Fangzhi Zuo | 57b9f33 | 2022-07-06 15:52:46 -0400 | [diff] [blame] | 1649 | {} |
Tsung-hua Lin | 503dc81 | 2022-11-09 12:54:22 +0800 | [diff] [blame] | 1650 | /* TODO: refactor this from a fixed table to a dynamic option */ |
Fangzhi Zuo | 57b9f33 | 2022-07-06 15:52:46 -0400 | [diff] [blame] | 1651 | }; |
| 1652 | |
| 1653 | static void retrieve_dmi_info(struct amdgpu_display_manager *dm) |
| 1654 | { |
| 1655 | const struct dmi_system_id *dmi_id; |
| 1656 | |
| 1657 | dm->aux_hpd_discon_quirk = false; |
| 1658 | |
| 1659 | dmi_id = dmi_first_match(hpd_disconnect_quirk_table); |
| 1660 | if (dmi_id) { |
| 1661 | dm->aux_hpd_discon_quirk = true; |
| 1662 | DRM_INFO("aux_hpd_discon_quirk attached\n"); |
| 1663 | } |
| 1664 | } |
| 1665 | |
Aurabindo Pillai | 234e945 | 2024-05-21 19:46:31 +0000 | [diff] [blame] | 1666 | void* |
| 1667 | dm_allocate_gpu_mem( |
| 1668 | struct amdgpu_device *adev, |
| 1669 | enum dc_gpu_mem_alloc_type type, |
| 1670 | size_t size, |
| 1671 | long long *addr) |
| 1672 | { |
| 1673 | struct dal_allocation *da; |
| 1674 | u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? |
| 1675 | AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; |
| 1676 | int ret; |
| 1677 | |
| 1678 | da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); |
| 1679 | if (!da) |
| 1680 | return NULL; |
| 1681 | |
| 1682 | ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, |
| 1683 | domain, &da->bo, |
| 1684 | &da->gpu_addr, &da->cpu_ptr); |
| 1685 | |
| 1686 | *addr = da->gpu_addr; |
| 1687 | |
| 1688 | if (ret) { |
| 1689 | kfree(da); |
| 1690 | return NULL; |
| 1691 | } |
| 1692 | |
| 1693 | /* add da to list in dm */ |
| 1694 | list_add(&da->list, &adev->dm.da_list); |
| 1695 | |
| 1696 | return da->cpu_ptr; |
| 1697 | } |
| 1698 | |
| 1699 | static enum dmub_status |
| 1700 | dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev, |
| 1701 | enum dmub_gpint_command command_code, |
| 1702 | uint16_t param, |
| 1703 | uint32_t timeout_us) |
| 1704 | { |
| 1705 | union dmub_gpint_data_register reg, test; |
| 1706 | uint32_t i; |
| 1707 | |
| 1708 | /* Assume that VBIOS DMUB is ready to take commands */ |
| 1709 | |
| 1710 | reg.bits.status = 1; |
| 1711 | reg.bits.command_code = command_code; |
| 1712 | reg.bits.param = param; |
| 1713 | |
| 1714 | cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all); |
| 1715 | |
| 1716 | for (i = 0; i < timeout_us; ++i) { |
| 1717 | udelay(1); |
| 1718 | |
| 1719 | /* Check if our GPINT got acked */ |
| 1720 | reg.bits.status = 0; |
| 1721 | test = (union dmub_gpint_data_register) |
| 1722 | cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8); |
| 1723 | |
| 1724 | if (test.all == reg.all) |
| 1725 | return DMUB_STATUS_OK; |
| 1726 | } |
| 1727 | |
| 1728 | return DMUB_STATUS_TIMEOUT; |
| 1729 | } |
| 1730 | |
| 1731 | static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev) |
| 1732 | { |
| 1733 | struct dml2_soc_bb *bb; |
| 1734 | long long addr; |
| 1735 | int i = 0; |
| 1736 | uint16_t chunk; |
| 1737 | enum dmub_gpint_command send_addrs[] = { |
| 1738 | DMUB_GPINT__SET_BB_ADDR_WORD0, |
| 1739 | DMUB_GPINT__SET_BB_ADDR_WORD1, |
| 1740 | DMUB_GPINT__SET_BB_ADDR_WORD2, |
| 1741 | DMUB_GPINT__SET_BB_ADDR_WORD3, |
| 1742 | }; |
| 1743 | enum dmub_status ret; |
| 1744 | |
| 1745 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
| 1746 | case IP_VERSION(4, 0, 1): |
| 1747 | break; |
| 1748 | default: |
| 1749 | return NULL; |
| 1750 | } |
| 1751 | |
| 1752 | bb = dm_allocate_gpu_mem(adev, |
| 1753 | DC_MEM_ALLOC_TYPE_GART, |
| 1754 | sizeof(struct dml2_soc_bb), |
| 1755 | &addr); |
| 1756 | if (!bb) |
| 1757 | return NULL; |
| 1758 | |
| 1759 | for (i = 0; i < 4; i++) { |
| 1760 | /* Extract 16-bit chunk */ |
| 1761 | chunk = ((uint64_t) addr >> (i * 16)) & 0xFFFF; |
| 1762 | /* Send the chunk */ |
| 1763 | ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000); |
| 1764 | if (ret != DMUB_STATUS_OK) |
Aurabindo Pillai | f59549c | 2024-07-03 16:41:52 -0400 | [diff] [blame] | 1765 | /* No need to free bb here since it shall be done in dm_sw_fini() */ |
Aurabindo Pillai | 234e945 | 2024-05-21 19:46:31 +0000 | [diff] [blame] | 1766 | return NULL; |
| 1767 | } |
| 1768 | |
| 1769 | /* Now ask DMUB to copy the bb */ |
| 1770 | ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000); |
| 1771 | if (ret != DMUB_STATUS_OK) |
| 1772 | return NULL; |
| 1773 | |
| 1774 | return bb; |
| 1775 | } |
| 1776 | |
Leo Li | 28d43d0 | 2024-08-27 11:29:53 -0400 | [diff] [blame] | 1777 | static enum dmub_ips_disable_type dm_get_default_ips_mode( |
| 1778 | struct amdgpu_device *adev) |
| 1779 | { |
Roman Li | 199888a | 2024-09-05 14:22:30 -0400 | [diff] [blame] | 1780 | enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE; |
Leo Li | 28d43d0 | 2024-08-27 11:29:53 -0400 | [diff] [blame] | 1781 | |
Roman Li | 199888a | 2024-09-05 14:22:30 -0400 | [diff] [blame] | 1782 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
| 1783 | case IP_VERSION(3, 5, 0): |
| 1784 | /* |
| 1785 | * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to |
| 1786 | * cause a hard hang. A fix exists for newer PMFW. |
| 1787 | * |
| 1788 | * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest |
| 1789 | * IPS state in all cases, except for s0ix and all displays off (DPMS), |
| 1790 | * where IPS2 is allowed. |
| 1791 | * |
| 1792 | * When checking pmfw version, use the major and minor only. |
| 1793 | */ |
| 1794 | if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300) |
| 1795 | ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; |
| 1796 | else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0)) |
| 1797 | /* |
| 1798 | * Other ASICs with DCN35 that have residency issues with |
| 1799 | * IPS2 in idle. |
| 1800 | * We want them to use IPS2 only in display off cases. |
| 1801 | */ |
| 1802 | ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; |
| 1803 | break; |
| 1804 | case IP_VERSION(3, 5, 1): |
| 1805 | ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; |
| 1806 | break; |
| 1807 | default: |
| 1808 | /* ASICs older than DCN35 do not have IPSs */ |
| 1809 | if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0)) |
| 1810 | ret = DMUB_IPS_DISABLE_ALL; |
| 1811 | break; |
| 1812 | } |
Leo Li | 28d43d0 | 2024-08-27 11:29:53 -0400 | [diff] [blame] | 1813 | |
Roman Li | 199888a | 2024-09-05 14:22:30 -0400 | [diff] [blame] | 1814 | return ret; |
Leo Li | 28d43d0 | 2024-08-27 11:29:53 -0400 | [diff] [blame] | 1815 | } |
| 1816 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 1817 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1818 | { |
| 1819 | struct dc_init_data init_data; |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 1820 | struct dc_callback_init init_params; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1821 | int r; |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 1822 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 1823 | adev->dm.ddev = adev_to_drm(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1824 | adev->dm.adev = adev; |
| 1825 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1826 | /* Zero all the fields */ |
| 1827 | memset(&init_data, 0, sizeof(init_data)); |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 1828 | memset(&init_params, 0, sizeof(init_params)); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1829 | |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 1830 | mutex_init(&adev->dm.dpia_aux_lock); |
Nicholas Kazlauskas | 674e78a | 2018-12-05 14:59:07 -0500 | [diff] [blame] | 1831 | mutex_init(&adev->dm.dc_lock); |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 1832 | mutex_init(&adev->dm.audio_lock); |
Nicholas Kazlauskas | 674e78a | 2018-12-05 14:59:07 -0500 | [diff] [blame] | 1833 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 1834 | if (amdgpu_dm_irq_init(adev)) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1835 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); |
| 1836 | goto error; |
| 1837 | } |
| 1838 | |
| 1839 | init_data.asic_id.chip_family = adev->family; |
| 1840 | |
Aly-Tawfik | 2dc31ca | 2020-02-25 14:56:37 -0500 | [diff] [blame] | 1841 | init_data.asic_id.pci_revision_id = adev->pdev->revision; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1842 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; |
Charlene Liu | dae66a0 | 2021-09-20 14:30:02 -0400 | [diff] [blame] | 1843 | init_data.asic_id.chip_id = adev->pdev->device; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1844 | |
Christian König | 770d13b1 | 2018-01-12 14:52:22 +0100 | [diff] [blame] | 1845 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1846 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
| 1847 | init_data.asic_id.atombios_base_address = |
| 1848 | adev->mode_info.atom_context->bios; |
| 1849 | |
| 1850 | init_data.driver = adev; |
| 1851 | |
Aurabindo Pillai | 7920af2 | 2024-05-16 10:23:19 -0400 | [diff] [blame] | 1852 | /* cgs_device was created in dm_sw_init() */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1853 | init_data.cgs_device = adev->dm.cgs_device; |
| 1854 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1855 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
| 1856 | |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 1857 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Alex Deucher | fd546bc | 2022-02-21 14:34:53 -0500 | [diff] [blame] | 1858 | case IP_VERSION(2, 1, 0): |
| 1859 | switch (adev->dm.dmcub_fw_version) { |
| 1860 | case 0: /* development */ |
| 1861 | case 0x1: /* linux-firmware.git hash 6d9f399 */ |
| 1862 | case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ |
| 1863 | init_data.flags.disable_dmcu = false; |
| 1864 | break; |
| 1865 | default: |
| 1866 | init_data.flags.disable_dmcu = true; |
| 1867 | } |
| 1868 | break; |
| 1869 | case IP_VERSION(2, 0, 3): |
| 1870 | init_data.flags.disable_dmcu = true; |
| 1871 | break; |
| 1872 | default: |
| 1873 | break; |
| 1874 | } |
| 1875 | |
Yifan Zhang | 098c130 | 2023-09-27 12:56:15 +0800 | [diff] [blame] | 1876 | /* APU support S/G display by default except: |
| 1877 | * ASICs before Carrizo, |
| 1878 | * RAVEN1 (Users reported stability issue) |
| 1879 | */ |
Harry Wentland | 6e22730 | 2017-10-30 13:41:51 -0400 | [diff] [blame] | 1880 | |
Yifan Zhang | 098c130 | 2023-09-27 12:56:15 +0800 | [diff] [blame] | 1881 | if (adev->asic_type < CHIP_CARRIZO) { |
| 1882 | init_data.flags.gpu_vm_support = false; |
| 1883 | } else if (adev->asic_type == CHIP_RAVEN) { |
| 1884 | if (adev->apu_flags & AMD_APU_IS_RAVEN) |
| 1885 | init_data.flags.gpu_vm_support = false; |
| 1886 | else |
| 1887 | init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); |
| 1888 | } else { |
| 1889 | init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); |
| 1890 | } |
| 1891 | |
Hamza Mahfooz | 1efdd37 | 2023-10-26 11:50:45 -0400 | [diff] [blame] | 1892 | adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; |
Alex Deucher | a7f520b | 2022-02-21 14:48:42 -0500 | [diff] [blame] | 1893 | |
Alex Deucher | 04b94af | 2018-11-06 15:19:49 -0500 | [diff] [blame] | 1894 | if (amdgpu_dc_feature_mask & DC_FBC_MASK) |
| 1895 | init_data.flags.fbc_support = true; |
| 1896 | |
Alex Deucher | d99f38a | 2019-08-22 14:17:57 -0500 | [diff] [blame] | 1897 | if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) |
| 1898 | init_data.flags.multi_mon_pp_mclk_switch = true; |
| 1899 | |
Leo Li | eaf5641 | 2019-10-21 14:58:47 -0400 | [diff] [blame] | 1900 | if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) |
| 1901 | init_data.flags.disable_fractional_pwm = true; |
| 1902 | |
Zhan Liu | a514824 | 2021-06-14 14:54:14 -0400 | [diff] [blame] | 1903 | if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) |
| 1904 | init_data.flags.edp_no_power_sequencing = true; |
| 1905 | |
Aurabindo Pillai | 1232027 | 2021-12-07 12:14:40 -0500 | [diff] [blame] | 1906 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) |
| 1907 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; |
| 1908 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) |
| 1909 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; |
Aurabindo Pillai | 1232027 | 2021-12-07 12:14:40 -0500 | [diff] [blame] | 1910 | |
Jarif Aftab | 7aba117 | 2021-11-16 18:24:06 -0500 | [diff] [blame] | 1911 | init_data.flags.seamless_boot_edp_requested = false; |
Thomas Lim | 78ad75f | 2019-05-07 15:08:22 -0500 | [diff] [blame] | 1912 | |
Mario Limonciello | bb0f842 | 2023-09-05 14:25:58 -0500 | [diff] [blame] | 1913 | if (amdgpu_device_seamless_boot_supported(adev)) { |
Jarif Aftab | 7aba117 | 2021-11-16 18:24:06 -0500 | [diff] [blame] | 1914 | init_data.flags.seamless_boot_edp_requested = true; |
Zhan Liu | 1edf5ae | 2021-11-08 19:31:00 -0500 | [diff] [blame] | 1915 | init_data.flags.allow_seamless_boot_optimization = true; |
| 1916 | DRM_INFO("Seamless boot condition check passed\n"); |
| 1917 | } |
| 1918 | |
Leung, Martin | a820190 | 2022-05-13 17:40:42 -0400 | [diff] [blame] | 1919 | init_data.flags.enable_mipi_converter_optimization = true; |
| 1920 | |
Harry Wentland | e5028e9 | 2022-02-01 15:37:37 -0500 | [diff] [blame] | 1921 | init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; |
Aurabindo Pillai | 2a93292 | 2022-04-04 13:38:57 -0400 | [diff] [blame] | 1922 | init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; |
Qingqing Zhuo | 8774029 | 2023-08-02 23:37:49 -0400 | [diff] [blame] | 1923 | init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; |
Harry Wentland | e5028e9 | 2022-02-01 15:37:37 -0500 | [diff] [blame] | 1924 | |
Roman Li | c82eb25 | 2024-01-23 15:18:24 -0500 | [diff] [blame] | 1925 | if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) |
| 1926 | init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; |
Leo Li | a08d759 | 2024-08-06 13:29:13 -0400 | [diff] [blame] | 1927 | else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) |
| 1928 | init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; |
| 1929 | else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) |
| 1930 | init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; |
| 1931 | else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) |
Roman Li | 9ba971b | 2024-04-12 14:34:30 -0400 | [diff] [blame] | 1932 | init_data.flags.disable_ips = DMUB_IPS_ENABLE; |
Roman Li | 1481393 | 2024-03-22 14:32:19 -0400 | [diff] [blame] | 1933 | else |
Leo Li | 28d43d0 | 2024-08-27 11:29:53 -0400 | [diff] [blame] | 1934 | init_data.flags.disable_ips = dm_get_default_ips_mode(adev); |
Roman Li | 1692704 | 2023-12-19 14:57:11 -0500 | [diff] [blame] | 1935 | |
Roman Li | 1481393 | 2024-03-22 14:32:19 -0400 | [diff] [blame] | 1936 | init_data.flags.disable_ips_in_vpb = 0; |
Nicholas Kazlauskas | ff8caad | 2023-12-07 14:12:03 -0500 | [diff] [blame] | 1937 | |
Harry Wentland | 198891f | 2023-12-01 06:25:23 -0700 | [diff] [blame] | 1938 | /* Enable DWB for tested platforms only */ |
Lijo Lazar | ed342a2 | 2023-12-01 17:13:46 +0530 | [diff] [blame] | 1939 | if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) |
Harry Wentland | 198891f | 2023-12-01 06:25:23 -0700 | [diff] [blame] | 1940 | init_data.num_virtual_links = 1; |
| 1941 | |
Fangzhi Zuo | 57b9f33 | 2022-07-06 15:52:46 -0400 | [diff] [blame] | 1942 | retrieve_dmi_info(&adev->dm); |
| 1943 | |
Aurabindo Pillai | 234e945 | 2024-05-21 19:46:31 +0000 | [diff] [blame] | 1944 | if (adev->dm.bb_from_dmub) |
| 1945 | init_data.bb_from_dmub = adev->dm.bb_from_dmub; |
| 1946 | else |
| 1947 | init_data.bb_from_dmub = NULL; |
| 1948 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1949 | /* Display Core create. */ |
| 1950 | adev->dm.dc = dc_create(&init_data); |
| 1951 | |
Ernst Sjöstrand | 423788c | 2017-11-07 21:06:59 +0100 | [diff] [blame] | 1952 | if (adev->dm.dc) { |
Aurabindo Pillai | 9788d087 | 2023-05-05 13:16:32 -0400 | [diff] [blame] | 1953 | DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, |
Rodrigo Siqueira | bf7fda0 | 2023-04-25 14:42:29 -0600 | [diff] [blame] | 1954 | dce_version_to_string(adev->dm.dc->ctx->dce_version)); |
Ernst Sjöstrand | 423788c | 2017-11-07 21:06:59 +0100 | [diff] [blame] | 1955 | } else { |
Cong Liu | 0c3601a | 2023-09-26 13:56:17 +0800 | [diff] [blame] | 1956 | DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); |
Ernst Sjöstrand | 423788c | 2017-11-07 21:06:59 +0100 | [diff] [blame] | 1957 | goto error; |
| 1958 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 1959 | |
Harry Wentland | 8a791da | 2020-05-01 14:23:37 -0400 | [diff] [blame] | 1960 | if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { |
| 1961 | adev->dm.dc->debug.force_single_disp_pipe_split = false; |
| 1962 | adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; |
| 1963 | } |
| 1964 | |
Harry Wentland | f99d876 | 2020-05-07 11:34:08 -0400 | [diff] [blame] | 1965 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
| 1966 | adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; |
Alex Deucher | 3ce5164 | 2021-10-20 16:45:00 -0400 | [diff] [blame] | 1967 | if (dm_should_disable_stutter(adev->pdev)) |
| 1968 | adev->dm.dc->debug.disable_stutter = true; |
Harry Wentland | f99d876 | 2020-05-07 11:34:08 -0400 | [diff] [blame] | 1969 | |
Harry Wentland | 8a791da | 2020-05-01 14:23:37 -0400 | [diff] [blame] | 1970 | if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) |
| 1971 | adev->dm.dc->debug.disable_stutter = true; |
| 1972 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 1973 | if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) |
Harry Wentland | 8a791da | 2020-05-01 14:23:37 -0400 | [diff] [blame] | 1974 | adev->dm.dc->debug.disable_dsc = true; |
| 1975 | |
| 1976 | if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) |
| 1977 | adev->dm.dc->debug.disable_clock_gate = true; |
| 1978 | |
Aurabindo Pillai | cfb979f | 2022-06-28 17:26:35 -0400 | [diff] [blame] | 1979 | if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) |
| 1980 | adev->dm.dc->debug.force_subvp_mclk_switch = true; |
| 1981 | |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 1982 | if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { |
Aurabindo Pillai | a568c49 | 2023-12-10 23:52:25 -0500 | [diff] [blame] | 1983 | adev->dm.dc->debug.using_dml2 = true; |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 1984 | adev->dm.dc->debug.using_dml21 = true; |
| 1985 | } |
Aurabindo Pillai | a568c49 | 2023-12-10 23:52:25 -0500 | [diff] [blame] | 1986 | |
Leo Li | 792a0cd | 2022-07-06 14:48:52 -0400 | [diff] [blame] | 1987 | adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; |
| 1988 | |
Fangzhi Zuo | d1bc26c | 2022-10-20 11:46:41 -0400 | [diff] [blame] | 1989 | /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ |
| 1990 | adev->dm.dc->debug.ignore_cable_id = true; |
| 1991 | |
Fangzhi Zuo | e383449 | 2023-01-16 16:29:26 -0500 | [diff] [blame] | 1992 | if (adev->dm.dc->caps.dp_hdmi21_pcon_support) |
| 1993 | DRM_INFO("DP-HDMI FRL PCON supported\n"); |
| 1994 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 1995 | r = dm_dmub_hw_init(adev); |
| 1996 | if (r) { |
| 1997 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); |
| 1998 | goto error; |
| 1999 | } |
| 2000 | |
Nicholas Kazlauskas | bb6785c | 2020-01-10 09:17:58 -0500 | [diff] [blame] | 2001 | dc_hardware_init(adev->dm.dc); |
| 2002 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 2003 | adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); |
| 2004 | if (!adev->dm.hpd_rx_offload_wq) { |
| 2005 | DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); |
| 2006 | goto error; |
| 2007 | } |
| 2008 | |
Aaron Liu | 3ca001a | 2021-08-23 12:26:50 +0800 | [diff] [blame] | 2009 | if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { |
Alex Deucher | e6cd859 | 2020-10-27 11:02:26 -0400 | [diff] [blame] | 2010 | struct dc_phy_addr_space_config pa_config; |
| 2011 | |
Yifan Zhang | 0b08c54 | 2020-10-20 14:40:16 +0800 | [diff] [blame] | 2012 | mmhub_read_system_context(adev, &pa_config); |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 2013 | |
Yifan Zhang | 0b08c54 | 2020-10-20 14:40:16 +0800 | [diff] [blame] | 2014 | // Call the DC init_memory func |
| 2015 | dc_setup_system_context(adev->dm.dc, &pa_config); |
| 2016 | } |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 2017 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2018 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
| 2019 | if (!adev->dm.freesync_module) { |
| 2020 | DRM_ERROR( |
| 2021 | "amdgpu: failed to initialize freesync_module.\n"); |
| 2022 | } else |
Harry Wentland | f1ad2f5 | 2017-09-12 20:04:48 -0400 | [diff] [blame] | 2023 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2024 | adev->dm.freesync_module); |
| 2025 | |
Leo (Sunpeng) Li | e277adc | 2018-02-02 10:18:56 -0500 | [diff] [blame] | 2026 | amdgpu_dm_init_color_mod(); |
| 2027 | |
Qingqing Zhuo | ea3b424 | 2021-02-09 16:36:41 -0500 | [diff] [blame] | 2028 | if (adev->dm.dc->caps.max_links > 0) { |
Nicholas Kazlauskas | 09a5df6 | 2021-08-03 15:12:26 -0400 | [diff] [blame] | 2029 | adev->dm.vblank_control_workqueue = |
| 2030 | create_singlethread_workqueue("dm_vblank_control_workqueue"); |
| 2031 | if (!adev->dm.vblank_control_workqueue) |
Qingqing Zhuo | ea3b424 | 2021-02-09 16:36:41 -0500 | [diff] [blame] | 2032 | DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); |
Qingqing Zhuo | ea3b424 | 2021-02-09 16:36:41 -0500 | [diff] [blame] | 2033 | } |
Qingqing Zhuo | ea3b424 | 2021-02-09 16:36:41 -0500 | [diff] [blame] | 2034 | |
Leo Li | ef785ca | 2024-09-11 17:27:08 -0400 | [diff] [blame] | 2035 | if (adev->dm.dc->caps.ips_support && |
| 2036 | adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) |
Roman Li | afca033 | 2024-04-03 12:13:56 -0400 | [diff] [blame] | 2037 | adev->dm.idle_workqueue = idle_create_workqueue(adev); |
| 2038 | |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2039 | if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { |
Bhawanpreet Lakha | e50dc17 | 2019-12-12 16:28:23 -0500 | [diff] [blame] | 2040 | adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 2041 | |
Bhawanpreet Lakha | 96a3b32 | 2019-06-24 14:54:13 -0400 | [diff] [blame] | 2042 | if (!adev->dm.hdcp_workqueue) |
| 2043 | DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); |
| 2044 | else |
| 2045 | DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 2046 | |
Bhawanpreet Lakha | 96a3b32 | 2019-06-24 14:54:13 -0400 | [diff] [blame] | 2047 | dc_init_callbacks(adev->dm.dc, &init_params); |
| 2048 | } |
Stylon Wang | 11d526f | 2022-07-07 16:23:29 +0800 | [diff] [blame] | 2049 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 2050 | init_completion(&adev->dm.dmub_aux_transfer_done); |
| 2051 | adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); |
| 2052 | if (!adev->dm.dmub_notify) { |
| 2053 | DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); |
| 2054 | goto error; |
| 2055 | } |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 2056 | |
| 2057 | adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); |
| 2058 | if (!adev->dm.delayed_hpd_wq) { |
| 2059 | DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); |
| 2060 | goto error; |
| 2061 | } |
| 2062 | |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 2063 | amdgpu_dm_outbox_init(adev); |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 2064 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, |
| 2065 | dmub_aux_setconfig_callback, false)) { |
| 2066 | DRM_ERROR("amdgpu: fail to register dmub aux callback"); |
| 2067 | goto error; |
| 2068 | } |
Wayne Lin | 22e1dc4 | 2024-02-02 17:34:11 +0800 | [diff] [blame] | 2069 | /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. |
| 2070 | * It is expected that DMUB will resend any pending notifications at this point. Note |
| 2071 | * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to |
| 2072 | * align legacy interface initialization sequence. Connection status will be proactivly |
| 2073 | * detected once in the amdgpu_dm_initialize_drm_device. |
| 2074 | */ |
Stylon Wang | 11d526f | 2022-07-07 16:23:29 +0800 | [diff] [blame] | 2075 | dc_enable_dmub_outbox(adev->dm.dc); |
| 2076 | |
Stylon Wang | 7ce34cb | 2023-06-30 16:46:09 +0800 | [diff] [blame] | 2077 | /* DPIA trace goes to dmesg logs only if outbox is enabled */ |
| 2078 | if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) |
| 2079 | dc_dmub_srv_enable_dpia_trace(adev->dm.dc); |
| 2080 | } |
| 2081 | |
Stylon Wang | 1c43a48 | 2022-10-24 15:36:16 +0800 | [diff] [blame] | 2082 | if (amdgpu_dm_initialize_drm_device(adev)) { |
| 2083 | DRM_ERROR( |
| 2084 | "amdgpu: failed to initialize sw for display support.\n"); |
| 2085 | goto error; |
| 2086 | } |
| 2087 | |
Alex Deucher | f74367e | 2020-07-10 17:50:00 -0400 | [diff] [blame] | 2088 | /* create fake encoders for MST */ |
| 2089 | dm_dp_create_fake_mst_encoders(adev); |
| 2090 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2091 | /* TODO: Add_display_info? */ |
| 2092 | |
| 2093 | /* TODO use dynamic cursor width */ |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 2094 | adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
| 2095 | adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2096 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 2097 | if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2098 | DRM_ERROR( |
| 2099 | "amdgpu: failed to initialize sw for display support.\n"); |
| 2100 | goto error; |
| 2101 | } |
| 2102 | |
Alan Liu | f477c7b | 2023-04-10 11:35:44 +0800 | [diff] [blame] | 2103 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 2104 | adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); |
| 2105 | if (!adev->dm.secure_display_ctxs) |
| 2106 | DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); |
| 2107 | #endif |
Yifan Zhang | c0fb85ae0 | 2020-08-31 15:56:24 +0800 | [diff] [blame] | 2108 | |
Harry Wentland | f1ad2f5 | 2017-09-12 20:04:48 -0400 | [diff] [blame] | 2109 | DRM_DEBUG_DRIVER("KMS initialized.\n"); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2110 | |
| 2111 | return 0; |
| 2112 | error: |
| 2113 | amdgpu_dm_fini(adev); |
| 2114 | |
Alex Deucher | 59d0f39 | 2018-09-13 11:01:28 -0500 | [diff] [blame] | 2115 | return -EINVAL; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2116 | } |
| 2117 | |
Andrey Grodzovsky | e9669fb | 2021-05-19 23:20:57 -0400 | [diff] [blame] | 2118 | static int amdgpu_dm_early_fini(void *handle) |
| 2119 | { |
| 2120 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2121 | |
| 2122 | amdgpu_dm_audio_fini(adev); |
| 2123 | |
| 2124 | return 0; |
| 2125 | } |
| 2126 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 2127 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2128 | { |
Alex Deucher | f74367e | 2020-07-10 17:50:00 -0400 | [diff] [blame] | 2129 | int i; |
| 2130 | |
Nicholas Kazlauskas | 09a5df6 | 2021-08-03 15:12:26 -0400 | [diff] [blame] | 2131 | if (adev->dm.vblank_control_workqueue) { |
| 2132 | destroy_workqueue(adev->dm.vblank_control_workqueue); |
| 2133 | adev->dm.vblank_control_workqueue = NULL; |
| 2134 | } |
Nicholas Kazlauskas | 09a5df6 | 2021-08-03 15:12:26 -0400 | [diff] [blame] | 2135 | |
Roman Li | afca033 | 2024-04-03 12:13:56 -0400 | [diff] [blame] | 2136 | if (adev->dm.idle_workqueue) { |
| 2137 | if (adev->dm.idle_workqueue->running) { |
| 2138 | adev->dm.idle_workqueue->enable = false; |
| 2139 | flush_work(&adev->dm.idle_workqueue->work); |
| 2140 | } |
| 2141 | |
| 2142 | kfree(adev->dm.idle_workqueue); |
| 2143 | adev->dm.idle_workqueue = NULL; |
| 2144 | } |
| 2145 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2146 | amdgpu_dm_destroy_drm_device(&adev->dm); |
Emily Deng | c8bdf2b | 2019-05-27 11:12:51 +0800 | [diff] [blame] | 2147 | |
Wayne Lin | 9a65df1 | 2021-03-02 13:21:07 +0800 | [diff] [blame] | 2148 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
Alan Liu | 1b11ff7 | 2022-10-19 18:15:14 +0800 | [diff] [blame] | 2149 | if (adev->dm.secure_display_ctxs) { |
Hamza Mahfooz | c3d7496 | 2023-01-11 12:25:14 -0500 | [diff] [blame] | 2150 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
Alan Liu | 1b11ff7 | 2022-10-19 18:15:14 +0800 | [diff] [blame] | 2151 | if (adev->dm.secure_display_ctxs[i].crtc) { |
| 2152 | flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); |
| 2153 | flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); |
| 2154 | } |
| 2155 | } |
| 2156 | kfree(adev->dm.secure_display_ctxs); |
| 2157 | adev->dm.secure_display_ctxs = NULL; |
Wayne Lin | 9a65df1 | 2021-03-02 13:21:07 +0800 | [diff] [blame] | 2158 | } |
| 2159 | #endif |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 2160 | if (adev->dm.hdcp_workqueue) { |
Nirmoy Das | e96b1b297 | 2021-02-10 18:11:04 +0100 | [diff] [blame] | 2161 | hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 2162 | adev->dm.hdcp_workqueue = NULL; |
| 2163 | } |
| 2164 | |
Nikita Zhandarovich | 2a3cfb9 | 2024-02-06 08:50:56 -0800 | [diff] [blame] | 2165 | if (adev->dm.dc) { |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 2166 | dc_deinit_callbacks(adev->dm.dc); |
Igor Artemiev | 52f1783 | 2023-04-03 16:10:37 +0300 | [diff] [blame] | 2167 | dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); |
Nikita Zhandarovich | 2a3cfb9 | 2024-02-06 08:50:56 -0800 | [diff] [blame] | 2168 | if (dc_enable_dmub_notifications(adev->dm.dc)) { |
| 2169 | kfree(adev->dm.dmub_notify); |
| 2170 | adev->dm.dmub_notify = NULL; |
| 2171 | destroy_workqueue(adev->dm.delayed_hpd_wq); |
| 2172 | adev->dm.delayed_hpd_wq = NULL; |
| 2173 | } |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 2174 | } |
| 2175 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2176 | if (adev->dm.dmub_bo) |
| 2177 | amdgpu_bo_free_kernel(&adev->dm.dmub_bo, |
| 2178 | &adev->dm.dmub_bo_gpu_addr, |
| 2179 | &adev->dm.dmub_bo_cpu_addr); |
Bhawanpreet Lakha | 52704fc | 2019-05-24 15:44:20 -0400 | [diff] [blame] | 2180 | |
Srinivasan Shanmugam | 10cd2bf | 2024-02-06 09:34:25 +0530 | [diff] [blame] | 2181 | if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { |
Andrey Grodzovsky | 006c26a | 2021-09-15 16:07:49 -0400 | [diff] [blame] | 2182 | for (i = 0; i < adev->dm.dc->caps.max_links; i++) { |
| 2183 | if (adev->dm.hpd_rx_offload_wq[i].wq) { |
| 2184 | destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); |
| 2185 | adev->dm.hpd_rx_offload_wq[i].wq = NULL; |
| 2186 | } |
| 2187 | } |
| 2188 | |
| 2189 | kfree(adev->dm.hpd_rx_offload_wq); |
| 2190 | adev->dm.hpd_rx_offload_wq = NULL; |
| 2191 | } |
| 2192 | |
Emily Deng | c8bdf2b | 2019-05-27 11:12:51 +0800 | [diff] [blame] | 2193 | /* DC Destroy TODO: Replace destroy DAL */ |
| 2194 | if (adev->dm.dc) |
| 2195 | dc_destroy(&adev->dm.dc); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2196 | /* |
| 2197 | * TODO: pageflip, vlank interrupt |
| 2198 | * |
| 2199 | * amdgpu_dm_irq_fini(adev); |
| 2200 | */ |
| 2201 | |
| 2202 | if (adev->dm.cgs_device) { |
| 2203 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); |
| 2204 | adev->dm.cgs_device = NULL; |
| 2205 | } |
| 2206 | if (adev->dm.freesync_module) { |
| 2207 | mod_freesync_destroy(adev->dm.freesync_module); |
| 2208 | adev->dm.freesync_module = NULL; |
| 2209 | } |
Nicholas Kazlauskas | 674e78a | 2018-12-05 14:59:07 -0500 | [diff] [blame] | 2210 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 2211 | mutex_destroy(&adev->dm.audio_lock); |
Nicholas Kazlauskas | 674e78a | 2018-12-05 14:59:07 -0500 | [diff] [blame] | 2212 | mutex_destroy(&adev->dm.dc_lock); |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 2213 | mutex_destroy(&adev->dm.dpia_aux_lock); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2214 | } |
| 2215 | |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2216 | static int load_dmcu_fw(struct amdgpu_device *adev) |
| 2217 | { |
Harry Wentland | a7669af | 2019-04-29 09:39:15 -0400 | [diff] [blame] | 2218 | const char *fw_name_dmcu = NULL; |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2219 | int r; |
| 2220 | const struct dmcu_firmware_header_v1_0 *hdr; |
| 2221 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 2222 | switch (adev->asic_type) { |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 2223 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 2224 | case CHIP_TAHITI: |
| 2225 | case CHIP_PITCAIRN: |
| 2226 | case CHIP_VERDE: |
| 2227 | case CHIP_OLAND: |
| 2228 | #endif |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2229 | case CHIP_BONAIRE: |
| 2230 | case CHIP_HAWAII: |
| 2231 | case CHIP_KAVERI: |
| 2232 | case CHIP_KABINI: |
| 2233 | case CHIP_MULLINS: |
| 2234 | case CHIP_TONGA: |
| 2235 | case CHIP_FIJI: |
| 2236 | case CHIP_CARRIZO: |
| 2237 | case CHIP_STONEY: |
| 2238 | case CHIP_POLARIS11: |
| 2239 | case CHIP_POLARIS10: |
| 2240 | case CHIP_POLARIS12: |
| 2241 | case CHIP_VEGAM: |
| 2242 | case CHIP_VEGA10: |
| 2243 | case CHIP_VEGA12: |
| 2244 | case CHIP_VEGA20: |
| 2245 | return 0; |
Roman Li | 5ea2393 | 2020-02-05 09:39:41 -0500 | [diff] [blame] | 2246 | case CHIP_NAVI12: |
| 2247 | fw_name_dmcu = FIRMWARE_NAVI12_DMCU; |
| 2248 | break; |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2249 | case CHIP_RAVEN: |
Harry Wentland | a7669af | 2019-04-29 09:39:15 -0400 | [diff] [blame] | 2250 | if (ASICREV_IS_PICASSO(adev->external_rev_id)) |
| 2251 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; |
| 2252 | else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) |
| 2253 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; |
| 2254 | else |
Harry Wentland | a7669af | 2019-04-29 09:39:15 -0400 | [diff] [blame] | 2255 | return 0; |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2256 | break; |
| 2257 | default: |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 2258 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2259 | case IP_VERSION(2, 0, 2): |
| 2260 | case IP_VERSION(2, 0, 3): |
| 2261 | case IP_VERSION(2, 0, 0): |
| 2262 | case IP_VERSION(2, 1, 0): |
| 2263 | case IP_VERSION(3, 0, 0): |
| 2264 | case IP_VERSION(3, 0, 2): |
| 2265 | case IP_VERSION(3, 0, 3): |
| 2266 | case IP_VERSION(3, 0, 1): |
| 2267 | case IP_VERSION(3, 1, 2): |
| 2268 | case IP_VERSION(3, 1, 3): |
Roman Li | f3cd57e | 2022-07-19 11:55:07 -0400 | [diff] [blame] | 2269 | case IP_VERSION(3, 1, 4): |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 2270 | case IP_VERSION(3, 1, 5): |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 2271 | case IP_VERSION(3, 1, 6): |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 2272 | case IP_VERSION(3, 2, 0): |
| 2273 | case IP_VERSION(3, 2, 1): |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 2274 | case IP_VERSION(3, 5, 0): |
Hamza Mahfooz | 10740e4 | 2024-02-26 09:11:00 -0500 | [diff] [blame] | 2275 | case IP_VERSION(3, 5, 1): |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 2276 | case IP_VERSION(4, 0, 1): |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2277 | return 0; |
| 2278 | default: |
| 2279 | break; |
| 2280 | } |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2281 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
Alex Deucher | 59d0f39 | 2018-09-13 11:01:28 -0500 | [diff] [blame] | 2282 | return -EINVAL; |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2283 | } |
| 2284 | |
| 2285 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 2286 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); |
| 2287 | return 0; |
| 2288 | } |
| 2289 | |
Arnd Bergmann | 0206204 | 2024-07-19 12:08:28 +0200 | [diff] [blame] | 2290 | r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, "%s", fw_name_dmcu); |
Mario Limonciello | 46fa907 | 2023-01-04 08:38:42 -0600 | [diff] [blame] | 2291 | if (r == -ENODEV) { |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2292 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ |
| 2293 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); |
| 2294 | adev->dm.fw_dmcu = NULL; |
| 2295 | return 0; |
| 2296 | } |
| 2297 | if (r) { |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2298 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", |
| 2299 | fw_name_dmcu); |
Mario Limonciello | 5152663 | 2023-01-03 23:49:43 -0600 | [diff] [blame] | 2300 | amdgpu_ucode_release(&adev->dm.fw_dmcu); |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2301 | return r; |
| 2302 | } |
| 2303 | |
| 2304 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; |
| 2305 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; |
| 2306 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; |
| 2307 | adev->firmware.fw_size += |
| 2308 | ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); |
| 2309 | |
| 2310 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; |
| 2311 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; |
| 2312 | adev->firmware.fw_size += |
| 2313 | ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); |
| 2314 | |
David Francis | ee6e89c | 2018-09-13 15:36:27 -0400 | [diff] [blame] | 2315 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); |
| 2316 | |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2317 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); |
| 2318 | |
| 2319 | return 0; |
| 2320 | } |
| 2321 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2322 | static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) |
| 2323 | { |
| 2324 | struct amdgpu_device *adev = ctx; |
| 2325 | |
| 2326 | return dm_read_reg(adev->dm.dc->ctx, address); |
| 2327 | } |
| 2328 | |
| 2329 | static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, |
| 2330 | uint32_t value) |
| 2331 | { |
| 2332 | struct amdgpu_device *adev = ctx; |
| 2333 | |
| 2334 | return dm_write_reg(adev->dm.dc->ctx, address, value); |
| 2335 | } |
| 2336 | |
| 2337 | static int dm_dmub_sw_init(struct amdgpu_device *adev) |
| 2338 | { |
| 2339 | struct dmub_srv_create_params create_params; |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2340 | struct dmub_srv_region_params region_params; |
| 2341 | struct dmub_srv_region_info region_info; |
Lewis Huang | 5911d02 | 2023-10-19 17:22:21 +0800 | [diff] [blame] | 2342 | struct dmub_srv_memory_params memory_params; |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2343 | struct dmub_srv_fb_info *fb_info; |
| 2344 | struct dmub_srv *dmub_srv; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2345 | const struct dmcub_firmware_header_v1_0 *hdr; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2346 | enum dmub_asic dmub_asic; |
| 2347 | enum dmub_status status; |
Fudongwang | 624e0d7 | 2023-12-19 10:20:12 +0800 | [diff] [blame] | 2348 | static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = { |
| 2349 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST |
| 2350 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK |
| 2351 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA |
| 2352 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS |
| 2353 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX |
| 2354 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF |
| 2355 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE |
Nicholas Kazlauskas | b5e161e | 2024-01-30 15:24:56 -0500 | [diff] [blame] | 2356 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM |
| 2357 | DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE |
Fudongwang | 624e0d7 | 2023-12-19 10:20:12 +0800 | [diff] [blame] | 2358 | }; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2359 | int r; |
| 2360 | |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 2361 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2362 | case IP_VERSION(2, 1, 0): |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2363 | dmub_asic = DMUB_ASIC_DCN21; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2364 | break; |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2365 | case IP_VERSION(3, 0, 0): |
Jiapeng Chong | 35a45d6 | 2023-01-12 11:20:49 +0800 | [diff] [blame] | 2366 | dmub_asic = DMUB_ASIC_DCN30; |
Bhawanpreet Lakha | 7903732 | 2020-05-21 12:48:41 -0400 | [diff] [blame] | 2367 | break; |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2368 | case IP_VERSION(3, 0, 1): |
Roman Li | 469989c | 2020-09-23 17:02:12 -0400 | [diff] [blame] | 2369 | dmub_asic = DMUB_ASIC_DCN301; |
Roman Li | 469989c | 2020-09-23 17:02:12 -0400 | [diff] [blame] | 2370 | break; |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2371 | case IP_VERSION(3, 0, 2): |
Bhawanpreet Lakha | 2a41120 | 2020-09-25 14:00:24 -0400 | [diff] [blame] | 2372 | dmub_asic = DMUB_ASIC_DCN302; |
Bhawanpreet Lakha | 2a41120 | 2020-09-25 14:00:24 -0400 | [diff] [blame] | 2373 | break; |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2374 | case IP_VERSION(3, 0, 3): |
Aurabindo Pillai | 656fe9b | 2021-03-10 15:53:11 -0500 | [diff] [blame] | 2375 | dmub_asic = DMUB_ASIC_DCN303; |
Aurabindo Pillai | 656fe9b | 2021-03-10 15:53:11 -0500 | [diff] [blame] | 2376 | break; |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2377 | case IP_VERSION(3, 1, 2): |
| 2378 | case IP_VERSION(3, 1, 3): |
Hansen | 3137f79 | 2021-09-09 15:12:32 -0400 | [diff] [blame] | 2379 | dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; |
Nicholas Kazlauskas | 1ebcaeb | 2021-05-19 12:55:44 -0400 | [diff] [blame] | 2380 | break; |
Roman Li | e850f6b | 2022-06-28 18:41:37 -0400 | [diff] [blame] | 2381 | case IP_VERSION(3, 1, 4): |
| 2382 | dmub_asic = DMUB_ASIC_DCN314; |
Roman Li | e850f6b | 2022-06-28 18:41:37 -0400 | [diff] [blame] | 2383 | break; |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 2384 | case IP_VERSION(3, 1, 5): |
| 2385 | dmub_asic = DMUB_ASIC_DCN315; |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 2386 | break; |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 2387 | case IP_VERSION(3, 1, 6): |
Leo Li | 868f435 | 2022-01-27 14:29:31 -0500 | [diff] [blame] | 2388 | dmub_asic = DMUB_ASIC_DCN316; |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 2389 | break; |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 2390 | case IP_VERSION(3, 2, 0): |
| 2391 | dmub_asic = DMUB_ASIC_DCN32; |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 2392 | break; |
| 2393 | case IP_VERSION(3, 2, 1): |
| 2394 | dmub_asic = DMUB_ASIC_DCN321; |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 2395 | break; |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 2396 | case IP_VERSION(3, 5, 0): |
Hamza Mahfooz | 10740e4 | 2024-02-26 09:11:00 -0500 | [diff] [blame] | 2397 | case IP_VERSION(3, 5, 1): |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 2398 | dmub_asic = DMUB_ASIC_DCN35; |
| 2399 | break; |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 2400 | case IP_VERSION(4, 0, 1): |
| 2401 | dmub_asic = DMUB_ASIC_DCN401; |
| 2402 | break; |
| 2403 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2404 | default: |
| 2405 | /* ASIC doesn't support DMUB. */ |
| 2406 | return 0; |
| 2407 | } |
| 2408 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2409 | hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; |
Shirish S | 72a74a1 | 2021-08-03 14:03:44 +0530 | [diff] [blame] | 2410 | adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); |
Nicholas Kazlauskas | 9a6ed54 | 2020-01-28 15:14:07 -0500 | [diff] [blame] | 2411 | |
| 2412 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
| 2413 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = |
| 2414 | AMDGPU_UCODE_ID_DMCUB; |
| 2415 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = |
| 2416 | adev->dm.dmub_fw; |
| 2417 | adev->firmware.fw_size += |
| 2418 | ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); |
| 2419 | |
| 2420 | DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", |
| 2421 | adev->dm.dmcub_fw_version); |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2422 | } |
| 2423 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2424 | |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2425 | adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); |
| 2426 | dmub_srv = adev->dm.dmub_srv; |
| 2427 | |
| 2428 | if (!dmub_srv) { |
| 2429 | DRM_ERROR("Failed to allocate DMUB service!\n"); |
| 2430 | return -ENOMEM; |
| 2431 | } |
| 2432 | |
| 2433 | memset(&create_params, 0, sizeof(create_params)); |
| 2434 | create_params.user_ctx = adev; |
| 2435 | create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; |
| 2436 | create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; |
| 2437 | create_params.asic = dmub_asic; |
| 2438 | |
| 2439 | /* Create the DMUB service. */ |
| 2440 | status = dmub_srv_create(dmub_srv, &create_params); |
| 2441 | if (status != DMUB_STATUS_OK) { |
| 2442 | DRM_ERROR("Error creating DMUB service: %d\n", status); |
| 2443 | return -EINVAL; |
| 2444 | } |
| 2445 | |
| 2446 | /* Calculate the size of all the regions for the DMUB service. */ |
| 2447 | memset(®ion_params, 0, sizeof(region_params)); |
| 2448 | |
| 2449 | region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - |
| 2450 | PSP_HEADER_BYTES - PSP_FOOTER_BYTES; |
| 2451 | region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); |
| 2452 | region_params.vbios_size = adev->bios_size; |
Nicholas Kazlauskas | 0922b89 | 2020-04-30 12:24:05 -0400 | [diff] [blame] | 2453 | region_params.fw_bss_data = region_params.bss_data_size ? |
Nicholas Kazlauskas | 1f0674f | 2019-11-28 15:21:26 -0500 | [diff] [blame] | 2454 | adev->dm.dmub_fw->data + |
| 2455 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + |
Nicholas Kazlauskas | 0922b89 | 2020-04-30 12:24:05 -0400 | [diff] [blame] | 2456 | le32_to_cpu(hdr->inst_const_bytes) : NULL; |
Nicholas Kazlauskas | a576b34 | 2020-04-05 16:41:14 -0400 | [diff] [blame] | 2457 | region_params.fw_inst_const = |
| 2458 | adev->dm.dmub_fw->data + |
| 2459 | le32_to_cpu(hdr->header.ucode_array_offset_bytes) + |
| 2460 | PSP_HEADER_BYTES; |
Fudongwang | 624e0d7 | 2023-12-19 10:20:12 +0800 | [diff] [blame] | 2461 | region_params.window_memory_type = window_memory_type; |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2462 | |
| 2463 | status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, |
| 2464 | ®ion_info); |
| 2465 | |
| 2466 | if (status != DMUB_STATUS_OK) { |
| 2467 | DRM_ERROR("Error calculating DMUB region info: %d\n", status); |
| 2468 | return -EINVAL; |
| 2469 | } |
| 2470 | |
| 2471 | /* |
| 2472 | * Allocate a framebuffer based on the total size of all the regions. |
| 2473 | * TODO: Move this into GART. |
| 2474 | */ |
| 2475 | r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, |
Christian König | 58ab2c0 | 2022-01-14 16:49:44 +0100 | [diff] [blame] | 2476 | AMDGPU_GEM_DOMAIN_VRAM | |
| 2477 | AMDGPU_GEM_DOMAIN_GTT, |
| 2478 | &adev->dm.dmub_bo, |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2479 | &adev->dm.dmub_bo_gpu_addr, |
| 2480 | &adev->dm.dmub_bo_cpu_addr); |
| 2481 | if (r) |
| 2482 | return r; |
| 2483 | |
| 2484 | /* Rebase the regions on the framebuffer address. */ |
Lewis Huang | 5911d02 | 2023-10-19 17:22:21 +0800 | [diff] [blame] | 2485 | memset(&memory_params, 0, sizeof(memory_params)); |
| 2486 | memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; |
| 2487 | memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; |
| 2488 | memory_params.region_info = ®ion_info; |
Fudongwang | 624e0d7 | 2023-12-19 10:20:12 +0800 | [diff] [blame] | 2489 | memory_params.window_memory_type = window_memory_type; |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2490 | |
| 2491 | adev->dm.dmub_fb_info = |
| 2492 | kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); |
| 2493 | fb_info = adev->dm.dmub_fb_info; |
| 2494 | |
| 2495 | if (!fb_info) { |
| 2496 | DRM_ERROR( |
| 2497 | "Failed to allocate framebuffer info for DMUB service!\n"); |
| 2498 | return -ENOMEM; |
| 2499 | } |
| 2500 | |
Lewis Huang | 5911d02 | 2023-10-19 17:22:21 +0800 | [diff] [blame] | 2501 | status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2502 | if (status != DMUB_STATUS_OK) { |
| 2503 | DRM_ERROR("Error calculating DMUB FB info: %d\n", status); |
| 2504 | return -EINVAL; |
| 2505 | } |
| 2506 | |
Aurabindo Pillai | 234e945 | 2024-05-21 19:46:31 +0000 | [diff] [blame] | 2507 | adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev); |
| 2508 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2509 | return 0; |
| 2510 | } |
| 2511 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2512 | static int dm_sw_init(void *handle) |
| 2513 | { |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2514 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2515 | int r; |
| 2516 | |
Aurabindo Pillai | 7920af2 | 2024-05-16 10:23:19 -0400 | [diff] [blame] | 2517 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); |
| 2518 | |
| 2519 | if (!adev->dm.cgs_device) { |
| 2520 | DRM_ERROR("amdgpu: failed to create cgs device.\n"); |
| 2521 | return -EINVAL; |
| 2522 | } |
| 2523 | |
| 2524 | /* Moved from dm init since we need to use allocations for storing bounding box data */ |
| 2525 | INIT_LIST_HEAD(&adev->dm.da_list); |
| 2526 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2527 | r = dm_dmub_sw_init(adev); |
| 2528 | if (r) |
| 2529 | return r; |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2530 | |
| 2531 | return load_dmcu_fw(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2532 | } |
| 2533 | |
| 2534 | static int dm_sw_fini(void *handle) |
| 2535 | { |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2536 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Aurabindo Pillai | f59549c | 2024-07-03 16:41:52 -0400 | [diff] [blame] | 2537 | struct dal_allocation *da; |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2538 | |
Aurabindo Pillai | f59549c | 2024-07-03 16:41:52 -0400 | [diff] [blame] | 2539 | list_for_each_entry(da, &adev->dm.da_list, list) { |
| 2540 | if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { |
| 2541 | amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); |
| 2542 | list_del(&da->list); |
| 2543 | kfree(da); |
| 2544 | break; |
| 2545 | } |
| 2546 | } |
| 2547 | |
Aurabindo Pillai | 234e945 | 2024-05-21 19:46:31 +0000 | [diff] [blame] | 2548 | adev->dm.bb_from_dmub = NULL; |
| 2549 | |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 2550 | kfree(adev->dm.dmub_fb_info); |
| 2551 | adev->dm.dmub_fb_info = NULL; |
| 2552 | |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2553 | if (adev->dm.dmub_srv) { |
| 2554 | dmub_srv_destroy(adev->dm.dmub_srv); |
Armin Wolf | bae6789 | 2024-02-13 01:50:50 +0100 | [diff] [blame] | 2555 | kfree(adev->dm.dmub_srv); |
Nicholas Kazlauskas | 743b978 | 2019-10-24 20:38:48 -0400 | [diff] [blame] | 2556 | adev->dm.dmub_srv = NULL; |
| 2557 | } |
| 2558 | |
Mario Limonciello | 5152663 | 2023-01-03 23:49:43 -0600 | [diff] [blame] | 2559 | amdgpu_ucode_release(&adev->dm.dmub_fw); |
| 2560 | amdgpu_ucode_release(&adev->dm.fw_dmcu); |
David Francis | a94d556 | 2018-09-11 13:49:49 -0400 | [diff] [blame] | 2561 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2562 | return 0; |
| 2563 | } |
| 2564 | |
Andrey Grodzovsky | 7abcf6b | 2016-12-29 13:21:31 -0500 | [diff] [blame] | 2565 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2566 | { |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 2567 | struct amdgpu_dm_connector *aconnector; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2568 | struct drm_connector *connector; |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2569 | struct drm_connector_list_iter iter; |
Andrey Grodzovsky | 7abcf6b | 2016-12-29 13:21:31 -0500 | [diff] [blame] | 2570 | int ret = 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2571 | |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2572 | drm_connector_list_iter_begin(dev, &iter); |
| 2573 | drm_for_each_connector_iter(connector, &iter) { |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 2574 | |
| 2575 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 2576 | continue; |
| 2577 | |
Ernst Sjöstrand | b349f76 | 2017-11-07 21:06:57 +0100 | [diff] [blame] | 2578 | aconnector = to_amdgpu_dm_connector(connector); |
Jerry (Fangzhi) Zuo | 30ec2b9 | 2017-11-03 16:04:34 -0400 | [diff] [blame] | 2579 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
| 2580 | aconnector->mst_mgr.aux) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 2581 | drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n", |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2582 | aconnector, |
| 2583 | aconnector->base.base.id); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2584 | |
Andrey Grodzovsky | 7abcf6b | 2016-12-29 13:21:31 -0500 | [diff] [blame] | 2585 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); |
| 2586 | if (ret < 0) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 2587 | drm_err(dev, "DM_MST: Failed to start MST\n"); |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2588 | aconnector->dc_link->type = |
| 2589 | dc_connection_single; |
Roman Li | 3f6752b | 2022-12-01 09:49:23 -0500 | [diff] [blame] | 2590 | ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
| 2591 | aconnector->dc_link); |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2592 | break; |
Andrey Grodzovsky | 7abcf6b | 2016-12-29 13:21:31 -0500 | [diff] [blame] | 2593 | } |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2594 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2595 | } |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2596 | drm_connector_list_iter_end(&iter); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2597 | |
Andrey Grodzovsky | 7abcf6b | 2016-12-29 13:21:31 -0500 | [diff] [blame] | 2598 | return ret; |
| 2599 | } |
| 2600 | |
| 2601 | static int dm_late_init(void *handle) |
| 2602 | { |
Roman Li | 42e67c3 | 2017-12-13 17:25:02 -0500 | [diff] [blame] | 2603 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Andrey Grodzovsky | 7abcf6b | 2016-12-29 13:21:31 -0500 | [diff] [blame] | 2604 | |
David Francis | bbf854d | 2018-11-26 11:38:33 -0500 | [diff] [blame] | 2605 | struct dmcu_iram_parameters params; |
| 2606 | unsigned int linear_lut[16]; |
| 2607 | int i; |
Jerry (Fangzhi) Zuo | 17bdb4a | 2020-04-24 14:09:23 -0400 | [diff] [blame] | 2608 | struct dmcu *dmcu = NULL; |
David Francis | bbf854d | 2018-11-26 11:38:33 -0500 | [diff] [blame] | 2609 | |
Jerry (Fangzhi) Zuo | 17bdb4a | 2020-04-24 14:09:23 -0400 | [diff] [blame] | 2610 | dmcu = adev->dm.dc->res_pool->dmcu; |
| 2611 | |
David Francis | bbf854d | 2018-11-26 11:38:33 -0500 | [diff] [blame] | 2612 | for (i = 0; i < 16; i++) |
| 2613 | linear_lut[i] = 0xFFFF * i / 15; |
| 2614 | |
| 2615 | params.set = 0; |
Josip Pavic | 7506899 | 2021-09-17 11:01:47 -0400 | [diff] [blame] | 2616 | params.backlight_ramping_override = false; |
David Francis | bbf854d | 2018-11-26 11:38:33 -0500 | [diff] [blame] | 2617 | params.backlight_ramping_start = 0xCCCC; |
| 2618 | params.backlight_ramping_reduction = 0xCCCCCCCC; |
| 2619 | params.backlight_lut_array_size = 16; |
| 2620 | params.backlight_lut_array = linear_lut; |
| 2621 | |
Anthony Koo | 2ad0cdf | 2019-08-29 10:49:12 -0400 | [diff] [blame] | 2622 | /* Min backlight level after ABM reduction, Don't allow below 1% |
| 2623 | * 0xFFFF x 0.01 = 0x28F |
| 2624 | */ |
| 2625 | params.min_abm_backlight = 0x28F; |
Roman Li | 5cb3241 | 2020-07-10 10:33:05 -0400 | [diff] [blame] | 2626 | /* In the case where abm is implemented on dmcub, |
Uwe Kleine-König | 3335a13 | 2023-03-27 18:07:54 +0200 | [diff] [blame] | 2627 | * dmcu object will be null. |
| 2628 | * ABM 2.4 and up are implemented on dmcub. |
| 2629 | */ |
Jake Wang | 6e568e4 | 2021-04-23 16:42:35 -0400 | [diff] [blame] | 2630 | if (dmcu) { |
| 2631 | if (!dmcu_load_iram(dmcu, params)) |
| 2632 | return -EINVAL; |
| 2633 | } else if (adev->dm.dc->ctx->dmub_srv) { |
| 2634 | struct dc_link *edp_links[MAX_NUM_EDP]; |
| 2635 | int edp_num; |
David Francis | bbf854d | 2018-11-26 11:38:33 -0500 | [diff] [blame] | 2636 | |
Wenjing Liu | 7ae1dbe | 2023-02-06 17:58:52 -0500 | [diff] [blame] | 2637 | dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); |
Jake Wang | 6e568e4 | 2021-04-23 16:42:35 -0400 | [diff] [blame] | 2638 | for (i = 0; i < edp_num; i++) { |
| 2639 | if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) |
| 2640 | return -EINVAL; |
| 2641 | } |
| 2642 | } |
David Francis | bbf854d | 2018-11-26 11:38:33 -0500 | [diff] [blame] | 2643 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 2644 | return detect_mst_link_for_all_connectors(adev_to_drm(adev)); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2645 | } |
| 2646 | |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2647 | static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) |
| 2648 | { |
Jani Nikula | b71ccff | 2024-08-12 15:23:12 +0300 | [diff] [blame] | 2649 | u8 buf[UUID_SIZE]; |
| 2650 | guid_t guid; |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2651 | int ret; |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2652 | |
| 2653 | mutex_lock(&mgr->lock); |
| 2654 | if (!mgr->mst_primary) |
| 2655 | goto out_fail; |
| 2656 | |
| 2657 | if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { |
| 2658 | drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); |
| 2659 | goto out_fail; |
| 2660 | } |
| 2661 | |
| 2662 | ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, |
| 2663 | DP_MST_EN | |
Wayne Lin | e336971 | 2024-05-23 12:18:07 +0800 | [diff] [blame] | 2664 | DP_UP_REQ_EN | |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2665 | DP_UPSTREAM_IS_SRC); |
| 2666 | if (ret < 0) { |
| 2667 | drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); |
| 2668 | goto out_fail; |
| 2669 | } |
| 2670 | |
| 2671 | /* Some hubs forget their guids after they resume */ |
Jani Nikula | b71ccff | 2024-08-12 15:23:12 +0300 | [diff] [blame] | 2672 | ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); |
| 2673 | if (ret != sizeof(buf)) { |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2674 | drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); |
| 2675 | goto out_fail; |
| 2676 | } |
| 2677 | |
Jani Nikula | b71ccff | 2024-08-12 15:23:12 +0300 | [diff] [blame] | 2678 | import_guid(&guid, buf); |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2679 | |
Jani Nikula | b71ccff | 2024-08-12 15:23:12 +0300 | [diff] [blame] | 2680 | if (guid_is_null(&guid)) { |
| 2681 | guid_gen(&guid); |
| 2682 | export_guid(buf, &guid); |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2683 | |
Jani Nikula | b71ccff | 2024-08-12 15:23:12 +0300 | [diff] [blame] | 2684 | ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); |
| 2685 | |
| 2686 | if (ret != sizeof(buf)) { |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2687 | drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); |
| 2688 | goto out_fail; |
| 2689 | } |
| 2690 | } |
| 2691 | |
Jani Nikula | b71ccff | 2024-08-12 15:23:12 +0300 | [diff] [blame] | 2692 | guid_copy(&mgr->mst_primary->guid, &guid); |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2693 | |
| 2694 | out_fail: |
| 2695 | mutex_unlock(&mgr->lock); |
| 2696 | } |
| 2697 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2698 | static void s3_handle_mst(struct drm_device *dev, bool suspend) |
| 2699 | { |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 2700 | struct amdgpu_dm_connector *aconnector; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2701 | struct drm_connector *connector; |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2702 | struct drm_connector_list_iter iter; |
Lyude Paul | fe7553b | 2019-01-08 16:11:27 -0500 | [diff] [blame] | 2703 | struct drm_dp_mst_topology_mgr *mgr; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2704 | |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2705 | drm_connector_list_iter_begin(dev, &iter); |
| 2706 | drm_for_each_connector_iter(connector, &iter) { |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 2707 | |
| 2708 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 2709 | continue; |
| 2710 | |
Lyude Paul | fe7553b | 2019-01-08 16:11:27 -0500 | [diff] [blame] | 2711 | aconnector = to_amdgpu_dm_connector(connector); |
| 2712 | if (aconnector->dc_link->type != dc_connection_mst_branch || |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 2713 | aconnector->mst_root) |
Lyude Paul | fe7553b | 2019-01-08 16:11:27 -0500 | [diff] [blame] | 2714 | continue; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2715 | |
Lyude Paul | fe7553b | 2019-01-08 16:11:27 -0500 | [diff] [blame] | 2716 | mgr = &aconnector->mst_mgr; |
| 2717 | |
| 2718 | if (suspend) { |
| 2719 | drm_dp_mst_topology_mgr_suspend(mgr); |
| 2720 | } else { |
Ryan Lin | 1e5d4d8 | 2023-02-07 23:03:48 +0800 | [diff] [blame] | 2721 | /* if extended timeout is supported in hardware, |
| 2722 | * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer |
| 2723 | * CTS 4.2.1.1 regression introduced by CTS specs requirement update. |
| 2724 | */ |
| 2725 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); |
| 2726 | if (!dp_is_lttpr_present(aconnector->dc_link)) |
| 2727 | try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); |
| 2728 | |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 2729 | /* TODO: move resume_mst_branch_status() into drm mst resume again |
| 2730 | * once topology probing work is pulled out from mst resume into mst |
| 2731 | * resume 2nd step. mst resume 2nd step should be called after old |
| 2732 | * state getting restored (i.e. drm_atomic_helper_resume()). |
| 2733 | */ |
| 2734 | resume_mst_branch_status(mgr); |
Lyude Paul | fe7553b | 2019-01-08 16:11:27 -0500 | [diff] [blame] | 2735 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2736 | } |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 2737 | drm_connector_list_iter_end(&iter); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2738 | } |
| 2739 | |
Hersen Wu | 9340dfd | 2020-02-13 10:50:13 -0500 | [diff] [blame] | 2740 | static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) |
| 2741 | { |
Hersen Wu | 9340dfd | 2020-02-13 10:50:13 -0500 | [diff] [blame] | 2742 | int ret = 0; |
| 2743 | |
Hersen Wu | 9340dfd | 2020-02-13 10:50:13 -0500 | [diff] [blame] | 2744 | /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends |
| 2745 | * on window driver dc implementation. |
| 2746 | * For Navi1x, clock settings of dcn watermarks are fixed. the settings |
| 2747 | * should be passed to smu during boot up and resume from s3. |
| 2748 | * boot up: dc calculate dcn watermark clock settings within dc_create, |
| 2749 | * dcn20_resource_construct |
| 2750 | * then call pplib functions below to pass the settings to smu: |
| 2751 | * smu_set_watermarks_for_clock_ranges |
| 2752 | * smu_set_watermarks_table |
| 2753 | * navi10_set_watermarks_table |
| 2754 | * smu_write_watermarks_table |
| 2755 | * |
| 2756 | * For Renoir, clock settings of dcn watermark are also fixed values. |
| 2757 | * dc has implemented different flow for window driver: |
| 2758 | * dc_hardware_init / dc_set_power_state |
| 2759 | * dcn10_init_hw |
| 2760 | * notify_wm_ranges |
| 2761 | * set_wm_ranges |
| 2762 | * -- Linux |
| 2763 | * smu_set_watermarks_for_clock_ranges |
| 2764 | * renoir_set_watermarks_table |
| 2765 | * smu_write_watermarks_table |
| 2766 | * |
| 2767 | * For Linux, |
| 2768 | * dc_hardware_init -> amdgpu_dm_init |
| 2769 | * dc_set_power_state --> dm_resume |
| 2770 | * |
| 2771 | * therefore, this function apply to navi10/12/14 but not Renoir |
| 2772 | * * |
| 2773 | */ |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 2774 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 2775 | case IP_VERSION(2, 0, 2): |
| 2776 | case IP_VERSION(2, 0, 0): |
Hersen Wu | 9340dfd | 2020-02-13 10:50:13 -0500 | [diff] [blame] | 2777 | break; |
| 2778 | default: |
| 2779 | return 0; |
| 2780 | } |
| 2781 | |
Evan Quan | 13f5dbd | 2021-11-22 11:09:08 +0800 | [diff] [blame] | 2782 | ret = amdgpu_dpm_write_watermarks_table(adev); |
Evan Quan | e7a95ee | 2020-07-07 15:52:39 +0800 | [diff] [blame] | 2783 | if (ret) { |
| 2784 | DRM_ERROR("Failed to update WMTABLE!\n"); |
| 2785 | return ret; |
Hersen Wu | 9340dfd | 2020-02-13 10:50:13 -0500 | [diff] [blame] | 2786 | } |
| 2787 | |
Hersen Wu | 9340dfd | 2020-02-13 10:50:13 -0500 | [diff] [blame] | 2788 | return 0; |
| 2789 | } |
| 2790 | |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 2791 | /** |
| 2792 | * dm_hw_init() - Initialize DC device |
Christophe JAILLET | 28d687e | 2019-10-05 13:32:05 +0200 | [diff] [blame] | 2793 | * @handle: The base driver device containing the amdgpu_dm device. |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 2794 | * |
| 2795 | * Initialize the &struct amdgpu_display_manager device. This involves calling |
| 2796 | * the initializers of each DM component, then populating the struct with them. |
| 2797 | * |
| 2798 | * Although the function implies hardware initialization, both hardware and |
| 2799 | * software are initialized here. Splitting them out to their relevant init |
| 2800 | * hooks is a future TODO item. |
| 2801 | * |
| 2802 | * Some notable things that are initialized here: |
| 2803 | * |
| 2804 | * - Display Core, both software and hardware |
| 2805 | * - DC modules that we need (freesync and color management) |
| 2806 | * - DRM software states |
| 2807 | * - Interrupt sources and handlers |
| 2808 | * - Vblank support |
| 2809 | * - Debug FS entries, if enabled |
| 2810 | */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2811 | static int dm_hw_init(void *handle) |
| 2812 | { |
| 2813 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Mario Limonciello | 400c49e | 2024-05-19 08:02:23 -0500 | [diff] [blame] | 2814 | int r; |
| 2815 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2816 | /* Create DAL display manager */ |
Mario Limonciello | 400c49e | 2024-05-19 08:02:23 -0500 | [diff] [blame] | 2817 | r = amdgpu_dm_init(adev); |
| 2818 | if (r) |
| 2819 | return r; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2820 | amdgpu_dm_hpd_init(adev); |
| 2821 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2822 | return 0; |
| 2823 | } |
| 2824 | |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 2825 | /** |
| 2826 | * dm_hw_fini() - Teardown DC device |
Christophe JAILLET | 28d687e | 2019-10-05 13:32:05 +0200 | [diff] [blame] | 2827 | * @handle: The base driver device containing the amdgpu_dm device. |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 2828 | * |
| 2829 | * Teardown components within &struct amdgpu_display_manager that require |
| 2830 | * cleanup. This involves cleaning up the DRM device, DC, and any modules that |
| 2831 | * were loaded. Also flush IRQ workqueues and disable them. |
| 2832 | */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2833 | static int dm_hw_fini(void *handle) |
| 2834 | { |
| 2835 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2836 | |
| 2837 | amdgpu_dm_hpd_fini(adev); |
| 2838 | |
| 2839 | amdgpu_dm_irq_fini(adev); |
Rex Zhu | 21de339 | 2017-05-22 13:11:15 +0800 | [diff] [blame] | 2840 | amdgpu_dm_fini(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2841 | return 0; |
| 2842 | } |
| 2843 | |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2844 | |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2845 | static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, |
| 2846 | struct dc_state *state, bool enable) |
| 2847 | { |
| 2848 | enum dc_irq_source irq_source; |
| 2849 | struct amdgpu_crtc *acrtc; |
| 2850 | int rc = -EBUSY; |
| 2851 | int i = 0; |
| 2852 | |
| 2853 | for (i = 0; i < state->stream_count; i++) { |
| 2854 | acrtc = get_crtc_by_otg_inst( |
| 2855 | adev, state->stream_status[i].primary_otg_inst); |
| 2856 | |
| 2857 | if (acrtc && state->stream_status[i].plane_count != 0) { |
| 2858 | irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; |
| 2859 | rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2860 | if (rc) |
| 2861 | DRM_WARN("Failed to %s pflip interrupts\n", |
| 2862 | enable ? "enable" : "disable"); |
| 2863 | |
| 2864 | if (enable) { |
Alan Liu | cd465a6 | 2023-05-02 17:54:50 +0800 | [diff] [blame] | 2865 | if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) |
| 2866 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); |
| 2867 | } else |
| 2868 | rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2869 | |
Alan Liu | cd465a6 | 2023-05-02 17:54:50 +0800 | [diff] [blame] | 2870 | if (rc) |
| 2871 | DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); |
| 2872 | |
| 2873 | irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; |
| 2874 | /* During gpu-reset we disable and then enable vblank irq, so |
| 2875 | * don't use amdgpu_irq_get/put() to avoid refcount change. |
| 2876 | */ |
| 2877 | if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) |
| 2878 | DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2879 | } |
| 2880 | } |
| 2881 | |
| 2882 | } |
| 2883 | |
Nirmoy Das | dfd84d9 | 2020-06-18 15:07:13 +0200 | [diff] [blame] | 2884 | static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2885 | { |
| 2886 | struct dc_state *context = NULL; |
| 2887 | enum dc_status res = DC_ERROR_UNEXPECTED; |
| 2888 | int i; |
| 2889 | struct dc_stream_state *del_streams[MAX_PIPES]; |
| 2890 | int del_streams_count = 0; |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 2891 | struct dc_commit_streams_params params = {}; |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2892 | |
| 2893 | memset(del_streams, 0, sizeof(del_streams)); |
| 2894 | |
Dillon Varone | 012a04b | 2023-11-21 15:07:01 -0500 | [diff] [blame] | 2895 | context = dc_state_create_current_copy(dc); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2896 | if (context == NULL) |
| 2897 | goto context_alloc_fail; |
| 2898 | |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2899 | /* First remove from context all streams */ |
| 2900 | for (i = 0; i < context->stream_count; i++) { |
| 2901 | struct dc_stream_state *stream = context->streams[i]; |
| 2902 | |
| 2903 | del_streams[del_streams_count++] = stream; |
| 2904 | } |
| 2905 | |
| 2906 | /* Remove all planes for removed streams and then remove the streams */ |
| 2907 | for (i = 0; i < del_streams_count; i++) { |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 2908 | if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) { |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2909 | res = DC_FAIL_DETACH_SURFACES; |
| 2910 | goto fail; |
| 2911 | } |
| 2912 | |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 2913 | res = dc_state_remove_stream(dc, context, del_streams[i]); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2914 | if (res != DC_OK) |
| 2915 | goto fail; |
| 2916 | } |
| 2917 | |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 2918 | params.streams = context->streams; |
| 2919 | params.stream_count = context->stream_count; |
| 2920 | res = dc_commit_streams(dc, ¶ms); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2921 | |
| 2922 | fail: |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 2923 | dc_state_release(context); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2924 | |
| 2925 | context_alloc_fail: |
| 2926 | return res; |
| 2927 | } |
| 2928 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 2929 | static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) |
| 2930 | { |
| 2931 | int i; |
| 2932 | |
| 2933 | if (dm->hpd_rx_offload_wq) { |
| 2934 | for (i = 0; i < dm->dc->caps.max_links; i++) |
| 2935 | flush_workqueue(dm->hpd_rx_offload_wq[i].wq); |
| 2936 | } |
| 2937 | } |
| 2938 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2939 | static int dm_suspend(void *handle) |
| 2940 | { |
| 2941 | struct amdgpu_device *adev = handle; |
| 2942 | struct amdgpu_display_manager *dm = &adev->dm; |
| 2943 | int ret = 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2944 | |
Dennis Li | 53b3f8f | 2020-08-19 17:23:03 +0800 | [diff] [blame] | 2945 | if (amdgpu_in_reset(adev)) { |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2946 | mutex_lock(&dm->dc_lock); |
Bhawanpreet Lakha | 98ab5f3 | 2021-01-11 14:45:12 -0500 | [diff] [blame] | 2947 | |
Bhawanpreet Lakha | 98ab5f3 | 2021-01-11 14:45:12 -0500 | [diff] [blame] | 2948 | dc_allow_idle_optimizations(adev->dm.dc, false); |
Bhawanpreet Lakha | 98ab5f3 | 2021-01-11 14:45:12 -0500 | [diff] [blame] | 2949 | |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 2950 | dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2951 | |
Alex Hung | 8092aa3 | 2024-06-04 16:33:18 -0600 | [diff] [blame] | 2952 | if (dm->cached_dc_state) |
| 2953 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2954 | |
| 2955 | amdgpu_dm_commit_zero_streams(dm->dc); |
| 2956 | |
| 2957 | amdgpu_dm_irq_suspend(adev); |
| 2958 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 2959 | hpd_rx_irq_work_suspend(dm); |
| 2960 | |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 2961 | return ret; |
| 2962 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2963 | |
Leo (Hanghong) Ma | d2f0b53 | 2019-01-24 15:07:52 -0500 | [diff] [blame] | 2964 | WARN_ON(adev->dm.cached_state); |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 2965 | adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); |
Mario Limonciello | f7fbf79 | 2023-10-06 13:50:24 -0500 | [diff] [blame] | 2966 | if (IS_ERR(adev->dm.cached_state)) |
| 2967 | return PTR_ERR(adev->dm.cached_state); |
Leo (Hanghong) Ma | d2f0b53 | 2019-01-24 15:07:52 -0500 | [diff] [blame] | 2968 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 2969 | s3_handle_mst(adev_to_drm(adev), true); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2970 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2971 | amdgpu_dm_irq_suspend(adev); |
| 2972 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 2973 | hpd_rx_irq_work_suspend(dm); |
| 2974 | |
Tom St Denis | 32f5062 | 2017-10-17 08:48:44 -0400 | [diff] [blame] | 2975 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
Hamza Mahfooz | 79bc412 | 2024-10-04 15:22:57 -0400 | [diff] [blame] | 2976 | |
| 2977 | if (dm->dc->caps.ips_support && adev->in_s0ix) |
| 2978 | dc_allow_idle_optimizations(dm->dc, true); |
| 2979 | |
Samson Tam | 0f65793 | 2023-11-28 16:53:12 -0500 | [diff] [blame] | 2980 | dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2981 | |
Jason Yan | 1c2075d | 2020-05-04 19:32:13 +0800 | [diff] [blame] | 2982 | return 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2983 | } |
| 2984 | |
Harry Wentland | 748b091 | 2023-12-01 06:25:26 -0700 | [diff] [blame] | 2985 | struct drm_connector * |
Alex Deucher | 1daf8c6 | 2017-10-13 14:04:26 -0400 | [diff] [blame] | 2986 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, |
| 2987 | struct drm_crtc *crtc) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2988 | { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 2989 | u32 i; |
Leo (Sunpeng) Li | c2cea70 | 2017-10-12 17:15:08 -0400 | [diff] [blame] | 2990 | struct drm_connector_state *new_con_state; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2991 | struct drm_connector *connector; |
| 2992 | struct drm_crtc *crtc_from_state; |
| 2993 | |
Leo (Sunpeng) Li | c2cea70 | 2017-10-12 17:15:08 -0400 | [diff] [blame] | 2994 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
| 2995 | crtc_from_state = new_con_state->crtc; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2996 | |
| 2997 | if (crtc_from_state == crtc) |
Harry Wentland | 748b091 | 2023-12-01 06:25:26 -0700 | [diff] [blame] | 2998 | return connector; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 2999 | } |
| 3000 | |
| 3001 | return NULL; |
| 3002 | } |
| 3003 | |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3004 | static void emulated_link_detect(struct dc_link *link) |
| 3005 | { |
| 3006 | struct dc_sink_init_data sink_init_data = { 0 }; |
| 3007 | struct display_sink_capability sink_caps = { 0 }; |
| 3008 | enum dc_edid_status edid_status; |
| 3009 | struct dc_context *dc_ctx = link->ctx; |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 3010 | struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3011 | struct dc_sink *sink = NULL; |
| 3012 | struct dc_sink *prev_sink = NULL; |
| 3013 | |
| 3014 | link->type = dc_connection_none; |
| 3015 | prev_sink = link->local_sink; |
| 3016 | |
Victor Lu | 30164a1 | 2021-01-14 22:24:14 -0500 | [diff] [blame] | 3017 | if (prev_sink) |
| 3018 | dc_sink_release(prev_sink); |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3019 | |
| 3020 | switch (link->connector_signal) { |
| 3021 | case SIGNAL_TYPE_HDMI_TYPE_A: { |
| 3022 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 3023 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; |
| 3024 | break; |
| 3025 | } |
| 3026 | |
| 3027 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { |
| 3028 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 3029 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; |
| 3030 | break; |
| 3031 | } |
| 3032 | |
| 3033 | case SIGNAL_TYPE_DVI_DUAL_LINK: { |
| 3034 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 3035 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; |
| 3036 | break; |
| 3037 | } |
| 3038 | |
| 3039 | case SIGNAL_TYPE_LVDS: { |
| 3040 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 3041 | sink_caps.signal = SIGNAL_TYPE_LVDS; |
| 3042 | break; |
| 3043 | } |
| 3044 | |
| 3045 | case SIGNAL_TYPE_EDP: { |
| 3046 | sink_caps.transaction_type = |
| 3047 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; |
| 3048 | sink_caps.signal = SIGNAL_TYPE_EDP; |
| 3049 | break; |
| 3050 | } |
| 3051 | |
| 3052 | case SIGNAL_TYPE_DISPLAY_PORT: { |
| 3053 | sink_caps.transaction_type = |
| 3054 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; |
| 3055 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; |
| 3056 | break; |
| 3057 | } |
| 3058 | |
| 3059 | default: |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 3060 | drm_err(dev, "Invalid connector type! signal:%d\n", |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3061 | link->connector_signal); |
| 3062 | return; |
| 3063 | } |
| 3064 | |
| 3065 | sink_init_data.link = link; |
| 3066 | sink_init_data.sink_signal = sink_caps.signal; |
| 3067 | |
| 3068 | sink = dc_sink_create(&sink_init_data); |
| 3069 | if (!sink) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 3070 | drm_err(dev, "Failed to create sink!\n"); |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3071 | return; |
| 3072 | } |
| 3073 | |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3074 | /* dc_sink_create returns a new reference */ |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3075 | link->local_sink = sink; |
| 3076 | |
| 3077 | edid_status = dm_helpers_read_local_edid( |
| 3078 | link->ctx, |
| 3079 | link, |
| 3080 | sink); |
| 3081 | |
| 3082 | if (edid_status != EDID_OK) |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 3083 | drm_err(dev, "Failed to read EDID\n"); |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3084 | |
| 3085 | } |
| 3086 | |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3087 | static void dm_gpureset_commit_state(struct dc_state *dc_state, |
| 3088 | struct amdgpu_display_manager *dm) |
| 3089 | { |
| 3090 | struct { |
| 3091 | struct dc_surface_update surface_updates[MAX_SURFACES]; |
| 3092 | struct dc_plane_info plane_infos[MAX_SURFACES]; |
| 3093 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; |
| 3094 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; |
| 3095 | struct dc_stream_update stream_update; |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3096 | } *bundle; |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3097 | int k, m; |
| 3098 | |
| 3099 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); |
| 3100 | |
| 3101 | if (!bundle) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 3102 | drm_err(dm->ddev, "Failed to allocate update bundle\n"); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3103 | goto cleanup; |
| 3104 | } |
| 3105 | |
| 3106 | for (k = 0; k < dc_state->stream_count; k++) { |
| 3107 | bundle->stream_update.stream = dc_state->streams[k]; |
| 3108 | |
| 3109 | for (m = 0; m < dc_state->stream_status->plane_count; m++) { |
| 3110 | bundle->surface_updates[m].surface = |
| 3111 | dc_state->stream_status->plane_states[m]; |
| 3112 | bundle->surface_updates[m].surface->force_full_update = |
| 3113 | true; |
| 3114 | } |
Rodrigo Siqueira | f751128 | 2022-10-06 16:40:55 -0400 | [diff] [blame] | 3115 | |
Rodrigo Siqueira | 81f743a | 2023-02-23 11:36:08 -0700 | [diff] [blame] | 3116 | update_planes_and_stream_adapter(dm->dc, |
| 3117 | UPDATE_TYPE_FULL, |
| 3118 | dc_state->stream_status->plane_count, |
| 3119 | dc_state->streams[k], |
| 3120 | &bundle->stream_update, |
| 3121 | bundle->surface_updates); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3122 | } |
| 3123 | |
| 3124 | cleanup: |
| 3125 | kfree(bundle); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3126 | } |
| 3127 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3128 | static int dm_resume(void *handle) |
| 3129 | { |
| 3130 | struct amdgpu_device *adev = handle; |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 3131 | struct drm_device *ddev = adev_to_drm(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3132 | struct amdgpu_display_manager *dm = &adev->dm; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 3133 | struct amdgpu_dm_connector *aconnector; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3134 | struct drm_connector *connector; |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 3135 | struct drm_connector_list_iter iter; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3136 | struct drm_crtc *crtc; |
Leo (Sunpeng) Li | c2cea70 | 2017-10-12 17:15:08 -0400 | [diff] [blame] | 3137 | struct drm_crtc_state *new_crtc_state; |
Leo (Sunpeng) Li | fcb4019 | 2017-11-01 16:49:14 -0400 | [diff] [blame] | 3138 | struct dm_crtc_state *dm_new_crtc_state; |
| 3139 | struct drm_plane *plane; |
| 3140 | struct drm_plane_state *new_plane_state; |
| 3141 | struct dm_plane_state *dm_new_plane_state; |
Leo Li | 113b7a0 | 2019-03-19 19:29:16 -0400 | [diff] [blame] | 3142 | struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3143 | enum dc_connection_type new_connection_type = dc_connection_none; |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3144 | struct dc_state *dc_state; |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 3145 | int i, r, j, ret; |
| 3146 | bool need_hotplug = false; |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 3147 | struct dc_commit_streams_params commit_params = {}; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3148 | |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 3149 | if (dm->dc->caps.ips_support) { |
Nicholas Kazlauskas | 8e57c06 | 2023-12-04 14:10:05 -0500 | [diff] [blame] | 3150 | dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 3151 | } |
| 3152 | |
Dennis Li | 53b3f8f | 2020-08-19 17:23:03 +0800 | [diff] [blame] | 3153 | if (amdgpu_in_reset(adev)) { |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3154 | dc_state = dm->cached_dc_state; |
| 3155 | |
Nicholas Kazlauskas | 6d63fcc | 2021-11-09 16:03:21 -0500 | [diff] [blame] | 3156 | /* |
| 3157 | * The dc->current_state is backed up into dm->cached_dc_state |
| 3158 | * before we commit 0 streams. |
| 3159 | * |
| 3160 | * DC will clear link encoder assignments on the real state |
| 3161 | * but the changes won't propagate over to the copy we made |
| 3162 | * before the 0 streams commit. |
| 3163 | * |
| 3164 | * DC expects that link encoder assignments are *not* valid |
Nicholas Kazlauskas | 32685b3 | 2022-02-28 10:48:56 -0500 | [diff] [blame] | 3165 | * when committing a state, so as a workaround we can copy |
| 3166 | * off of the current state. |
| 3167 | * |
| 3168 | * We lose the previous assignments, but we had already |
| 3169 | * commit 0 streams anyway. |
Nicholas Kazlauskas | 6d63fcc | 2021-11-09 16:03:21 -0500 | [diff] [blame] | 3170 | */ |
Nicholas Kazlauskas | 32685b3 | 2022-02-28 10:48:56 -0500 | [diff] [blame] | 3171 | link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); |
Nicholas Kazlauskas | 6d63fcc | 2021-11-09 16:03:21 -0500 | [diff] [blame] | 3172 | |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3173 | r = dm_dmub_hw_init(adev); |
| 3174 | if (r) |
| 3175 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); |
| 3176 | |
Samson Tam | 0f65793 | 2023-11-28 16:53:12 -0500 | [diff] [blame] | 3177 | dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3178 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); |
Mario Limonciello | 7441ef0 | 2023-09-21 09:50:04 -0500 | [diff] [blame] | 3179 | |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3180 | dc_resume(dm->dc); |
| 3181 | |
| 3182 | amdgpu_dm_irq_resume_early(adev); |
| 3183 | |
| 3184 | for (i = 0; i < dc_state->stream_count; i++) { |
| 3185 | dc_state->streams[i]->mode_changed = true; |
Nicholas Kazlauskas | 6984fa4 | 2021-11-09 11:24:10 -0500 | [diff] [blame] | 3186 | for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { |
| 3187 | dc_state->stream_status[i].plane_states[j]->update_flags.raw |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3188 | = 0xffffffff; |
| 3189 | } |
| 3190 | } |
| 3191 | |
Stylon Wang | 11d526f | 2022-07-07 16:23:29 +0800 | [diff] [blame] | 3192 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
| 3193 | amdgpu_dm_outbox_init(adev); |
| 3194 | dc_enable_dmub_outbox(adev->dm.dc); |
| 3195 | } |
| 3196 | |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 3197 | commit_params.streams = dc_state->streams; |
| 3198 | commit_params.stream_count = dc_state->stream_count; |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 3199 | dc_exit_ips_for_hw_access(dm->dc); |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 3200 | WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3201 | |
| 3202 | dm_gpureset_commit_state(dm->cached_dc_state, dm); |
| 3203 | |
| 3204 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); |
| 3205 | |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 3206 | dc_state_release(dm->cached_dc_state); |
Bhawanpreet Lakha | cdaae83 | 2020-05-11 14:21:17 -0400 | [diff] [blame] | 3207 | dm->cached_dc_state = NULL; |
| 3208 | |
| 3209 | amdgpu_dm_irq_resume_late(adev); |
| 3210 | |
| 3211 | mutex_unlock(&dm->dc_lock); |
| 3212 | |
| 3213 | return 0; |
| 3214 | } |
Leo Li | 113b7a0 | 2019-03-19 19:29:16 -0400 | [diff] [blame] | 3215 | /* Recreate dc_state - DC invalidates it when setting power state to S3. */ |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 3216 | dc_state_release(dm_state->context); |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 3217 | dm_state->context = dc_state_create(dm->dc, NULL); |
Leo Li | 113b7a0 | 2019-03-19 19:29:16 -0400 | [diff] [blame] | 3218 | /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ |
Leo Li | 113b7a0 | 2019-03-19 19:29:16 -0400 | [diff] [blame] | 3219 | |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 3220 | /* Before powering on DC we need to re-initialize DMUB. */ |
Nicholas Kazlauskas | 79d6b93 | 2021-12-15 18:18:41 -0500 | [diff] [blame] | 3221 | dm_dmub_hw_resume(adev); |
Nicholas Kazlauskas | 8c7aea4 | 2019-11-25 09:49:27 -0500 | [diff] [blame] | 3222 | |
Stylon Wang | 11d526f | 2022-07-07 16:23:29 +0800 | [diff] [blame] | 3223 | /* Re-enable outbox interrupts for DPIA. */ |
| 3224 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
| 3225 | amdgpu_dm_outbox_init(adev); |
| 3226 | dc_enable_dmub_outbox(adev->dm.dc); |
| 3227 | } |
| 3228 | |
Mikita Lipski | a80aa93 | 2018-02-03 14:18:07 -0500 | [diff] [blame] | 3229 | /* power on hardware */ |
Samson Tam | 0f65793 | 2023-11-28 16:53:12 -0500 | [diff] [blame] | 3230 | dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); |
Jiapeng Chong | b63eae9 | 2023-10-19 11:38:26 +0800 | [diff] [blame] | 3231 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); |
Mikita Lipski | a80aa93 | 2018-02-03 14:18:07 -0500 | [diff] [blame] | 3232 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3233 | /* program HPD filter */ |
| 3234 | dc_resume(dm->dc); |
| 3235 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3236 | /* |
| 3237 | * early enable HPD Rx IRQ, should be done before set mode as short |
| 3238 | * pulse interrupts are used for MST |
| 3239 | */ |
| 3240 | amdgpu_dm_irq_resume_early(adev); |
| 3241 | |
Lyude Paul | d20ebea | 2019-07-16 18:22:16 -0400 | [diff] [blame] | 3242 | /* On resume we need to rewrite the MSTM control bits to enable MST*/ |
Lyude Paul | 684cd48 | 2019-09-25 17:52:48 -0400 | [diff] [blame] | 3243 | s3_handle_mst(ddev, false); |
| 3244 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3245 | /* Do detection*/ |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 3246 | drm_connector_list_iter_begin(ddev, &iter); |
| 3247 | drm_for_each_connector_iter(connector, &iter) { |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 3248 | |
| 3249 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 3250 | continue; |
| 3251 | |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 3252 | aconnector = to_amdgpu_dm_connector(connector); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3253 | |
Roman Li | 7a7175a | 2022-12-01 09:06:42 -0500 | [diff] [blame] | 3254 | if (!aconnector->dc_link) |
| 3255 | continue; |
| 3256 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3257 | /* |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 3258 | * this is the case when traversing through already created end sink |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3259 | * MST connectors, should be skipped |
| 3260 | */ |
Alex Hung | db39d57 | 2024-06-06 19:49:23 -0600 | [diff] [blame] | 3261 | if (aconnector->mst_root) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3262 | continue; |
| 3263 | |
Arindam Nath | 03ea364 | 2017-04-26 17:39:56 +0530 | [diff] [blame] | 3264 | mutex_lock(&aconnector->hpd_lock); |
Wenjing Liu | 5461888 | 2023-01-18 17:31:24 -0500 | [diff] [blame] | 3265 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3266 | DRM_ERROR("KMS: Failed to detect connector\n"); |
| 3267 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3268 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3269 | emulated_link_detect(aconnector->dc_link); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3270 | } else { |
| 3271 | mutex_lock(&dm->dc_lock); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 3272 | dc_exit_ips_for_hw_access(dm->dc); |
Wayne Lin | e336971 | 2024-05-23 12:18:07 +0800 | [diff] [blame] | 3273 | dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3274 | mutex_unlock(&dm->dc_lock); |
| 3275 | } |
Roman Li | 3eb4eba | 2017-10-20 10:15:18 -0400 | [diff] [blame] | 3276 | |
| 3277 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) |
| 3278 | aconnector->fake_enable = false; |
| 3279 | |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3280 | if (aconnector->dc_sink) |
| 3281 | dc_sink_release(aconnector->dc_sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3282 | aconnector->dc_sink = NULL; |
| 3283 | amdgpu_dm_update_connector_after_detect(aconnector); |
Arindam Nath | 03ea364 | 2017-04-26 17:39:56 +0530 | [diff] [blame] | 3284 | mutex_unlock(&aconnector->hpd_lock); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3285 | } |
Lyude Paul | f8d2d39 | 2019-09-03 16:46:01 -0400 | [diff] [blame] | 3286 | drm_connector_list_iter_end(&iter); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3287 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3288 | /* Force mode set in atomic commit */ |
Tom Chung | df18a4d | 2024-07-12 17:29:07 +0800 | [diff] [blame] | 3289 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
Leo (Sunpeng) Li | c2cea70 | 2017-10-12 17:15:08 -0400 | [diff] [blame] | 3290 | new_crtc_state->active_changed = true; |
Tom Chung | df18a4d | 2024-07-12 17:29:07 +0800 | [diff] [blame] | 3291 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 3292 | reset_freesync_config_for_crtc(dm_new_crtc_state); |
| 3293 | } |
Andrey Grodzovsky | a3621485 | 2017-04-20 15:59:25 -0400 | [diff] [blame] | 3294 | |
Leo (Sunpeng) Li | fcb4019 | 2017-11-01 16:49:14 -0400 | [diff] [blame] | 3295 | /* |
| 3296 | * atomic_check is expected to create the dc states. We need to release |
| 3297 | * them here, since they were duplicated as part of the suspend |
| 3298 | * procedure. |
| 3299 | */ |
Mikita Lipski | a80aa93 | 2018-02-03 14:18:07 -0500 | [diff] [blame] | 3300 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
Leo (Sunpeng) Li | fcb4019 | 2017-11-01 16:49:14 -0400 | [diff] [blame] | 3301 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 3302 | if (dm_new_crtc_state->stream) { |
| 3303 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); |
| 3304 | dc_stream_release(dm_new_crtc_state->stream); |
| 3305 | dm_new_crtc_state->stream = NULL; |
| 3306 | } |
Joshua Ashton | 6e7a417 | 2023-11-02 04:21:55 +0000 | [diff] [blame] | 3307 | dm_new_crtc_state->base.color_mgmt_changed = true; |
Leo (Sunpeng) Li | fcb4019 | 2017-11-01 16:49:14 -0400 | [diff] [blame] | 3308 | } |
| 3309 | |
Mikita Lipski | a80aa93 | 2018-02-03 14:18:07 -0500 | [diff] [blame] | 3310 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { |
Leo (Sunpeng) Li | fcb4019 | 2017-11-01 16:49:14 -0400 | [diff] [blame] | 3311 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
| 3312 | if (dm_new_plane_state->dc_state) { |
| 3313 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); |
| 3314 | dc_plane_state_release(dm_new_plane_state->dc_state); |
| 3315 | dm_new_plane_state->dc_state = NULL; |
| 3316 | } |
| 3317 | } |
| 3318 | |
Lyude Paul | 2d1af6a | 2019-01-08 16:11:28 -0500 | [diff] [blame] | 3319 | drm_atomic_helper_resume(ddev, dm->cached_state); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3320 | |
Mikita Lipski | a80aa93 | 2018-02-03 14:18:07 -0500 | [diff] [blame] | 3321 | dm->cached_state = NULL; |
Andrey Grodzovsky | 0a214e2 | 2017-07-13 10:56:48 -0400 | [diff] [blame] | 3322 | |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 3323 | /* Do mst topology probing after resuming cached state*/ |
| 3324 | drm_connector_list_iter_begin(ddev, &iter); |
| 3325 | drm_for_each_connector_iter(connector, &iter) { |
Alex Hung | cf82a80 | 2024-03-15 21:25:25 -0600 | [diff] [blame] | 3326 | |
| 3327 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 3328 | continue; |
| 3329 | |
Wayne Lin | ec5fa9f | 2023-08-22 16:03:17 +0800 | [diff] [blame] | 3330 | aconnector = to_amdgpu_dm_connector(connector); |
| 3331 | if (aconnector->dc_link->type != dc_connection_mst_branch || |
| 3332 | aconnector->mst_root) |
| 3333 | continue; |
| 3334 | |
| 3335 | ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); |
| 3336 | |
| 3337 | if (ret < 0) { |
| 3338 | dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
| 3339 | aconnector->dc_link); |
| 3340 | need_hotplug = true; |
| 3341 | } |
| 3342 | } |
| 3343 | drm_connector_list_iter_end(&iter); |
| 3344 | |
| 3345 | if (need_hotplug) |
| 3346 | drm_kms_helper_hotplug_event(ddev); |
| 3347 | |
Andrey Grodzovsky | 9faa423 | 2017-03-31 14:15:31 -0400 | [diff] [blame] | 3348 | amdgpu_dm_irq_resume_late(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3349 | |
Hersen Wu | 9340dfd | 2020-02-13 10:50:13 -0500 | [diff] [blame] | 3350 | amdgpu_dm_smu_write_watermarks_table(adev); |
| 3351 | |
Lyude Paul | 2d1af6a | 2019-01-08 16:11:28 -0500 | [diff] [blame] | 3352 | return 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3353 | } |
| 3354 | |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 3355 | /** |
| 3356 | * DOC: DM Lifecycle |
| 3357 | * |
| 3358 | * DM (and consequently DC) is registered in the amdgpu base driver as a IP |
| 3359 | * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to |
| 3360 | * the base driver's device list to be initialized and torn down accordingly. |
| 3361 | * |
| 3362 | * The functions to do so are provided as hooks in &struct amd_ip_funcs. |
| 3363 | */ |
| 3364 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3365 | static const struct amd_ip_funcs amdgpu_dm_funcs = { |
| 3366 | .name = "dm", |
| 3367 | .early_init = dm_early_init, |
Andrey Grodzovsky | 7abcf6b | 2016-12-29 13:21:31 -0500 | [diff] [blame] | 3368 | .late_init = dm_late_init, |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3369 | .sw_init = dm_sw_init, |
| 3370 | .sw_fini = dm_sw_fini, |
Andrey Grodzovsky | e9669fb | 2021-05-19 23:20:57 -0400 | [diff] [blame] | 3371 | .early_fini = amdgpu_dm_early_fini, |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3372 | .hw_init = dm_hw_init, |
| 3373 | .hw_fini = dm_hw_fini, |
| 3374 | .suspend = dm_suspend, |
| 3375 | .resume = dm_resume, |
| 3376 | .is_idle = dm_is_idle, |
| 3377 | .wait_for_idle = dm_wait_for_idle, |
| 3378 | .check_soft_reset = dm_check_soft_reset, |
| 3379 | .soft_reset = dm_soft_reset, |
| 3380 | .set_clockgating_state = dm_set_clockgating_state, |
| 3381 | .set_powergating_state = dm_set_powergating_state, |
Sunil Khatri | e21d253 | 2024-04-01 15:58:38 +0530 | [diff] [blame] | 3382 | .dump_ip_state = NULL, |
Sunil Khatri | 4035654 | 2024-04-16 16:30:50 +0530 | [diff] [blame] | 3383 | .print_ip_state = NULL, |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3384 | }; |
| 3385 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3386 | const struct amdgpu_ip_block_version dm_ip_block = { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3387 | .type = AMD_IP_BLOCK_TYPE_DCE, |
| 3388 | .major = 1, |
| 3389 | .minor = 0, |
| 3390 | .rev = 0, |
| 3391 | .funcs = &amdgpu_dm_funcs, |
| 3392 | }; |
| 3393 | |
Harry Wentland | ca3268c | 2017-06-27 11:55:43 -0400 | [diff] [blame] | 3394 | |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 3395 | /** |
| 3396 | * DOC: atomic |
| 3397 | * |
| 3398 | * *WIP* |
| 3399 | */ |
Andrey Grodzovsky | 0a323b8 | 2017-07-11 14:42:57 -0400 | [diff] [blame] | 3400 | |
Harry Wentland | b3663f7 | 2017-06-27 11:12:37 -0400 | [diff] [blame] | 3401 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
Samuel Li | 4d4772f | 2018-01-19 12:24:39 -0500 | [diff] [blame] | 3402 | .fb_create = amdgpu_display_user_framebuffer_create, |
David Tadokoro | 8bf0d9c | 2023-03-05 23:24:27 -0300 | [diff] [blame] | 3403 | .get_format_info = amdgpu_dm_plane_get_format_info, |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3404 | .atomic_check = amdgpu_dm_atomic_check, |
Rodrigo Siqueira | 0269764 | 2020-12-07 17:20:27 -0500 | [diff] [blame] | 3405 | .atomic_commit = drm_atomic_helper_commit, |
Andrey Grodzovsky | 54f5499 | 2017-04-20 15:57:05 -0400 | [diff] [blame] | 3406 | }; |
| 3407 | |
| 3408 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { |
Lyude Paul | a5c2c0d | 2022-08-17 15:38:37 -0400 | [diff] [blame] | 3409 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, |
| 3410 | .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3411 | }; |
| 3412 | |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3413 | static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) |
| 3414 | { |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3415 | struct amdgpu_dm_backlight_caps *caps; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3416 | struct drm_connector *conn_base; |
| 3417 | struct amdgpu_device *adev; |
Jouni Högander | a61bb34 | 2022-07-19 12:56:59 +0300 | [diff] [blame] | 3418 | struct drm_luminance_range_info *luminance_range; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3419 | |
Hans de Goede | f196198 | 2023-03-12 20:17:48 +0100 | [diff] [blame] | 3420 | if (aconnector->bl_idx == -1 || |
| 3421 | aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
hersen wu | ec11fe3 | 2020-06-22 13:29:16 -0400 | [diff] [blame] | 3422 | return; |
| 3423 | |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3424 | conn_base = &aconnector->base; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 3425 | adev = drm_to_adev(conn_base->dev); |
Hans de Goede | f196198 | 2023-03-12 20:17:48 +0100 | [diff] [blame] | 3426 | |
| 3427 | caps = &adev->dm.backlight_caps[aconnector->bl_idx]; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3428 | caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; |
| 3429 | caps->aux_support = false; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3430 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3431 | if (caps->ext_caps->bits.oled == 1 |
| 3432 | /* |
| 3433 | * || |
| 3434 | * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || |
| 3435 | * caps->ext_caps->bits.hdr_aux_backlight_control == 1 |
| 3436 | */) |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3437 | caps->aux_support = true; |
| 3438 | |
Takashi Iwai | 7a46f05 | 2021-02-03 13:42:41 +0100 | [diff] [blame] | 3439 | if (amdgpu_backlight == 0) |
| 3440 | caps->aux_support = false; |
| 3441 | else if (amdgpu_backlight == 1) |
| 3442 | caps->aux_support = true; |
| 3443 | |
Jouni Högander | a61bb34 | 2022-07-19 12:56:59 +0300 | [diff] [blame] | 3444 | luminance_range = &conn_base->display_info.luminance_range; |
Swapnil Patel | 932698c | 2023-02-24 20:16:09 -0500 | [diff] [blame] | 3445 | |
| 3446 | if (luminance_range->max_luminance) { |
| 3447 | caps->aux_min_input_signal = luminance_range->min_luminance; |
| 3448 | caps->aux_max_input_signal = luminance_range->max_luminance; |
| 3449 | } else { |
| 3450 | caps->aux_min_input_signal = 0; |
| 3451 | caps->aux_max_input_signal = 512; |
| 3452 | } |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3453 | } |
| 3454 | |
Hersen Wu | 97e51c16 | 2020-02-13 12:44:35 -0500 | [diff] [blame] | 3455 | void amdgpu_dm_update_connector_after_detect( |
| 3456 | struct amdgpu_dm_connector *aconnector) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3457 | { |
| 3458 | struct drm_connector *connector = &aconnector->base; |
| 3459 | struct drm_device *dev = connector->dev; |
Harry Wentland | b73a22d | 2017-07-24 14:04:27 -0400 | [diff] [blame] | 3460 | struct dc_sink *sink; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3461 | |
| 3462 | /* MST handled by drm_mst framework */ |
| 3463 | if (aconnector->mst_mgr.mst_state == true) |
| 3464 | return; |
| 3465 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3466 | sink = aconnector->dc_link->local_sink; |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3467 | if (sink) |
| 3468 | dc_sink_retain(sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3469 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3470 | /* |
| 3471 | * Edid mgmt connector gets first update only in mode_valid hook and then |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3472 | * the connector sink is set to either fake or physical sink depends on link status. |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3473 | * Skip if already done during boot. |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3474 | */ |
| 3475 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED |
| 3476 | && aconnector->dc_em_sink) { |
| 3477 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3478 | /* |
| 3479 | * For S3 resume with headless use eml_sink to fake stream |
| 3480 | * because on resume connector->sink is set to NULL |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3481 | */ |
| 3482 | mutex_lock(&dev->mode_config.mutex); |
| 3483 | |
| 3484 | if (sink) { |
Andrey Grodzovsky | 922aa1e | 2016-12-07 14:10:05 -0500 | [diff] [blame] | 3485 | if (aconnector->dc_sink) { |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 3486 | amdgpu_dm_update_freesync_caps(connector, NULL); |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3487 | /* |
| 3488 | * retain and release below are used to |
| 3489 | * bump up refcount for sink because the link doesn't point |
| 3490 | * to it anymore after disconnect, so on next crtc to connector |
Andrey Grodzovsky | 922aa1e | 2016-12-07 14:10:05 -0500 | [diff] [blame] | 3491 | * reshuffle by UMD we will get into unwanted dc_sink release |
| 3492 | */ |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3493 | dc_sink_release(aconnector->dc_sink); |
Andrey Grodzovsky | 922aa1e | 2016-12-07 14:10:05 -0500 | [diff] [blame] | 3494 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3495 | aconnector->dc_sink = sink; |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3496 | dc_sink_retain(aconnector->dc_sink); |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 3497 | amdgpu_dm_update_freesync_caps(connector, |
| 3498 | aconnector->edid); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3499 | } else { |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 3500 | amdgpu_dm_update_freesync_caps(connector, NULL); |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3501 | if (!aconnector->dc_sink) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3502 | aconnector->dc_sink = aconnector->dc_em_sink; |
Andrey Grodzovsky | 922aa1e | 2016-12-07 14:10:05 -0500 | [diff] [blame] | 3503 | dc_sink_retain(aconnector->dc_sink); |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3504 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3505 | } |
| 3506 | |
| 3507 | mutex_unlock(&dev->mode_config.mutex); |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3508 | |
| 3509 | if (sink) |
| 3510 | dc_sink_release(sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3511 | return; |
| 3512 | } |
| 3513 | |
| 3514 | /* |
| 3515 | * TODO: temporary guard to look for proper fix |
| 3516 | * if this sink is MST sink, we should not do anything |
| 3517 | */ |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3518 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { |
| 3519 | dc_sink_release(sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3520 | return; |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3521 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3522 | |
| 3523 | if (aconnector->dc_sink == sink) { |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3524 | /* |
| 3525 | * We got a DP short pulse (Link Loss, DP CTS, etc...). |
| 3526 | * Do nothing!! |
| 3527 | */ |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 3528 | drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n", |
| 3529 | aconnector->connector_id); |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3530 | if (sink) |
| 3531 | dc_sink_release(sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3532 | return; |
| 3533 | } |
| 3534 | |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 3535 | drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", |
| 3536 | aconnector->connector_id, aconnector->dc_sink, sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3537 | |
| 3538 | mutex_lock(&dev->mode_config.mutex); |
| 3539 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3540 | /* |
| 3541 | * 1. Update status of the drm connector |
| 3542 | * 2. Send an event and let userspace tell us what to do |
| 3543 | */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3544 | if (sink) { |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3545 | /* |
| 3546 | * TODO: check if we still need the S3 mode update workaround. |
| 3547 | * If yes, put it here. |
| 3548 | */ |
Victor Lu | c64b0d6 | 2021-01-15 11:02:48 -0500 | [diff] [blame] | 3549 | if (aconnector->dc_sink) { |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 3550 | amdgpu_dm_update_freesync_caps(connector, NULL); |
Victor Lu | c64b0d6 | 2021-01-15 11:02:48 -0500 | [diff] [blame] | 3551 | dc_sink_release(aconnector->dc_sink); |
| 3552 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3553 | |
| 3554 | aconnector->dc_sink = sink; |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3555 | dc_sink_retain(aconnector->dc_sink); |
Tom St Denis | 900b3cb | 2017-10-17 08:59:18 -0400 | [diff] [blame] | 3556 | if (sink->dc_edid.length == 0) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3557 | aconnector->edid = NULL; |
Aurabindo Pillai | e6142dd | 2020-04-22 14:37:33 -0400 | [diff] [blame] | 3558 | if (aconnector->dc_link->aux_mode) { |
| 3559 | drm_dp_cec_unset_edid( |
| 3560 | &aconnector->dm_dp_aux.aux); |
| 3561 | } |
Tom St Denis | 900b3cb | 2017-10-17 08:59:18 -0400 | [diff] [blame] | 3562 | } else { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3563 | aconnector->edid = |
Aurabindo Pillai | e6142dd | 2020-04-22 14:37:33 -0400 | [diff] [blame] | 3564 | (struct edid *)sink->dc_edid.raw_edid; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3565 | |
Aurabindo Pillai | e6142dd | 2020-04-22 14:37:33 -0400 | [diff] [blame] | 3566 | if (aconnector->dc_link->aux_mode) |
| 3567 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, |
| 3568 | aconnector->edid); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3569 | } |
Aurabindo Pillai | e6142dd | 2020-04-22 14:37:33 -0400 | [diff] [blame] | 3570 | |
Hersen Wu | 025ce39 | 2023-03-27 09:10:48 -0400 | [diff] [blame] | 3571 | if (!aconnector->timing_requested) { |
| 3572 | aconnector->timing_requested = |
| 3573 | kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); |
| 3574 | if (!aconnector->timing_requested) |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 3575 | drm_err(dev, |
| 3576 | "failed to create aconnector->requested_timing\n"); |
Hersen Wu | 025ce39 | 2023-03-27 09:10:48 -0400 | [diff] [blame] | 3577 | } |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 3578 | |
Claudio Suarez | 20543be | 2021-10-17 13:34:58 +0200 | [diff] [blame] | 3579 | drm_connector_update_edid_property(connector, aconnector->edid); |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 3580 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 3581 | update_connector_ext_caps(aconnector); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3582 | } else { |
Hans Verkuil | e86e894 | 2018-08-27 10:08:18 +0200 | [diff] [blame] | 3583 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 3584 | amdgpu_dm_update_freesync_caps(connector, NULL); |
Daniel Vetter | c555f02 | 2018-07-09 10:40:06 +0200 | [diff] [blame] | 3585 | drm_connector_update_edid_property(connector, NULL); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3586 | aconnector->num_modes = 0; |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3587 | dc_sink_release(aconnector->dc_sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3588 | aconnector->dc_sink = NULL; |
Mikita Lipski | 5326c45 | 2018-04-27 09:09:52 -0400 | [diff] [blame] | 3589 | aconnector->edid = NULL; |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 3590 | kfree(aconnector->timing_requested); |
| 3591 | aconnector->timing_requested = NULL; |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 3592 | /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ |
| 3593 | if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) |
| 3594 | connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3595 | } |
| 3596 | |
| 3597 | mutex_unlock(&dev->mode_config.mutex); |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3598 | |
Oleg Vasilev | 0f87789 | 2020-04-24 18:20:55 +0530 | [diff] [blame] | 3599 | update_subconnector_property(aconnector); |
| 3600 | |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 3601 | if (sink) |
| 3602 | dc_sink_release(sink); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3603 | } |
| 3604 | |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 3605 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3606 | { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3607 | struct drm_connector *connector = &aconnector->base; |
| 3608 | struct drm_device *dev = connector->dev; |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3609 | enum dc_connection_type new_connection_type = dc_connection_none; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 3610 | struct amdgpu_device *adev = drm_to_adev(dev); |
Bhawanpreet Lakha | 97f6c91 | 2019-09-26 16:55:24 -0400 | [diff] [blame] | 3611 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 3612 | struct dc *dc = aconnector->dc_link->ctx->dc; |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3613 | bool ret = false; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3614 | |
Harry Wentland | b972b4f | 2020-10-02 13:32:00 -0400 | [diff] [blame] | 3615 | if (adev->dm.disable_hpd_irq) |
| 3616 | return; |
| 3617 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3618 | /* |
| 3619 | * In case of failure or MST no need to update connector status or notify the OS |
| 3620 | * since (for MST case) MST does this in its own context. |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3621 | */ |
| 3622 | mutex_lock(&aconnector->hpd_lock); |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 3623 | |
Bhawanpreet Lakha | 97f6c91 | 2019-09-26 16:55:24 -0400 | [diff] [blame] | 3624 | if (adev->dm.hdcp_workqueue) { |
Bhawanpreet Lakha | 96a3b32 | 2019-06-24 14:54:13 -0400 | [diff] [blame] | 3625 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); |
Bhawanpreet Lakha | 97f6c91 | 2019-09-26 16:55:24 -0400 | [diff] [blame] | 3626 | dm_con_state->update_hdcp = true; |
| 3627 | } |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 3628 | if (aconnector->fake_enable) |
| 3629 | aconnector->fake_enable = false; |
| 3630 | |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 3631 | aconnector->timing_changed = false; |
| 3632 | |
Wenjing Liu | 5461888 | 2023-01-18 17:31:24 -0500 | [diff] [blame] | 3633 | if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3634 | DRM_ERROR("KMS: Failed to detect connector\n"); |
| 3635 | |
| 3636 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
| 3637 | emulated_link_detect(aconnector->dc_link); |
| 3638 | |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3639 | drm_modeset_lock_all(dev); |
| 3640 | dm_restore_drm_connector_state(dev, connector); |
| 3641 | drm_modeset_unlock_all(dev); |
| 3642 | |
| 3643 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
Simon Ser | fc320a6 | 2021-10-18 08:47:28 +0000 | [diff] [blame] | 3644 | drm_kms_helper_connector_hotplug_event(connector); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3645 | } else { |
| 3646 | mutex_lock(&adev->dm.dc_lock); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 3647 | dc_exit_ips_for_hw_access(dc); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3648 | ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); |
| 3649 | mutex_unlock(&adev->dm.dc_lock); |
| 3650 | if (ret) { |
| 3651 | amdgpu_dm_update_connector_after_detect(aconnector); |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3652 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3653 | drm_modeset_lock_all(dev); |
| 3654 | dm_restore_drm_connector_state(dev, connector); |
| 3655 | drm_modeset_unlock_all(dev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3656 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3657 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
| 3658 | drm_kms_helper_connector_hotplug_event(connector); |
| 3659 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3660 | } |
| 3661 | mutex_unlock(&aconnector->hpd_lock); |
| 3662 | |
| 3663 | } |
| 3664 | |
Jude Shih | e27c41d | 2021-07-25 13:55:02 +0800 | [diff] [blame] | 3665 | static void handle_hpd_irq(void *param) |
| 3666 | { |
| 3667 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
| 3668 | |
| 3669 | handle_hpd_irq_helper(aconnector); |
| 3670 | |
| 3671 | } |
| 3672 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 3673 | static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, |
| 3674 | union hpd_irq_data hpd_irq_data) |
| 3675 | { |
| 3676 | struct hpd_rx_irq_offload_work *offload_work = |
| 3677 | kzalloc(sizeof(*offload_work), GFP_KERNEL); |
| 3678 | |
| 3679 | if (!offload_work) { |
| 3680 | DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); |
| 3681 | return; |
| 3682 | } |
| 3683 | |
| 3684 | INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); |
| 3685 | offload_work->data = hpd_irq_data; |
| 3686 | offload_work->offload_wq = offload_wq; |
| 3687 | |
| 3688 | queue_work(offload_wq->wq, &offload_work->work); |
| 3689 | DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); |
| 3690 | } |
| 3691 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3692 | static void handle_hpd_rx_irq(void *param) |
| 3693 | { |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 3694 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3695 | struct drm_connector *connector = &aconnector->base; |
| 3696 | struct drm_device *dev = connector->dev; |
Tom St Denis | 53cbf65 | 2017-10-17 09:04:25 -0400 | [diff] [blame] | 3697 | struct dc_link *dc_link = aconnector->dc_link; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3698 | bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
Qingqing Zhuo | c8ea79a | 2020-10-01 15:56:28 -0400 | [diff] [blame] | 3699 | bool result = false; |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3700 | enum dc_connection_type new_connection_type = dc_connection_none; |
Qingqing Zhuo | c8ea79a | 2020-10-01 15:56:28 -0400 | [diff] [blame] | 3701 | struct amdgpu_device *adev = drm_to_adev(dev); |
Bhawanpreet Lakha | 2a0f927 | 2019-06-10 16:18:38 -0400 | [diff] [blame] | 3702 | union hpd_irq_data hpd_irq_data; |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 3703 | bool link_loss = false; |
| 3704 | bool has_left_work = false; |
Hersen Wu | e322843 | 2023-01-17 10:58:34 -0500 | [diff] [blame] | 3705 | int idx = dc_link->link_index; |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 3706 | struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 3707 | struct dc *dc = aconnector->dc_link->ctx->dc; |
Bhawanpreet Lakha | 2a0f927 | 2019-06-10 16:18:38 -0400 | [diff] [blame] | 3708 | |
| 3709 | memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3710 | |
Harry Wentland | b972b4f | 2020-10-02 13:32:00 -0400 | [diff] [blame] | 3711 | if (adev->dm.disable_hpd_irq) |
| 3712 | return; |
| 3713 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 3714 | /* |
| 3715 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3716 | * conflict, after implement i2c helper, this mutex should be |
| 3717 | * retired. |
| 3718 | */ |
Nikola Cornij | b86e7ee | 2021-04-30 19:34:29 -0400 | [diff] [blame] | 3719 | mutex_lock(&aconnector->hpd_lock); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3720 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 3721 | result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, |
| 3722 | &link_loss, true, &has_left_work); |
Qingqing Zhuo | 3083a98 | 2020-11-23 17:56:35 -0500 | [diff] [blame] | 3723 | |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 3724 | if (!has_left_work) |
| 3725 | goto out; |
| 3726 | |
| 3727 | if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
| 3728 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); |
| 3729 | goto out; |
| 3730 | } |
| 3731 | |
| 3732 | if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
| 3733 | if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || |
| 3734 | hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { |
Wayne Lin | bb4fa52 | 2022-03-09 17:05:05 +0800 | [diff] [blame] | 3735 | bool skip = false; |
| 3736 | |
| 3737 | /* |
| 3738 | * DOWN_REP_MSG_RDY is also handled by polling method |
| 3739 | * mgr->cbs->poll_hpd_irq() |
| 3740 | */ |
| 3741 | spin_lock(&offload_wq->offload_lock); |
| 3742 | skip = offload_wq->is_handling_mst_msg_rdy_event; |
| 3743 | |
| 3744 | if (!skip) |
| 3745 | offload_wq->is_handling_mst_msg_rdy_event = true; |
| 3746 | |
| 3747 | spin_unlock(&offload_wq->offload_lock); |
| 3748 | |
| 3749 | if (!skip) |
| 3750 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); |
| 3751 | |
Qingqing Zhuo | 3083a98 | 2020-11-23 17:56:35 -0500 | [diff] [blame] | 3752 | goto out; |
Wayne Lin | 8e79442 | 2021-07-23 11:50:28 +0800 | [diff] [blame] | 3753 | } |
| 3754 | |
| 3755 | if (link_loss) { |
| 3756 | bool skip = false; |
| 3757 | |
| 3758 | spin_lock(&offload_wq->offload_lock); |
| 3759 | skip = offload_wq->is_handling_link_loss; |
| 3760 | |
| 3761 | if (!skip) |
| 3762 | offload_wq->is_handling_link_loss = true; |
| 3763 | |
| 3764 | spin_unlock(&offload_wq->offload_lock); |
| 3765 | |
| 3766 | if (!skip) |
| 3767 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); |
| 3768 | |
Qingqing Zhuo | 3083a98 | 2020-11-23 17:56:35 -0500 | [diff] [blame] | 3769 | goto out; |
| 3770 | } |
| 3771 | } |
| 3772 | |
Qingqing Zhuo | 3083a98 | 2020-11-23 17:56:35 -0500 | [diff] [blame] | 3773 | out: |
Qingqing Zhuo | c8ea79a | 2020-10-01 15:56:28 -0400 | [diff] [blame] | 3774 | if (result && !is_mst_root_connector) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3775 | /* Downstream Port status changed. */ |
Wenjing Liu | 5461888 | 2023-01-18 17:31:24 -0500 | [diff] [blame] | 3776 | if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 3777 | DRM_ERROR("KMS: Failed to detect connector\n"); |
| 3778 | |
| 3779 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
| 3780 | emulated_link_detect(dc_link); |
| 3781 | |
| 3782 | if (aconnector->fake_enable) |
| 3783 | aconnector->fake_enable = false; |
| 3784 | |
| 3785 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 3786 | |
| 3787 | |
| 3788 | drm_modeset_lock_all(dev); |
| 3789 | dm_restore_drm_connector_state(dev, connector); |
| 3790 | drm_modeset_unlock_all(dev); |
| 3791 | |
Simon Ser | fc320a6 | 2021-10-18 08:47:28 +0000 | [diff] [blame] | 3792 | drm_kms_helper_connector_hotplug_event(connector); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3793 | } else { |
| 3794 | bool ret = false; |
Roman Li | 88ac3dd | 2018-02-09 16:57:38 -0500 | [diff] [blame] | 3795 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3796 | mutex_lock(&adev->dm.dc_lock); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 3797 | dc_exit_ips_for_hw_access(dc); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3798 | ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); |
| 3799 | mutex_unlock(&adev->dm.dc_lock); |
Roman Li | 88ac3dd | 2018-02-09 16:57:38 -0500 | [diff] [blame] | 3800 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3801 | if (ret) { |
| 3802 | if (aconnector->fake_enable) |
| 3803 | aconnector->fake_enable = false; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3804 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3805 | amdgpu_dm_update_connector_after_detect(aconnector); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3806 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3807 | drm_modeset_lock_all(dev); |
| 3808 | dm_restore_drm_connector_state(dev, connector); |
| 3809 | drm_modeset_unlock_all(dev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3810 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 3811 | drm_kms_helper_connector_hotplug_event(connector); |
| 3812 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3813 | } |
| 3814 | } |
Dan Carpenter | 95f247e | 2020-02-24 13:31:20 +0300 | [diff] [blame] | 3815 | if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { |
| 3816 | if (adev->dm.hdcp_workqueue) |
| 3817 | hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); |
| 3818 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3819 | |
Nikola Cornij | b86e7ee | 2021-04-30 19:34:29 -0400 | [diff] [blame] | 3820 | if (dc_link->type != dc_connection_mst_branch) |
Hans Verkuil | e86e894 | 2018-08-27 10:08:18 +0200 | [diff] [blame] | 3821 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); |
Nikola Cornij | b86e7ee | 2021-04-30 19:34:29 -0400 | [diff] [blame] | 3822 | |
| 3823 | mutex_unlock(&aconnector->hpd_lock); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3824 | } |
| 3825 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3826 | static int register_hpd_handlers(struct amdgpu_device *adev) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3827 | { |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 3828 | struct drm_device *dev = adev_to_drm(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3829 | struct drm_connector *connector; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 3830 | struct amdgpu_dm_connector *aconnector; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3831 | const struct dc_link *dc_link; |
| 3832 | struct dc_interrupt_params int_params = {0}; |
| 3833 | |
| 3834 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3835 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3836 | |
Wayne Lin | 22e1dc4 | 2024-02-02 17:34:11 +0800 | [diff] [blame] | 3837 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3838 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, |
| 3839 | dmub_hpd_callback, true)) { |
Wayne Lin | 22e1dc4 | 2024-02-02 17:34:11 +0800 | [diff] [blame] | 3840 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3841 | return -EINVAL; |
| 3842 | } |
Wayne Lin | 22e1dc4 | 2024-02-02 17:34:11 +0800 | [diff] [blame] | 3843 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3844 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, |
| 3845 | dmub_hpd_callback, true)) { |
Wayne Lin | 22e1dc4 | 2024-02-02 17:34:11 +0800 | [diff] [blame] | 3846 | DRM_ERROR("amdgpu: fail to register dmub hpd callback"); |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3847 | return -EINVAL; |
| 3848 | } |
Roman Li | 5a3d3e1 | 2024-08-21 10:53:15 -0400 | [diff] [blame] | 3849 | |
| 3850 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_SENSE_NOTIFY, |
| 3851 | dmub_hpd_sense_callback, true)) { |
| 3852 | DRM_ERROR("amdgpu: fail to register dmub hpd sense callback"); |
| 3853 | return -EINVAL; |
| 3854 | } |
Wayne Lin | 22e1dc4 | 2024-02-02 17:34:11 +0800 | [diff] [blame] | 3855 | } |
| 3856 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3857 | list_for_each_entry(connector, |
| 3858 | &dev->mode_config.connector_list, head) { |
| 3859 | |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 3860 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 3861 | continue; |
| 3862 | |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 3863 | aconnector = to_amdgpu_dm_connector(connector); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3864 | dc_link = aconnector->dc_link; |
| 3865 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3866 | if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3867 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
| 3868 | int_params.irq_source = dc_link->irq_source_hpd; |
| 3869 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3870 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 3871 | int_params.irq_source < DC_IRQ_SOURCE_HPD1 || |
| 3872 | int_params.irq_source > DC_IRQ_SOURCE_HPD6) { |
| 3873 | DRM_ERROR("Failed to register hpd irq!\n"); |
| 3874 | return -EINVAL; |
| 3875 | } |
| 3876 | |
| 3877 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3878 | handle_hpd_irq, (void *) aconnector)) |
| 3879 | return -ENOMEM; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3880 | } |
| 3881 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3882 | if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3883 | |
| 3884 | /* Also register for DP short pulse (hpd_rx). */ |
| 3885 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
| 3886 | int_params.irq_source = dc_link->irq_source_hpd_rx; |
| 3887 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3888 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 3889 | int_params.irq_source < DC_IRQ_SOURCE_HPD1RX || |
| 3890 | int_params.irq_source > DC_IRQ_SOURCE_HPD6RX) { |
| 3891 | DRM_ERROR("Failed to register hpd rx irq!\n"); |
| 3892 | return -EINVAL; |
| 3893 | } |
| 3894 | |
| 3895 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3896 | handle_hpd_rx_irq, (void *) aconnector)) |
| 3897 | return -ENOMEM; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3898 | } |
| 3899 | } |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3900 | return 0; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 3901 | } |
| 3902 | |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3903 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 3904 | /* Register IRQ sources and initialize IRQ callbacks */ |
| 3905 | static int dce60_register_irq_handlers(struct amdgpu_device *adev) |
| 3906 | { |
| 3907 | struct dc *dc = adev->dm.dc; |
| 3908 | struct common_irq_params *c_irq_params; |
| 3909 | struct dc_interrupt_params int_params = {0}; |
| 3910 | int r; |
| 3911 | int i; |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3912 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3913 | |
| 3914 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3915 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3916 | |
| 3917 | /* |
| 3918 | * Actions of amdgpu_irq_add_id(): |
| 3919 | * 1. Register a set() function with base driver. |
| 3920 | * Base driver will call set() function to enable/disable an |
| 3921 | * interrupt in DC hardware. |
| 3922 | * 2. Register amdgpu_dm_irq_handler(). |
| 3923 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts |
| 3924 | * coming from DC hardware. |
| 3925 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3926 | * for acknowledging and handling. |
| 3927 | */ |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3928 | |
| 3929 | /* Use VBLANK interrupt */ |
| 3930 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3931 | r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3932 | if (r) { |
| 3933 | DRM_ERROR("Failed to add crtc irq id!\n"); |
| 3934 | return r; |
| 3935 | } |
| 3936 | |
| 3937 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3938 | int_params.irq_source = |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 3939 | dc_interrupt_to_irq_source(dc, i + 1, 0); |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3940 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3941 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 3942 | int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || |
| 3943 | int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { |
| 3944 | DRM_ERROR("Failed to register vblank irq!\n"); |
| 3945 | return -EINVAL; |
| 3946 | } |
| 3947 | |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3948 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
| 3949 | |
| 3950 | c_irq_params->adev = adev; |
| 3951 | c_irq_params->irq_src = int_params.irq_source; |
| 3952 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3953 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3954 | dm_crtc_high_irq, c_irq_params)) |
| 3955 | return -ENOMEM; |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3956 | } |
| 3957 | |
| 3958 | /* Use GRPH_PFLIP interrupt */ |
| 3959 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
| 3960 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { |
| 3961 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
| 3962 | if (r) { |
| 3963 | DRM_ERROR("Failed to add page flip irq id!\n"); |
| 3964 | return r; |
| 3965 | } |
| 3966 | |
| 3967 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3968 | int_params.irq_source = |
| 3969 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3970 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3971 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 3972 | int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || |
| 3973 | int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { |
| 3974 | DRM_ERROR("Failed to register pflip irq!\n"); |
| 3975 | return -EINVAL; |
| 3976 | } |
| 3977 | |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3978 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; |
| 3979 | |
| 3980 | c_irq_params->adev = adev; |
| 3981 | c_irq_params->irq_src = int_params.irq_source; |
| 3982 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3983 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3984 | dm_pflip_high_irq, c_irq_params)) |
| 3985 | return -ENOMEM; |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3986 | } |
| 3987 | |
| 3988 | /* HPD */ |
| 3989 | r = amdgpu_irq_add_id(adev, client_id, |
| 3990 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); |
| 3991 | if (r) { |
| 3992 | DRM_ERROR("Failed to add hpd irq id!\n"); |
| 3993 | return r; |
| 3994 | } |
| 3995 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3996 | r = register_hpd_handlers(adev); |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3997 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 3998 | return r; |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 3999 | } |
| 4000 | #endif |
| 4001 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4002 | /* Register IRQ sources and initialize IRQ callbacks */ |
| 4003 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) |
| 4004 | { |
| 4005 | struct dc *dc = adev->dm.dc; |
| 4006 | struct common_irq_params *c_irq_params; |
| 4007 | struct dc_interrupt_params int_params = {0}; |
| 4008 | int r; |
| 4009 | int i; |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 4010 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
Alex Deucher | 2c8ad2d | 2017-06-15 16:20:24 -0400 | [diff] [blame] | 4011 | |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 4012 | if (adev->family >= AMDGPU_FAMILY_AI) |
Oak Zeng | 3760f76 | 2018-03-08 16:44:47 -0500 | [diff] [blame] | 4013 | client_id = SOC15_IH_CLIENTID_DCE; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4014 | |
| 4015 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 4016 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 4017 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 4018 | /* |
| 4019 | * Actions of amdgpu_irq_add_id(): |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4020 | * 1. Register a set() function with base driver. |
| 4021 | * Base driver will call set() function to enable/disable an |
| 4022 | * interrupt in DC hardware. |
| 4023 | * 2. Register amdgpu_dm_irq_handler(). |
| 4024 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts |
| 4025 | * coming from DC hardware. |
| 4026 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 4027 | * for acknowledging and handling. |
| 4028 | */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4029 | |
Andrey Grodzovsky | b57de80 | 2017-04-19 13:29:11 -0400 | [diff] [blame] | 4030 | /* Use VBLANK interrupt */ |
Andrey Grodzovsky | e902915 | 2017-03-23 15:30:35 -0400 | [diff] [blame] | 4031 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { |
Alex Deucher | 2c8ad2d | 2017-06-15 16:20:24 -0400 | [diff] [blame] | 4032 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4033 | if (r) { |
| 4034 | DRM_ERROR("Failed to add crtc irq id!\n"); |
| 4035 | return r; |
| 4036 | } |
| 4037 | |
| 4038 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 4039 | int_params.irq_source = |
Andrey Grodzovsky | 3d761e7 | 2017-04-19 13:55:35 -0400 | [diff] [blame] | 4040 | dc_interrupt_to_irq_source(dc, i, 0); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4041 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4042 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 4043 | int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || |
| 4044 | int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { |
| 4045 | DRM_ERROR("Failed to register vblank irq!\n"); |
| 4046 | return -EINVAL; |
| 4047 | } |
| 4048 | |
Andrey Grodzovsky | b57de80 | 2017-04-19 13:29:11 -0400 | [diff] [blame] | 4049 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4050 | |
| 4051 | c_irq_params->adev = adev; |
| 4052 | c_irq_params->irq_src = int_params.irq_source; |
| 4053 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4054 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4055 | dm_crtc_high_irq, c_irq_params)) |
| 4056 | return -ENOMEM; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4057 | } |
| 4058 | |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 4059 | /* Use VUPDATE interrupt */ |
| 4060 | for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { |
| 4061 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); |
| 4062 | if (r) { |
| 4063 | DRM_ERROR("Failed to add vupdate irq id!\n"); |
| 4064 | return r; |
| 4065 | } |
| 4066 | |
| 4067 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 4068 | int_params.irq_source = |
| 4069 | dc_interrupt_to_irq_source(dc, i, 0); |
| 4070 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4071 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 4072 | int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || |
| 4073 | int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { |
| 4074 | DRM_ERROR("Failed to register vupdate irq!\n"); |
| 4075 | return -EINVAL; |
| 4076 | } |
| 4077 | |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 4078 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; |
| 4079 | |
| 4080 | c_irq_params->adev = adev; |
| 4081 | c_irq_params->irq_src = int_params.irq_source; |
| 4082 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4083 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4084 | dm_vupdate_high_irq, c_irq_params)) |
| 4085 | return -ENOMEM; |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 4086 | } |
| 4087 | |
Andrey Grodzovsky | 3d761e7 | 2017-04-19 13:55:35 -0400 | [diff] [blame] | 4088 | /* Use GRPH_PFLIP interrupt */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4089 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
| 4090 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { |
Alex Deucher | 2c8ad2d | 2017-06-15 16:20:24 -0400 | [diff] [blame] | 4091 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4092 | if (r) { |
| 4093 | DRM_ERROR("Failed to add page flip irq id!\n"); |
| 4094 | return r; |
| 4095 | } |
| 4096 | |
| 4097 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 4098 | int_params.irq_source = |
| 4099 | dc_interrupt_to_irq_source(dc, i, 0); |
| 4100 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4101 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 4102 | int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || |
| 4103 | int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { |
| 4104 | DRM_ERROR("Failed to register pflip irq!\n"); |
| 4105 | return -EINVAL; |
| 4106 | } |
| 4107 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4108 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; |
| 4109 | |
| 4110 | c_irq_params->adev = adev; |
| 4111 | c_irq_params->irq_src = int_params.irq_source; |
| 4112 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4113 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4114 | dm_pflip_high_irq, c_irq_params)) |
| 4115 | return -ENOMEM; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4116 | } |
| 4117 | |
| 4118 | /* HPD */ |
Alex Deucher | 2c8ad2d | 2017-06-15 16:20:24 -0400 | [diff] [blame] | 4119 | r = amdgpu_irq_add_id(adev, client_id, |
| 4120 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4121 | if (r) { |
| 4122 | DRM_ERROR("Failed to add hpd irq id!\n"); |
| 4123 | return r; |
| 4124 | } |
| 4125 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4126 | r = register_hpd_handlers(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4127 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4128 | return r; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4129 | } |
| 4130 | |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4131 | /* Register IRQ sources and initialize IRQ callbacks */ |
| 4132 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) |
| 4133 | { |
| 4134 | struct dc *dc = adev->dm.dc; |
| 4135 | struct common_irq_params *c_irq_params; |
| 4136 | struct dc_interrupt_params int_params = {0}; |
| 4137 | int r; |
| 4138 | int i; |
Wayne Lin | 660d540 | 2021-03-10 13:53:24 +0800 | [diff] [blame] | 4139 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 4140 | static const unsigned int vrtl_int_srcid[] = { |
| 4141 | DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, |
| 4142 | DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, |
| 4143 | DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, |
| 4144 | DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, |
| 4145 | DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, |
| 4146 | DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL |
| 4147 | }; |
| 4148 | #endif |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4149 | |
| 4150 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 4151 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 4152 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 4153 | /* |
| 4154 | * Actions of amdgpu_irq_add_id(): |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4155 | * 1. Register a set() function with base driver. |
| 4156 | * Base driver will call set() function to enable/disable an |
| 4157 | * interrupt in DC hardware. |
| 4158 | * 2. Register amdgpu_dm_irq_handler(). |
| 4159 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts |
| 4160 | * coming from DC hardware. |
| 4161 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC |
| 4162 | * for acknowledging and handling. |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 4163 | */ |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4164 | |
| 4165 | /* Use VSTARTUP interrupt */ |
| 4166 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; |
| 4167 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; |
| 4168 | i++) { |
Oak Zeng | 3760f76 | 2018-03-08 16:44:47 -0500 | [diff] [blame] | 4169 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4170 | |
| 4171 | if (r) { |
| 4172 | DRM_ERROR("Failed to add crtc irq id!\n"); |
| 4173 | return r; |
| 4174 | } |
| 4175 | |
| 4176 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 4177 | int_params.irq_source = |
| 4178 | dc_interrupt_to_irq_source(dc, i, 0); |
| 4179 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4180 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 4181 | int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || |
| 4182 | int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { |
| 4183 | DRM_ERROR("Failed to register vblank irq!\n"); |
| 4184 | return -EINVAL; |
| 4185 | } |
| 4186 | |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4187 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
| 4188 | |
| 4189 | c_irq_params->adev = adev; |
| 4190 | c_irq_params->irq_src = int_params.irq_source; |
| 4191 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4192 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4193 | dm_crtc_high_irq, c_irq_params)) |
| 4194 | return -ENOMEM; |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 4195 | } |
| 4196 | |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 4197 | /* Use otg vertical line interrupt */ |
| 4198 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
Wayne Lin | 660d540 | 2021-03-10 13:53:24 +0800 | [diff] [blame] | 4199 | for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { |
| 4200 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, |
| 4201 | vrtl_int_srcid[i], &adev->vline0_irq); |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 4202 | |
| 4203 | if (r) { |
| 4204 | DRM_ERROR("Failed to add vline0 irq id!\n"); |
| 4205 | return r; |
| 4206 | } |
| 4207 | |
| 4208 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 4209 | int_params.irq_source = |
Wayne Lin | 660d540 | 2021-03-10 13:53:24 +0800 | [diff] [blame] | 4210 | dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); |
| 4211 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4212 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 4213 | int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 || |
| 4214 | int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) { |
| 4215 | DRM_ERROR("Failed to register vline0 irq!\n"); |
| 4216 | return -EINVAL; |
Wayne Lin | 660d540 | 2021-03-10 13:53:24 +0800 | [diff] [blame] | 4217 | } |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 4218 | |
| 4219 | c_irq_params = &adev->dm.vline0_params[int_params.irq_source |
| 4220 | - DC_IRQ_SOURCE_DC1_VLINE0]; |
| 4221 | |
| 4222 | c_irq_params->adev = adev; |
| 4223 | c_irq_params->irq_src = int_params.irq_source; |
| 4224 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4225 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4226 | dm_dcn_vertical_interrupt0_high_irq, |
| 4227 | c_irq_params)) |
| 4228 | return -ENOMEM; |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 4229 | } |
| 4230 | #endif |
| 4231 | |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 4232 | /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to |
| 4233 | * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx |
| 4234 | * to trigger at end of each vblank, regardless of state of the lock, |
| 4235 | * matching DCE behaviour. |
| 4236 | */ |
| 4237 | for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; |
| 4238 | i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; |
| 4239 | i++) { |
| 4240 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); |
| 4241 | |
| 4242 | if (r) { |
| 4243 | DRM_ERROR("Failed to add vupdate irq id!\n"); |
| 4244 | return r; |
| 4245 | } |
| 4246 | |
| 4247 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 4248 | int_params.irq_source = |
| 4249 | dc_interrupt_to_irq_source(dc, i, 0); |
| 4250 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4251 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 4252 | int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || |
| 4253 | int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { |
| 4254 | DRM_ERROR("Failed to register vupdate irq!\n"); |
| 4255 | return -EINVAL; |
| 4256 | } |
| 4257 | |
Nicholas Kazlauskas | 2346ef4 | 2020-05-06 15:47:54 -0400 | [diff] [blame] | 4258 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; |
| 4259 | |
| 4260 | c_irq_params->adev = adev; |
| 4261 | c_irq_params->irq_src = int_params.irq_source; |
| 4262 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4263 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4264 | dm_vupdate_high_irq, c_irq_params)) |
| 4265 | return -ENOMEM; |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 4266 | } |
| 4267 | |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4268 | /* Use GRPH_PFLIP interrupt */ |
| 4269 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; |
Roman Li | de95753 | 2022-02-02 14:30:09 -0500 | [diff] [blame] | 4270 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4271 | i++) { |
Oak Zeng | 3760f76 | 2018-03-08 16:44:47 -0500 | [diff] [blame] | 4272 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4273 | if (r) { |
| 4274 | DRM_ERROR("Failed to add page flip irq id!\n"); |
| 4275 | return r; |
| 4276 | } |
| 4277 | |
| 4278 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 4279 | int_params.irq_source = |
| 4280 | dc_interrupt_to_irq_source(dc, i, 0); |
| 4281 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4282 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || |
| 4283 | int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || |
| 4284 | int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { |
| 4285 | DRM_ERROR("Failed to register pflip irq!\n"); |
| 4286 | return -EINVAL; |
| 4287 | } |
| 4288 | |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4289 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; |
| 4290 | |
| 4291 | c_irq_params->adev = adev; |
| 4292 | c_irq_params->irq_src = int_params.irq_source; |
| 4293 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4294 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4295 | dm_pflip_high_irq, c_irq_params)) |
| 4296 | return -ENOMEM; |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4297 | } |
| 4298 | |
| 4299 | /* HPD */ |
Oak Zeng | 3760f76 | 2018-03-08 16:44:47 -0500 | [diff] [blame] | 4300 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4301 | &adev->hpd_irq); |
| 4302 | if (r) { |
| 4303 | DRM_ERROR("Failed to add hpd irq id!\n"); |
| 4304 | return r; |
| 4305 | } |
| 4306 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4307 | r = register_hpd_handlers(adev); |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4308 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4309 | return r; |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4310 | } |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 4311 | /* Register Outbox IRQ sources and initialize IRQ callbacks */ |
| 4312 | static int register_outbox_irq_handlers(struct amdgpu_device *adev) |
| 4313 | { |
| 4314 | struct dc *dc = adev->dm.dc; |
| 4315 | struct common_irq_params *c_irq_params; |
| 4316 | struct dc_interrupt_params int_params = {0}; |
| 4317 | int r, i; |
| 4318 | |
| 4319 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 4320 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 4321 | |
| 4322 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, |
| 4323 | &adev->dmub_outbox_irq); |
| 4324 | if (r) { |
| 4325 | DRM_ERROR("Failed to add outbox irq id!\n"); |
| 4326 | return r; |
| 4327 | } |
| 4328 | |
| 4329 | if (dc->ctx->dmub_srv) { |
| 4330 | i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; |
| 4331 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
| 4332 | int_params.irq_source = |
| 4333 | dc_interrupt_to_irq_source(dc, i, 0); |
| 4334 | |
| 4335 | c_irq_params = &adev->dm.dmub_outbox_params[0]; |
| 4336 | |
| 4337 | c_irq_params->adev = adev; |
| 4338 | c_irq_params->irq_src = int_params.irq_source; |
| 4339 | |
Hersen Wu | 6e41709 | 2024-04-23 19:14:16 -0400 | [diff] [blame] | 4340 | if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 4341 | dm_dmub_outbox1_low_irq, c_irq_params)) |
| 4342 | return -ENOMEM; |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 4343 | } |
| 4344 | |
| 4345 | return 0; |
| 4346 | } |
Alex Deucher | ff5ef99 | 2017-06-15 16:27:42 -0400 | [diff] [blame] | 4347 | |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4348 | /* |
| 4349 | * Acquires the lock for the atomic state object and returns |
| 4350 | * the new atomic state. |
| 4351 | * |
| 4352 | * This should only be called during atomic check. |
| 4353 | */ |
Roman Li | 17ce8a6 | 2022-01-28 12:29:01 -0500 | [diff] [blame] | 4354 | int dm_atomic_get_state(struct drm_atomic_state *state, |
| 4355 | struct dm_atomic_state **dm_state) |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4356 | { |
| 4357 | struct drm_device *dev = state->dev; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 4358 | struct amdgpu_device *adev = drm_to_adev(dev); |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4359 | struct amdgpu_display_manager *dm = &adev->dm; |
| 4360 | struct drm_private_state *priv_state; |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4361 | |
| 4362 | if (*dm_state) |
| 4363 | return 0; |
| 4364 | |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4365 | priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); |
| 4366 | if (IS_ERR(priv_state)) |
| 4367 | return PTR_ERR(priv_state); |
| 4368 | |
| 4369 | *dm_state = to_dm_atomic_state(priv_state); |
| 4370 | |
| 4371 | return 0; |
| 4372 | } |
| 4373 | |
Nirmoy Das | dfd84d9 | 2020-06-18 15:07:13 +0200 | [diff] [blame] | 4374 | static struct dm_atomic_state * |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4375 | dm_atomic_get_new_state(struct drm_atomic_state *state) |
| 4376 | { |
| 4377 | struct drm_device *dev = state->dev; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 4378 | struct amdgpu_device *adev = drm_to_adev(dev); |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4379 | struct amdgpu_display_manager *dm = &adev->dm; |
| 4380 | struct drm_private_obj *obj; |
| 4381 | struct drm_private_state *new_obj_state; |
| 4382 | int i; |
| 4383 | |
| 4384 | for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { |
| 4385 | if (obj->funcs == dm->atomic_obj.funcs) |
| 4386 | return to_dm_atomic_state(new_obj_state); |
| 4387 | } |
| 4388 | |
| 4389 | return NULL; |
| 4390 | } |
| 4391 | |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4392 | static struct drm_private_state * |
| 4393 | dm_atomic_duplicate_state(struct drm_private_obj *obj) |
| 4394 | { |
| 4395 | struct dm_atomic_state *old_state, *new_state; |
| 4396 | |
| 4397 | new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); |
| 4398 | if (!new_state) |
| 4399 | return NULL; |
| 4400 | |
| 4401 | __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); |
| 4402 | |
Aidan Wood | 813d20d | 2019-02-22 13:37:03 -0500 | [diff] [blame] | 4403 | old_state = to_dm_atomic_state(obj->state); |
| 4404 | |
| 4405 | if (old_state && old_state->context) |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 4406 | new_state->context = dc_state_create_copy(old_state->context); |
Aidan Wood | 813d20d | 2019-02-22 13:37:03 -0500 | [diff] [blame] | 4407 | |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4408 | if (!new_state->context) { |
| 4409 | kfree(new_state); |
| 4410 | return NULL; |
| 4411 | } |
| 4412 | |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4413 | return &new_state->base; |
| 4414 | } |
| 4415 | |
| 4416 | static void dm_atomic_destroy_state(struct drm_private_obj *obj, |
| 4417 | struct drm_private_state *state) |
| 4418 | { |
| 4419 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); |
| 4420 | |
| 4421 | if (dm_state && dm_state->context) |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 4422 | dc_state_release(dm_state->context); |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4423 | |
| 4424 | kfree(dm_state); |
| 4425 | } |
| 4426 | |
| 4427 | static struct drm_private_state_funcs dm_atomic_state_funcs = { |
| 4428 | .atomic_duplicate_state = dm_atomic_duplicate_state, |
| 4429 | .atomic_destroy_state = dm_atomic_destroy_state, |
| 4430 | }; |
| 4431 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4432 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
| 4433 | { |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4434 | struct dm_atomic_state *state; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4435 | int r; |
| 4436 | |
| 4437 | adev->mode_info.mode_config_initialized = true; |
| 4438 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 4439 | adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
| 4440 | adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4441 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 4442 | adev_to_drm(adev)->mode_config.max_width = 16384; |
| 4443 | adev_to_drm(adev)->mode_config.max_height = 16384; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4444 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 4445 | adev_to_drm(adev)->mode_config.preferred_depth = 24; |
Alex Deucher | a6250bd | 2022-08-09 11:44:05 -0400 | [diff] [blame] | 4446 | if (adev->asic_type == CHIP_HAWAII) |
| 4447 | /* disable prefer shadow for now due to hibernation issues */ |
| 4448 | adev_to_drm(adev)->mode_config.prefer_shadow = 0; |
| 4449 | else |
| 4450 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 4451 | /* indicates support for immediate flip */ |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 4452 | adev_to_drm(adev)->mode_config.async_page_flip = true; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4453 | |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4454 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
| 4455 | if (!state) |
| 4456 | return -ENOMEM; |
| 4457 | |
Dillon Varone | 012a04b | 2023-11-21 15:07:01 -0500 | [diff] [blame] | 4458 | state->context = dc_state_create_current_copy(adev->dm.dc); |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4459 | if (!state->context) { |
| 4460 | kfree(state); |
| 4461 | return -ENOMEM; |
| 4462 | } |
| 4463 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 4464 | drm_atomic_private_obj_init(adev_to_drm(adev), |
Dave Airlie | 8c1a765 | 2019-01-10 05:53:51 +1000 | [diff] [blame] | 4465 | &adev->dm.atomic_obj, |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 4466 | &state->base, |
| 4467 | &dm_atomic_state_funcs); |
| 4468 | |
Samuel Li | 3dc9b1c | 2018-01-19 12:47:40 -0500 | [diff] [blame] | 4469 | r = amdgpu_display_modeset_create_props(adev); |
Dinghao Liu | b67a468 | 2020-08-26 21:24:58 +0800 | [diff] [blame] | 4470 | if (r) { |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 4471 | dc_state_release(state->context); |
Dinghao Liu | b67a468 | 2020-08-26 21:24:58 +0800 | [diff] [blame] | 4472 | kfree(state); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4473 | return r; |
Dinghao Liu | b67a468 | 2020-08-26 21:24:58 +0800 | [diff] [blame] | 4474 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4475 | |
Melissa Wen | 9342a9a | 2023-11-16 18:57:44 -0100 | [diff] [blame] | 4476 | #ifdef AMD_PRIVATE_COLOR |
Hersen Wu | 52cbcf9 | 2024-04-24 20:32:53 -0400 | [diff] [blame] | 4477 | if (amdgpu_dm_create_color_properties(adev)) { |
| 4478 | dc_state_release(state->context); |
| 4479 | kfree(state); |
Melissa Wen | 9342a9a | 2023-11-16 18:57:44 -0100 | [diff] [blame] | 4480 | return -ENOMEM; |
Hersen Wu | 52cbcf9 | 2024-04-24 20:32:53 -0400 | [diff] [blame] | 4481 | } |
Melissa Wen | 9342a9a | 2023-11-16 18:57:44 -0100 | [diff] [blame] | 4482 | #endif |
| 4483 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 4484 | r = amdgpu_dm_audio_init(adev); |
Dinghao Liu | b67a468 | 2020-08-26 21:24:58 +0800 | [diff] [blame] | 4485 | if (r) { |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 4486 | dc_state_release(state->context); |
Dinghao Liu | b67a468 | 2020-08-26 21:24:58 +0800 | [diff] [blame] | 4487 | kfree(state); |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 4488 | return r; |
Dinghao Liu | b67a468 | 2020-08-26 21:24:58 +0800 | [diff] [blame] | 4489 | } |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 4490 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4491 | return 0; |
| 4492 | } |
| 4493 | |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4494 | #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 |
| 4495 | #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 |
Mario Limonciello | 327e62f | 2024-09-13 13:00:39 -0500 | [diff] [blame] | 4496 | #define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2) |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4497 | #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4498 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4499 | static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, |
| 4500 | int bl_idx) |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4501 | { |
| 4502 | #if defined(CONFIG_ACPI) |
| 4503 | struct amdgpu_dm_backlight_caps caps; |
| 4504 | |
Furquan Shaikh | 5896585 | 2020-08-20 00:52:41 -0700 | [diff] [blame] | 4505 | memset(&caps, 0, sizeof(caps)); |
| 4506 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4507 | if (dm->backlight_caps[bl_idx].caps_valid) |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4508 | return; |
| 4509 | |
Alex Deucher | f9b7f37 | 2021-05-25 17:40:58 -0400 | [diff] [blame] | 4510 | amdgpu_acpi_get_backlight_caps(&caps); |
Mario Limonciello | 327e62f | 2024-09-13 13:00:39 -0500 | [diff] [blame] | 4511 | |
| 4512 | /* validate the firmware value is sane */ |
| 4513 | if (caps.caps_valid) { |
| 4514 | int spread = caps.max_input_signal - caps.min_input_signal; |
| 4515 | |
| 4516 | if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || |
Mario Limonciello | 87d749a | 2024-09-15 14:28:37 -0500 | [diff] [blame] | 4517 | caps.min_input_signal < 0 || |
Mario Limonciello | 327e62f | 2024-09-13 13:00:39 -0500 | [diff] [blame] | 4518 | spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || |
| 4519 | spread < AMDGPU_DM_MIN_SPREAD) { |
| 4520 | DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n", |
| 4521 | caps.min_input_signal, caps.max_input_signal); |
| 4522 | caps.caps_valid = false; |
| 4523 | } |
| 4524 | } |
| 4525 | |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4526 | if (caps.caps_valid) { |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4527 | dm->backlight_caps[bl_idx].caps_valid = true; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4528 | if (caps.aux_support) |
| 4529 | return; |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4530 | dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; |
| 4531 | dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4532 | } else { |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4533 | dm->backlight_caps[bl_idx].min_input_signal = |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4534 | AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4535 | dm->backlight_caps[bl_idx].max_input_signal = |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4536 | AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; |
| 4537 | } |
| 4538 | #else |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4539 | if (dm->backlight_caps[bl_idx].aux_support) |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4540 | return; |
| 4541 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4542 | dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
| 4543 | dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4544 | #endif |
| 4545 | } |
| 4546 | |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4547 | static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 4548 | unsigned int *min, unsigned int *max) |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4549 | { |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4550 | if (!caps) |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4551 | return 0; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4552 | |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4553 | if (caps->aux_support) { |
| 4554 | // Firmware limits are in nits, DC API wants millinits. |
| 4555 | *max = 1000 * caps->aux_max_input_signal; |
| 4556 | *min = 1000 * caps->aux_min_input_signal; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4557 | } else { |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4558 | // Firmware limits are 8-bit, PWM control is 16-bit. |
| 4559 | *max = 0x101 * caps->max_input_signal; |
| 4560 | *min = 0x101 * caps->min_input_signal; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4561 | } |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4562 | return 1; |
| 4563 | } |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4564 | |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4565 | static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, |
| 4566 | uint32_t brightness) |
| 4567 | { |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 4568 | unsigned int min, max; |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4569 | |
| 4570 | if (!get_brightness_range(caps, &min, &max)) |
| 4571 | return brightness; |
| 4572 | |
| 4573 | // Rescale 0..255 to min..max |
| 4574 | return min + DIV_ROUND_CLOSEST((max - min) * brightness, |
| 4575 | AMDGPU_MAX_BL_LEVEL); |
| 4576 | } |
| 4577 | |
| 4578 | static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, |
| 4579 | uint32_t brightness) |
| 4580 | { |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 4581 | unsigned int min, max; |
Alexander Monakov | 69d9f42 | 2020-08-04 23:13:13 +0300 | [diff] [blame] | 4582 | |
| 4583 | if (!get_brightness_range(caps, &min, &max)) |
| 4584 | return brightness; |
| 4585 | |
| 4586 | if (brightness < min) |
| 4587 | return 0; |
| 4588 | // Rescale min..max to 0..255 |
| 4589 | return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), |
| 4590 | max - min); |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4591 | } |
| 4592 | |
Shirish S | 4052287 | 2022-03-11 20:30:17 +0530 | [diff] [blame] | 4593 | static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4594 | int bl_idx, |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4595 | u32 user_brightness) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4596 | { |
David Francis | 206bbafe | 2018-11-26 11:44:06 -0500 | [diff] [blame] | 4597 | struct amdgpu_dm_backlight_caps caps; |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4598 | struct dc_link *link; |
| 4599 | u32 brightness; |
Leo Li | 988fe28 | 2024-08-20 14:34:15 -0400 | [diff] [blame] | 4600 | bool rc, reallow_idle = false; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4601 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4602 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
| 4603 | caps = dm->backlight_caps[bl_idx]; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4604 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4605 | dm->brightness[bl_idx] = user_brightness; |
Alex Deucher | 1f57925 | 2021-11-23 10:44:48 -0500 | [diff] [blame] | 4606 | /* update scratch register */ |
| 4607 | if (bl_idx == 0) |
| 4608 | amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4609 | brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); |
| 4610 | link = (struct dc_link *)dm->backlight_link[bl_idx]; |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4611 | |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4612 | /* Change brightness based on AUX property */ |
Leo Li | 988fe28 | 2024-08-20 14:34:15 -0400 | [diff] [blame] | 4613 | mutex_lock(&dm->dc_lock); |
| 4614 | if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) { |
| 4615 | dc_allow_idle_optimizations(dm->dc, false); |
| 4616 | reallow_idle = true; |
| 4617 | } |
| 4618 | |
Mikita Lipski | 118b462 | 2021-04-14 14:51:02 -0400 | [diff] [blame] | 4619 | if (caps.aux_support) { |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4620 | rc = dc_link_set_backlight_level_nits(link, true, brightness, |
| 4621 | AUX_BL_DEFAULT_TRANSITION_TIME_MS); |
| 4622 | if (!rc) |
| 4623 | DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); |
Mikita Lipski | 118b462 | 2021-04-14 14:51:02 -0400 | [diff] [blame] | 4624 | } else { |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4625 | rc = dc_link_set_backlight_level(link, brightness, 0); |
| 4626 | if (!rc) |
| 4627 | DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); |
Mikita Lipski | 118b462 | 2021-04-14 14:51:02 -0400 | [diff] [blame] | 4628 | } |
Rodrigo Siqueira | 9456281 | 2020-01-24 10:44:20 -0500 | [diff] [blame] | 4629 | |
Leo Li | 988fe28 | 2024-08-20 14:34:15 -0400 | [diff] [blame] | 4630 | if (dm->dc->caps.ips_support && reallow_idle) |
| 4631 | dc_allow_idle_optimizations(dm->dc, true); |
| 4632 | |
| 4633 | mutex_unlock(&dm->dc_lock); |
| 4634 | |
Shirish S | 4052287 | 2022-03-11 20:30:17 +0530 | [diff] [blame] | 4635 | if (rc) |
| 4636 | dm->actual_brightness[bl_idx] = user_brightness; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4637 | } |
| 4638 | |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4639 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4640 | { |
David Francis | 620a0d2 | 2018-07-19 11:25:05 -0400 | [diff] [blame] | 4641 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4642 | int i; |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4643 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4644 | for (i = 0; i < dm->num_of_edps; i++) { |
| 4645 | if (bd == dm->backlight_dev[i]) |
| 4646 | break; |
| 4647 | } |
| 4648 | if (i >= AMDGPU_DM_MAX_NUM_EDP) |
| 4649 | i = 0; |
| 4650 | amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4651 | |
| 4652 | return 0; |
| 4653 | } |
| 4654 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4655 | static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, |
| 4656 | int bl_idx) |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4657 | { |
Srinivasan Shanmugam | 53e1db0 | 2023-07-23 14:52:09 +0530 | [diff] [blame] | 4658 | int ret; |
Alex Deucher | 0ad3e64 | 2020-12-10 01:45:12 -0500 | [diff] [blame] | 4659 | struct amdgpu_dm_backlight_caps caps; |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4660 | struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; |
David Francis | 620a0d2 | 2018-07-19 11:25:05 -0400 | [diff] [blame] | 4661 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4662 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
| 4663 | caps = dm->backlight_caps[bl_idx]; |
Alex Deucher | 0ad3e64 | 2020-12-10 01:45:12 -0500 | [diff] [blame] | 4664 | |
| 4665 | if (caps.aux_support) { |
Alex Deucher | 0ad3e64 | 2020-12-10 01:45:12 -0500 | [diff] [blame] | 4666 | u32 avg, peak; |
| 4667 | bool rc; |
| 4668 | |
| 4669 | rc = dc_link_get_backlight_level_nits(link, &avg, &peak); |
| 4670 | if (!rc) |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4671 | return dm->brightness[bl_idx]; |
Alex Deucher | 0ad3e64 | 2020-12-10 01:45:12 -0500 | [diff] [blame] | 4672 | return convert_brightness_to_user(&caps, avg); |
Alex Deucher | 0ad3e64 | 2020-12-10 01:45:12 -0500 | [diff] [blame] | 4673 | } |
Srinivasan Shanmugam | 53e1db0 | 2023-07-23 14:52:09 +0530 | [diff] [blame] | 4674 | |
| 4675 | ret = dc_link_get_backlight_level(link); |
| 4676 | |
| 4677 | if (ret == DC_ERROR_UNEXPECTED) |
| 4678 | return dm->brightness[bl_idx]; |
| 4679 | |
| 4680 | return convert_brightness_to_user(&caps, ret); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4681 | } |
| 4682 | |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4683 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) |
| 4684 | { |
| 4685 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4686 | int i; |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4687 | |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 4688 | for (i = 0; i < dm->num_of_edps; i++) { |
| 4689 | if (bd == dm->backlight_dev[i]) |
| 4690 | break; |
| 4691 | } |
| 4692 | if (i >= AMDGPU_DM_MAX_NUM_EDP) |
| 4693 | i = 0; |
| 4694 | return amdgpu_dm_backlight_get_level(dm, i); |
Alex Deucher | 3d6c916 | 2021-05-11 11:37:09 -0400 | [diff] [blame] | 4695 | } |
| 4696 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4697 | static const struct backlight_ops amdgpu_dm_backlight_ops = { |
Kai-Heng Feng | bb26422 | 2019-09-02 16:33:42 +0800 | [diff] [blame] | 4698 | .options = BL_CORE_SUSPENDRESUME, |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4699 | .get_brightness = amdgpu_dm_backlight_get_brightness, |
| 4700 | .update_status = amdgpu_dm_backlight_update_status, |
| 4701 | }; |
| 4702 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 4703 | static void |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4704 | amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4705 | { |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4706 | struct drm_device *drm = aconnector->base.dev; |
| 4707 | struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4708 | struct backlight_properties props = { 0 }; |
Mario Limonciello | 2fe87f5 | 2024-06-07 01:02:28 -0500 | [diff] [blame] | 4709 | struct amdgpu_dm_backlight_caps caps = { 0 }; |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4710 | char bl_name[16]; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4711 | |
Hans de Goede | 62f03da | 2023-03-12 20:17:51 +0100 | [diff] [blame] | 4712 | if (aconnector->bl_idx == -1) |
| 4713 | return; |
| 4714 | |
Hans de Goede | da11ef8 | 2022-04-15 22:22:41 +0200 | [diff] [blame] | 4715 | if (!acpi_video_backlight_use_native()) { |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4716 | drm_info(drm, "Skipping amdgpu DM backlight registration\n"); |
Hans de Goede | c0f50c5 | 2022-05-16 11:32:33 +0200 | [diff] [blame] | 4717 | /* Try registering an ACPI video backlight device instead. */ |
| 4718 | acpi_video_register_backlight(); |
Hans de Goede | da11ef8 | 2022-04-15 22:22:41 +0200 | [diff] [blame] | 4719 | return; |
| 4720 | } |
| 4721 | |
Mario Limonciello | 2fe87f5 | 2024-06-07 01:02:28 -0500 | [diff] [blame] | 4722 | amdgpu_acpi_get_backlight_caps(&caps); |
| 4723 | if (caps.caps_valid) { |
| 4724 | if (power_supply_is_system_supplied() > 0) |
| 4725 | props.brightness = caps.ac_level; |
| 4726 | else |
| 4727 | props.brightness = caps.dc_level; |
| 4728 | } else |
| 4729 | props.brightness = AMDGPU_MAX_BL_LEVEL; |
| 4730 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4731 | props.max_brightness = AMDGPU_MAX_BL_LEVEL; |
| 4732 | props.type = BACKLIGHT_RAW; |
| 4733 | |
| 4734 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4735 | drm->primary->index + aconnector->bl_idx); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4736 | |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4737 | dm->backlight_dev[aconnector->bl_idx] = |
Hans de Goede | 62f03da | 2023-03-12 20:17:51 +0100 | [diff] [blame] | 4738 | backlight_device_register(bl_name, aconnector->base.kdev, dm, |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4739 | &amdgpu_dm_backlight_ops, &props); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4740 | |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4741 | if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4742 | DRM_ERROR("DM: Backlight registration failed!\n"); |
Hans de Goede | 213eca2 | 2023-03-12 20:17:50 +0100 | [diff] [blame] | 4743 | dm->backlight_dev[aconnector->bl_idx] = NULL; |
Hans de Goede | 4db231d | 2023-03-12 20:17:46 +0100 | [diff] [blame] | 4744 | } else |
Harry Wentland | f1ad2f5 | 2017-09-12 20:04:48 -0400 | [diff] [blame] | 4745 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4746 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4747 | |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4748 | static int initialize_plane(struct amdgpu_display_manager *dm, |
Nicholas Kazlauskas | b2fddb1 | 2019-01-18 13:42:34 -0500 | [diff] [blame] | 4749 | struct amdgpu_mode_info *mode_info, int plane_id, |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4750 | enum drm_plane_type plane_type, |
| 4751 | const struct dc_plane_cap *plane_cap) |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4752 | { |
Harry Wentland | f180b4b | 2018-10-05 11:58:34 -0400 | [diff] [blame] | 4753 | struct drm_plane *plane; |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4754 | unsigned long possible_crtcs; |
| 4755 | int ret = 0; |
| 4756 | |
Harry Wentland | f180b4b | 2018-10-05 11:58:34 -0400 | [diff] [blame] | 4757 | plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4758 | if (!plane) { |
| 4759 | DRM_ERROR("KMS: Failed to allocate plane\n"); |
| 4760 | return -ENOMEM; |
| 4761 | } |
Nicholas Kazlauskas | b2fddb1 | 2019-01-18 13:42:34 -0500 | [diff] [blame] | 4762 | plane->type = plane_type; |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4763 | |
| 4764 | /* |
Nicholas Kazlauskas | b2fddb1 | 2019-01-18 13:42:34 -0500 | [diff] [blame] | 4765 | * HACK: IGT tests expect that the primary plane for a CRTC |
| 4766 | * can only have one possible CRTC. Only expose support for |
| 4767 | * any CRTC if they're not going to be used as a primary plane |
| 4768 | * for a CRTC - like overlay or underlay planes. |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4769 | */ |
| 4770 | possible_crtcs = 1 << plane_id; |
| 4771 | if (plane_id >= dm->dc->caps.max_streams) |
| 4772 | possible_crtcs = 0xff; |
| 4773 | |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4774 | ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4775 | |
| 4776 | if (ret) { |
| 4777 | DRM_ERROR("KMS: Failed to initialize plane\n"); |
Nicholas Kazlauskas | 5408776 | 2019-03-14 12:53:12 -0400 | [diff] [blame] | 4778 | kfree(plane); |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4779 | return ret; |
| 4780 | } |
| 4781 | |
Nicholas Kazlauskas | 5408776 | 2019-03-14 12:53:12 -0400 | [diff] [blame] | 4782 | if (mode_info) |
| 4783 | mode_info->planes[plane_id] = plane; |
| 4784 | |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4785 | return ret; |
| 4786 | } |
| 4787 | |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 4788 | |
Hans de Goede | 618e51c | 2023-03-12 20:17:49 +0100 | [diff] [blame] | 4789 | static void setup_backlight_device(struct amdgpu_display_manager *dm, |
| 4790 | struct amdgpu_dm_connector *aconnector) |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 4791 | { |
Hans de Goede | f196198 | 2023-03-12 20:17:48 +0100 | [diff] [blame] | 4792 | struct dc_link *link = aconnector->dc_link; |
Hans de Goede | ceb4a56 | 2023-03-12 20:17:47 +0100 | [diff] [blame] | 4793 | int bl_idx = dm->num_of_edps; |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 4794 | |
Hans de Goede | ceb4a56 | 2023-03-12 20:17:47 +0100 | [diff] [blame] | 4795 | if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || |
| 4796 | link->type == dc_connection_none) |
| 4797 | return; |
| 4798 | |
| 4799 | if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { |
| 4800 | drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); |
| 4801 | return; |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 4802 | } |
Hans de Goede | ceb4a56 | 2023-03-12 20:17:47 +0100 | [diff] [blame] | 4803 | |
Hans de Goede | f196198 | 2023-03-12 20:17:48 +0100 | [diff] [blame] | 4804 | aconnector->bl_idx = bl_idx; |
| 4805 | |
Hans de Goede | 618e51c | 2023-03-12 20:17:49 +0100 | [diff] [blame] | 4806 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
| 4807 | dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; |
Hans de Goede | ceb4a56 | 2023-03-12 20:17:47 +0100 | [diff] [blame] | 4808 | dm->backlight_link[bl_idx] = link; |
| 4809 | dm->num_of_edps++; |
Hans de Goede | 618e51c | 2023-03-12 20:17:49 +0100 | [diff] [blame] | 4810 | |
| 4811 | update_connector_ext_caps(aconnector); |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 4812 | } |
| 4813 | |
Melissa Wen | acc96ae | 2022-08-04 15:13:49 -0100 | [diff] [blame] | 4814 | static void amdgpu_set_panel_orientation(struct drm_connector *connector); |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 4815 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 4816 | /* |
| 4817 | * In this architecture, the association |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4818 | * connector -> encoder -> crtc |
| 4819 | * id not really requried. The crtc and connector will hold the |
| 4820 | * display_index as an abstraction to use with DAL component |
| 4821 | * |
| 4822 | * Returns 0 on success |
| 4823 | */ |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 4824 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4825 | { |
| 4826 | struct amdgpu_display_manager *dm = &adev->dm; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 4827 | s32 i; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 4828 | struct amdgpu_dm_connector *aconnector = NULL; |
Harry Wentland | f2a0f5e | 2017-04-03 13:36:26 -0400 | [diff] [blame] | 4829 | struct amdgpu_encoder *aencoder = NULL; |
Alex Deucher | d4e13b0 | 2017-06-15 16:24:01 -0400 | [diff] [blame] | 4830 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 4831 | u32 link_cnt; |
| 4832 | s32 primary_planes; |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 4833 | enum dc_connection_type new_connection_type = dc_connection_none; |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4834 | const struct dc_plane_cap *plane; |
Nicholas Kazlauskas | 9470620 | 2021-10-05 10:55:57 -0400 | [diff] [blame] | 4835 | bool psr_feature_enabled = false; |
Tom Chung | 5950efe | 2023-12-06 22:07:51 +0800 | [diff] [blame] | 4836 | bool replay_feature_enabled = false; |
Bhawanpreet Lakha | 35f3308 | 2023-01-17 14:35:41 -0500 | [diff] [blame] | 4837 | int max_overlay = dm->dc->caps.max_slave_planes; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4838 | |
Alex Deucher | d58159d | 2020-12-03 16:06:26 -0500 | [diff] [blame] | 4839 | dm->display_indexes_num = dm->dc->caps.max_streams; |
| 4840 | /* Update the actual used number of crtc */ |
| 4841 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; |
| 4842 | |
tiancyin | 60971b2 | 2023-02-08 14:10:04 +0800 | [diff] [blame] | 4843 | amdgpu_dm_set_irq_funcs(adev); |
| 4844 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4845 | link_cnt = dm->dc->caps.max_links; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4846 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
| 4847 | DRM_ERROR("DM: Failed to initialize mode config\n"); |
Alex Deucher | 59d0f39 | 2018-09-13 11:01:28 -0500 | [diff] [blame] | 4848 | return -EINVAL; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4849 | } |
| 4850 | |
Nicholas Kazlauskas | b2fddb1 | 2019-01-18 13:42:34 -0500 | [diff] [blame] | 4851 | /* There is one primary plane per CRTC */ |
| 4852 | primary_planes = dm->dc->caps.max_streams; |
Hersen Wu | 84723eb | 2024-04-24 16:00:19 -0400 | [diff] [blame] | 4853 | if (primary_planes > AMDGPU_MAX_PLANES) { |
| 4854 | DRM_ERROR("DM: Plane nums out of 6 planes\n"); |
| 4855 | return -EINVAL; |
| 4856 | } |
Harry Wentland | efa6a8b | 2017-10-20 08:42:41 -0400 | [diff] [blame] | 4857 | |
Nicholas Kazlauskas | b2fddb1 | 2019-01-18 13:42:34 -0500 | [diff] [blame] | 4858 | /* |
| 4859 | * Initialize primary planes, implicit planes for legacy IOCTLS. |
| 4860 | * Order is reversed to match iteration order in atomic check. |
| 4861 | */ |
| 4862 | for (i = (primary_planes - 1); i >= 0; i--) { |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4863 | plane = &dm->dc->caps.planes[i]; |
| 4864 | |
Nicholas Kazlauskas | b2fddb1 | 2019-01-18 13:42:34 -0500 | [diff] [blame] | 4865 | if (initialize_plane(dm, mode_info, i, |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4866 | DRM_PLANE_TYPE_PRIMARY, plane)) { |
Shirish S | df534ff | 2018-02-27 14:48:13 +0530 | [diff] [blame] | 4867 | DRM_ERROR("KMS: Failed to initialize primary plane\n"); |
Leo (Sunpeng) Li | 92f3ac4 | 2017-06-16 15:59:17 -0400 | [diff] [blame] | 4868 | goto fail; |
| 4869 | } |
| 4870 | } |
| 4871 | |
Nicholas Kazlauskas | 0d579c7 | 2019-01-18 13:57:14 -0500 | [diff] [blame] | 4872 | /* |
| 4873 | * Initialize overlay planes, index starting after primary planes. |
| 4874 | * These planes have a higher DRM index than the primary planes since |
| 4875 | * they should be considered as having a higher z-order. |
| 4876 | * Order is reversed to match iteration order in atomic check. |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4877 | * |
| 4878 | * Only support DCN for now, and only expose one so we don't encourage |
| 4879 | * userspace to use up all the pipes. |
Nicholas Kazlauskas | 0d579c7 | 2019-01-18 13:57:14 -0500 | [diff] [blame] | 4880 | */ |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4881 | for (i = 0; i < dm->dc->caps.max_planes; ++i) { |
| 4882 | struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; |
| 4883 | |
Leo Li | 8813381 | 2022-07-06 14:56:28 -0400 | [diff] [blame] | 4884 | /* Do not create overlay if MPO disabled */ |
| 4885 | if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) |
| 4886 | break; |
| 4887 | |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4888 | if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) |
| 4889 | continue; |
| 4890 | |
Jun Lei | ea36ad3 | 2019-03-26 17:32:59 -0400 | [diff] [blame] | 4891 | if (!plane->pixel_format_support.argb8888) |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4892 | continue; |
| 4893 | |
Bhawanpreet Lakha | 35f3308 | 2023-01-17 14:35:41 -0500 | [diff] [blame] | 4894 | if (max_overlay-- == 0) |
| 4895 | break; |
| 4896 | |
Nicholas Kazlauskas | 5408776 | 2019-03-14 12:53:12 -0400 | [diff] [blame] | 4897 | if (initialize_plane(dm, NULL, primary_planes + i, |
Nicholas Kazlauskas | cc1fec5 | 2019-03-14 15:58:51 -0400 | [diff] [blame] | 4898 | DRM_PLANE_TYPE_OVERLAY, plane)) { |
Nicholas Kazlauskas | 0d579c7 | 2019-01-18 13:57:14 -0500 | [diff] [blame] | 4899 | DRM_ERROR("KMS: Failed to initialize overlay plane\n"); |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 4900 | goto fail; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4901 | } |
| 4902 | } |
| 4903 | |
Alex Deucher | d4e13b0 | 2017-06-15 16:24:01 -0400 | [diff] [blame] | 4904 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
Harry Wentland | f180b4b | 2018-10-05 11:58:34 -0400 | [diff] [blame] | 4905 | if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { |
Alex Deucher | d4e13b0 | 2017-06-15 16:24:01 -0400 | [diff] [blame] | 4906 | DRM_ERROR("KMS: Failed to initialize crtc\n"); |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 4907 | goto fail; |
Alex Deucher | d4e13b0 | 2017-06-15 16:24:01 -0400 | [diff] [blame] | 4908 | } |
| 4909 | |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 4910 | /* Use Outbox interrupt */ |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 4911 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 4912 | case IP_VERSION(3, 0, 0): |
| 4913 | case IP_VERSION(3, 1, 2): |
| 4914 | case IP_VERSION(3, 1, 3): |
Roman Li | e850f6b | 2022-06-28 18:41:37 -0400 | [diff] [blame] | 4915 | case IP_VERSION(3, 1, 4): |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 4916 | case IP_VERSION(3, 1, 5): |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 4917 | case IP_VERSION(3, 1, 6): |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 4918 | case IP_VERSION(3, 2, 0): |
| 4919 | case IP_VERSION(3, 2, 1): |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 4920 | case IP_VERSION(2, 1, 0): |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 4921 | case IP_VERSION(3, 5, 0): |
Hamza Mahfooz | 10740e4 | 2024-02-26 09:11:00 -0500 | [diff] [blame] | 4922 | case IP_VERSION(3, 5, 1): |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 4923 | case IP_VERSION(4, 0, 1): |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 4924 | if (register_outbox_irq_handlers(dm->adev)) { |
| 4925 | DRM_ERROR("DM: Failed to initialize IRQ\n"); |
| 4926 | goto fail; |
| 4927 | } |
| 4928 | break; |
| 4929 | default: |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 4930 | DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 4931 | amdgpu_ip_version(adev, DCE_HWIP, 0)); |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 4932 | } |
Nicholas Kazlauskas | 9470620 | 2021-10-05 10:55:57 -0400 | [diff] [blame] | 4933 | |
| 4934 | /* Determine whether to enable PSR support by default. */ |
| 4935 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 4936 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Nicholas Kazlauskas | 9470620 | 2021-10-05 10:55:57 -0400 | [diff] [blame] | 4937 | case IP_VERSION(3, 1, 2): |
| 4938 | case IP_VERSION(3, 1, 3): |
Roman Li | e850f6b | 2022-06-28 18:41:37 -0400 | [diff] [blame] | 4939 | case IP_VERSION(3, 1, 4): |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 4940 | case IP_VERSION(3, 1, 5): |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 4941 | case IP_VERSION(3, 1, 6): |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 4942 | case IP_VERSION(3, 2, 0): |
| 4943 | case IP_VERSION(3, 2, 1): |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 4944 | case IP_VERSION(3, 5, 0): |
Hamza Mahfooz | 10740e4 | 2024-02-26 09:11:00 -0500 | [diff] [blame] | 4945 | case IP_VERSION(3, 5, 1): |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 4946 | case IP_VERSION(4, 0, 1): |
Nicholas Kazlauskas | 9470620 | 2021-10-05 10:55:57 -0400 | [diff] [blame] | 4947 | psr_feature_enabled = true; |
| 4948 | break; |
| 4949 | default: |
| 4950 | psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; |
| 4951 | break; |
| 4952 | } |
| 4953 | } |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 4954 | |
Tom Chung | 5950efe | 2023-12-06 22:07:51 +0800 | [diff] [blame] | 4955 | /* Determine whether to enable Replay support by default. */ |
| 4956 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { |
| 4957 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Tom Chung | be64336 | 2024-06-26 17:02:23 +0800 | [diff] [blame] | 4958 | case IP_VERSION(3, 1, 4): |
| 4959 | case IP_VERSION(3, 2, 0): |
| 4960 | case IP_VERSION(3, 2, 1): |
| 4961 | case IP_VERSION(3, 5, 0): |
| 4962 | case IP_VERSION(3, 5, 1): |
| 4963 | replay_feature_enabled = true; |
| 4964 | break; |
| 4965 | |
Tom Chung | 5950efe | 2023-12-06 22:07:51 +0800 | [diff] [blame] | 4966 | default: |
| 4967 | replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; |
| 4968 | break; |
| 4969 | } |
| 4970 | } |
| 4971 | |
Hersen Wu | cf8b168 | 2024-04-24 16:15:15 -0400 | [diff] [blame] | 4972 | if (link_cnt > MAX_LINKS) { |
| 4973 | DRM_ERROR( |
| 4974 | "KMS: Cannot support more than %d display indexes\n", |
| 4975 | MAX_LINKS); |
| 4976 | goto fail; |
| 4977 | } |
| 4978 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4979 | /* loops over all connectors on the board */ |
| 4980 | for (i = 0; i < link_cnt; i++) { |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 4981 | struct dc_link *link = NULL; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 4982 | |
Harry Wentland | 198891f | 2023-12-01 06:25:23 -0700 | [diff] [blame] | 4983 | link = dc_get_link_at_index(dm->dc, i); |
| 4984 | |
Alex Hung | dfc0358 | 2023-12-01 06:25:24 -0700 | [diff] [blame] | 4985 | if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { |
Harry Wentland | ff73d4c | 2023-12-01 06:25:29 -0700 | [diff] [blame] | 4986 | struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL); |
Alex Hung | dfc0358 | 2023-12-01 06:25:24 -0700 | [diff] [blame] | 4987 | |
| 4988 | if (!wbcon) { |
| 4989 | DRM_ERROR("KMS: Failed to allocate writeback connector\n"); |
| 4990 | continue; |
| 4991 | } |
| 4992 | |
Harry Wentland | ff73d4c | 2023-12-01 06:25:29 -0700 | [diff] [blame] | 4993 | if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { |
Alex Hung | dfc0358 | 2023-12-01 06:25:24 -0700 | [diff] [blame] | 4994 | DRM_ERROR("KMS: Failed to initialize writeback connector\n"); |
| 4995 | kfree(wbcon); |
| 4996 | continue; |
| 4997 | } |
| 4998 | |
| 4999 | link->psr_settings.psr_feature_enabled = false; |
| 5000 | link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; |
| 5001 | |
Harry Wentland | 198891f | 2023-12-01 06:25:23 -0700 | [diff] [blame] | 5002 | continue; |
Alex Hung | dfc0358 | 2023-12-01 06:25:24 -0700 | [diff] [blame] | 5003 | } |
Harry Wentland | 198891f | 2023-12-01 06:25:23 -0700 | [diff] [blame] | 5004 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5005 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); |
| 5006 | if (!aconnector) |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 5007 | goto fail; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5008 | |
| 5009 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); |
Tom St Denis | 8440c30 | 2017-10-17 09:09:42 -0400 | [diff] [blame] | 5010 | if (!aencoder) |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 5011 | goto fail; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5012 | |
| 5013 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { |
| 5014 | DRM_ERROR("KMS: Failed to initialize encoder\n"); |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 5015 | goto fail; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5016 | } |
| 5017 | |
| 5018 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { |
| 5019 | DRM_ERROR("KMS: Failed to initialize connector\n"); |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 5020 | goto fail; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5021 | } |
| 5022 | |
Wayne Lin | 22e1dc4 | 2024-02-02 17:34:11 +0800 | [diff] [blame] | 5023 | if (dm->hpd_rx_offload_wq) |
| 5024 | dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = |
| 5025 | aconnector; |
| 5026 | |
Wenjing Liu | 5461888 | 2023-01-18 17:31:24 -0500 | [diff] [blame] | 5027 | if (!dc_link_detect_connection_type(link, &new_connection_type)) |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 5028 | DRM_ERROR("KMS: Failed to detect connector\n"); |
| 5029 | |
| 5030 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
| 5031 | emulated_link_detect(link); |
| 5032 | amdgpu_dm_update_connector_after_detect(aconnector); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 5033 | } else { |
| 5034 | bool ret = false; |
Bhawanpreet Lakha | fbbdadf | 2018-09-26 13:42:10 -0400 | [diff] [blame] | 5035 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 5036 | mutex_lock(&dm->dc_lock); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 5037 | dc_exit_ips_for_hw_access(dm->dc); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 5038 | ret = dc_link_detect(link, DETECT_REASON_BOOT); |
| 5039 | mutex_unlock(&dm->dc_lock); |
Michel Dänzer | fdda8f3 | 2022-02-15 19:53:37 +0100 | [diff] [blame] | 5040 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 5041 | if (ret) { |
| 5042 | amdgpu_dm_update_connector_after_detect(aconnector); |
Hans de Goede | 618e51c | 2023-03-12 20:17:49 +0100 | [diff] [blame] | 5043 | setup_backlight_device(dm, aconnector); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 5044 | |
Tom Chung | 5950efe | 2023-12-06 22:07:51 +0800 | [diff] [blame] | 5045 | /* Disable PSR if Replay can be enabled */ |
| 5046 | if (replay_feature_enabled) |
| 5047 | if (amdgpu_dm_set_replay_caps(link, aconnector)) |
| 5048 | psr_feature_enabled = false; |
| 5049 | |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 5050 | if (psr_feature_enabled) |
| 5051 | amdgpu_dm_set_psr_caps(link); |
Wayne Lin | 15c735e | 2022-05-31 17:46:24 +0800 | [diff] [blame] | 5052 | } |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 5053 | } |
Melissa Wen | acc96ae | 2022-08-04 15:13:49 -0100 | [diff] [blame] | 5054 | amdgpu_set_panel_orientation(&aconnector->base); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5055 | } |
| 5056 | |
| 5057 | /* Software is initialized. Now we can register interrupt handlers. */ |
| 5058 | switch (adev->asic_type) { |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 5059 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 5060 | case CHIP_TAHITI: |
| 5061 | case CHIP_PITCAIRN: |
| 5062 | case CHIP_VERDE: |
| 5063 | case CHIP_OLAND: |
| 5064 | if (dce60_register_irq_handlers(dm->adev)) { |
| 5065 | DRM_ERROR("DM: Failed to initialize IRQ\n"); |
| 5066 | goto fail; |
| 5067 | } |
| 5068 | break; |
| 5069 | #endif |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5070 | case CHIP_BONAIRE: |
| 5071 | case CHIP_HAWAII: |
Alex Deucher | cd4b356 | 2017-08-10 14:39:47 -0400 | [diff] [blame] | 5072 | case CHIP_KAVERI: |
| 5073 | case CHIP_KABINI: |
| 5074 | case CHIP_MULLINS: |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5075 | case CHIP_TONGA: |
| 5076 | case CHIP_FIJI: |
| 5077 | case CHIP_CARRIZO: |
| 5078 | case CHIP_STONEY: |
| 5079 | case CHIP_POLARIS11: |
| 5080 | case CHIP_POLARIS10: |
Jordan Lazare | b264d34 | 2016-12-14 15:35:13 -0500 | [diff] [blame] | 5081 | case CHIP_POLARIS12: |
Jerry (Fangzhi) Zuo | 7737de9 | 2017-11-09 11:51:13 -0500 | [diff] [blame] | 5082 | case CHIP_VEGAM: |
Alex Deucher | 2c8ad2d | 2017-06-15 16:20:24 -0400 | [diff] [blame] | 5083 | case CHIP_VEGA10: |
Alex Deucher | 2325ff3 | 2017-09-02 02:01:55 -0400 | [diff] [blame] | 5084 | case CHIP_VEGA12: |
Feifei Xu | 1fe6bf2 | 2018-04-20 19:50:01 +0800 | [diff] [blame] | 5085 | case CHIP_VEGA20: |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5086 | if (dce110_register_irq_handlers(dm->adev)) { |
| 5087 | DRM_ERROR("DM: Failed to initialize IRQ\n"); |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 5088 | goto fail; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5089 | } |
| 5090 | break; |
| 5091 | default: |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 5092 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Alex Deucher | 559f591 | 2021-08-03 17:47:14 -0400 | [diff] [blame] | 5093 | case IP_VERSION(1, 0, 0): |
| 5094 | case IP_VERSION(1, 0, 1): |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 5095 | case IP_VERSION(2, 0, 2): |
| 5096 | case IP_VERSION(2, 0, 3): |
| 5097 | case IP_VERSION(2, 0, 0): |
| 5098 | case IP_VERSION(2, 1, 0): |
| 5099 | case IP_VERSION(3, 0, 0): |
| 5100 | case IP_VERSION(3, 0, 2): |
| 5101 | case IP_VERSION(3, 0, 3): |
| 5102 | case IP_VERSION(3, 0, 1): |
| 5103 | case IP_VERSION(3, 1, 2): |
| 5104 | case IP_VERSION(3, 1, 3): |
Roman Li | e850f6b | 2022-06-28 18:41:37 -0400 | [diff] [blame] | 5105 | case IP_VERSION(3, 1, 4): |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 5106 | case IP_VERSION(3, 1, 5): |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 5107 | case IP_VERSION(3, 1, 6): |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 5108 | case IP_VERSION(3, 2, 0): |
| 5109 | case IP_VERSION(3, 2, 1): |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 5110 | case IP_VERSION(3, 5, 0): |
Hamza Mahfooz | 10740e4 | 2024-02-26 09:11:00 -0500 | [diff] [blame] | 5111 | case IP_VERSION(3, 5, 1): |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 5112 | case IP_VERSION(4, 0, 1): |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 5113 | if (dcn10_register_irq_handlers(dm->adev)) { |
| 5114 | DRM_ERROR("DM: Failed to initialize IRQ\n"); |
| 5115 | goto fail; |
| 5116 | } |
| 5117 | break; |
| 5118 | default: |
Guchun Chen | 2cbc6f4 | 2021-08-09 15:44:29 +0800 | [diff] [blame] | 5119 | DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 5120 | amdgpu_ip_version(adev, DCE_HWIP, 0)); |
Guchun Chen | 2cbc6f4 | 2021-08-09 15:44:29 +0800 | [diff] [blame] | 5121 | goto fail; |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 5122 | } |
Guchun Chen | 2cbc6f4 | 2021-08-09 15:44:29 +0800 | [diff] [blame] | 5123 | break; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5124 | } |
| 5125 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5126 | return 0; |
Harry Wentland | cd8a2ae | 2017-10-20 08:28:59 -0400 | [diff] [blame] | 5127 | fail: |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5128 | kfree(aencoder); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5129 | kfree(aconnector); |
Nicholas Kazlauskas | 5408776 | 2019-03-14 12:53:12 -0400 | [diff] [blame] | 5130 | |
Alex Deucher | 59d0f39 | 2018-09-13 11:01:28 -0500 | [diff] [blame] | 5131 | return -EINVAL; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5132 | } |
| 5133 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 5134 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5135 | { |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 5136 | drm_atomic_private_obj_fini(&dm->atomic_obj); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5137 | } |
| 5138 | |
| 5139 | /****************************************************************************** |
| 5140 | * amdgpu_display_funcs functions |
| 5141 | *****************************************************************************/ |
| 5142 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 5143 | /* |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5144 | * dm_bandwidth_update - program display watermarks |
| 5145 | * |
| 5146 | * @adev: amdgpu_device pointer |
| 5147 | * |
| 5148 | * Calculate and program the display watermarks and line buffer allocation. |
| 5149 | */ |
| 5150 | static void dm_bandwidth_update(struct amdgpu_device *adev) |
| 5151 | { |
Arindam Nath | 49c07a9 | 2016-12-05 19:21:26 +0530 | [diff] [blame] | 5152 | /* TODO: implement later */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5153 | } |
| 5154 | |
Alex Deucher | 39cc5be | 2016-12-13 15:42:48 -0500 | [diff] [blame] | 5155 | static const struct amdgpu_display_funcs dm_display_funcs = { |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5156 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
| 5157 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ |
Harry Wentland | 7b42573 | 2018-07-19 14:17:30 -0400 | [diff] [blame] | 5158 | .backlight_set_level = NULL, /* never called for DC */ |
| 5159 | .backlight_get_level = NULL, /* never called for DC */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5160 | .hpd_sense = NULL,/* called unconditionally */ |
| 5161 | .hpd_set_polarity = NULL, /* called unconditionally */ |
| 5162 | .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5163 | .page_flip_get_scanoutpos = |
| 5164 | dm_crtc_get_scanoutpos,/* called unconditionally */ |
| 5165 | .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ |
| 5166 | .add_connector = NULL, /* VBIOS parsing. DAL does it. */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5167 | }; |
| 5168 | |
| 5169 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
| 5170 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 5171 | static ssize_t s3_debug_store(struct device *device, |
| 5172 | struct device_attribute *attr, |
| 5173 | const char *buf, |
| 5174 | size_t count) |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5175 | { |
| 5176 | int ret; |
| 5177 | int s3_state; |
Chuhong Yuan | ef1de36 | 2019-07-23 17:04:22 +0800 | [diff] [blame] | 5178 | struct drm_device *drm_dev = dev_get_drvdata(device); |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 5179 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5180 | |
| 5181 | ret = kstrtoint(buf, 0, &s3_state); |
| 5182 | |
| 5183 | if (ret == 0) { |
| 5184 | if (s3_state) { |
| 5185 | dm_resume(adev); |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 5186 | drm_kms_helper_hotplug_event(adev_to_drm(adev)); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5187 | } else |
| 5188 | dm_suspend(adev); |
| 5189 | } |
| 5190 | |
| 5191 | return ret == 0 ? count : 0; |
| 5192 | } |
| 5193 | |
| 5194 | DEVICE_ATTR_WO(s3_debug); |
| 5195 | |
| 5196 | #endif |
| 5197 | |
Mario Limonciello | a7ab345 | 2023-01-03 15:04:23 -0600 | [diff] [blame] | 5198 | static int dm_init_microcode(struct amdgpu_device *adev) |
| 5199 | { |
| 5200 | char *fw_name_dmub; |
| 5201 | int r; |
| 5202 | |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 5203 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Mario Limonciello | a7ab345 | 2023-01-03 15:04:23 -0600 | [diff] [blame] | 5204 | case IP_VERSION(2, 1, 0): |
| 5205 | fw_name_dmub = FIRMWARE_RENOIR_DMUB; |
| 5206 | if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) |
| 5207 | fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; |
| 5208 | break; |
| 5209 | case IP_VERSION(3, 0, 0): |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 5210 | if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) |
Mario Limonciello | a7ab345 | 2023-01-03 15:04:23 -0600 | [diff] [blame] | 5211 | fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; |
| 5212 | else |
| 5213 | fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; |
| 5214 | break; |
| 5215 | case IP_VERSION(3, 0, 1): |
| 5216 | fw_name_dmub = FIRMWARE_VANGOGH_DMUB; |
| 5217 | break; |
| 5218 | case IP_VERSION(3, 0, 2): |
| 5219 | fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; |
| 5220 | break; |
| 5221 | case IP_VERSION(3, 0, 3): |
| 5222 | fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; |
| 5223 | break; |
| 5224 | case IP_VERSION(3, 1, 2): |
| 5225 | case IP_VERSION(3, 1, 3): |
| 5226 | fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; |
| 5227 | break; |
| 5228 | case IP_VERSION(3, 1, 4): |
| 5229 | fw_name_dmub = FIRMWARE_DCN_314_DMUB; |
| 5230 | break; |
| 5231 | case IP_VERSION(3, 1, 5): |
| 5232 | fw_name_dmub = FIRMWARE_DCN_315_DMUB; |
| 5233 | break; |
| 5234 | case IP_VERSION(3, 1, 6): |
| 5235 | fw_name_dmub = FIRMWARE_DCN316_DMUB; |
| 5236 | break; |
| 5237 | case IP_VERSION(3, 2, 0): |
| 5238 | fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; |
| 5239 | break; |
| 5240 | case IP_VERSION(3, 2, 1): |
| 5241 | fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; |
| 5242 | break; |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 5243 | case IP_VERSION(3, 5, 0): |
| 5244 | fw_name_dmub = FIRMWARE_DCN_35_DMUB; |
| 5245 | break; |
Li Ma | 2dbe9c2 | 2024-03-28 10:55:10 +0800 | [diff] [blame] | 5246 | case IP_VERSION(3, 5, 1): |
| 5247 | fw_name_dmub = FIRMWARE_DCN_351_DMUB; |
| 5248 | break; |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 5249 | case IP_VERSION(4, 0, 1): |
| 5250 | fw_name_dmub = FIRMWARE_DCN_401_DMUB; |
| 5251 | break; |
Mario Limonciello | a7ab345 | 2023-01-03 15:04:23 -0600 | [diff] [blame] | 5252 | default: |
| 5253 | /* ASIC doesn't support DMUB. */ |
| 5254 | return 0; |
| 5255 | } |
Arnd Bergmann | 0206204 | 2024-07-19 12:08:28 +0200 | [diff] [blame] | 5256 | r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, "%s", fw_name_dmub); |
Mario Limonciello | a7ab345 | 2023-01-03 15:04:23 -0600 | [diff] [blame] | 5257 | return r; |
| 5258 | } |
| 5259 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5260 | static int dm_early_init(void *handle) |
| 5261 | { |
| 5262 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | 44900af | 2023-01-25 14:35:16 -0500 | [diff] [blame] | 5263 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
| 5264 | struct atom_context *ctx = mode_info->atom_context; |
| 5265 | int index = GetIndexIntoMasterTable(DATA, Object_Header); |
| 5266 | u16 data_offset; |
| 5267 | |
| 5268 | /* if there is no object header, skip DM */ |
| 5269 | if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { |
| 5270 | adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; |
| 5271 | dev_info(adev->dev, "No object header, skipping DM\n"); |
| 5272 | return -ENOENT; |
| 5273 | } |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5274 | |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5275 | switch (adev->asic_type) { |
Mauro Rossi | 55e5638 | 2019-05-26 17:33:45 +0200 | [diff] [blame] | 5276 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 5277 | case CHIP_TAHITI: |
| 5278 | case CHIP_PITCAIRN: |
| 5279 | case CHIP_VERDE: |
| 5280 | adev->mode_info.num_crtc = 6; |
| 5281 | adev->mode_info.num_hpd = 6; |
| 5282 | adev->mode_info.num_dig = 6; |
| 5283 | break; |
| 5284 | case CHIP_OLAND: |
| 5285 | adev->mode_info.num_crtc = 2; |
| 5286 | adev->mode_info.num_hpd = 2; |
| 5287 | adev->mode_info.num_dig = 2; |
| 5288 | break; |
| 5289 | #endif |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5290 | case CHIP_BONAIRE: |
| 5291 | case CHIP_HAWAII: |
| 5292 | adev->mode_info.num_crtc = 6; |
| 5293 | adev->mode_info.num_hpd = 6; |
| 5294 | adev->mode_info.num_dig = 6; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5295 | break; |
Alex Deucher | cd4b356 | 2017-08-10 14:39:47 -0400 | [diff] [blame] | 5296 | case CHIP_KAVERI: |
| 5297 | adev->mode_info.num_crtc = 4; |
| 5298 | adev->mode_info.num_hpd = 6; |
| 5299 | adev->mode_info.num_dig = 7; |
Alex Deucher | cd4b356 | 2017-08-10 14:39:47 -0400 | [diff] [blame] | 5300 | break; |
| 5301 | case CHIP_KABINI: |
| 5302 | case CHIP_MULLINS: |
| 5303 | adev->mode_info.num_crtc = 2; |
| 5304 | adev->mode_info.num_hpd = 6; |
| 5305 | adev->mode_info.num_dig = 6; |
Alex Deucher | cd4b356 | 2017-08-10 14:39:47 -0400 | [diff] [blame] | 5306 | break; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5307 | case CHIP_FIJI: |
| 5308 | case CHIP_TONGA: |
| 5309 | adev->mode_info.num_crtc = 6; |
| 5310 | adev->mode_info.num_hpd = 6; |
| 5311 | adev->mode_info.num_dig = 7; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5312 | break; |
| 5313 | case CHIP_CARRIZO: |
| 5314 | adev->mode_info.num_crtc = 3; |
| 5315 | adev->mode_info.num_hpd = 6; |
| 5316 | adev->mode_info.num_dig = 9; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5317 | break; |
| 5318 | case CHIP_STONEY: |
| 5319 | adev->mode_info.num_crtc = 2; |
| 5320 | adev->mode_info.num_hpd = 6; |
| 5321 | adev->mode_info.num_dig = 9; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5322 | break; |
| 5323 | case CHIP_POLARIS11: |
Jordan Lazare | b264d34 | 2016-12-14 15:35:13 -0500 | [diff] [blame] | 5324 | case CHIP_POLARIS12: |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5325 | adev->mode_info.num_crtc = 5; |
| 5326 | adev->mode_info.num_hpd = 5; |
| 5327 | adev->mode_info.num_dig = 5; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5328 | break; |
| 5329 | case CHIP_POLARIS10: |
Jerry (Fangzhi) Zuo | 7737de9 | 2017-11-09 11:51:13 -0500 | [diff] [blame] | 5330 | case CHIP_VEGAM: |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5331 | adev->mode_info.num_crtc = 6; |
| 5332 | adev->mode_info.num_hpd = 6; |
| 5333 | adev->mode_info.num_dig = 6; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5334 | break; |
Alex Deucher | 2c8ad2d | 2017-06-15 16:20:24 -0400 | [diff] [blame] | 5335 | case CHIP_VEGA10: |
Alex Deucher | 2325ff3 | 2017-09-02 02:01:55 -0400 | [diff] [blame] | 5336 | case CHIP_VEGA12: |
Feifei Xu | 1fe6bf2 | 2018-04-20 19:50:01 +0800 | [diff] [blame] | 5337 | case CHIP_VEGA20: |
Alex Deucher | 2c8ad2d | 2017-06-15 16:20:24 -0400 | [diff] [blame] | 5338 | adev->mode_info.num_crtc = 6; |
| 5339 | adev->mode_info.num_hpd = 6; |
| 5340 | adev->mode_info.num_dig = 6; |
| 5341 | break; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5342 | default: |
Alex Hung | cae5c1a | 2022-04-25 15:12:02 -0600 | [diff] [blame] | 5343 | |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 5344 | switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 5345 | case IP_VERSION(2, 0, 2): |
| 5346 | case IP_VERSION(3, 0, 0): |
| 5347 | adev->mode_info.num_crtc = 6; |
| 5348 | adev->mode_info.num_hpd = 6; |
| 5349 | adev->mode_info.num_dig = 6; |
| 5350 | break; |
| 5351 | case IP_VERSION(2, 0, 0): |
| 5352 | case IP_VERSION(3, 0, 2): |
| 5353 | adev->mode_info.num_crtc = 5; |
| 5354 | adev->mode_info.num_hpd = 5; |
| 5355 | adev->mode_info.num_dig = 5; |
| 5356 | break; |
| 5357 | case IP_VERSION(2, 0, 3): |
| 5358 | case IP_VERSION(3, 0, 3): |
| 5359 | adev->mode_info.num_crtc = 2; |
| 5360 | adev->mode_info.num_hpd = 2; |
| 5361 | adev->mode_info.num_dig = 2; |
| 5362 | break; |
Alex Deucher | 559f591 | 2021-08-03 17:47:14 -0400 | [diff] [blame] | 5363 | case IP_VERSION(1, 0, 0): |
| 5364 | case IP_VERSION(1, 0, 1): |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 5365 | case IP_VERSION(3, 0, 1): |
| 5366 | case IP_VERSION(2, 1, 0): |
| 5367 | case IP_VERSION(3, 1, 2): |
| 5368 | case IP_VERSION(3, 1, 3): |
Roman Li | e850f6b | 2022-06-28 18:41:37 -0400 | [diff] [blame] | 5369 | case IP_VERSION(3, 1, 4): |
Qingqing Zhuo | b5b8ed4 | 2022-02-10 15:20:31 -0500 | [diff] [blame] | 5370 | case IP_VERSION(3, 1, 5): |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 5371 | case IP_VERSION(3, 1, 6): |
Aurabindo Pillai | 577359c | 2022-02-23 19:05:09 -0500 | [diff] [blame] | 5372 | case IP_VERSION(3, 2, 0): |
| 5373 | case IP_VERSION(3, 2, 1): |
Qingqing Zhuo | 06b1661 | 2023-08-03 02:34:54 -0400 | [diff] [blame] | 5374 | case IP_VERSION(3, 5, 0): |
Hamza Mahfooz | 10740e4 | 2024-02-26 09:11:00 -0500 | [diff] [blame] | 5375 | case IP_VERSION(3, 5, 1): |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 5376 | case IP_VERSION(4, 0, 1): |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 5377 | adev->mode_info.num_crtc = 4; |
| 5378 | adev->mode_info.num_hpd = 4; |
| 5379 | adev->mode_info.num_dig = 4; |
| 5380 | break; |
| 5381 | default: |
Guchun Chen | 2cbc6f4 | 2021-08-09 15:44:29 +0800 | [diff] [blame] | 5382 | DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", |
Lijo Lazar | 4e8303c | 2023-09-11 13:48:11 +0530 | [diff] [blame] | 5383 | amdgpu_ip_version(adev, DCE_HWIP, 0)); |
Guchun Chen | 2cbc6f4 | 2021-08-09 15:44:29 +0800 | [diff] [blame] | 5384 | return -EINVAL; |
Alex Deucher | c08182f | 2021-09-29 14:04:42 -0400 | [diff] [blame] | 5385 | } |
Guchun Chen | 2cbc6f4 | 2021-08-09 15:44:29 +0800 | [diff] [blame] | 5386 | break; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5387 | } |
| 5388 | |
Alex Deucher | 39cc5be | 2016-12-13 15:42:48 -0500 | [diff] [blame] | 5389 | if (adev->mode_info.funcs == NULL) |
| 5390 | adev->mode_info.funcs = &dm_display_funcs; |
| 5391 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 5392 | /* |
| 5393 | * Note: Do NOT change adev->audio_endpt_rreg and |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5394 | * adev->audio_endpt_wreg because they are initialised in |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 5395 | * amdgpu_device_init() |
| 5396 | */ |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5397 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
| 5398 | device_create_file( |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 5399 | adev_to_drm(adev)->dev, |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5400 | &dev_attr_s3_debug); |
| 5401 | #endif |
Alex Deucher | d09ef24 | 2022-07-19 14:18:41 -0400 | [diff] [blame] | 5402 | adev->dc_enabled = true; |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5403 | |
Mario Limonciello | a7ab345 | 2023-01-03 15:04:23 -0600 | [diff] [blame] | 5404 | return dm_init_microcode(adev); |
Harry Wentland | 4562236 | 2017-09-12 15:58:20 -0400 | [diff] [blame] | 5405 | } |
| 5406 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5407 | static bool modereset_required(struct drm_crtc_state *crtc_state) |
| 5408 | { |
Michel Dänzer | 2afda73 | 2020-07-22 14:38:13 +0200 | [diff] [blame] | 5409 | return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5410 | } |
| 5411 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 5412 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5413 | { |
| 5414 | drm_encoder_cleanup(encoder); |
| 5415 | kfree(encoder); |
| 5416 | } |
| 5417 | |
| 5418 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { |
| 5419 | .destroy = amdgpu_dm_encoder_destroy, |
| 5420 | }; |
| 5421 | |
Nicholas Kazlauskas | 004fefa | 2019-03-15 10:31:50 -0400 | [diff] [blame] | 5422 | static int |
| 5423 | fill_plane_color_attributes(const struct drm_plane_state *plane_state, |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5424 | const enum surface_pixel_format format, |
Nicholas Kazlauskas | 004fefa | 2019-03-15 10:31:50 -0400 | [diff] [blame] | 5425 | enum dc_color_space *color_space) |
| 5426 | { |
| 5427 | bool full_range; |
| 5428 | |
| 5429 | *color_space = COLOR_SPACE_SRGB; |
| 5430 | |
| 5431 | /* DRM color properties only affect non-RGB formats. */ |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5432 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
Nicholas Kazlauskas | 004fefa | 2019-03-15 10:31:50 -0400 | [diff] [blame] | 5433 | return 0; |
| 5434 | |
| 5435 | full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); |
| 5436 | |
| 5437 | switch (plane_state->color_encoding) { |
| 5438 | case DRM_COLOR_YCBCR_BT601: |
| 5439 | if (full_range) |
| 5440 | *color_space = COLOR_SPACE_YCBCR601; |
| 5441 | else |
| 5442 | *color_space = COLOR_SPACE_YCBCR601_LIMITED; |
| 5443 | break; |
| 5444 | |
| 5445 | case DRM_COLOR_YCBCR_BT709: |
| 5446 | if (full_range) |
| 5447 | *color_space = COLOR_SPACE_YCBCR709; |
| 5448 | else |
| 5449 | *color_space = COLOR_SPACE_YCBCR709_LIMITED; |
| 5450 | break; |
| 5451 | |
| 5452 | case DRM_COLOR_YCBCR_BT2020: |
| 5453 | if (full_range) |
| 5454 | *color_space = COLOR_SPACE_2020_YCBCR; |
| 5455 | else |
| 5456 | return -EINVAL; |
| 5457 | break; |
| 5458 | |
| 5459 | default: |
| 5460 | return -EINVAL; |
| 5461 | } |
| 5462 | |
| 5463 | return 0; |
| 5464 | } |
| 5465 | |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5466 | static int |
| 5467 | fill_dc_plane_info_and_addr(struct amdgpu_device *adev, |
| 5468 | const struct drm_plane_state *plane_state, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 5469 | const u64 tiling_flags, |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5470 | struct dc_plane_info *plane_info, |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 5471 | struct dc_plane_address *address, |
Harry Wentland | 5888f07 | 2020-04-22 17:54:55 -0400 | [diff] [blame] | 5472 | bool tmz_surface, |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 5473 | bool force_disable_dcc) |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5474 | { |
| 5475 | const struct drm_framebuffer *fb = plane_state->fb; |
| 5476 | const struct amdgpu_framebuffer *afb = |
| 5477 | to_amdgpu_framebuffer(plane_state->fb); |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5478 | int ret; |
| 5479 | |
| 5480 | memset(plane_info, 0, sizeof(*plane_info)); |
| 5481 | |
| 5482 | switch (fb->format->format) { |
| 5483 | case DRM_FORMAT_C8: |
| 5484 | plane_info->format = |
| 5485 | SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; |
| 5486 | break; |
| 5487 | case DRM_FORMAT_RGB565: |
| 5488 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; |
| 5489 | break; |
| 5490 | case DRM_FORMAT_XRGB8888: |
| 5491 | case DRM_FORMAT_ARGB8888: |
| 5492 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
| 5493 | break; |
| 5494 | case DRM_FORMAT_XRGB2101010: |
| 5495 | case DRM_FORMAT_ARGB2101010: |
| 5496 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; |
| 5497 | break; |
| 5498 | case DRM_FORMAT_XBGR2101010: |
| 5499 | case DRM_FORMAT_ABGR2101010: |
| 5500 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; |
| 5501 | break; |
| 5502 | case DRM_FORMAT_XBGR8888: |
| 5503 | case DRM_FORMAT_ABGR8888: |
| 5504 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; |
| 5505 | break; |
| 5506 | case DRM_FORMAT_NV21: |
| 5507 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; |
| 5508 | break; |
| 5509 | case DRM_FORMAT_NV12: |
| 5510 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; |
| 5511 | break; |
Stylon Wang | cbec647 | 2020-03-06 09:55:29 -0500 | [diff] [blame] | 5512 | case DRM_FORMAT_P010: |
| 5513 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; |
| 5514 | break; |
Stylon Wang | 492548d | 2020-04-21 20:47:41 +0800 | [diff] [blame] | 5515 | case DRM_FORMAT_XRGB16161616F: |
| 5516 | case DRM_FORMAT_ARGB16161616F: |
| 5517 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; |
| 5518 | break; |
Mario Kleiner | 2a5195d | 2020-05-15 07:19:23 +0200 | [diff] [blame] | 5519 | case DRM_FORMAT_XBGR16161616F: |
| 5520 | case DRM_FORMAT_ABGR16161616F: |
| 5521 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; |
| 5522 | break; |
Mario Kleiner | 5802040 | 2021-03-19 22:03:17 +0100 | [diff] [blame] | 5523 | case DRM_FORMAT_XRGB16161616: |
| 5524 | case DRM_FORMAT_ARGB16161616: |
| 5525 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; |
| 5526 | break; |
| 5527 | case DRM_FORMAT_XBGR16161616: |
| 5528 | case DRM_FORMAT_ABGR16161616: |
| 5529 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; |
| 5530 | break; |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5531 | default: |
| 5532 | DRM_ERROR( |
Sakari Ailus | 92f1d09 | 2021-02-16 17:57:22 +0200 | [diff] [blame] | 5533 | "Unsupported screen format %p4cc\n", |
| 5534 | &fb->format->format); |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5535 | return -EINVAL; |
| 5536 | } |
| 5537 | |
| 5538 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { |
| 5539 | case DRM_MODE_ROTATE_0: |
| 5540 | plane_info->rotation = ROTATION_ANGLE_0; |
| 5541 | break; |
| 5542 | case DRM_MODE_ROTATE_90: |
| 5543 | plane_info->rotation = ROTATION_ANGLE_90; |
| 5544 | break; |
| 5545 | case DRM_MODE_ROTATE_180: |
| 5546 | plane_info->rotation = ROTATION_ANGLE_180; |
| 5547 | break; |
| 5548 | case DRM_MODE_ROTATE_270: |
| 5549 | plane_info->rotation = ROTATION_ANGLE_270; |
| 5550 | break; |
| 5551 | default: |
| 5552 | plane_info->rotation = ROTATION_ANGLE_0; |
| 5553 | break; |
| 5554 | } |
| 5555 | |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 5556 | |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5557 | plane_info->visible = true; |
| 5558 | plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; |
| 5559 | |
Leo Li | 22c42b0 | 2022-08-30 16:38:16 -0400 | [diff] [blame] | 5560 | plane_info->layer_index = plane_state->normalized_zpos; |
Michael Strauss | 6d83a32 | 2019-07-26 12:04:12 -0400 | [diff] [blame] | 5561 | |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5562 | ret = fill_plane_color_attributes(plane_state, plane_info->format, |
| 5563 | &plane_info->color_space); |
| 5564 | if (ret) |
| 5565 | return ret; |
| 5566 | |
David Tadokoro | 8bf0d9c | 2023-03-05 23:24:27 -0300 | [diff] [blame] | 5567 | ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5568 | plane_info->rotation, tiling_flags, |
| 5569 | &plane_info->tiling_info, |
| 5570 | &plane_info->plane_size, |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 5571 | &plane_info->dcc, address, |
| 5572 | tmz_surface, force_disable_dcc); |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5573 | if (ret) |
| 5574 | return ret; |
| 5575 | |
David Tadokoro | 8bf0d9c | 2023-03-05 23:24:27 -0300 | [diff] [blame] | 5576 | amdgpu_dm_plane_fill_blending_from_plane_state( |
Sung Joon Kim | 76818cd | 2022-05-19 17:46:36 -0400 | [diff] [blame] | 5577 | plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5578 | &plane_info->global_alpha, &plane_info->global_alpha_value); |
| 5579 | |
| 5580 | return 0; |
| 5581 | } |
| 5582 | |
| 5583 | static int fill_dc_plane_attributes(struct amdgpu_device *adev, |
| 5584 | struct dc_plane_state *dc_plane_state, |
| 5585 | struct drm_plane_state *plane_state, |
| 5586 | struct drm_crtc_state *crtc_state) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5587 | { |
Nicholas Kazlauskas | cf020d49 | 2019-05-09 12:14:58 -0400 | [diff] [blame] | 5588 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 5589 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5590 | struct dc_scaling_info scaling_info; |
| 5591 | struct dc_plane_info plane_info; |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5592 | int ret; |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 5593 | bool force_disable_dcc = false; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5594 | |
David Tadokoro | 8bf0d9c | 2023-03-05 23:24:27 -0300 | [diff] [blame] | 5595 | ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5596 | if (ret) |
| 5597 | return ret; |
| 5598 | |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5599 | dc_plane_state->src_rect = scaling_info.src_rect; |
| 5600 | dc_plane_state->dst_rect = scaling_info.dst_rect; |
| 5601 | dc_plane_state->clip_rect = scaling_info.clip_rect; |
| 5602 | dc_plane_state->scaling_quality = scaling_info.scaling_quality; |
| 5603 | |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 5604 | force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; |
Nicholas Kazlauskas | 707477b | 2020-07-28 09:44:26 -0400 | [diff] [blame] | 5605 | ret = fill_dc_plane_info_and_addr(adev, plane_state, |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 5606 | afb->tiling_flags, |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5607 | &plane_info, |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 5608 | &dc_plane_state->address, |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 5609 | afb->tmz_surface, |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 5610 | force_disable_dcc); |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5611 | if (ret) |
| 5612 | return ret; |
| 5613 | |
| 5614 | dc_plane_state->format = plane_info.format; |
| 5615 | dc_plane_state->color_space = plane_info.color_space; |
| 5616 | dc_plane_state->format = plane_info.format; |
| 5617 | dc_plane_state->plane_size = plane_info.plane_size; |
| 5618 | dc_plane_state->rotation = plane_info.rotation; |
| 5619 | dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; |
| 5620 | dc_plane_state->stereo_format = plane_info.stereo_format; |
| 5621 | dc_plane_state->tiling_info = plane_info.tiling_info; |
| 5622 | dc_plane_state->visible = plane_info.visible; |
| 5623 | dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; |
Sung Joon Kim | 76818cd | 2022-05-19 17:46:36 -0400 | [diff] [blame] | 5624 | dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5625 | dc_plane_state->global_alpha = plane_info.global_alpha; |
| 5626 | dc_plane_state->global_alpha_value = plane_info.global_alpha_value; |
| 5627 | dc_plane_state->dcc = plane_info.dcc; |
Leo Li | 22c42b0 | 2022-08-30 16:38:16 -0400 | [diff] [blame] | 5628 | dc_plane_state->layer_index = plane_info.layer_index; |
Qingqing Zhuo | 7afa003 | 2021-02-19 17:17:50 -0500 | [diff] [blame] | 5629 | dc_plane_state->flip_int_enabled = true; |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 5630 | |
Leo (Sunpeng) Li | e277adc | 2018-02-02 10:18:56 -0500 | [diff] [blame] | 5631 | /* |
| 5632 | * Always set input transfer function, since plane state is refreshed |
| 5633 | * every time. |
| 5634 | */ |
Joshua Ashton | 980f871 | 2023-11-16 18:57:59 -0100 | [diff] [blame] | 5635 | ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, |
| 5636 | plane_state, |
| 5637 | dc_plane_state); |
Nicholas Kazlauskas | cf020d49 | 2019-05-09 12:14:58 -0400 | [diff] [blame] | 5638 | if (ret) |
| 5639 | return ret; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5640 | |
Nicholas Kazlauskas | cf020d49 | 2019-05-09 12:14:58 -0400 | [diff] [blame] | 5641 | return 0; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5642 | } |
| 5643 | |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5644 | static inline void fill_dc_dirty_rect(struct drm_plane *plane, |
| 5645 | struct rect *dirty_rect, int32_t x, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 5646 | s32 y, s32 width, s32 height, |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5647 | int *i, bool ffu) |
| 5648 | { |
Hamza Mahfooz | af22d6a | 2023-06-21 15:19:05 -0400 | [diff] [blame] | 5649 | WARN_ON(*i >= DC_MAX_DIRTY_RECTS); |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5650 | |
| 5651 | dirty_rect->x = x; |
| 5652 | dirty_rect->y = y; |
| 5653 | dirty_rect->width = width; |
| 5654 | dirty_rect->height = height; |
| 5655 | |
| 5656 | if (ffu) |
| 5657 | drm_dbg(plane->dev, |
| 5658 | "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", |
| 5659 | plane->base.id, width, height); |
| 5660 | else |
| 5661 | drm_dbg(plane->dev, |
| 5662 | "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", |
| 5663 | plane->base.id, x, y, width, height); |
| 5664 | |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5665 | (*i)++; |
| 5666 | } |
| 5667 | |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5668 | /** |
| 5669 | * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates |
| 5670 | * |
| 5671 | * @plane: DRM plane containing dirty regions that need to be flushed to the eDP |
| 5672 | * remote fb |
| 5673 | * @old_plane_state: Old state of @plane |
| 5674 | * @new_plane_state: New state of @plane |
| 5675 | * @crtc_state: New state of CRTC connected to the @plane |
| 5676 | * @flip_addrs: DC flip tracking struct, which also tracts dirty rects |
Srinivasan Shanmugam | 3651306 | 2024-02-15 18:25:40 +0530 | [diff] [blame] | 5677 | * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. |
| 5678 | * If PSR SU is enabled and damage clips are available, only the regions of the screen |
| 5679 | * that have changed will be updated. If PSR SU is not enabled, |
| 5680 | * or if damage clips are not available, the entire screen will be updated. |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 5681 | * @dirty_regions_changed: dirty regions changed |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5682 | * |
| 5683 | * For PSR SU, DC informs the DMUB uController of dirty rectangle regions |
| 5684 | * (referred to as "damage clips" in DRM nomenclature) that require updating on |
| 5685 | * the eDP remote buffer. The responsibility of specifying the dirty regions is |
| 5686 | * amdgpu_dm's. |
| 5687 | * |
| 5688 | * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the |
| 5689 | * plane with regions that require flushing to the eDP remote buffer. In |
| 5690 | * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - |
| 5691 | * implicitly provide damage clips without any client support via the plane |
| 5692 | * bounds. |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5693 | */ |
| 5694 | static void fill_dc_dirty_rects(struct drm_plane *plane, |
| 5695 | struct drm_plane_state *old_plane_state, |
| 5696 | struct drm_plane_state *new_plane_state, |
| 5697 | struct drm_crtc_state *crtc_state, |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 5698 | struct dc_flip_addrs *flip_addrs, |
Hamza Mahfooz | fc184db | 2024-02-08 16:23:29 -0500 | [diff] [blame] | 5699 | bool is_psr_su, |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 5700 | bool *dirty_regions_changed) |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5701 | { |
| 5702 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); |
| 5703 | struct rect *dirty_rects = flip_addrs->dirty_rects; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 5704 | u32 num_clips; |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5705 | struct drm_mode_rect *clips; |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5706 | bool bb_changed; |
| 5707 | bool fb_changed; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 5708 | u32 i = 0; |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 5709 | *dirty_regions_changed = false; |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5710 | |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5711 | /* |
| 5712 | * Cursor plane has it's own dirty rect update interface. See |
| 5713 | * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data |
| 5714 | */ |
| 5715 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
| 5716 | return; |
| 5717 | |
Hamza Mahfooz | 0497ae6 | 2023-12-05 14:55:04 -0500 | [diff] [blame] | 5718 | if (new_plane_state->rotation != DRM_MODE_ROTATE_0) |
| 5719 | goto ffu; |
| 5720 | |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5721 | num_clips = drm_plane_get_damage_clips_count(new_plane_state); |
| 5722 | clips = drm_plane_get_damage_clips(new_plane_state); |
| 5723 | |
Hamza Mahfooz | fc184db | 2024-02-08 16:23:29 -0500 | [diff] [blame] | 5724 | if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && |
| 5725 | is_psr_su))) |
| 5726 | goto ffu; |
| 5727 | |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5728 | if (!dm_crtc_state->mpo_requested) { |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5729 | if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) |
| 5730 | goto ffu; |
| 5731 | |
| 5732 | for (; flip_addrs->dirty_rect_count < num_clips; clips++) |
| 5733 | fill_dc_dirty_rect(new_plane_state->plane, |
Benjamin Cheng | 566b657 | 2023-03-12 20:47:39 -0400 | [diff] [blame] | 5734 | &dirty_rects[flip_addrs->dirty_rect_count], |
| 5735 | clips->x1, clips->y1, |
| 5736 | clips->x2 - clips->x1, clips->y2 - clips->y1, |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5737 | &flip_addrs->dirty_rect_count, |
| 5738 | false); |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5739 | return; |
| 5740 | } |
| 5741 | |
| 5742 | /* |
| 5743 | * MPO is requested. Add entire plane bounding box to dirty rects if |
| 5744 | * flipped to or damaged. |
| 5745 | * |
| 5746 | * If plane is moved or resized, also add old bounding box to dirty |
| 5747 | * rects. |
| 5748 | */ |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5749 | fb_changed = old_plane_state->fb->base.id != |
| 5750 | new_plane_state->fb->base.id; |
| 5751 | bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || |
| 5752 | old_plane_state->crtc_y != new_plane_state->crtc_y || |
| 5753 | old_plane_state->crtc_w != new_plane_state->crtc_w || |
| 5754 | old_plane_state->crtc_h != new_plane_state->crtc_h); |
| 5755 | |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5756 | drm_dbg(plane->dev, |
| 5757 | "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", |
| 5758 | new_plane_state->plane->base.id, |
| 5759 | bb_changed, fb_changed, num_clips); |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5760 | |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 5761 | *dirty_regions_changed = bb_changed; |
| 5762 | |
Hamza Mahfooz | af22d6a | 2023-06-21 15:19:05 -0400 | [diff] [blame] | 5763 | if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) |
| 5764 | goto ffu; |
| 5765 | |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5766 | if (bb_changed) { |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5767 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
| 5768 | new_plane_state->crtc_x, |
| 5769 | new_plane_state->crtc_y, |
| 5770 | new_plane_state->crtc_w, |
| 5771 | new_plane_state->crtc_h, &i, false); |
| 5772 | |
| 5773 | /* Add old plane bounding-box if plane is moved or resized */ |
| 5774 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
| 5775 | old_plane_state->crtc_x, |
| 5776 | old_plane_state->crtc_y, |
| 5777 | old_plane_state->crtc_w, |
| 5778 | old_plane_state->crtc_h, &i, false); |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5779 | } |
| 5780 | |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5781 | if (num_clips) { |
| 5782 | for (; i < num_clips; clips++) |
| 5783 | fill_dc_dirty_rect(new_plane_state->plane, |
| 5784 | &dirty_rects[i], clips->x1, |
| 5785 | clips->y1, clips->x2 - clips->x1, |
| 5786 | clips->y2 - clips->y1, &i, false); |
| 5787 | } else if (fb_changed && !bb_changed) { |
| 5788 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
| 5789 | new_plane_state->crtc_x, |
| 5790 | new_plane_state->crtc_y, |
| 5791 | new_plane_state->crtc_w, |
| 5792 | new_plane_state->crtc_h, &i, false); |
| 5793 | } |
| 5794 | |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5795 | flip_addrs->dirty_rect_count = i; |
Hamza Mahfooz | 30ebe41 | 2022-11-15 11:58:45 -0500 | [diff] [blame] | 5796 | return; |
| 5797 | |
| 5798 | ffu: |
| 5799 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, |
| 5800 | dm_crtc_state->base.mode.crtc_hdisplay, |
| 5801 | dm_crtc_state->base.mode.crtc_vdisplay, |
| 5802 | &flip_addrs->dirty_rect_count, true); |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 5803 | } |
| 5804 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 5805 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
| 5806 | const struct dm_connector_state *dm_state, |
| 5807 | struct dc_stream_state *stream) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5808 | { |
| 5809 | enum amdgpu_rmx_type rmx_type; |
| 5810 | |
| 5811 | struct rect src = { 0 }; /* viewport in composition space*/ |
| 5812 | struct rect dst = { 0 }; /* stream addressable area */ |
| 5813 | |
| 5814 | /* no mode. nothing to be done */ |
| 5815 | if (!mode) |
| 5816 | return; |
| 5817 | |
| 5818 | /* Full screen scaling by default */ |
| 5819 | src.width = mode->hdisplay; |
| 5820 | src.height = mode->vdisplay; |
| 5821 | dst.width = stream->timing.h_addressable; |
| 5822 | dst.height = stream->timing.v_addressable; |
| 5823 | |
Harry Wentland | f4791779a | 2017-12-18 13:48:12 -0500 | [diff] [blame] | 5824 | if (dm_state) { |
| 5825 | rmx_type = dm_state->scaling; |
| 5826 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { |
| 5827 | if (src.width * dst.height < |
| 5828 | src.height * dst.width) { |
| 5829 | /* height needs less upscaling/more downscaling */ |
| 5830 | dst.width = src.width * |
| 5831 | dst.height / src.height; |
| 5832 | } else { |
| 5833 | /* width needs less upscaling/more downscaling */ |
| 5834 | dst.height = src.height * |
| 5835 | dst.width / src.width; |
| 5836 | } |
| 5837 | } else if (rmx_type == RMX_CENTER) { |
| 5838 | dst = src; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5839 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5840 | |
Harry Wentland | f4791779a | 2017-12-18 13:48:12 -0500 | [diff] [blame] | 5841 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
| 5842 | dst.y = (stream->timing.v_addressable - dst.height) / 2; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5843 | |
Harry Wentland | f4791779a | 2017-12-18 13:48:12 -0500 | [diff] [blame] | 5844 | if (dm_state->underscan_enable) { |
| 5845 | dst.x += dm_state->underscan_hborder / 2; |
| 5846 | dst.y += dm_state->underscan_vborder / 2; |
| 5847 | dst.width -= dm_state->underscan_hborder; |
| 5848 | dst.height -= dm_state->underscan_vborder; |
| 5849 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5850 | } |
| 5851 | |
| 5852 | stream->src = src; |
| 5853 | stream->dst = dst; |
| 5854 | |
Luben Tuikov | 4711c03 | 2021-03-19 23:49:38 -0400 | [diff] [blame] | 5855 | DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", |
| 5856 | dst.x, dst.y, dst.width, dst.height); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5857 | |
| 5858 | } |
| 5859 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 5860 | static enum dc_color_depth |
Nicholas Kazlauskas | 42ba01f | 2019-05-22 12:00:55 -0400 | [diff] [blame] | 5861 | convert_color_depth_from_display_info(const struct drm_connector *connector, |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 5862 | bool is_y420, int requested_bpc) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5863 | { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 5864 | u8 bpc; |
Nicholas Kazlauskas | 01c2299 | 2019-08-21 11:27:13 -0400 | [diff] [blame] | 5865 | |
Stylon Wang | 1bc22f2 | 2019-09-20 15:40:55 +0800 | [diff] [blame] | 5866 | if (is_y420) { |
| 5867 | bpc = 8; |
| 5868 | |
| 5869 | /* Cap display bpc based on HDMI 2.0 HF-VSDB */ |
| 5870 | if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) |
| 5871 | bpc = 16; |
| 5872 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) |
| 5873 | bpc = 12; |
| 5874 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) |
| 5875 | bpc = 10; |
| 5876 | } else { |
| 5877 | bpc = (uint8_t)connector->display_info.bpc; |
| 5878 | /* Assume 8 bpc by default if no bpc is specified. */ |
| 5879 | bpc = bpc ? bpc : 8; |
| 5880 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5881 | |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 5882 | if (requested_bpc > 0) { |
Nicholas Kazlauskas | 01c2299 | 2019-08-21 11:27:13 -0400 | [diff] [blame] | 5883 | /* |
| 5884 | * Cap display bpc based on the user requested value. |
| 5885 | * |
| 5886 | * The value for state->max_bpc may not correctly updated |
| 5887 | * depending on when the connector gets added to the state |
| 5888 | * or if this was called outside of atomic check, so it |
| 5889 | * can't be used directly. |
| 5890 | */ |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 5891 | bpc = min_t(u8, bpc, requested_bpc); |
Nicholas Kazlauskas | 01c2299 | 2019-08-21 11:27:13 -0400 | [diff] [blame] | 5892 | |
Nicholas Kazlauskas | 1825fd3 | 2019-05-22 12:00:54 -0400 | [diff] [blame] | 5893 | /* Round down to the nearest even number. */ |
| 5894 | bpc = bpc - (bpc & 1); |
| 5895 | } |
Nicholas Kazlauskas | 07e3a1cf | 2018-11-15 17:21:34 -0500 | [diff] [blame] | 5896 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5897 | switch (bpc) { |
| 5898 | case 0: |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 5899 | /* |
| 5900 | * Temporary Work around, DRM doesn't parse color depth for |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5901 | * EDID revision before 1.4 |
| 5902 | * TODO: Fix edid parsing |
| 5903 | */ |
| 5904 | return COLOR_DEPTH_888; |
| 5905 | case 6: |
| 5906 | return COLOR_DEPTH_666; |
| 5907 | case 8: |
| 5908 | return COLOR_DEPTH_888; |
| 5909 | case 10: |
| 5910 | return COLOR_DEPTH_101010; |
| 5911 | case 12: |
| 5912 | return COLOR_DEPTH_121212; |
| 5913 | case 14: |
| 5914 | return COLOR_DEPTH_141414; |
| 5915 | case 16: |
| 5916 | return COLOR_DEPTH_161616; |
| 5917 | default: |
| 5918 | return COLOR_DEPTH_UNDEFINED; |
| 5919 | } |
| 5920 | } |
| 5921 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 5922 | static enum dc_aspect_ratio |
| 5923 | get_aspect_ratio(const struct drm_display_mode *mode_in) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5924 | { |
Leo (Sunpeng) Li | e11d414 | 2018-07-19 08:22:16 -0400 | [diff] [blame] | 5925 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
| 5926 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5927 | } |
| 5928 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 5929 | static enum dc_color_space |
Harry Wentland | 2e65682 | 2022-03-29 15:30:05 -0400 | [diff] [blame] | 5930 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, |
| 5931 | const struct drm_connector_state *connector_state) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5932 | { |
| 5933 | enum dc_color_space color_space = COLOR_SPACE_SRGB; |
| 5934 | |
Harry Wentland | 2e65682 | 2022-03-29 15:30:05 -0400 | [diff] [blame] | 5935 | switch (connector_state->colorspace) { |
| 5936 | case DRM_MODE_COLORIMETRY_BT601_YCC: |
| 5937 | if (dc_crtc_timing->flags.Y_ONLY) |
| 5938 | color_space = COLOR_SPACE_YCBCR601_LIMITED; |
| 5939 | else |
| 5940 | color_space = COLOR_SPACE_YCBCR601; |
| 5941 | break; |
| 5942 | case DRM_MODE_COLORIMETRY_BT709_YCC: |
| 5943 | if (dc_crtc_timing->flags.Y_ONLY) |
| 5944 | color_space = COLOR_SPACE_YCBCR709_LIMITED; |
| 5945 | else |
| 5946 | color_space = COLOR_SPACE_YCBCR709; |
| 5947 | break; |
| 5948 | case DRM_MODE_COLORIMETRY_OPRGB: |
| 5949 | color_space = COLOR_SPACE_ADOBERGB; |
| 5950 | break; |
| 5951 | case DRM_MODE_COLORIMETRY_BT2020_RGB: |
| 5952 | case DRM_MODE_COLORIMETRY_BT2020_YCC: |
| 5953 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) |
| 5954 | color_space = COLOR_SPACE_2020_RGB_FULLRANGE; |
| 5955 | else |
| 5956 | color_space = COLOR_SPACE_2020_YCBCR; |
| 5957 | break; |
| 5958 | case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 |
| 5959 | default: |
| 5960 | if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { |
| 5961 | color_space = COLOR_SPACE_SRGB; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5962 | /* |
| 5963 | * 27030khz is the separation point between HDTV and SDTV |
| 5964 | * according to HDMI spec, we use YCbCr709 and YCbCr601 |
| 5965 | * respectively |
| 5966 | */ |
Harry Wentland | 2e65682 | 2022-03-29 15:30:05 -0400 | [diff] [blame] | 5967 | } else if (dc_crtc_timing->pix_clk_100hz > 270300) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5968 | if (dc_crtc_timing->flags.Y_ONLY) |
| 5969 | color_space = |
| 5970 | COLOR_SPACE_YCBCR709_LIMITED; |
| 5971 | else |
| 5972 | color_space = COLOR_SPACE_YCBCR709; |
| 5973 | } else { |
| 5974 | if (dc_crtc_timing->flags.Y_ONLY) |
| 5975 | color_space = |
| 5976 | COLOR_SPACE_YCBCR601_LIMITED; |
| 5977 | else |
| 5978 | color_space = COLOR_SPACE_YCBCR601; |
| 5979 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 5980 | break; |
| 5981 | } |
| 5982 | |
| 5983 | return color_space; |
| 5984 | } |
| 5985 | |
Joshua Ashton | 4c4583f | 2023-09-12 15:01:56 -0100 | [diff] [blame] | 5986 | static enum display_content_type |
| 5987 | get_output_content_type(const struct drm_connector_state *connector_state) |
| 5988 | { |
| 5989 | switch (connector_state->content_type) { |
| 5990 | default: |
| 5991 | case DRM_MODE_CONTENT_TYPE_NO_DATA: |
| 5992 | return DISPLAY_CONTENT_TYPE_NO_DATA; |
| 5993 | case DRM_MODE_CONTENT_TYPE_GRAPHICS: |
| 5994 | return DISPLAY_CONTENT_TYPE_GRAPHICS; |
| 5995 | case DRM_MODE_CONTENT_TYPE_PHOTO: |
| 5996 | return DISPLAY_CONTENT_TYPE_PHOTO; |
| 5997 | case DRM_MODE_CONTENT_TYPE_CINEMA: |
| 5998 | return DISPLAY_CONTENT_TYPE_CINEMA; |
| 5999 | case DRM_MODE_CONTENT_TYPE_GAME: |
| 6000 | return DISPLAY_CONTENT_TYPE_GAME; |
| 6001 | } |
| 6002 | } |
| 6003 | |
Thomas Anderson | ea11731 | 2019-12-02 13:47:13 -0800 | [diff] [blame] | 6004 | static bool adjust_colour_depth_from_display_info( |
| 6005 | struct dc_crtc_timing *timing_out, |
| 6006 | const struct drm_display_info *info) |
Mikita Lipski | 400443e | 2018-07-03 09:42:51 -0400 | [diff] [blame] | 6007 | { |
Thomas Anderson | ea11731 | 2019-12-02 13:47:13 -0800 | [diff] [blame] | 6008 | enum dc_color_depth depth = timing_out->display_color_depth; |
Mikita Lipski | 400443e | 2018-07-03 09:42:51 -0400 | [diff] [blame] | 6009 | int normalized_clk; |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 6010 | |
Mikita Lipski | 400443e | 2018-07-03 09:42:51 -0400 | [diff] [blame] | 6011 | do { |
Ken Chalmers | 380604e | 2018-11-06 14:24:12 -0500 | [diff] [blame] | 6012 | normalized_clk = timing_out->pix_clk_100hz / 10; |
Mikita Lipski | 400443e | 2018-07-03 09:42:51 -0400 | [diff] [blame] | 6013 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ |
| 6014 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) |
| 6015 | normalized_clk /= 2; |
| 6016 | /* Adjusting pix clock following on HDMI spec based on colour depth */ |
Thomas Anderson | ea11731 | 2019-12-02 13:47:13 -0800 | [diff] [blame] | 6017 | switch (depth) { |
| 6018 | case COLOR_DEPTH_888: |
| 6019 | break; |
Mikita Lipski | 400443e | 2018-07-03 09:42:51 -0400 | [diff] [blame] | 6020 | case COLOR_DEPTH_101010: |
| 6021 | normalized_clk = (normalized_clk * 30) / 24; |
| 6022 | break; |
| 6023 | case COLOR_DEPTH_121212: |
| 6024 | normalized_clk = (normalized_clk * 36) / 24; |
| 6025 | break; |
| 6026 | case COLOR_DEPTH_161616: |
| 6027 | normalized_clk = (normalized_clk * 48) / 24; |
| 6028 | break; |
| 6029 | default: |
Thomas Anderson | ea11731 | 2019-12-02 13:47:13 -0800 | [diff] [blame] | 6030 | /* The above depths are the only ones valid for HDMI. */ |
| 6031 | return false; |
Mikita Lipski | 400443e | 2018-07-03 09:42:51 -0400 | [diff] [blame] | 6032 | } |
Thomas Anderson | ea11731 | 2019-12-02 13:47:13 -0800 | [diff] [blame] | 6033 | if (normalized_clk <= info->max_tmds_clock) { |
| 6034 | timing_out->display_color_depth = depth; |
| 6035 | return true; |
| 6036 | } |
| 6037 | } while (--depth > COLOR_DEPTH_666); |
| 6038 | return false; |
Mikita Lipski | 400443e | 2018-07-03 09:42:51 -0400 | [diff] [blame] | 6039 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6040 | |
Nicholas Kazlauskas | 42ba01f | 2019-05-22 12:00:55 -0400 | [diff] [blame] | 6041 | static void fill_stream_properties_from_drm_display_mode( |
| 6042 | struct dc_stream_state *stream, |
| 6043 | const struct drm_display_mode *mode_in, |
| 6044 | const struct drm_connector *connector, |
| 6045 | const struct drm_connector_state *connector_state, |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 6046 | const struct dc_stream_state *old_stream, |
| 6047 | int requested_bpc) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6048 | { |
| 6049 | struct dc_crtc_timing *timing_out = &stream->timing; |
Mikita Lipski | fe61a2f | 2018-07-04 09:27:02 -0400 | [diff] [blame] | 6050 | const struct drm_display_info *info = &connector->display_info; |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 6051 | struct amdgpu_dm_connector *aconnector = NULL; |
Wayne Lin | 1cb1d47 | 2019-09-04 06:12:22 +0800 | [diff] [blame] | 6052 | struct hdmi_vendor_infoframe hv_frame; |
| 6053 | struct hdmi_avi_infoframe avi_frame; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6054 | |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 6055 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) |
| 6056 | aconnector = to_amdgpu_dm_connector(connector); |
| 6057 | |
Wayne Lin | acf83f8 | 2019-10-21 13:24:36 +0800 | [diff] [blame] | 6058 | memset(&hv_frame, 0, sizeof(hv_frame)); |
| 6059 | memset(&avi_frame, 0, sizeof(avi_frame)); |
| 6060 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6061 | timing_out->h_border_left = 0; |
| 6062 | timing_out->h_border_right = 0; |
| 6063 | timing_out->v_border_top = 0; |
| 6064 | timing_out->v_border_bottom = 0; |
| 6065 | /* TODO: un-hardcode */ |
Mikita Lipski | fe61a2f | 2018-07-04 09:27:02 -0400 | [diff] [blame] | 6066 | if (drm_mode_is_420_only(info, mode_in) |
Jun Lei | ceb3dbb | 2018-11-09 09:21:21 -0500 | [diff] [blame] | 6067 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
Mikita Lipski | fe61a2f | 2018-07-04 09:27:02 -0400 | [diff] [blame] | 6068 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
Stylon Wang | d4252ee | 2019-08-20 14:48:37 -0400 | [diff] [blame] | 6069 | else if (drm_mode_is_420_also(info, mode_in) |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6070 | && aconnector |
Stylon Wang | d4252ee | 2019-08-20 14:48:37 -0400 | [diff] [blame] | 6071 | && aconnector->force_yuv420_output) |
| 6072 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
Maxime Ripard | c03d0b5 | 2022-01-20 16:16:13 +0100 | [diff] [blame] | 6073 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) |
Jun Lei | ceb3dbb | 2018-11-09 09:21:21 -0500 | [diff] [blame] | 6074 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6075 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; |
| 6076 | else |
| 6077 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; |
| 6078 | |
| 6079 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; |
| 6080 | timing_out->display_color_depth = convert_color_depth_from_display_info( |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 6081 | connector, |
| 6082 | (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), |
| 6083 | requested_bpc); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6084 | timing_out->scan_type = SCANNING_TYPE_NODATA; |
| 6085 | timing_out->hdmi_vic = 0; |
Bhawanpreet Lakha | b333730 | 2018-11-16 11:46:14 -0500 | [diff] [blame] | 6086 | |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6087 | if (old_stream) { |
Bhawanpreet Lakha | b333730 | 2018-11-16 11:46:14 -0500 | [diff] [blame] | 6088 | timing_out->vic = old_stream->timing.vic; |
| 6089 | timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; |
| 6090 | timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; |
| 6091 | } else { |
| 6092 | timing_out->vic = drm_match_cea_mode(mode_in); |
| 6093 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) |
| 6094 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; |
| 6095 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) |
| 6096 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; |
| 6097 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6098 | |
Wayne Lin | 1cb1d47 | 2019-09-04 06:12:22 +0800 | [diff] [blame] | 6099 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
| 6100 | drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); |
| 6101 | timing_out->vic = avi_frame.video_code; |
| 6102 | drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); |
| 6103 | timing_out->hdmi_vic = hv_frame.vic; |
| 6104 | } |
| 6105 | |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6106 | if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { |
Nikola Cornij | fe8858b | 2021-03-26 19:13:52 -0400 | [diff] [blame] | 6107 | timing_out->h_addressable = mode_in->hdisplay; |
| 6108 | timing_out->h_total = mode_in->htotal; |
| 6109 | timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; |
| 6110 | timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; |
| 6111 | timing_out->v_total = mode_in->vtotal; |
| 6112 | timing_out->v_addressable = mode_in->vdisplay; |
| 6113 | timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; |
| 6114 | timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; |
| 6115 | timing_out->pix_clk_100hz = mode_in->clock * 10; |
| 6116 | } else { |
| 6117 | timing_out->h_addressable = mode_in->crtc_hdisplay; |
| 6118 | timing_out->h_total = mode_in->crtc_htotal; |
| 6119 | timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; |
| 6120 | timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; |
| 6121 | timing_out->v_total = mode_in->crtc_vtotal; |
| 6122 | timing_out->v_addressable = mode_in->crtc_vdisplay; |
| 6123 | timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; |
| 6124 | timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; |
| 6125 | timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; |
| 6126 | } |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6127 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6128 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6129 | |
Alvin Lee | 285a705 | 2024-03-15 17:54:20 -0400 | [diff] [blame] | 6130 | stream->out_transfer_func.type = TF_TYPE_PREDEFINED; |
| 6131 | stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; |
Thomas Anderson | ea11731 | 2019-12-02 13:47:13 -0800 | [diff] [blame] | 6132 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
| 6133 | if (!adjust_colour_depth_from_display_info(timing_out, info) && |
| 6134 | drm_mode_is_420_also(info, mode_in) && |
| 6135 | timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { |
| 6136 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
| 6137 | adjust_colour_depth_from_display_info(timing_out, info); |
| 6138 | } |
| 6139 | } |
Joshua Ashton | 766f179 | 2023-01-10 20:12:21 +0000 | [diff] [blame] | 6140 | |
Harry Wentland | 2e65682 | 2022-03-29 15:30:05 -0400 | [diff] [blame] | 6141 | stream->output_color_space = get_output_color_space(timing_out, connector_state); |
Joshua Ashton | 4c4583f | 2023-09-12 15:01:56 -0100 | [diff] [blame] | 6142 | stream->content_type = get_output_content_type(connector_state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6143 | } |
| 6144 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 6145 | static void fill_audio_info(struct audio_info *audio_info, |
| 6146 | const struct drm_connector *drm_connector, |
| 6147 | const struct dc_sink *dc_sink) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6148 | { |
| 6149 | int i = 0; |
| 6150 | int cea_revision = 0; |
| 6151 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; |
| 6152 | |
| 6153 | audio_info->manufacture_id = edid_caps->manufacturer_id; |
| 6154 | audio_info->product_id = edid_caps->product_id; |
| 6155 | |
| 6156 | cea_revision = drm_connector->display_info.cea_rev; |
| 6157 | |
Nicholas Kazlauskas | 090afc1 | 2018-07-20 10:17:29 -0400 | [diff] [blame] | 6158 | strscpy(audio_info->display_name, |
Tom St Denis | d2b2562 | 2017-10-17 09:46:54 -0400 | [diff] [blame] | 6159 | edid_caps->display_name, |
Nicholas Kazlauskas | 090afc1 | 2018-07-20 10:17:29 -0400 | [diff] [blame] | 6160 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6161 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 6162 | if (cea_revision >= 3) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6163 | audio_info->mode_count = edid_caps->audio_mode_count; |
| 6164 | |
| 6165 | for (i = 0; i < audio_info->mode_count; ++i) { |
| 6166 | audio_info->modes[i].format_code = |
| 6167 | (enum audio_format_code) |
| 6168 | (edid_caps->audio_modes[i].format_code); |
| 6169 | audio_info->modes[i].channel_count = |
| 6170 | edid_caps->audio_modes[i].channel_count; |
| 6171 | audio_info->modes[i].sample_rates.all = |
| 6172 | edid_caps->audio_modes[i].sample_rate; |
| 6173 | audio_info->modes[i].sample_size = |
| 6174 | edid_caps->audio_modes[i].sample_size; |
| 6175 | } |
| 6176 | } |
| 6177 | |
| 6178 | audio_info->flags.all = edid_caps->speaker_flags; |
| 6179 | |
| 6180 | /* TODO: We only check for the progressive mode, check for interlace mode too */ |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 6181 | if (drm_connector->latency_present[0]) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6182 | audio_info->video_latency = drm_connector->video_latency[0]; |
| 6183 | audio_info->audio_latency = drm_connector->audio_latency[0]; |
| 6184 | } |
| 6185 | |
| 6186 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ |
| 6187 | |
| 6188 | } |
| 6189 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 6190 | static void |
| 6191 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, |
| 6192 | struct drm_display_mode *dst_mode) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6193 | { |
| 6194 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; |
| 6195 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; |
| 6196 | dst_mode->crtc_clock = src_mode->crtc_clock; |
| 6197 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; |
| 6198 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 6199 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6200 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
| 6201 | dst_mode->crtc_htotal = src_mode->crtc_htotal; |
| 6202 | dst_mode->crtc_hskew = src_mode->crtc_hskew; |
| 6203 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; |
| 6204 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; |
| 6205 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; |
| 6206 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; |
| 6207 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; |
| 6208 | } |
| 6209 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 6210 | static void |
| 6211 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, |
| 6212 | const struct drm_display_mode *native_mode, |
| 6213 | bool scale_enabled) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6214 | { |
| 6215 | if (scale_enabled) { |
| 6216 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); |
| 6217 | } else if (native_mode->clock == drm_mode->clock && |
| 6218 | native_mode->htotal == drm_mode->htotal && |
| 6219 | native_mode->vtotal == drm_mode->vtotal) { |
| 6220 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); |
| 6221 | } else { |
| 6222 | /* no scaling nor amdgpu inserted, no need to patch */ |
| 6223 | } |
| 6224 | } |
| 6225 | |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6226 | static struct dc_sink * |
Harry Wentland | 1fb9d7b | 2023-12-01 06:25:30 -0700 | [diff] [blame] | 6227 | create_fake_sink(struct dc_link *link) |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6228 | { |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6229 | struct dc_sink_init_data sink_init_data = { 0 }; |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6230 | struct dc_sink *sink = NULL; |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 6231 | |
Harry Wentland | 1fb9d7b | 2023-12-01 06:25:30 -0700 | [diff] [blame] | 6232 | sink_init_data.link = link; |
| 6233 | sink_init_data.sink_signal = link->connector_signal; |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6234 | |
| 6235 | sink = dc_sink_create(&sink_init_data); |
Ernst Sjöstrand | 423788c | 2017-11-07 21:06:59 +0100 | [diff] [blame] | 6236 | if (!sink) { |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6237 | DRM_ERROR("Failed to create sink!\n"); |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6238 | return NULL; |
Ernst Sjöstrand | 423788c | 2017-11-07 21:06:59 +0100 | [diff] [blame] | 6239 | } |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6240 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6241 | |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6242 | return sink; |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6243 | } |
| 6244 | |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6245 | static void set_multisync_trigger_params( |
| 6246 | struct dc_stream_state *stream) |
| 6247 | { |
Mikita Lipski | ec37218 | 2020-09-29 11:24:08 -0400 | [diff] [blame] | 6248 | struct dc_stream_state *master = NULL; |
| 6249 | |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6250 | if (stream->triggered_crtc_reset.enabled) { |
Mikita Lipski | ec37218 | 2020-09-29 11:24:08 -0400 | [diff] [blame] | 6251 | master = stream->triggered_crtc_reset.event_source; |
| 6252 | stream->triggered_crtc_reset.event = |
| 6253 | master->timing.flags.VSYNC_POSITIVE_POLARITY ? |
| 6254 | CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; |
| 6255 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6256 | } |
| 6257 | } |
| 6258 | |
| 6259 | static void set_master_stream(struct dc_stream_state *stream_set[], |
| 6260 | int stream_count) |
| 6261 | { |
| 6262 | int j, highest_rfr = 0, master_stream = 0; |
| 6263 | |
| 6264 | for (j = 0; j < stream_count; j++) { |
| 6265 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { |
| 6266 | int refresh_rate = 0; |
| 6267 | |
Ken Chalmers | 380604e | 2018-11-06 14:24:12 -0500 | [diff] [blame] | 6268 | refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6269 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); |
| 6270 | if (refresh_rate > highest_rfr) { |
| 6271 | highest_rfr = refresh_rate; |
| 6272 | master_stream = j; |
| 6273 | } |
| 6274 | } |
| 6275 | } |
| 6276 | for (j = 0; j < stream_count; j++) { |
Mikita Lipski | 03736f4 | 2017-12-18 10:34:56 -0500 | [diff] [blame] | 6277 | if (stream_set[j]) |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6278 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
| 6279 | } |
| 6280 | } |
| 6281 | |
| 6282 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) |
| 6283 | { |
| 6284 | int i = 0; |
Mikita Lipski | ec37218 | 2020-09-29 11:24:08 -0400 | [diff] [blame] | 6285 | struct dc_stream_state *stream; |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6286 | |
| 6287 | if (context->stream_count < 2) |
| 6288 | return; |
| 6289 | for (i = 0; i < context->stream_count ; i++) { |
| 6290 | if (!context->streams[i]) |
| 6291 | continue; |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 6292 | /* |
| 6293 | * TODO: add a function to read AMD VSDB bits and set |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6294 | * crtc_sync_master.multi_sync_enabled flag |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 6295 | * For now it's set to false |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6296 | */ |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6297 | } |
Mikita Lipski | ec37218 | 2020-09-29 11:24:08 -0400 | [diff] [blame] | 6298 | |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6299 | set_master_stream(context->streams, context->stream_count); |
Mikita Lipski | ec37218 | 2020-09-29 11:24:08 -0400 | [diff] [blame] | 6300 | |
| 6301 | for (i = 0; i < context->stream_count ; i++) { |
| 6302 | stream = context->streams[i]; |
| 6303 | |
| 6304 | if (!stream) |
| 6305 | continue; |
| 6306 | |
| 6307 | set_multisync_trigger_params(stream); |
| 6308 | } |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 6309 | } |
| 6310 | |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6311 | /** |
| 6312 | * DOC: FreeSync Video |
| 6313 | * |
| 6314 | * When a userspace application wants to play a video, the content follows a |
| 6315 | * standard format definition that usually specifies the FPS for that format. |
| 6316 | * The below list illustrates some video format and the expected FPS, |
| 6317 | * respectively: |
| 6318 | * |
| 6319 | * - TV/NTSC (23.976 FPS) |
| 6320 | * - Cinema (24 FPS) |
| 6321 | * - TV/PAL (25 FPS) |
| 6322 | * - TV/NTSC (29.97 FPS) |
| 6323 | * - TV/NTSC (30 FPS) |
| 6324 | * - Cinema HFR (48 FPS) |
| 6325 | * - TV/PAL (50 FPS) |
| 6326 | * - Commonly used (60 FPS) |
| 6327 | * - Multiples of 24 (48,72,96 FPS) |
| 6328 | * |
| 6329 | * The list of standards video format is not huge and can be added to the |
| 6330 | * connector modeset list beforehand. With that, userspace can leverage |
| 6331 | * FreeSync to extends the front porch in order to attain the target refresh |
| 6332 | * rate. Such a switch will happen seamlessly, without screen blanking or |
| 6333 | * reprogramming of the output in any other way. If the userspace requests a |
| 6334 | * modesetting change compatible with FreeSync modes that only differ in the |
| 6335 | * refresh rate, DC will skip the full update and avoid blink during the |
| 6336 | * transition. For example, the video player can change the modesetting from |
| 6337 | * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without |
| 6338 | * causing any display blink. This same concept can be applied to a mode |
| 6339 | * setting change. |
| 6340 | */ |
| 6341 | static struct drm_display_mode * |
| 6342 | get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, |
| 6343 | bool use_probed_modes) |
| 6344 | { |
| 6345 | struct drm_display_mode *m, *m_pref = NULL; |
| 6346 | u16 current_refresh, highest_refresh; |
| 6347 | struct list_head *list_head = use_probed_modes ? |
| 6348 | &aconnector->base.probed_modes : |
| 6349 | &aconnector->base.modes; |
| 6350 | |
Alex Hung | cf82a80 | 2024-03-15 21:25:25 -0600 | [diff] [blame] | 6351 | if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 6352 | return NULL; |
| 6353 | |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6354 | if (aconnector->freesync_vid_base.clock != 0) |
| 6355 | return &aconnector->freesync_vid_base; |
| 6356 | |
| 6357 | /* Find the preferred mode */ |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 6358 | list_for_each_entry(m, list_head, head) { |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6359 | if (m->type & DRM_MODE_TYPE_PREFERRED) { |
| 6360 | m_pref = m; |
| 6361 | break; |
| 6362 | } |
| 6363 | } |
| 6364 | |
| 6365 | if (!m_pref) { |
| 6366 | /* Probably an EDID with no preferred mode. Fallback to first entry */ |
| 6367 | m_pref = list_first_entry_or_null( |
| 6368 | &aconnector->base.modes, struct drm_display_mode, head); |
| 6369 | if (!m_pref) { |
| 6370 | DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); |
| 6371 | return NULL; |
| 6372 | } |
| 6373 | } |
| 6374 | |
| 6375 | highest_refresh = drm_mode_vrefresh(m_pref); |
| 6376 | |
| 6377 | /* |
| 6378 | * Find the mode with highest refresh rate with same resolution. |
| 6379 | * For some monitors, preferred mode is not the mode with highest |
| 6380 | * supported refresh rate. |
| 6381 | */ |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 6382 | list_for_each_entry(m, list_head, head) { |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6383 | current_refresh = drm_mode_vrefresh(m); |
| 6384 | |
| 6385 | if (m->hdisplay == m_pref->hdisplay && |
| 6386 | m->vdisplay == m_pref->vdisplay && |
| 6387 | highest_refresh < current_refresh) { |
| 6388 | highest_refresh = current_refresh; |
| 6389 | m_pref = m; |
| 6390 | } |
| 6391 | } |
| 6392 | |
| 6393 | drm_mode_copy(&aconnector->freesync_vid_base, m_pref); |
| 6394 | return m_pref; |
| 6395 | } |
| 6396 | |
| 6397 | static bool is_freesync_video_mode(const struct drm_display_mode *mode, |
| 6398 | struct amdgpu_dm_connector *aconnector) |
| 6399 | { |
| 6400 | struct drm_display_mode *high_mode; |
| 6401 | int timing_diff; |
| 6402 | |
| 6403 | high_mode = get_highest_refresh_rate_mode(aconnector, false); |
| 6404 | if (!high_mode || !mode) |
| 6405 | return false; |
| 6406 | |
| 6407 | timing_diff = high_mode->vtotal - mode->vtotal; |
| 6408 | |
| 6409 | if (high_mode->clock == 0 || high_mode->clock != mode->clock || |
| 6410 | high_mode->hdisplay != mode->hdisplay || |
| 6411 | high_mode->vdisplay != mode->vdisplay || |
| 6412 | high_mode->hsync_start != mode->hsync_start || |
| 6413 | high_mode->hsync_end != mode->hsync_end || |
| 6414 | high_mode->htotal != mode->htotal || |
| 6415 | high_mode->hskew != mode->hskew || |
| 6416 | high_mode->vscan != mode->vscan || |
| 6417 | high_mode->vsync_start - mode->vsync_start != timing_diff || |
| 6418 | high_mode->vsync_end - mode->vsync_end != timing_diff) |
| 6419 | return false; |
| 6420 | else |
| 6421 | return true; |
| 6422 | } |
| 6423 | |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 6424 | #if defined(CONFIG_DRM_AMD_DC_FP) |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6425 | static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6426 | struct dc_sink *sink, struct dc_stream_state *stream, |
| 6427 | struct dsc_dec_dpcd_caps *dsc_caps) |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6428 | { |
| 6429 | stream->timing.flags.DSC = 0; |
Mario Limonciello | 63ad5371 | 2022-01-05 12:48:16 -0600 | [diff] [blame] | 6430 | dsc_caps->is_dsc_supported = false; |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6431 | |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6432 | if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6433 | sink->sink_signal == SIGNAL_TYPE_EDP)) { |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6434 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || |
| 6435 | sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) |
| 6436 | dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, |
| 6437 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, |
| 6438 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, |
| 6439 | dsc_caps); |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6440 | } |
| 6441 | } |
| 6442 | |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6443 | static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, |
| 6444 | struct dc_sink *sink, struct dc_stream_state *stream, |
| 6445 | struct dsc_dec_dpcd_caps *dsc_caps, |
| 6446 | uint32_t max_dsc_target_bpp_limit_override) |
| 6447 | { |
| 6448 | const struct dc_link_settings *verified_link_cap = NULL; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 6449 | u32 link_bw_in_kbps; |
| 6450 | u32 edp_min_bpp_x16, edp_max_bpp_x16; |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6451 | struct dc *dc = sink->ctx->dc; |
| 6452 | struct dc_dsc_bw_range bw_range = {0}; |
| 6453 | struct dc_dsc_config dsc_cfg = {0}; |
Mike Hsieh | de534c1 | 2023-01-10 10:52:03 +0800 | [diff] [blame] | 6454 | struct dc_dsc_config_options dsc_options = {0}; |
| 6455 | |
| 6456 | dc_dsc_get_default_config_option(dc, &dsc_options); |
| 6457 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6458 | |
| 6459 | verified_link_cap = dc_link_get_link_cap(stream->link); |
| 6460 | link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); |
| 6461 | edp_min_bpp_x16 = 8 * 16; |
| 6462 | edp_max_bpp_x16 = 8 * 16; |
| 6463 | |
| 6464 | if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) |
| 6465 | edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; |
| 6466 | |
| 6467 | if (edp_max_bpp_x16 < edp_min_bpp_x16) |
| 6468 | edp_min_bpp_x16 = edp_max_bpp_x16; |
| 6469 | |
| 6470 | if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], |
| 6471 | dc->debug.dsc_min_slice_height_override, |
| 6472 | edp_min_bpp_x16, edp_max_bpp_x16, |
| 6473 | dsc_caps, |
| 6474 | &stream->timing, |
George Shen | 63c0bf9 | 2023-06-16 22:35:46 -0400 | [diff] [blame] | 6475 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6476 | &bw_range)) { |
| 6477 | |
| 6478 | if (bw_range.max_kbps < link_bw_in_kbps) { |
| 6479 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], |
| 6480 | dsc_caps, |
Mike Hsieh | de534c1 | 2023-01-10 10:52:03 +0800 | [diff] [blame] | 6481 | &dsc_options, |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6482 | 0, |
| 6483 | &stream->timing, |
George Shen | 63c0bf9 | 2023-06-16 22:35:46 -0400 | [diff] [blame] | 6484 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6485 | &dsc_cfg)) { |
| 6486 | stream->timing.dsc_cfg = dsc_cfg; |
| 6487 | stream->timing.flags.DSC = 1; |
| 6488 | stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; |
| 6489 | } |
| 6490 | return; |
| 6491 | } |
| 6492 | } |
| 6493 | |
| 6494 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], |
| 6495 | dsc_caps, |
Mike Hsieh | de534c1 | 2023-01-10 10:52:03 +0800 | [diff] [blame] | 6496 | &dsc_options, |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6497 | link_bw_in_kbps, |
| 6498 | &stream->timing, |
George Shen | 63c0bf9 | 2023-06-16 22:35:46 -0400 | [diff] [blame] | 6499 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6500 | &dsc_cfg)) { |
| 6501 | stream->timing.dsc_cfg = dsc_cfg; |
| 6502 | stream->timing.flags.DSC = 1; |
| 6503 | } |
| 6504 | } |
| 6505 | |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6506 | static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6507 | struct dc_sink *sink, struct dc_stream_state *stream, |
| 6508 | struct dsc_dec_dpcd_caps *dsc_caps) |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6509 | { |
| 6510 | struct drm_connector *drm_connector = &aconnector->base; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 6511 | u32 link_bandwidth_kbps; |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6512 | struct dc *dc = sink->ctx->dc; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 6513 | u32 max_supported_bw_in_kbps, timing_bw_in_kbps; |
| 6514 | u32 dsc_max_supported_bw_in_kbps; |
| 6515 | u32 max_dsc_target_bpp_limit_override = |
Hamza Mahfooz | 6e5abe9 | 2022-10-24 14:53:24 -0400 | [diff] [blame] | 6516 | drm_connector->display_info.max_dsc_bpp; |
Mike Hsieh | de534c1 | 2023-01-10 10:52:03 +0800 | [diff] [blame] | 6517 | struct dc_dsc_config_options dsc_options = {0}; |
| 6518 | |
| 6519 | dc_dsc_get_default_config_option(dc, &dsc_options); |
| 6520 | dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6521 | |
| 6522 | link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, |
| 6523 | dc_link_get_link_cap(aconnector->dc_link)); |
Prike Liang | de7cc1b | 2022-01-17 15:21:29 +0800 | [diff] [blame] | 6524 | |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6525 | /* Set DSC policy according to dsc_clock_en */ |
| 6526 | dc_dsc_policy_set_enable_dsc_when_not_needed( |
| 6527 | aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); |
| 6528 | |
Alex Hung | db39d57 | 2024-06-06 19:49:23 -0600 | [diff] [blame] | 6529 | if (sink->sink_signal == SIGNAL_TYPE_EDP && |
Ian Chen | c17a34e | 2022-08-04 15:44:27 +0800 | [diff] [blame] | 6530 | !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && |
Mikita Lipski | 2665f63 | 2021-10-20 08:51:04 -0400 | [diff] [blame] | 6531 | dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { |
| 6532 | |
| 6533 | apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); |
| 6534 | |
Alex Hung | db39d57 | 2024-06-06 19:49:23 -0600 | [diff] [blame] | 6535 | } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6536 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { |
| 6537 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6538 | dsc_caps, |
Mike Hsieh | de534c1 | 2023-01-10 10:52:03 +0800 | [diff] [blame] | 6539 | &dsc_options, |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6540 | link_bandwidth_kbps, |
| 6541 | &stream->timing, |
George Shen | 63c0bf9 | 2023-06-16 22:35:46 -0400 | [diff] [blame] | 6542 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6543 | &stream->timing.dsc_cfg)) { |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6544 | stream->timing.flags.DSC = 1; |
Fangzhi Zuo | 3715112 | 2024-08-02 15:03:39 -0400 | [diff] [blame] | 6545 | DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from SST RX\n", |
| 6546 | __func__, drm_connector->name); |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6547 | } |
| 6548 | } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { |
George Shen | 63c0bf9 | 2023-06-16 22:35:46 -0400 | [diff] [blame] | 6549 | timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, |
| 6550 | dc_link_get_highest_encoding_format(aconnector->dc_link)); |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6551 | max_supported_bw_in_kbps = link_bandwidth_kbps; |
| 6552 | dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; |
| 6553 | |
| 6554 | if (timing_bw_in_kbps > max_supported_bw_in_kbps && |
| 6555 | max_supported_bw_in_kbps > 0 && |
| 6556 | dsc_max_supported_bw_in_kbps > 0) |
| 6557 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], |
| 6558 | dsc_caps, |
Mike Hsieh | de534c1 | 2023-01-10 10:52:03 +0800 | [diff] [blame] | 6559 | &dsc_options, |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6560 | dsc_max_supported_bw_in_kbps, |
| 6561 | &stream->timing, |
George Shen | 63c0bf9 | 2023-06-16 22:35:46 -0400 | [diff] [blame] | 6562 | dc_link_get_highest_encoding_format(aconnector->dc_link), |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6563 | &stream->timing.dsc_cfg)) { |
| 6564 | stream->timing.flags.DSC = 1; |
Fangzhi Zuo | 3715112 | 2024-08-02 15:03:39 -0400 | [diff] [blame] | 6565 | DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from DP-HDMI PCON\n", |
Fangzhi Zuo | 50b1f44 | 2021-11-24 11:43:06 -0500 | [diff] [blame] | 6566 | __func__, drm_connector->name); |
| 6567 | } |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6568 | } |
| 6569 | } |
| 6570 | |
| 6571 | /* Overwrite the stream flag if DSC is enabled through debugfs */ |
| 6572 | if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) |
| 6573 | stream->timing.flags.DSC = 1; |
| 6574 | |
| 6575 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) |
| 6576 | stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; |
| 6577 | |
| 6578 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) |
| 6579 | stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; |
| 6580 | |
| 6581 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) |
| 6582 | stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6583 | } |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 6584 | #endif |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6585 | |
Maíra Canal | f11d937 | 2022-02-22 10:17:01 -0300 | [diff] [blame] | 6586 | static struct dc_stream_state * |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6587 | create_stream_for_sink(struct drm_connector *connector, |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 6588 | const struct drm_display_mode *drm_mode, |
Bhawanpreet Lakha | b333730 | 2018-11-16 11:46:14 -0500 | [diff] [blame] | 6589 | const struct dm_connector_state *dm_state, |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 6590 | const struct dc_stream_state *old_stream, |
| 6591 | int requested_bpc) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6592 | { |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6593 | struct amdgpu_dm_connector *aconnector = NULL; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6594 | struct drm_display_mode *preferred_mode = NULL; |
Harry Wentland | cb841d2 | 2022-04-01 13:45:29 -0400 | [diff] [blame] | 6595 | const struct drm_connector_state *con_state = &dm_state->base; |
Harry Wentland | 0971c40 | 2017-07-27 09:33:33 -0400 | [diff] [blame] | 6596 | struct dc_stream_state *stream = NULL; |
Ville Syrjälä | 0a204ce | 2022-11-07 21:25:39 +0200 | [diff] [blame] | 6597 | struct drm_display_mode mode; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6598 | struct drm_display_mode saved_mode; |
| 6599 | struct drm_display_mode *freesync_mode = NULL; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6600 | bool native_mode_found = false; |
Nicholas Kazlauskas | b078160 | 2021-05-19 16:12:19 -0400 | [diff] [blame] | 6601 | bool recalculate_timing = false; |
Harry Wentland | cb841d2 | 2022-04-01 13:45:29 -0400 | [diff] [blame] | 6602 | bool scale = dm_state->scaling != RMX_OFF; |
Bhawanpreet Lakha | b333730 | 2018-11-16 11:46:14 -0500 | [diff] [blame] | 6603 | int mode_refresh; |
Jerry (Fangzhi) Zuo | 58124bf | 2018-11-27 10:51:12 -0500 | [diff] [blame] | 6604 | int preferred_refresh = 0; |
Ma Hanghong | b1a98cf8 | 2022-10-20 11:46:56 -0400 | [diff] [blame] | 6605 | enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 6606 | #if defined(CONFIG_DRM_AMD_DC_FP) |
David Francis | df2f101 | 2019-06-19 14:30:59 -0400 | [diff] [blame] | 6607 | struct dsc_dec_dpcd_caps dsc_caps; |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 6608 | #endif |
Harry Wentland | 1fb9d7b | 2023-12-01 06:25:30 -0700 | [diff] [blame] | 6609 | struct dc_link *link = NULL; |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6610 | struct dc_sink *sink = NULL; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6611 | |
Ville Syrjälä | 0a204ce | 2022-11-07 21:25:39 +0200 | [diff] [blame] | 6612 | drm_mode_init(&mode, drm_mode); |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6613 | memset(&saved_mode, 0, sizeof(saved_mode)); |
| 6614 | |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6615 | if (connector == NULL) { |
| 6616 | DRM_ERROR("connector is NULL!\n"); |
Harry Wentland | 64245fa | 2017-12-18 13:46:19 -0500 | [diff] [blame] | 6617 | return stream; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6618 | } |
| 6619 | |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6620 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { |
| 6621 | aconnector = NULL; |
| 6622 | aconnector = to_amdgpu_dm_connector(connector); |
Harry Wentland | 1fb9d7b | 2023-12-01 06:25:30 -0700 | [diff] [blame] | 6623 | link = aconnector->dc_link; |
| 6624 | } else { |
| 6625 | struct drm_writeback_connector *wbcon = NULL; |
| 6626 | struct amdgpu_dm_wb_connector *dm_wbcon = NULL; |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6627 | |
Harry Wentland | 1fb9d7b | 2023-12-01 06:25:30 -0700 | [diff] [blame] | 6628 | wbcon = drm_connector_to_writeback(connector); |
| 6629 | dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); |
| 6630 | link = dm_wbcon->link; |
| 6631 | } |
| 6632 | |
| 6633 | if (!aconnector || !aconnector->dc_sink) { |
| 6634 | sink = create_fake_sink(link); |
Jerry (Fangzhi) Zuo | e3fa5c4 | 2019-01-23 11:41:18 -0500 | [diff] [blame] | 6635 | if (!sink) |
| 6636 | return stream; |
Harry Wentland | 1fb9d7b | 2023-12-01 06:25:30 -0700 | [diff] [blame] | 6637 | |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6638 | } else { |
| 6639 | sink = aconnector->dc_sink; |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 6640 | dc_sink_retain(sink); |
Jerry Zuo | f4ac176 | 2017-09-08 11:52:45 -0400 | [diff] [blame] | 6641 | } |
Harry Wentland | 2e0ac3d | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6642 | |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6643 | stream = dc_create_stream_for_sink(sink); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6644 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 6645 | if (stream == NULL) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6646 | DRM_ERROR("Failed to create stream for sink!\n"); |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6647 | goto finish; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6648 | } |
| 6649 | |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6650 | /* We leave this NULL for writeback connectors */ |
Jun Lei | ceb3dbb | 2018-11-09 09:21:21 -0500 | [diff] [blame] | 6651 | stream->dm_stream_context = aconnector; |
| 6652 | |
Wayne Lin | 4a36fcb | 2019-09-19 17:41:02 +0800 | [diff] [blame] | 6653 | stream->timing.flags.LTE_340MCSC_SCRAMBLE = |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6654 | connector->display_info.hdmi.scdc.scrambling.low_rates; |
Wayne Lin | 4a36fcb | 2019-09-19 17:41:02 +0800 | [diff] [blame] | 6655 | |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6656 | list_for_each_entry(preferred_mode, &connector->modes, head) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6657 | /* Search for preferred mode */ |
| 6658 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { |
| 6659 | native_mode_found = true; |
| 6660 | break; |
| 6661 | } |
| 6662 | } |
| 6663 | if (!native_mode_found) |
| 6664 | preferred_mode = list_first_entry_or_null( |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6665 | &connector->modes, |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6666 | struct drm_display_mode, |
| 6667 | head); |
| 6668 | |
Bhawanpreet Lakha | b333730 | 2018-11-16 11:46:14 -0500 | [diff] [blame] | 6669 | mode_refresh = drm_mode_vrefresh(&mode); |
| 6670 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 6671 | if (preferred_mode == NULL) { |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 6672 | /* |
| 6673 | * This may not be an error, the use case is when we have no |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6674 | * usermode calls to reset and set mode upon hotplug. In this |
| 6675 | * case, we call set mode ourselves to restore the previous mode |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 6676 | * and the modelist may not be filled in time. |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6677 | */ |
Harry Wentland | f1ad2f5 | 2017-09-12 20:04:48 -0400 | [diff] [blame] | 6678 | DRM_DEBUG_DRIVER("No preferred mode found\n"); |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6679 | } else if (aconnector) { |
Alex Deucher | 3c591fa | 2024-02-27 13:08:12 -0500 | [diff] [blame] | 6680 | recalculate_timing = amdgpu_freesync_vid_mode && |
| 6681 | is_freesync_video_mode(&mode, aconnector); |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6682 | if (recalculate_timing) { |
| 6683 | freesync_mode = get_highest_refresh_rate_mode(aconnector, false); |
Ville Syrjälä | 426c89a | 2022-02-18 12:03:45 +0200 | [diff] [blame] | 6684 | drm_mode_copy(&saved_mode, &mode); |
Tom Chung | 79f3e38 | 2024-01-30 15:34:08 +0800 | [diff] [blame] | 6685 | saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; |
Ville Syrjälä | 426c89a | 2022-02-18 12:03:45 +0200 | [diff] [blame] | 6686 | drm_mode_copy(&mode, freesync_mode); |
Tom Chung | 79f3e38 | 2024-01-30 15:34:08 +0800 | [diff] [blame] | 6687 | mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6688 | } else { |
| 6689 | decide_crtc_timing_for_drm_display_mode( |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6690 | &mode, preferred_mode, scale); |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6691 | |
Nicholas Kazlauskas | b078160 | 2021-05-19 16:12:19 -0400 | [diff] [blame] | 6692 | preferred_refresh = drm_mode_vrefresh(preferred_mode); |
| 6693 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6694 | } |
| 6695 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6696 | if (recalculate_timing) |
| 6697 | drm_mode_set_crtcinfo(&saved_mode, 0); |
Jerry (Fangzhi) Zuo | f783577 | 2018-01-17 13:24:28 -0500 | [diff] [blame] | 6698 | |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6699 | /* |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 6700 | * If scaling is enabled and refresh rate didn't change |
| 6701 | * we copy the vic and polarities of the old timings |
| 6702 | */ |
Nicholas Kazlauskas | b078160 | 2021-05-19 16:12:19 -0400 | [diff] [blame] | 6703 | if (!scale || mode_refresh != preferred_refresh) |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6704 | fill_stream_properties_from_drm_display_mode( |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6705 | stream, &mode, connector, con_state, NULL, |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6706 | requested_bpc); |
Bhawanpreet Lakha | b333730 | 2018-11-16 11:46:14 -0500 | [diff] [blame] | 6707 | else |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6708 | fill_stream_properties_from_drm_display_mode( |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6709 | stream, &mode, connector, con_state, old_stream, |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 6710 | requested_bpc); |
Bhawanpreet Lakha | b333730 | 2018-11-16 11:46:14 -0500 | [diff] [blame] | 6711 | |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6712 | /* The rest isn't needed for writeback connectors */ |
| 6713 | if (!aconnector) |
| 6714 | goto finish; |
| 6715 | |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 6716 | if (aconnector->timing_changed) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 6717 | drm_dbg(aconnector->base.dev, |
| 6718 | "overriding timing for automated test, bpc %d, changing to %d\n", |
| 6719 | stream->timing.display_color_depth, |
| 6720 | aconnector->timing_requested->display_color_depth); |
Qingqing Zhuo | 028c4cc | 2022-10-03 17:14:13 -0400 | [diff] [blame] | 6721 | stream->timing = *aconnector->timing_requested; |
| 6722 | } |
| 6723 | |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 6724 | #if defined(CONFIG_DRM_AMD_DC_FP) |
Fangzhi Zuo | 998b7ad | 2021-05-13 19:01:55 -0400 | [diff] [blame] | 6725 | /* SST DSC determination policy */ |
| 6726 | update_dsc_caps(aconnector, sink, stream, &dsc_caps); |
| 6727 | if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) |
| 6728 | apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 6729 | #endif |
Wenjing Liu | 39a4eb8 | 2019-05-16 13:01:51 -0400 | [diff] [blame] | 6730 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6731 | update_stream_scaling_settings(&mode, dm_state, stream); |
| 6732 | |
| 6733 | fill_audio_info( |
| 6734 | &stream->audio_info, |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 6735 | connector, |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6736 | sink); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6737 | |
Jun Lei | ceb3dbb | 2018-11-09 09:21:21 -0500 | [diff] [blame] | 6738 | update_stream_signal(stream, sink); |
Harry Wentland | 9182b4c | 2017-12-18 12:01:30 -0500 | [diff] [blame] | 6739 | |
Wayne Lin | d832fc3b | 2019-09-04 05:31:16 +0800 | [diff] [blame] | 6740 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
Wayne Lin | 75f77aa | 2020-07-15 16:45:09 +0800 | [diff] [blame] | 6741 | mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); |
Harry Wentland | 5daa294 | 2024-03-12 11:21:32 -0400 | [diff] [blame] | 6742 | |
Harry Wentland | 1abfb9f | 2024-03-12 11:55:52 -0400 | [diff] [blame] | 6743 | if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || |
| 6744 | stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || |
| 6745 | stream->signal == SIGNAL_TYPE_EDP) { |
Alex Hung | 05af800 | 2024-09-06 11:39:18 -0600 | [diff] [blame] | 6746 | const struct dc_edid_caps *edid_caps; |
| 6747 | unsigned int disable_colorimetry = 0; |
| 6748 | |
| 6749 | if (aconnector->dc_sink) { |
| 6750 | edid_caps = &aconnector->dc_sink->edid_caps; |
| 6751 | disable_colorimetry = edid_caps->panel_patch.disable_colorimetry; |
| 6752 | } |
| 6753 | |
Roman Li | 8a488f5 | 2020-06-26 10:27:31 -0400 | [diff] [blame] | 6754 | // |
| 6755 | // should decide stream support vsc sdp colorimetry capability |
| 6756 | // before building vsc info packet |
| 6757 | // |
Harry Wentland | 038e2e2 | 2024-03-21 11:13:38 -0400 | [diff] [blame] | 6758 | stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && |
Alex Hung | 05af800 | 2024-09-06 11:39:18 -0600 | [diff] [blame] | 6759 | stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && |
| 6760 | !disable_colorimetry; |
Harry Wentland | 038e2e2 | 2024-03-21 11:13:38 -0400 | [diff] [blame] | 6761 | |
Alvin Lee | 285a705 | 2024-03-15 17:54:20 -0400 | [diff] [blame] | 6762 | if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) |
Ma Hanghong | b1a98cf8 | 2022-10-20 11:46:56 -0400 | [diff] [blame] | 6763 | tf = TRANSFER_FUNC_GAMMA_22; |
| 6764 | mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); |
Tom Chung | b8d9d5f | 2024-10-29 15:38:16 +0800 | [diff] [blame] | 6765 | aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; |
Roman Li | 1a36568 | 2021-06-08 17:32:16 -0400 | [diff] [blame] | 6766 | |
Roman Li | 8c32230 | 2019-09-20 19:03:17 -0400 | [diff] [blame] | 6767 | } |
Mikita Lipski | aed1530 | 2018-05-01 11:33:25 -0400 | [diff] [blame] | 6768 | finish: |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 6769 | dc_sink_release(sink); |
Harry Wentland | 9e3efe3 | 2018-03-15 15:08:04 -0400 | [diff] [blame] | 6770 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6771 | return stream; |
| 6772 | } |
| 6773 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6774 | static enum drm_connector_status |
| 6775 | amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) |
| 6776 | { |
| 6777 | bool connected; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 6778 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6779 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 6780 | /* |
| 6781 | * Notes: |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6782 | * 1. This interface is NOT called in context of HPD irq. |
| 6783 | * 2. This interface *is called* in context of user-mode ioctl. Which |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 6784 | * makes it a bad place for *any* MST-related activity. |
| 6785 | */ |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6786 | |
Harry Wentland | 8580d60 | 2017-08-17 14:58:07 -0400 | [diff] [blame] | 6787 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && |
| 6788 | !aconnector->fake_enable) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6789 | connected = (aconnector->dc_sink != NULL); |
| 6790 | else |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 6791 | connected = (aconnector->base.force == DRM_FORCE_ON || |
| 6792 | aconnector->base.force == DRM_FORCE_ON_DIGITAL); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6793 | |
Oleg Vasilev | 0f87789 | 2020-04-24 18:20:55 +0530 | [diff] [blame] | 6794 | update_subconnector_property(aconnector); |
| 6795 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6796 | return (connected ? connector_status_connected : |
| 6797 | connector_status_disconnected); |
| 6798 | } |
| 6799 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 6800 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
| 6801 | struct drm_connector_state *connector_state, |
| 6802 | struct drm_property *property, |
| 6803 | uint64_t val) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6804 | { |
| 6805 | struct drm_device *dev = connector->dev; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 6806 | struct amdgpu_device *adev = drm_to_adev(dev); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6807 | struct dm_connector_state *dm_old_state = |
| 6808 | to_dm_connector_state(connector->state); |
| 6809 | struct dm_connector_state *dm_new_state = |
| 6810 | to_dm_connector_state(connector_state); |
| 6811 | |
| 6812 | int ret = -EINVAL; |
| 6813 | |
| 6814 | if (property == dev->mode_config.scaling_mode_property) { |
| 6815 | enum amdgpu_rmx_type rmx_type; |
| 6816 | |
| 6817 | switch (val) { |
| 6818 | case DRM_MODE_SCALE_CENTER: |
| 6819 | rmx_type = RMX_CENTER; |
| 6820 | break; |
| 6821 | case DRM_MODE_SCALE_ASPECT: |
| 6822 | rmx_type = RMX_ASPECT; |
| 6823 | break; |
| 6824 | case DRM_MODE_SCALE_FULLSCREEN: |
| 6825 | rmx_type = RMX_FULL; |
| 6826 | break; |
| 6827 | case DRM_MODE_SCALE_NONE: |
| 6828 | default: |
| 6829 | rmx_type = RMX_OFF; |
| 6830 | break; |
| 6831 | } |
| 6832 | |
| 6833 | if (dm_old_state->scaling == rmx_type) |
| 6834 | return 0; |
| 6835 | |
| 6836 | dm_new_state->scaling = rmx_type; |
| 6837 | ret = 0; |
| 6838 | } else if (property == adev->mode_info.underscan_hborder_property) { |
| 6839 | dm_new_state->underscan_hborder = val; |
| 6840 | ret = 0; |
| 6841 | } else if (property == adev->mode_info.underscan_vborder_property) { |
| 6842 | dm_new_state->underscan_vborder = val; |
| 6843 | ret = 0; |
| 6844 | } else if (property == adev->mode_info.underscan_property) { |
| 6845 | dm_new_state->underscan_enable = val; |
| 6846 | ret = 0; |
| 6847 | } |
| 6848 | |
| 6849 | return ret; |
| 6850 | } |
| 6851 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 6852 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
| 6853 | const struct drm_connector_state *state, |
| 6854 | struct drm_property *property, |
| 6855 | uint64_t *val) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6856 | { |
| 6857 | struct drm_device *dev = connector->dev; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 6858 | struct amdgpu_device *adev = drm_to_adev(dev); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6859 | struct dm_connector_state *dm_state = |
| 6860 | to_dm_connector_state(state); |
| 6861 | int ret = -EINVAL; |
| 6862 | |
| 6863 | if (property == dev->mode_config.scaling_mode_property) { |
| 6864 | switch (dm_state->scaling) { |
| 6865 | case RMX_CENTER: |
| 6866 | *val = DRM_MODE_SCALE_CENTER; |
| 6867 | break; |
| 6868 | case RMX_ASPECT: |
| 6869 | *val = DRM_MODE_SCALE_ASPECT; |
| 6870 | break; |
| 6871 | case RMX_FULL: |
| 6872 | *val = DRM_MODE_SCALE_FULLSCREEN; |
| 6873 | break; |
| 6874 | case RMX_OFF: |
| 6875 | default: |
| 6876 | *val = DRM_MODE_SCALE_NONE; |
| 6877 | break; |
| 6878 | } |
| 6879 | ret = 0; |
| 6880 | } else if (property == adev->mode_info.underscan_hborder_property) { |
| 6881 | *val = dm_state->underscan_hborder; |
| 6882 | ret = 0; |
| 6883 | } else if (property == adev->mode_info.underscan_vborder_property) { |
| 6884 | *val = dm_state->underscan_vborder; |
| 6885 | ret = 0; |
| 6886 | } else if (property == adev->mode_info.underscan_property) { |
| 6887 | *val = dm_state->underscan_enable; |
| 6888 | ret = 0; |
| 6889 | } |
David Francis | c1ee92f | 2018-11-26 15:51:09 -0500 | [diff] [blame] | 6890 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6891 | return ret; |
| 6892 | } |
| 6893 | |
Hamza Mahfooz | 63d0b87 | 2024-01-26 16:27:10 -0500 | [diff] [blame] | 6894 | /** |
| 6895 | * DOC: panel power savings |
| 6896 | * |
| 6897 | * The display manager allows you to set your desired **panel power savings** |
| 6898 | * level (between 0-4, with 0 representing off), e.g. using the following:: |
| 6899 | * |
| 6900 | * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings |
| 6901 | * |
| 6902 | * Modifying this value can have implications on color accuracy, so tread |
| 6903 | * carefully. |
| 6904 | */ |
| 6905 | |
| 6906 | static ssize_t panel_power_savings_show(struct device *device, |
| 6907 | struct device_attribute *attr, |
| 6908 | char *buf) |
| 6909 | { |
| 6910 | struct drm_connector *connector = dev_get_drvdata(device); |
| 6911 | struct drm_device *dev = connector->dev; |
| 6912 | u8 val; |
| 6913 | |
| 6914 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 6915 | val = to_dm_connector_state(connector->state)->abm_level == |
| 6916 | ABM_LEVEL_IMMEDIATE_DISABLE ? 0 : |
| 6917 | to_dm_connector_state(connector->state)->abm_level; |
| 6918 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 6919 | |
| 6920 | return sysfs_emit(buf, "%u\n", val); |
| 6921 | } |
| 6922 | |
| 6923 | static ssize_t panel_power_savings_store(struct device *device, |
| 6924 | struct device_attribute *attr, |
| 6925 | const char *buf, size_t count) |
| 6926 | { |
| 6927 | struct drm_connector *connector = dev_get_drvdata(device); |
| 6928 | struct drm_device *dev = connector->dev; |
| 6929 | long val; |
| 6930 | int ret; |
| 6931 | |
| 6932 | ret = kstrtol(buf, 0, &val); |
| 6933 | |
| 6934 | if (ret) |
| 6935 | return ret; |
| 6936 | |
| 6937 | if (val < 0 || val > 4) |
| 6938 | return -EINVAL; |
| 6939 | |
| 6940 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 6941 | to_dm_connector_state(connector->state)->abm_level = val ?: |
| 6942 | ABM_LEVEL_IMMEDIATE_DISABLE; |
| 6943 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 6944 | |
| 6945 | drm_kms_helper_hotplug_event(dev); |
| 6946 | |
| 6947 | return count; |
| 6948 | } |
| 6949 | |
| 6950 | static DEVICE_ATTR_RW(panel_power_savings); |
| 6951 | |
| 6952 | static struct attribute *amdgpu_attrs[] = { |
| 6953 | &dev_attr_panel_power_savings.attr, |
| 6954 | NULL |
| 6955 | }; |
| 6956 | |
| 6957 | static const struct attribute_group amdgpu_group = { |
| 6958 | .name = "amdgpu", |
| 6959 | .attrs = amdgpu_attrs |
| 6960 | }; |
| 6961 | |
Mario Limonciello | 76cb763 | 2024-05-09 12:05:24 -0500 | [diff] [blame] | 6962 | static bool |
| 6963 | amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) |
| 6964 | { |
| 6965 | if (amdgpu_dm_abm_level >= 0) |
| 6966 | return false; |
| 6967 | |
| 6968 | if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
| 6969 | return false; |
| 6970 | |
| 6971 | /* check for OLED panels */ |
| 6972 | if (amdgpu_dm_connector->bl_idx >= 0) { |
| 6973 | struct drm_device *drm = amdgpu_dm_connector->base.dev; |
| 6974 | struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; |
| 6975 | struct amdgpu_dm_backlight_caps *caps; |
| 6976 | |
| 6977 | caps = &dm->backlight_caps[amdgpu_dm_connector->bl_idx]; |
| 6978 | if (caps->aux_support) |
| 6979 | return false; |
| 6980 | } |
| 6981 | |
| 6982 | return true; |
| 6983 | } |
| 6984 | |
Emily Deng | 526c654 | 2019-05-31 17:35:27 +0800 | [diff] [blame] | 6985 | static void amdgpu_dm_connector_unregister(struct drm_connector *connector) |
| 6986 | { |
| 6987 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); |
| 6988 | |
Mario Limonciello | 76cb763 | 2024-05-09 12:05:24 -0500 | [diff] [blame] | 6989 | if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) |
Hamza Mahfooz | 63d0b87 | 2024-01-26 16:27:10 -0500 | [diff] [blame] | 6990 | sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); |
| 6991 | |
Emily Deng | 526c654 | 2019-05-31 17:35:27 +0800 | [diff] [blame] | 6992 | drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); |
| 6993 | } |
| 6994 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 6995 | static void amdgpu_dm_connector_destroy(struct drm_connector *connector) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6996 | { |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 6997 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 6998 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 6999 | struct amdgpu_display_manager *dm = &adev->dm; |
Harry Wentland | ada8ce1 | 2018-04-20 10:53:50 -0400 | [diff] [blame] | 7000 | |
Andrey Grodzovsky | 5dff80b | 2020-10-14 13:12:30 -0400 | [diff] [blame] | 7001 | /* |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 7002 | * Call only if mst_mgr was initialized before since it's not done |
Andrey Grodzovsky | 5dff80b | 2020-10-14 13:12:30 -0400 | [diff] [blame] | 7003 | * for all connector types. |
| 7004 | */ |
| 7005 | if (aconnector->mst_mgr.dev) |
| 7006 | drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); |
| 7007 | |
Hans de Goede | f196198 | 2023-03-12 20:17:48 +0100 | [diff] [blame] | 7008 | if (aconnector->bl_idx != -1) { |
| 7009 | backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); |
| 7010 | dm->backlight_dev[aconnector->bl_idx] = NULL; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7011 | } |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 7012 | |
| 7013 | if (aconnector->dc_em_sink) |
| 7014 | dc_sink_release(aconnector->dc_em_sink); |
| 7015 | aconnector->dc_em_sink = NULL; |
| 7016 | if (aconnector->dc_sink) |
| 7017 | dc_sink_release(aconnector->dc_sink); |
| 7018 | aconnector->dc_sink = NULL; |
| 7019 | |
Hans Verkuil | e86e894 | 2018-08-27 10:08:18 +0200 | [diff] [blame] | 7020 | drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7021 | drm_connector_unregister(connector); |
| 7022 | drm_connector_cleanup(connector); |
Emily Deng | 526c654 | 2019-05-31 17:35:27 +0800 | [diff] [blame] | 7023 | if (aconnector->i2c) { |
| 7024 | i2c_del_adapter(&aconnector->i2c->base); |
| 7025 | kfree(aconnector->i2c); |
| 7026 | } |
Alex Deucher | 7daec99 | 2020-04-16 14:44:52 -0400 | [diff] [blame] | 7027 | kfree(aconnector->dm_dp_aux.aux.name); |
Emily Deng | 526c654 | 2019-05-31 17:35:27 +0800 | [diff] [blame] | 7028 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7029 | kfree(connector); |
| 7030 | } |
| 7031 | |
| 7032 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) |
| 7033 | { |
| 7034 | struct dm_connector_state *state = |
| 7035 | to_dm_connector_state(connector->state); |
| 7036 | |
Leo (Sunpeng) Li | df099b9 | 2018-05-16 10:31:30 -0400 | [diff] [blame] | 7037 | if (connector->state) |
| 7038 | __drm_atomic_helper_connector_destroy_state(connector->state); |
| 7039 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7040 | kfree(state); |
| 7041 | |
| 7042 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
| 7043 | |
| 7044 | if (state) { |
| 7045 | state->scaling = RMX_OFF; |
| 7046 | state->underscan_enable = false; |
| 7047 | state->underscan_hborder = 0; |
| 7048 | state->underscan_vborder = 0; |
Nicholas Kazlauskas | 01933ba | 2019-06-05 12:33:59 -0400 | [diff] [blame] | 7049 | state->base.max_requested_bpc = 8; |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7050 | state->vcpi_slots = 0; |
| 7051 | state->pbn = 0; |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 7052 | |
Hamza Mahfooz | 040fdcd | 2024-02-09 14:45:15 -0500 | [diff] [blame] | 7053 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
| 7054 | if (amdgpu_dm_abm_level <= 0) |
| 7055 | state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; |
| 7056 | else |
| 7057 | state->abm_level = amdgpu_dm_abm_level; |
| 7058 | } |
Nicholas Kazlauskas | c3e50f8 | 2019-06-06 08:53:12 -0400 | [diff] [blame] | 7059 | |
Leo (Sunpeng) Li | df099b9 | 2018-05-16 10:31:30 -0400 | [diff] [blame] | 7060 | __drm_atomic_helper_connector_reset(connector, &state->base); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7061 | } |
| 7062 | } |
| 7063 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 7064 | struct drm_connector_state * |
| 7065 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7066 | { |
| 7067 | struct dm_connector_state *state = |
| 7068 | to_dm_connector_state(connector->state); |
| 7069 | |
| 7070 | struct dm_connector_state *new_state = |
| 7071 | kmemdup(state, sizeof(*state), GFP_KERNEL); |
| 7072 | |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 7073 | if (!new_state) |
| 7074 | return NULL; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7075 | |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 7076 | __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); |
| 7077 | |
| 7078 | new_state->freesync_capable = state->freesync_capable; |
David Francis | c1ee92f | 2018-11-26 15:51:09 -0500 | [diff] [blame] | 7079 | new_state->abm_level = state->abm_level; |
Nicholas Kazlauskas | 922454c | 2018-12-07 10:07:09 -0500 | [diff] [blame] | 7080 | new_state->scaling = state->scaling; |
| 7081 | new_state->underscan_enable = state->underscan_enable; |
| 7082 | new_state->underscan_hborder = state->underscan_hborder; |
| 7083 | new_state->underscan_vborder = state->underscan_vborder; |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7084 | new_state->vcpi_slots = state->vcpi_slots; |
| 7085 | new_state->pbn = state->pbn; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 7086 | return &new_state->base; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7087 | } |
| 7088 | |
Alex Deucher | 14f04fa | 2020-02-04 17:11:18 -0500 | [diff] [blame] | 7089 | static int |
| 7090 | amdgpu_dm_connector_late_register(struct drm_connector *connector) |
| 7091 | { |
| 7092 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
| 7093 | to_amdgpu_dm_connector(connector); |
Alex Deucher | 00a8037 | 2020-04-16 14:20:58 -0400 | [diff] [blame] | 7094 | int r; |
Alex Deucher | 14f04fa | 2020-02-04 17:11:18 -0500 | [diff] [blame] | 7095 | |
Mario Limonciello | 76cb763 | 2024-05-09 12:05:24 -0500 | [diff] [blame] | 7096 | if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) { |
Hamza Mahfooz | 63d0b87 | 2024-01-26 16:27:10 -0500 | [diff] [blame] | 7097 | r = sysfs_create_group(&connector->kdev->kobj, |
| 7098 | &amdgpu_group); |
| 7099 | if (r) |
| 7100 | return r; |
| 7101 | } |
| 7102 | |
Hans de Goede | 62f03da | 2023-03-12 20:17:51 +0100 | [diff] [blame] | 7103 | amdgpu_dm_register_backlight_device(amdgpu_dm_connector); |
| 7104 | |
Alex Deucher | 00a8037 | 2020-04-16 14:20:58 -0400 | [diff] [blame] | 7105 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
| 7106 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { |
| 7107 | amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; |
| 7108 | r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); |
| 7109 | if (r) |
| 7110 | return r; |
| 7111 | } |
| 7112 | |
| 7113 | #if defined(CONFIG_DEBUG_FS) |
Alex Deucher | 14f04fa | 2020-02-04 17:11:18 -0500 | [diff] [blame] | 7114 | connector_debugfs_init(amdgpu_dm_connector); |
| 7115 | #endif |
| 7116 | |
| 7117 | return 0; |
| 7118 | } |
| 7119 | |
Arnd Bergmann | dae343b | 2023-05-01 16:31:53 +0200 | [diff] [blame] | 7120 | static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) |
Alex Hung | 0ba4a78 | 2023-04-05 13:47:41 -0600 | [diff] [blame] | 7121 | { |
| 7122 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
| 7123 | struct dc_link *dc_link = aconnector->dc_link; |
| 7124 | struct dc_sink *dc_em_sink = aconnector->dc_em_sink; |
| 7125 | struct edid *edid; |
Melissa Wen | 9671761 | 2024-02-16 09:23:19 -0300 | [diff] [blame] | 7126 | struct i2c_adapter *ddc; |
| 7127 | |
Melissa Wen | 5d978e7 | 2024-02-27 16:08:25 -0300 | [diff] [blame] | 7128 | if (dc_link && dc_link->aux_mode) |
Melissa Wen | 9671761 | 2024-02-16 09:23:19 -0300 | [diff] [blame] | 7129 | ddc = &aconnector->dm_dp_aux.aux.ddc; |
| 7130 | else |
| 7131 | ddc = &aconnector->i2c->base; |
Alex Hung | 0ba4a78 | 2023-04-05 13:47:41 -0600 | [diff] [blame] | 7132 | |
Alex Hung | 0e859fa | 2023-08-25 13:21:28 -0600 | [diff] [blame] | 7133 | /* |
| 7134 | * Note: drm_get_edid gets edid in the following order: |
| 7135 | * 1) override EDID if set via edid_override debugfs, |
| 7136 | * 2) firmware EDID if set via edid_firmware module parameter |
| 7137 | * 3) regular DDC read. |
| 7138 | */ |
Melissa Wen | 9671761 | 2024-02-16 09:23:19 -0300 | [diff] [blame] | 7139 | edid = drm_get_edid(connector, ddc); |
Alex Hung | 0e859fa | 2023-08-25 13:21:28 -0600 | [diff] [blame] | 7140 | if (!edid) { |
| 7141 | DRM_ERROR("No EDID found on connector: %s.\n", connector->name); |
Alex Hung | 0ba4a78 | 2023-04-05 13:47:41 -0600 | [diff] [blame] | 7142 | return; |
Alex Hung | 0e859fa | 2023-08-25 13:21:28 -0600 | [diff] [blame] | 7143 | } |
Alex Hung | 0ba4a78 | 2023-04-05 13:47:41 -0600 | [diff] [blame] | 7144 | |
Alex Hung | 0ba4a78 | 2023-04-05 13:47:41 -0600 | [diff] [blame] | 7145 | aconnector->edid = edid; |
| 7146 | |
| 7147 | /* Update emulated (virtual) sink's EDID */ |
| 7148 | if (dc_em_sink && dc_link) { |
| 7149 | memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); |
| 7150 | memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); |
| 7151 | dm_helpers_parse_edid_caps( |
| 7152 | dc_link, |
| 7153 | &dc_em_sink->dc_edid, |
| 7154 | &dc_em_sink->edid_caps); |
| 7155 | } |
| 7156 | } |
| 7157 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7158 | static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { |
| 7159 | .reset = amdgpu_dm_connector_funcs_reset, |
| 7160 | .detect = amdgpu_dm_connector_detect, |
| 7161 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 7162 | .destroy = amdgpu_dm_connector_destroy, |
| 7163 | .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, |
| 7164 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
| 7165 | .atomic_set_property = amdgpu_dm_connector_atomic_set_property, |
Emily Deng | 526c654 | 2019-05-31 17:35:27 +0800 | [diff] [blame] | 7166 | .atomic_get_property = amdgpu_dm_connector_atomic_get_property, |
Alex Deucher | 14f04fa | 2020-02-04 17:11:18 -0500 | [diff] [blame] | 7167 | .late_register = amdgpu_dm_connector_late_register, |
Alex Hung | 0ba4a78 | 2023-04-05 13:47:41 -0600 | [diff] [blame] | 7168 | .early_unregister = amdgpu_dm_connector_unregister, |
| 7169 | .force = amdgpu_dm_connector_funcs_force |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7170 | }; |
| 7171 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7172 | static int get_modes(struct drm_connector *connector) |
| 7173 | { |
| 7174 | return amdgpu_dm_connector_get_modes(connector); |
| 7175 | } |
| 7176 | |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7177 | static void create_eml_sink(struct amdgpu_dm_connector *aconnector) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7178 | { |
Alex Hung | 0e859fa | 2023-08-25 13:21:28 -0600 | [diff] [blame] | 7179 | struct drm_connector *connector = &aconnector->base; |
Melissa Wen | 9671761 | 2024-02-16 09:23:19 -0300 | [diff] [blame] | 7180 | struct dc_link *dc_link = aconnector->dc_link; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7181 | struct dc_sink_init_data init_params = { |
| 7182 | .link = aconnector->dc_link, |
| 7183 | .sink_signal = SIGNAL_TYPE_VIRTUAL |
| 7184 | }; |
Harry Wentland | 70e8ffc | 2017-11-10 11:19:02 -0500 | [diff] [blame] | 7185 | struct edid *edid; |
Melissa Wen | 9671761 | 2024-02-16 09:23:19 -0300 | [diff] [blame] | 7186 | struct i2c_adapter *ddc; |
| 7187 | |
| 7188 | if (dc_link->aux_mode) |
| 7189 | ddc = &aconnector->dm_dp_aux.aux.ddc; |
| 7190 | else |
| 7191 | ddc = &aconnector->i2c->base; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7192 | |
Alex Hung | 0e859fa | 2023-08-25 13:21:28 -0600 | [diff] [blame] | 7193 | /* |
| 7194 | * Note: drm_get_edid gets edid in the following order: |
| 7195 | * 1) override EDID if set via edid_override debugfs, |
| 7196 | * 2) firmware EDID if set via edid_firmware module parameter |
| 7197 | * 3) regular DDC read. |
| 7198 | */ |
Melissa Wen | 9671761 | 2024-02-16 09:23:19 -0300 | [diff] [blame] | 7199 | edid = drm_get_edid(connector, ddc); |
Alex Hung | 0e859fa | 2023-08-25 13:21:28 -0600 | [diff] [blame] | 7200 | if (!edid) { |
| 7201 | DRM_ERROR("No EDID found on connector: %s.\n", connector->name); |
| 7202 | return; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7203 | } |
| 7204 | |
Alex Hung | fc0479a | 2023-10-03 15:25:30 -0600 | [diff] [blame] | 7205 | if (drm_detect_hdmi_monitor(edid)) |
| 7206 | init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; |
| 7207 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7208 | aconnector->edid = edid; |
| 7209 | |
| 7210 | aconnector->dc_em_sink = dc_link_add_remote_sink( |
| 7211 | aconnector->dc_link, |
| 7212 | (uint8_t *)edid, |
| 7213 | (edid->extensions + 1) * EDID_LENGTH, |
| 7214 | &init_params); |
| 7215 | |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 7216 | if (aconnector->base.force == DRM_FORCE_ON) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7217 | aconnector->dc_sink = aconnector->dc_link->local_sink ? |
| 7218 | aconnector->dc_link->local_sink : |
| 7219 | aconnector->dc_em_sink; |
Alex Hung | 8092aa3 | 2024-06-04 16:33:18 -0600 | [diff] [blame] | 7220 | if (aconnector->dc_sink) |
| 7221 | dc_sink_retain(aconnector->dc_sink); |
Mathias Fröhlich | dcd5fb8 | 2019-02-10 11:13:01 +0100 | [diff] [blame] | 7222 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7223 | } |
| 7224 | |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7225 | static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7226 | { |
| 7227 | struct dc_link *link = (struct dc_link *)aconnector->dc_link; |
| 7228 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 7229 | /* |
| 7230 | * In case of headless boot with force on for DP managed connector |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7231 | * Those settings have to be != 0 to get initial modeset |
| 7232 | */ |
| 7233 | if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { |
| 7234 | link->verified_link_cap.lane_count = LANE_COUNT_FOUR; |
| 7235 | link->verified_link_cap.link_rate = LINK_RATE_HIGH2; |
| 7236 | } |
| 7237 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7238 | create_eml_sink(aconnector); |
| 7239 | } |
| 7240 | |
Fangzhi Zuo | 5468c36 | 2022-10-20 16:06:26 -0400 | [diff] [blame] | 7241 | static enum dc_status dm_validate_stream_and_context(struct dc *dc, |
| 7242 | struct dc_stream_state *stream) |
| 7243 | { |
| 7244 | enum dc_status dc_result = DC_ERROR_UNEXPECTED; |
| 7245 | struct dc_plane_state *dc_plane_state = NULL; |
| 7246 | struct dc_state *dc_state = NULL; |
| 7247 | |
| 7248 | if (!stream) |
| 7249 | goto cleanup; |
| 7250 | |
| 7251 | dc_plane_state = dc_create_plane_state(dc); |
| 7252 | if (!dc_plane_state) |
| 7253 | goto cleanup; |
| 7254 | |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 7255 | dc_state = dc_state_create(dc, NULL); |
Fangzhi Zuo | 5468c36 | 2022-10-20 16:06:26 -0400 | [diff] [blame] | 7256 | if (!dc_state) |
| 7257 | goto cleanup; |
| 7258 | |
| 7259 | /* populate stream to plane */ |
| 7260 | dc_plane_state->src_rect.height = stream->src.height; |
| 7261 | dc_plane_state->src_rect.width = stream->src.width; |
| 7262 | dc_plane_state->dst_rect.height = stream->src.height; |
| 7263 | dc_plane_state->dst_rect.width = stream->src.width; |
| 7264 | dc_plane_state->clip_rect.height = stream->src.height; |
| 7265 | dc_plane_state->clip_rect.width = stream->src.width; |
| 7266 | dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; |
| 7267 | dc_plane_state->plane_size.surface_size.height = stream->src.height; |
| 7268 | dc_plane_state->plane_size.surface_size.width = stream->src.width; |
| 7269 | dc_plane_state->plane_size.chroma_size.height = stream->src.height; |
| 7270 | dc_plane_state->plane_size.chroma_size.width = stream->src.width; |
Fangzhi Zuo | 5468c36 | 2022-10-20 16:06:26 -0400 | [diff] [blame] | 7271 | dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
| 7272 | dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; |
| 7273 | dc_plane_state->rotation = ROTATION_ANGLE_0; |
| 7274 | dc_plane_state->is_tiling_rotated = false; |
| 7275 | dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; |
| 7276 | |
| 7277 | dc_result = dc_validate_stream(dc, stream); |
| 7278 | if (dc_result == DC_OK) |
| 7279 | dc_result = dc_validate_plane(dc, dc_plane_state); |
| 7280 | |
| 7281 | if (dc_result == DC_OK) |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 7282 | dc_result = dc_state_add_stream(dc, dc_state, stream); |
Fangzhi Zuo | 5468c36 | 2022-10-20 16:06:26 -0400 | [diff] [blame] | 7283 | |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 7284 | if (dc_result == DC_OK && !dc_state_add_plane( |
Fangzhi Zuo | 5468c36 | 2022-10-20 16:06:26 -0400 | [diff] [blame] | 7285 | dc, |
| 7286 | stream, |
| 7287 | dc_plane_state, |
| 7288 | dc_state)) |
| 7289 | dc_result = DC_FAIL_ATTACH_SURFACES; |
| 7290 | |
| 7291 | if (dc_result == DC_OK) |
| 7292 | dc_result = dc_validate_global_state(dc, dc_state, true); |
| 7293 | |
| 7294 | cleanup: |
| 7295 | if (dc_state) |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 7296 | dc_state_release(dc_state); |
Fangzhi Zuo | 5468c36 | 2022-10-20 16:06:26 -0400 | [diff] [blame] | 7297 | |
| 7298 | if (dc_plane_state) |
| 7299 | dc_plane_state_release(dc_plane_state); |
| 7300 | |
| 7301 | return dc_result; |
| 7302 | } |
| 7303 | |
Roman Li | 17ce8a6 | 2022-01-28 12:29:01 -0500 | [diff] [blame] | 7304 | struct dc_stream_state * |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7305 | create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
| 7306 | const struct drm_display_mode *drm_mode, |
| 7307 | const struct dm_connector_state *dm_state, |
| 7308 | const struct dc_stream_state *old_stream) |
| 7309 | { |
| 7310 | struct drm_connector *connector = &aconnector->base; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 7311 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7312 | struct dc_stream_state *stream; |
Stylon Wang | 4b7da34 | 2020-06-12 19:04:18 +0800 | [diff] [blame] | 7313 | const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; |
| 7314 | int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7315 | enum dc_status dc_result = DC_OK; |
| 7316 | |
Alex Hung | 1ff12bc | 2024-06-27 17:38:16 -0600 | [diff] [blame] | 7317 | if (!dm_state) |
| 7318 | return NULL; |
| 7319 | |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7320 | do { |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 7321 | stream = create_stream_for_sink(connector, drm_mode, |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7322 | dm_state, old_stream, |
| 7323 | requested_bpc); |
| 7324 | if (stream == NULL) { |
| 7325 | DRM_ERROR("Failed to create stream for sink!\n"); |
| 7326 | break; |
| 7327 | } |
| 7328 | |
Alex Hung | dbf5d3d | 2023-12-01 06:25:28 -0700 | [diff] [blame] | 7329 | if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 7330 | return stream; |
| 7331 | |
Rodrigo Siqueira | e9a7d23 | 2022-06-16 16:48:22 -0400 | [diff] [blame] | 7332 | dc_result = dc_validate_stream(adev->dm.dc, stream); |
| 7333 | if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) |
hersen wu | f04d275 | 2022-05-29 12:12:32 -0400 | [diff] [blame] | 7334 | dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); |
| 7335 | |
Fangzhi Zuo | 5468c36 | 2022-10-20 16:06:26 -0400 | [diff] [blame] | 7336 | if (dc_result == DC_OK) |
| 7337 | dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); |
| 7338 | |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7339 | if (dc_result != DC_OK) { |
Rodrigo Siqueira | 74a1667 | 2020-05-26 16:53:38 -0400 | [diff] [blame] | 7340 | DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7341 | drm_mode->hdisplay, |
| 7342 | drm_mode->vdisplay, |
| 7343 | drm_mode->clock, |
Rodrigo Siqueira | 74a1667 | 2020-05-26 16:53:38 -0400 | [diff] [blame] | 7344 | dc_result, |
| 7345 | dc_status_to_str(dc_result)); |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7346 | |
| 7347 | dc_stream_release(stream); |
| 7348 | stream = NULL; |
| 7349 | requested_bpc -= 2; /* lower bpc to retry validation */ |
| 7350 | } |
| 7351 | |
| 7352 | } while (stream == NULL && requested_bpc >= 6); |
| 7353 | |
Werner Sembach | 68eb3ae | 2021-03-17 16:13:48 +0100 | [diff] [blame] | 7354 | if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { |
| 7355 | DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); |
| 7356 | |
| 7357 | aconnector->force_yuv420_output = true; |
| 7358 | stream = create_validate_stream_for_sink(aconnector, drm_mode, |
| 7359 | dm_state, old_stream); |
| 7360 | aconnector->force_yuv420_output = false; |
| 7361 | } |
| 7362 | |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7363 | return stream; |
| 7364 | } |
| 7365 | |
Luc Van Oostenryck | ba9ca08 | 2018-04-24 15:14:18 +0200 | [diff] [blame] | 7366 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 7367 | struct drm_display_mode *mode) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7368 | { |
| 7369 | int result = MODE_ERROR; |
| 7370 | struct dc_sink *dc_sink; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7371 | /* TODO: Unhardcode stream count */ |
Harry Wentland | 0971c40 | 2017-07-27 09:33:33 -0400 | [diff] [blame] | 7372 | struct dc_stream_state *stream; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7373 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7374 | |
| 7375 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || |
| 7376 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) |
| 7377 | return result; |
| 7378 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 7379 | /* |
| 7380 | * Only run this the first time mode_valid is called to initilialize |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7381 | * EDID mgmt |
| 7382 | */ |
| 7383 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && |
| 7384 | !aconnector->dc_em_sink) |
| 7385 | handle_edid_mgmt(aconnector); |
| 7386 | |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7387 | dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7388 | |
Victor Lu | ad975f4 | 2020-09-29 16:03:10 -0400 | [diff] [blame] | 7389 | if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && |
| 7390 | aconnector->base.force != DRM_FORCE_ON) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7391 | DRM_ERROR("dc_sink is NULL!\n"); |
| 7392 | goto fail; |
| 7393 | } |
| 7394 | |
Hamza Mahfooz | 1101185 | 2023-09-13 14:48:08 -0400 | [diff] [blame] | 7395 | drm_mode_set_crtcinfo(mode, 0); |
| 7396 | |
Harry Wentland | cb841d2 | 2022-04-01 13:45:29 -0400 | [diff] [blame] | 7397 | stream = create_validate_stream_for_sink(aconnector, mode, |
| 7398 | to_dm_connector_state(connector->state), |
| 7399 | NULL); |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7400 | if (stream) { |
| 7401 | dc_stream_release(stream); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7402 | result = MODE_OK; |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7403 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7404 | |
| 7405 | fail: |
| 7406 | /* TODO: error handling*/ |
| 7407 | return result; |
| 7408 | } |
| 7409 | |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7410 | static int fill_hdr_info_packet(const struct drm_connector_state *state, |
| 7411 | struct dc_info_packet *out) |
| 7412 | { |
| 7413 | struct hdmi_drm_infoframe frame; |
| 7414 | unsigned char buf[30]; /* 26 + 4 */ |
| 7415 | ssize_t len; |
| 7416 | int ret, i; |
| 7417 | |
| 7418 | memset(out, 0, sizeof(*out)); |
| 7419 | |
| 7420 | if (!state->hdr_output_metadata) |
| 7421 | return 0; |
| 7422 | |
| 7423 | ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); |
| 7424 | if (ret) |
| 7425 | return ret; |
| 7426 | |
| 7427 | len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); |
| 7428 | if (len < 0) |
| 7429 | return (int)len; |
| 7430 | |
| 7431 | /* Static metadata is a fixed 26 bytes + 4 byte header. */ |
| 7432 | if (len != 30) |
| 7433 | return -EINVAL; |
| 7434 | |
| 7435 | /* Prepare the infopacket for DC. */ |
| 7436 | switch (state->connector->connector_type) { |
| 7437 | case DRM_MODE_CONNECTOR_HDMIA: |
| 7438 | out->hb0 = 0x87; /* type */ |
| 7439 | out->hb1 = 0x01; /* version */ |
| 7440 | out->hb2 = 0x1A; /* length */ |
| 7441 | out->sb[0] = buf[3]; /* checksum */ |
| 7442 | i = 1; |
| 7443 | break; |
| 7444 | |
| 7445 | case DRM_MODE_CONNECTOR_DisplayPort: |
| 7446 | case DRM_MODE_CONNECTOR_eDP: |
| 7447 | out->hb0 = 0x00; /* sdp id, zero */ |
| 7448 | out->hb1 = 0x87; /* type */ |
| 7449 | out->hb2 = 0x1D; /* payload len - 1 */ |
| 7450 | out->hb3 = (0x13 << 2); /* sdp version */ |
| 7451 | out->sb[0] = 0x01; /* version */ |
| 7452 | out->sb[1] = 0x1A; /* length */ |
| 7453 | i = 2; |
| 7454 | break; |
| 7455 | |
| 7456 | default: |
| 7457 | return -EINVAL; |
| 7458 | } |
| 7459 | |
| 7460 | memcpy(&out->sb[i], &buf[4], 26); |
| 7461 | out->valid = true; |
| 7462 | |
| 7463 | print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, |
| 7464 | sizeof(out->sb), false); |
| 7465 | |
| 7466 | return 0; |
| 7467 | } |
| 7468 | |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7469 | static int |
| 7470 | amdgpu_dm_connector_atomic_check(struct drm_connector *conn, |
Sean Paul | 51e857a | 2019-06-13 20:27:00 -0400 | [diff] [blame] | 7471 | struct drm_atomic_state *state) |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7472 | { |
Sean Paul | 51e857a | 2019-06-13 20:27:00 -0400 | [diff] [blame] | 7473 | struct drm_connector_state *new_con_state = |
| 7474 | drm_atomic_get_new_connector_state(state, conn); |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7475 | struct drm_connector_state *old_con_state = |
| 7476 | drm_atomic_get_old_connector_state(state, conn); |
| 7477 | struct drm_crtc *crtc = new_con_state->crtc; |
| 7478 | struct drm_crtc_state *new_crtc_state; |
Lyude Paul | a76eb42 | 2022-08-17 15:38:42 -0400 | [diff] [blame] | 7479 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7480 | int ret; |
| 7481 | |
Rodrigo Siqueira | e8a9823 | 2020-09-04 14:37:53 -0400 | [diff] [blame] | 7482 | trace_amdgpu_dm_connector_atomic_check(new_con_state); |
| 7483 | |
Lyude Paul | a76eb42 | 2022-08-17 15:38:42 -0400 | [diff] [blame] | 7484 | if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
| 7485 | ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); |
| 7486 | if (ret < 0) |
| 7487 | return ret; |
| 7488 | } |
| 7489 | |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7490 | if (!crtc) |
| 7491 | return 0; |
| 7492 | |
Harry Wentland | a0b433c | 2022-03-29 11:26:23 -0400 | [diff] [blame] | 7493 | if (new_con_state->colorspace != old_con_state->colorspace) { |
| 7494 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 7495 | if (IS_ERR(new_crtc_state)) |
| 7496 | return PTR_ERR(new_crtc_state); |
| 7497 | |
| 7498 | new_crtc_state->mode_changed = true; |
| 7499 | } |
| 7500 | |
Joshua Ashton | 4c4583f | 2023-09-12 15:01:56 -0100 | [diff] [blame] | 7501 | if (new_con_state->content_type != old_con_state->content_type) { |
| 7502 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 7503 | if (IS_ERR(new_crtc_state)) |
| 7504 | return PTR_ERR(new_crtc_state); |
| 7505 | |
| 7506 | new_crtc_state->mode_changed = true; |
| 7507 | } |
| 7508 | |
Maxime Ripard | 72921cd | 2021-04-30 11:44:48 +0200 | [diff] [blame] | 7509 | if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7510 | struct dc_info_packet hdr_infopacket; |
| 7511 | |
| 7512 | ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); |
| 7513 | if (ret) |
| 7514 | return ret; |
| 7515 | |
| 7516 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); |
| 7517 | if (IS_ERR(new_crtc_state)) |
| 7518 | return PTR_ERR(new_crtc_state); |
| 7519 | |
| 7520 | /* |
| 7521 | * DC considers the stream backends changed if the |
| 7522 | * static metadata changes. Forcing the modeset also |
| 7523 | * gives a simple way for userspace to switch from |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 7524 | * 8bpc to 10bpc when setting the metadata to enter |
| 7525 | * or exit HDR. |
| 7526 | * |
| 7527 | * Changing the static metadata after it's been |
| 7528 | * set is permissible, however. So only force a |
| 7529 | * modeset if we're entering or exiting HDR. |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7530 | */ |
Harry Wentland | a0b433c | 2022-03-29 11:26:23 -0400 | [diff] [blame] | 7531 | new_crtc_state->mode_changed = new_crtc_state->mode_changed || |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 7532 | !old_con_state->hdr_output_metadata || |
| 7533 | !new_con_state->hdr_output_metadata; |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7534 | } |
| 7535 | |
| 7536 | return 0; |
| 7537 | } |
| 7538 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7539 | static const struct drm_connector_helper_funcs |
| 7540 | amdgpu_dm_connector_helper_funcs = { |
| 7541 | /* |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 7542 | * If hotplugging a second bigger display in FB Con mode, bigger resolution |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7543 | * modes will be filtered by drm_mode_validate_size(), and those modes |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 7544 | * are missing after user start lightdm. So we need to renew modes list. |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7545 | * in get_modes call back, not just return the modes count |
| 7546 | */ |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7547 | .get_modes = get_modes, |
| 7548 | .mode_valid = amdgpu_dm_connector_mode_valid, |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 7549 | .atomic_check = amdgpu_dm_connector_atomic_check, |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7550 | }; |
| 7551 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7552 | static void dm_encoder_helper_disable(struct drm_encoder *encoder) |
| 7553 | { |
| 7554 | |
| 7555 | } |
| 7556 | |
hersen wu | f04d275 | 2022-05-29 12:12:32 -0400 | [diff] [blame] | 7557 | int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7558 | { |
| 7559 | switch (display_color_depth) { |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 7560 | case COLOR_DEPTH_666: |
| 7561 | return 6; |
| 7562 | case COLOR_DEPTH_888: |
| 7563 | return 8; |
| 7564 | case COLOR_DEPTH_101010: |
| 7565 | return 10; |
| 7566 | case COLOR_DEPTH_121212: |
| 7567 | return 12; |
| 7568 | case COLOR_DEPTH_141414: |
| 7569 | return 14; |
| 7570 | case COLOR_DEPTH_161616: |
| 7571 | return 16; |
| 7572 | default: |
| 7573 | break; |
| 7574 | } |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7575 | return 0; |
| 7576 | } |
| 7577 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 7578 | static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, |
| 7579 | struct drm_crtc_state *crtc_state, |
| 7580 | struct drm_connector_state *conn_state) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7581 | { |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7582 | struct drm_atomic_state *state = crtc_state->state; |
| 7583 | struct drm_connector *connector = conn_state->connector; |
| 7584 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
| 7585 | struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); |
| 7586 | const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; |
| 7587 | struct drm_dp_mst_topology_mgr *mst_mgr; |
| 7588 | struct drm_dp_mst_port *mst_port; |
Lyude Paul | 4d07b0b | 2022-08-17 15:38:46 -0400 | [diff] [blame] | 7589 | struct drm_dp_mst_topology_state *mst_state; |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7590 | enum dc_color_depth color_depth; |
| 7591 | int clock, bpp = 0; |
Stylon Wang | 1bc22f2 | 2019-09-20 15:40:55 +0800 | [diff] [blame] | 7592 | bool is_y420 = false; |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7593 | |
Fangzhi Zuo | 91b38ca | 2023-05-10 16:43:30 -0400 | [diff] [blame] | 7594 | if (!aconnector->mst_output_port) |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7595 | return 0; |
| 7596 | |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 7597 | mst_port = aconnector->mst_output_port; |
| 7598 | mst_mgr = &aconnector->mst_root->mst_mgr; |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7599 | |
| 7600 | if (!crtc_state->connectors_changed && !crtc_state->mode_changed) |
| 7601 | return 0; |
| 7602 | |
Lyude Paul | 4d07b0b | 2022-08-17 15:38:46 -0400 | [diff] [blame] | 7603 | mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); |
| 7604 | if (IS_ERR(mst_state)) |
| 7605 | return PTR_ERR(mst_state); |
| 7606 | |
Wayne Lin | efae5a9 | 2023-12-04 10:09:33 +0800 | [diff] [blame] | 7607 | mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); |
Lyude Paul | 4d07b0b | 2022-08-17 15:38:46 -0400 | [diff] [blame] | 7608 | |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7609 | if (!state->duplicated) { |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7610 | int max_bpc = conn_state->max_requested_bpc; |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 7611 | |
Stylon Wang | 1bc22f2 | 2019-09-20 15:40:55 +0800 | [diff] [blame] | 7612 | is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 7613 | aconnector->force_yuv420_output; |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 7614 | color_depth = convert_color_depth_from_display_info(connector, |
| 7615 | is_y420, |
| 7616 | max_bpc); |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7617 | bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; |
| 7618 | clock = adjusted_mode->clock; |
Ville Syrjälä | 7707dd6 | 2023-10-24 04:08:57 +0300 | [diff] [blame] | 7619 | dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7620 | } |
Lyude Paul | 4d07b0b | 2022-08-17 15:38:46 -0400 | [diff] [blame] | 7621 | |
| 7622 | dm_new_connector_state->vcpi_slots = |
| 7623 | drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, |
| 7624 | dm_new_connector_state->pbn); |
Mikita Lipski | 3261e01 | 2019-11-06 14:23:55 -0500 | [diff] [blame] | 7625 | if (dm_new_connector_state->vcpi_slots < 0) { |
| 7626 | DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); |
| 7627 | return dm_new_connector_state->vcpi_slots; |
| 7628 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7629 | return 0; |
| 7630 | } |
| 7631 | |
| 7632 | const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { |
| 7633 | .disable = dm_encoder_helper_disable, |
| 7634 | .atomic_check = dm_encoder_helper_atomic_check |
| 7635 | }; |
| 7636 | |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7637 | static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, |
Hersen Wu | 6513104b | 2021-08-25 16:27:47 -0400 | [diff] [blame] | 7638 | struct dc_state *dc_state, |
| 7639 | struct dsc_mst_fairness_vars *vars) |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7640 | { |
| 7641 | struct dc_stream_state *stream = NULL; |
| 7642 | struct drm_connector *connector; |
Guenter Roeck | 5760dcb | 2021-04-21 09:18:02 -0700 | [diff] [blame] | 7643 | struct drm_connector_state *new_con_state; |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7644 | struct amdgpu_dm_connector *aconnector; |
| 7645 | struct dm_connector_state *dm_conn_state; |
Lyude Paul | 7cce4cd6 | 2022-11-14 17:17:52 -0500 | [diff] [blame] | 7646 | int i, j, ret; |
Alex Hung | f95bcb0 | 2024-04-15 19:02:56 -0600 | [diff] [blame] | 7647 | int vcpi, pbn_div, pbn = 0, slot_num = 0; |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7648 | |
Guenter Roeck | 5760dcb | 2021-04-21 09:18:02 -0700 | [diff] [blame] | 7649 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7650 | |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 7651 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 7652 | continue; |
| 7653 | |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7654 | aconnector = to_amdgpu_dm_connector(connector); |
| 7655 | |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 7656 | if (!aconnector->mst_output_port) |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7657 | continue; |
| 7658 | |
| 7659 | if (!new_con_state || !new_con_state->crtc) |
| 7660 | continue; |
| 7661 | |
| 7662 | dm_conn_state = to_dm_connector_state(new_con_state); |
| 7663 | |
| 7664 | for (j = 0; j < dc_state->stream_count; j++) { |
| 7665 | stream = dc_state->streams[j]; |
| 7666 | if (!stream) |
| 7667 | continue; |
| 7668 | |
Rodrigo Siqueira | 5d945cb | 2022-07-20 15:31:42 -0400 | [diff] [blame] | 7669 | if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7670 | break; |
| 7671 | |
| 7672 | stream = NULL; |
| 7673 | } |
| 7674 | |
| 7675 | if (!stream) |
| 7676 | continue; |
| 7677 | |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7678 | pbn_div = dm_mst_get_pbn_divider(stream->link); |
Hersen Wu | 6513104b | 2021-08-25 16:27:47 -0400 | [diff] [blame] | 7679 | /* pbn is calculated by compute_mst_dsc_configs_for_state*/ |
| 7680 | for (j = 0; j < dc_state->stream_count; j++) { |
| 7681 | if (vars[j].aconnector == aconnector) { |
| 7682 | pbn = vars[j].pbn; |
| 7683 | break; |
| 7684 | } |
| 7685 | } |
| 7686 | |
Alex Hung | 116a678 | 2024-06-18 16:21:20 -0600 | [diff] [blame] | 7687 | if (j == dc_state->stream_count || pbn_div == 0) |
Hersen Wu | a550bb1 | 2021-10-17 20:09:04 -0400 | [diff] [blame] | 7688 | continue; |
| 7689 | |
| 7690 | slot_num = DIV_ROUND_UP(pbn, pbn_div); |
| 7691 | |
| 7692 | if (stream->timing.flags.DSC != 1) { |
| 7693 | dm_conn_state->pbn = pbn; |
| 7694 | dm_conn_state->vcpi_slots = slot_num; |
| 7695 | |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 7696 | ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, |
Lyude Paul | 7cce4cd6 | 2022-11-14 17:17:52 -0500 | [diff] [blame] | 7697 | dm_conn_state->pbn, false); |
| 7698 | if (ret < 0) |
| 7699 | return ret; |
| 7700 | |
Hersen Wu | a550bb1 | 2021-10-17 20:09:04 -0400 | [diff] [blame] | 7701 | continue; |
| 7702 | } |
| 7703 | |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 7704 | vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 7705 | if (vcpi < 0) |
| 7706 | return vcpi; |
| 7707 | |
| 7708 | dm_conn_state->pbn = pbn; |
| 7709 | dm_conn_state->vcpi_slots = vcpi; |
| 7710 | } |
| 7711 | return 0; |
| 7712 | } |
| 7713 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7714 | static int to_drm_connector_type(enum signal_type st) |
| 7715 | { |
| 7716 | switch (st) { |
| 7717 | case SIGNAL_TYPE_HDMI_TYPE_A: |
| 7718 | return DRM_MODE_CONNECTOR_HDMIA; |
| 7719 | case SIGNAL_TYPE_EDP: |
| 7720 | return DRM_MODE_CONNECTOR_eDP; |
Alex Deucher | 11c3ee4 | 2018-08-14 14:53:52 -0500 | [diff] [blame] | 7721 | case SIGNAL_TYPE_LVDS: |
| 7722 | return DRM_MODE_CONNECTOR_LVDS; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7723 | case SIGNAL_TYPE_RGB: |
| 7724 | return DRM_MODE_CONNECTOR_VGA; |
| 7725 | case SIGNAL_TYPE_DISPLAY_PORT: |
| 7726 | case SIGNAL_TYPE_DISPLAY_PORT_MST: |
| 7727 | return DRM_MODE_CONNECTOR_DisplayPort; |
| 7728 | case SIGNAL_TYPE_DVI_DUAL_LINK: |
| 7729 | case SIGNAL_TYPE_DVI_SINGLE_LINK: |
| 7730 | return DRM_MODE_CONNECTOR_DVID; |
| 7731 | case SIGNAL_TYPE_VIRTUAL: |
| 7732 | return DRM_MODE_CONNECTOR_VIRTUAL; |
| 7733 | |
| 7734 | default: |
| 7735 | return DRM_MODE_CONNECTOR_Unknown; |
| 7736 | } |
| 7737 | } |
| 7738 | |
Daniel Vetter | 2b4c1c0 | 2018-10-04 22:24:26 +0200 | [diff] [blame] | 7739 | static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) |
| 7740 | { |
José Roberto de Souza | 62afb4a | 2019-09-13 16:28:57 -0700 | [diff] [blame] | 7741 | struct drm_encoder *encoder; |
| 7742 | |
| 7743 | /* There is only one encoder per connector */ |
| 7744 | drm_connector_for_each_possible_encoder(connector, encoder) |
| 7745 | return encoder; |
| 7746 | |
| 7747 | return NULL; |
Daniel Vetter | 2b4c1c0 | 2018-10-04 22:24:26 +0200 | [diff] [blame] | 7748 | } |
| 7749 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7750 | static void amdgpu_dm_get_native_mode(struct drm_connector *connector) |
| 7751 | { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7752 | struct drm_encoder *encoder; |
| 7753 | struct amdgpu_encoder *amdgpu_encoder; |
| 7754 | |
Daniel Vetter | 2b4c1c0 | 2018-10-04 22:24:26 +0200 | [diff] [blame] | 7755 | encoder = amdgpu_dm_connector_to_encoder(connector); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7756 | |
| 7757 | if (encoder == NULL) |
| 7758 | return; |
| 7759 | |
| 7760 | amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 7761 | |
| 7762 | amdgpu_encoder->native_mode.clock = 0; |
| 7763 | |
| 7764 | if (!list_empty(&connector->probed_modes)) { |
| 7765 | struct drm_display_mode *preferred_mode = NULL; |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7766 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7767 | list_for_each_entry(preferred_mode, |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7768 | &connector->probed_modes, |
| 7769 | head) { |
| 7770 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) |
| 7771 | amdgpu_encoder->native_mode = *preferred_mode; |
| 7772 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7773 | break; |
| 7774 | } |
| 7775 | |
| 7776 | } |
| 7777 | } |
| 7778 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 7779 | static struct drm_display_mode * |
| 7780 | amdgpu_dm_create_common_mode(struct drm_encoder *encoder, |
| 7781 | char *name, |
| 7782 | int hdisplay, int vdisplay) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7783 | { |
| 7784 | struct drm_device *dev = encoder->dev; |
| 7785 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 7786 | struct drm_display_mode *mode = NULL; |
| 7787 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; |
| 7788 | |
| 7789 | mode = drm_mode_duplicate(dev, native_mode); |
| 7790 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7791 | if (mode == NULL) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7792 | return NULL; |
| 7793 | |
| 7794 | mode->hdisplay = hdisplay; |
| 7795 | mode->vdisplay = vdisplay; |
| 7796 | mode->type &= ~DRM_MODE_TYPE_PREFERRED; |
Nicholas Kazlauskas | 090afc1 | 2018-07-20 10:17:29 -0400 | [diff] [blame] | 7797 | strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7798 | |
| 7799 | return mode; |
| 7800 | |
| 7801 | } |
| 7802 | |
| 7803 | static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 7804 | struct drm_connector *connector) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7805 | { |
| 7806 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 7807 | struct drm_display_mode *mode = NULL; |
| 7808 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7809 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
| 7810 | to_amdgpu_dm_connector(connector); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7811 | int i; |
| 7812 | int n; |
| 7813 | struct mode_size { |
| 7814 | char name[DRM_DISPLAY_MODE_LEN]; |
| 7815 | int w; |
| 7816 | int h; |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7817 | } common_modes[] = { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7818 | { "640x480", 640, 480}, |
| 7819 | { "800x600", 800, 600}, |
| 7820 | { "1024x768", 1024, 768}, |
| 7821 | { "1280x720", 1280, 720}, |
| 7822 | { "1280x800", 1280, 800}, |
| 7823 | {"1280x1024", 1280, 1024}, |
| 7824 | { "1440x900", 1440, 900}, |
| 7825 | {"1680x1050", 1680, 1050}, |
| 7826 | {"1600x1200", 1600, 1200}, |
| 7827 | {"1920x1080", 1920, 1080}, |
| 7828 | {"1920x1200", 1920, 1200} |
| 7829 | }; |
| 7830 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7831 | n = ARRAY_SIZE(common_modes); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7832 | |
| 7833 | for (i = 0; i < n; i++) { |
| 7834 | struct drm_display_mode *curmode = NULL; |
| 7835 | bool mode_existed = false; |
| 7836 | |
| 7837 | if (common_modes[i].w > native_mode->hdisplay || |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7838 | common_modes[i].h > native_mode->vdisplay || |
| 7839 | (common_modes[i].w == native_mode->hdisplay && |
| 7840 | common_modes[i].h == native_mode->vdisplay)) |
| 7841 | continue; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7842 | |
| 7843 | list_for_each_entry(curmode, &connector->probed_modes, head) { |
| 7844 | if (common_modes[i].w == curmode->hdisplay && |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 7845 | common_modes[i].h == curmode->vdisplay) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7846 | mode_existed = true; |
| 7847 | break; |
| 7848 | } |
| 7849 | } |
| 7850 | |
| 7851 | if (mode_existed) |
| 7852 | continue; |
| 7853 | |
| 7854 | mode = amdgpu_dm_create_common_mode(encoder, |
| 7855 | common_modes[i].name, common_modes[i].w, |
| 7856 | common_modes[i].h); |
Zhou Qingyang | 588a701 | 2022-01-25 00:57:29 +0800 | [diff] [blame] | 7857 | if (!mode) |
| 7858 | continue; |
| 7859 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7860 | drm_mode_probed_add(connector, mode); |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7861 | amdgpu_dm_connector->num_modes++; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7862 | } |
| 7863 | } |
| 7864 | |
Simon Ser | d77de78 | 2021-09-10 15:37:41 +0000 | [diff] [blame] | 7865 | static void amdgpu_set_panel_orientation(struct drm_connector *connector) |
| 7866 | { |
| 7867 | struct drm_encoder *encoder; |
| 7868 | struct amdgpu_encoder *amdgpu_encoder; |
| 7869 | const struct drm_display_mode *native_mode; |
| 7870 | |
| 7871 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && |
| 7872 | connector->connector_type != DRM_MODE_CONNECTOR_LVDS) |
| 7873 | return; |
| 7874 | |
Melissa Wen | acc96ae | 2022-08-04 15:13:49 -0100 | [diff] [blame] | 7875 | mutex_lock(&connector->dev->mode_config.mutex); |
| 7876 | amdgpu_dm_connector_get_modes(connector); |
| 7877 | mutex_unlock(&connector->dev->mode_config.mutex); |
| 7878 | |
Simon Ser | d77de78 | 2021-09-10 15:37:41 +0000 | [diff] [blame] | 7879 | encoder = amdgpu_dm_connector_to_encoder(connector); |
| 7880 | if (!encoder) |
| 7881 | return; |
| 7882 | |
| 7883 | amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 7884 | |
| 7885 | native_mode = &amdgpu_encoder->native_mode; |
| 7886 | if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) |
| 7887 | return; |
| 7888 | |
| 7889 | drm_connector_set_panel_orientation_with_quirk(connector, |
| 7890 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN, |
| 7891 | native_mode->hdisplay, |
| 7892 | native_mode->vdisplay); |
| 7893 | } |
| 7894 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 7895 | static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, |
| 7896 | struct edid *edid) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7897 | { |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7898 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
| 7899 | to_amdgpu_dm_connector(connector); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7900 | |
| 7901 | if (edid) { |
| 7902 | /* empty probed_modes */ |
| 7903 | INIT_LIST_HEAD(&connector->probed_modes); |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7904 | amdgpu_dm_connector->num_modes = |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7905 | drm_add_edid_modes(connector, edid); |
| 7906 | |
Yogesh Mohan Marimuthu | f1e5e91 | 2019-05-17 15:46:58 +0530 | [diff] [blame] | 7907 | /* sorting the probed modes before calling function |
| 7908 | * amdgpu_dm_get_native_mode() since EDID can have |
| 7909 | * more than one preferred mode. The modes that are |
| 7910 | * later in the probed mode list could be of higher |
| 7911 | * and preferred resolution. For example, 3840x2160 |
| 7912 | * resolution in base EDID preferred timing and 4096x2160 |
| 7913 | * preferred resolution in DID extension block later. |
| 7914 | */ |
| 7915 | drm_mode_sort(&connector->probed_modes); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7916 | amdgpu_dm_get_native_mode(connector); |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 7917 | |
| 7918 | /* Freesync capabilities are reset by calling |
| 7919 | * drm_add_edid_modes() and need to be |
| 7920 | * restored here. |
| 7921 | */ |
| 7922 | amdgpu_dm_update_freesync_caps(connector, edid); |
Tom St Denis | a8d8d3d | 2017-10-17 10:38:27 -0400 | [diff] [blame] | 7923 | } else { |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 7924 | amdgpu_dm_connector->num_modes = 0; |
Tom St Denis | a8d8d3d | 2017-10-17 10:38:27 -0400 | [diff] [blame] | 7925 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 7926 | } |
| 7927 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 7928 | static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, |
| 7929 | struct drm_display_mode *mode) |
| 7930 | { |
| 7931 | struct drm_display_mode *m; |
| 7932 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 7933 | list_for_each_entry(m, &aconnector->base.probed_modes, head) { |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 7934 | if (drm_mode_equal(m, mode)) |
| 7935 | return true; |
| 7936 | } |
| 7937 | |
| 7938 | return false; |
| 7939 | } |
| 7940 | |
| 7941 | static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) |
| 7942 | { |
| 7943 | const struct drm_display_mode *m; |
| 7944 | struct drm_display_mode *new_mode; |
| 7945 | uint i; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 7946 | u32 new_modes_count = 0; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 7947 | |
| 7948 | /* Standard FPS values |
| 7949 | * |
Solomon Chiu | 12cdff6b | 2021-10-05 20:52:42 +0800 | [diff] [blame] | 7950 | * 23.976 - TV/NTSC |
Uwe Kleine-König | 3335a13 | 2023-03-27 18:07:54 +0200 | [diff] [blame] | 7951 | * 24 - Cinema |
| 7952 | * 25 - TV/PAL |
Solomon Chiu | 12cdff6b | 2021-10-05 20:52:42 +0800 | [diff] [blame] | 7953 | * 29.97 - TV/NTSC |
Uwe Kleine-König | 3335a13 | 2023-03-27 18:07:54 +0200 | [diff] [blame] | 7954 | * 30 - TV/NTSC |
| 7955 | * 48 - Cinema HFR |
| 7956 | * 50 - TV/PAL |
| 7957 | * 60 - Commonly used |
Solomon Chiu | 12cdff6b | 2021-10-05 20:52:42 +0800 | [diff] [blame] | 7958 | * 48,72,96,120 - Multiples of 24 |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 7959 | */ |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 7960 | static const u32 common_rates[] = { |
Colin Ian King | 9ce5ed6 | 2021-07-15 15:37:40 +0100 | [diff] [blame] | 7961 | 23976, 24000, 25000, 29970, 30000, |
Solomon Chiu | 12cdff6b | 2021-10-05 20:52:42 +0800 | [diff] [blame] | 7962 | 48000, 50000, 60000, 72000, 96000, 120000 |
Colin Ian King | 9ce5ed6 | 2021-07-15 15:37:40 +0100 | [diff] [blame] | 7963 | }; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 7964 | |
| 7965 | /* |
| 7966 | * Find mode with highest refresh rate with the same resolution |
| 7967 | * as the preferred mode. Some monitors report a preferred mode |
| 7968 | * with lower resolution than the highest refresh rate supported. |
| 7969 | */ |
| 7970 | |
| 7971 | m = get_highest_refresh_rate_mode(aconnector, true); |
| 7972 | if (!m) |
| 7973 | return 0; |
| 7974 | |
| 7975 | for (i = 0; i < ARRAY_SIZE(common_rates); i++) { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 7976 | u64 target_vtotal, target_vtotal_diff; |
| 7977 | u64 num, den; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 7978 | |
| 7979 | if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) |
| 7980 | continue; |
| 7981 | |
| 7982 | if (common_rates[i] < aconnector->min_vfreq * 1000 || |
| 7983 | common_rates[i] > aconnector->max_vfreq * 1000) |
| 7984 | continue; |
| 7985 | |
| 7986 | num = (unsigned long long)m->clock * 1000 * 1000; |
| 7987 | den = common_rates[i] * (unsigned long long)m->htotal; |
| 7988 | target_vtotal = div_u64(num, den); |
| 7989 | target_vtotal_diff = target_vtotal - m->vtotal; |
| 7990 | |
| 7991 | /* Check for illegal modes */ |
| 7992 | if (m->vsync_start + target_vtotal_diff < m->vdisplay || |
| 7993 | m->vsync_end + target_vtotal_diff < m->vsync_start || |
| 7994 | m->vtotal + target_vtotal_diff < m->vsync_end) |
| 7995 | continue; |
| 7996 | |
| 7997 | new_mode = drm_mode_duplicate(aconnector->base.dev, m); |
| 7998 | if (!new_mode) |
| 7999 | goto out; |
| 8000 | |
| 8001 | new_mode->vtotal += (u16)target_vtotal_diff; |
| 8002 | new_mode->vsync_start += (u16)target_vtotal_diff; |
| 8003 | new_mode->vsync_end += (u16)target_vtotal_diff; |
| 8004 | new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; |
| 8005 | new_mode->type |= DRM_MODE_TYPE_DRIVER; |
| 8006 | |
| 8007 | if (!is_duplicate_mode(aconnector, new_mode)) { |
| 8008 | drm_mode_probed_add(&aconnector->base, new_mode); |
| 8009 | new_modes_count += 1; |
| 8010 | } else |
| 8011 | drm_mode_destroy(aconnector->base.dev, new_mode); |
| 8012 | } |
| 8013 | out: |
| 8014 | return new_modes_count; |
| 8015 | } |
| 8016 | |
| 8017 | static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, |
| 8018 | struct edid *edid) |
| 8019 | { |
| 8020 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
| 8021 | to_amdgpu_dm_connector(connector); |
| 8022 | |
Alex Deucher | 3c591fa | 2024-02-27 13:08:12 -0500 | [diff] [blame] | 8023 | if (!(amdgpu_freesync_vid_mode && edid)) |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 8024 | return; |
Nikola Cornij | fe8858b | 2021-03-26 19:13:52 -0400 | [diff] [blame] | 8025 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 8026 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) |
| 8027 | amdgpu_dm_connector->num_modes += |
| 8028 | add_fs_modes(amdgpu_dm_connector); |
| 8029 | } |
| 8030 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 8031 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8032 | { |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 8033 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
| 8034 | to_amdgpu_dm_connector(connector); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8035 | struct drm_encoder *encoder; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 8036 | struct edid *edid = amdgpu_dm_connector->edid; |
Jasdeep Dhillon | c32699c | 2023-01-25 10:50:19 -0500 | [diff] [blame] | 8037 | struct dc_link_settings *verified_link_cap = |
| 8038 | &amdgpu_dm_connector->dc_link->verified_link_cap; |
Wenjing Liu | 98ce7d3 | 2023-02-23 17:04:47 -0500 | [diff] [blame] | 8039 | const struct dc *dc = amdgpu_dm_connector->dc_link->dc; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8040 | |
Daniel Vetter | 2b4c1c0 | 2018-10-04 22:24:26 +0200 | [diff] [blame] | 8041 | encoder = amdgpu_dm_connector_to_encoder(connector); |
Roman Li | 3e332d3 | 2018-02-06 18:47:26 -0500 | [diff] [blame] | 8042 | |
Bernard Zhao | 5c0e684 | 2020-11-10 00:03:13 -0800 | [diff] [blame] | 8043 | if (!drm_edid_is_valid(edid)) { |
Mikita Lipski | 1b369d3 | 2018-07-26 16:27:48 -0400 | [diff] [blame] | 8044 | amdgpu_dm_connector->num_modes = |
| 8045 | drm_add_modes_noedid(connector, 640, 480); |
Wenjing Liu | 98ce7d3 | 2023-02-23 17:04:47 -0500 | [diff] [blame] | 8046 | if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) |
Jasdeep Dhillon | c32699c | 2023-01-25 10:50:19 -0500 | [diff] [blame] | 8047 | amdgpu_dm_connector->num_modes += |
| 8048 | drm_add_modes_noedid(connector, 1920, 1080); |
Mikita Lipski | 85ee15d | 2018-05-28 10:08:30 -0400 | [diff] [blame] | 8049 | } else { |
| 8050 | amdgpu_dm_connector_ddc_get_modes(connector, edid); |
Alex Hung | 8092aa3 | 2024-06-04 16:33:18 -0600 | [diff] [blame] | 8051 | if (encoder) |
| 8052 | amdgpu_dm_connector_add_common_modes(encoder, connector); |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 8053 | amdgpu_dm_connector_add_freesync_modes(connector, edid); |
Mikita Lipski | 85ee15d | 2018-05-28 10:08:30 -0400 | [diff] [blame] | 8054 | } |
Roman Li | 3e332d3 | 2018-02-06 18:47:26 -0500 | [diff] [blame] | 8055 | amdgpu_dm_fbc_init(connector); |
Alex Deucher | 5099114b | 2018-05-31 09:09:59 -0500 | [diff] [blame] | 8056 | |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 8057 | return amdgpu_dm_connector->num_modes; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8058 | } |
| 8059 | |
Harry Wentland | 15f9dfd54 | 2022-03-25 15:30:28 -0400 | [diff] [blame] | 8060 | static const u32 supported_colorspaces = |
| 8061 | BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | |
| 8062 | BIT(DRM_MODE_COLORIMETRY_OPRGB) | |
| 8063 | BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | |
| 8064 | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); |
| 8065 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 8066 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
| 8067 | struct amdgpu_dm_connector *aconnector, |
| 8068 | int connector_type, |
| 8069 | struct dc_link *link, |
| 8070 | int link_index) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8071 | { |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 8072 | struct amdgpu_device *adev = drm_to_adev(dm->ddev); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8073 | |
Nicholas Kazlauskas | f04bee3 | 2019-06-04 15:21:14 -0400 | [diff] [blame] | 8074 | /* |
| 8075 | * Some of the properties below require access to state, like bpc. |
| 8076 | * Allocate some default initial connector state with our reset helper. |
| 8077 | */ |
| 8078 | if (aconnector->base.funcs->reset) |
| 8079 | aconnector->base.funcs->reset(&aconnector->base); |
| 8080 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8081 | aconnector->connector_id = link_index; |
Hans de Goede | f196198 | 2023-03-12 20:17:48 +0100 | [diff] [blame] | 8082 | aconnector->bl_idx = -1; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8083 | aconnector->dc_link = link; |
| 8084 | aconnector->base.interlace_allowed = false; |
| 8085 | aconnector->base.doublescan_allowed = false; |
| 8086 | aconnector->base.stereo_allowed = false; |
| 8087 | aconnector->base.dpms = DRM_MODE_DPMS_OFF; |
| 8088 | aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 8089 | aconnector->audio_inst = -1; |
Sung Joon Kim | 5b49da0 | 2023-01-12 10:38:10 -0500 | [diff] [blame] | 8090 | aconnector->pack_sdp_v1_3 = false; |
| 8091 | aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; |
| 8092 | memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8093 | mutex_init(&aconnector->hpd_lock); |
Wayne Lin | bb4fa52 | 2022-03-09 17:05:05 +0800 | [diff] [blame] | 8094 | mutex_init(&aconnector->handle_mst_msg_ready); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8095 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 8096 | /* |
| 8097 | * configure support HPD hot plug connector_>polled default value is 0 |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 8098 | * which means HPD hot plug not supported |
| 8099 | */ |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8100 | switch (connector_type) { |
| 8101 | case DRM_MODE_CONNECTOR_HDMIA: |
| 8102 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; |
Jerry (Fangzhi) Zuo | e7baae1 | 2018-06-22 17:12:47 -0400 | [diff] [blame] | 8103 | aconnector->base.ycbcr_420_allowed = |
Eric Bernstein | 9ea59d5a | 2018-09-25 15:56:41 -0400 | [diff] [blame] | 8104 | link->link_enc->features.hdmi_ycbcr420_supported ? true : false; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8105 | break; |
| 8106 | case DRM_MODE_CONNECTOR_DisplayPort: |
| 8107 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; |
Martin Tsai | d715c9a | 2022-01-23 13:19:58 -0500 | [diff] [blame] | 8108 | link->link_enc = link_enc_cfg_get_link_enc(link); |
Jude Shih | 7b201d5 | 2021-11-23 13:53:00 +0800 | [diff] [blame] | 8109 | ASSERT(link->link_enc); |
Jude Shih | f6e03f8 | 2021-09-13 14:41:34 +0800 | [diff] [blame] | 8110 | if (link->link_enc) |
| 8111 | aconnector->base.ycbcr_420_allowed = |
Eric Bernstein | 9ea59d5a | 2018-09-25 15:56:41 -0400 | [diff] [blame] | 8112 | link->link_enc->features.dp_ycbcr420_supported ? true : false; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8113 | break; |
| 8114 | case DRM_MODE_CONNECTOR_DVID: |
| 8115 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; |
| 8116 | break; |
| 8117 | default: |
| 8118 | break; |
| 8119 | } |
| 8120 | |
| 8121 | drm_object_attach_property(&aconnector->base.base, |
| 8122 | dm->ddev->mode_config.scaling_mode_property, |
| 8123 | DRM_MODE_SCALE_NONE); |
| 8124 | |
| 8125 | drm_object_attach_property(&aconnector->base.base, |
| 8126 | adev->mode_info.underscan_property, |
| 8127 | UNDERSCAN_OFF); |
| 8128 | drm_object_attach_property(&aconnector->base.base, |
| 8129 | adev->mode_info.underscan_hborder_property, |
| 8130 | 0); |
| 8131 | drm_object_attach_property(&aconnector->base.base, |
| 8132 | adev->mode_info.underscan_vborder_property, |
| 8133 | 0); |
Nicholas Kazlauskas | 1825fd3 | 2019-05-22 12:00:54 -0400 | [diff] [blame] | 8134 | |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 8135 | if (!aconnector->mst_root) |
Jerry (Fangzhi) Zuo | 8c61b31 | 2020-04-05 16:41:09 -0400 | [diff] [blame] | 8136 | drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); |
Nicholas Kazlauskas | 1825fd3 | 2019-05-22 12:00:54 -0400 | [diff] [blame] | 8137 | |
Harry Wentland | e47f169 | 2022-12-12 13:02:25 -0500 | [diff] [blame] | 8138 | aconnector->base.state->max_bpc = 16; |
Roman Li | 4a8ca46 | 2019-11-22 10:58:10 -0500 | [diff] [blame] | 8139 | aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8140 | |
Harry Wentland | 15f9dfd54 | 2022-03-25 15:30:28 -0400 | [diff] [blame] | 8141 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
Joshua Ashton | 4c4583f | 2023-09-12 15:01:56 -0100 | [diff] [blame] | 8142 | /* Content Type is currently only implemented for HDMI. */ |
| 8143 | drm_connector_attach_content_type_property(&aconnector->base); |
| 8144 | } |
| 8145 | |
| 8146 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
Harry Wentland | 15f9dfd54 | 2022-03-25 15:30:28 -0400 | [diff] [blame] | 8147 | if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) |
| 8148 | drm_connector_attach_colorspace_property(&aconnector->base); |
Fangzhi Zuo | 69a9596 | 2023-07-20 12:04:39 -0400 | [diff] [blame] | 8149 | } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || |
Harry Wentland | 15f9dfd54 | 2022-03-25 15:30:28 -0400 | [diff] [blame] | 8150 | connector_type == DRM_MODE_CONNECTOR_eDP) { |
| 8151 | if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) |
| 8152 | drm_connector_attach_colorspace_property(&aconnector->base); |
| 8153 | } |
| 8154 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8155 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA || |
Nicholas Kazlauskas | 7fad8da | 2019-01-31 13:58:21 -0500 | [diff] [blame] | 8156 | connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
| 8157 | connector_type == DRM_MODE_CONNECTOR_eDP) { |
Maxime Ripard | e057b52 | 2021-04-30 11:44:47 +0200 | [diff] [blame] | 8158 | drm_connector_attach_hdr_output_metadata_property(&aconnector->base); |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 8159 | |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 8160 | if (!aconnector->mst_root) |
Jerry (Fangzhi) Zuo | 8c61b31 | 2020-04-05 16:41:09 -0400 | [diff] [blame] | 8161 | drm_connector_attach_vrr_capable_property(&aconnector->base); |
| 8162 | |
Alex Deucher | e22bb56 | 2020-02-18 13:20:30 -0500 | [diff] [blame] | 8163 | if (adev->dm.hdcp_workqueue) |
Bhawanpreet Lakha | 53e108a | 2019-08-16 14:49:05 -0400 | [diff] [blame] | 8164 | drm_connector_attach_content_protection_property(&aconnector->base, true); |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8165 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8166 | } |
| 8167 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 8168 | static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, |
| 8169 | struct i2c_msg *msgs, int num) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8170 | { |
| 8171 | struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); |
| 8172 | struct ddc_service *ddc_service = i2c->ddc_service; |
| 8173 | struct i2c_command cmd; |
| 8174 | int i; |
| 8175 | int result = -EIO; |
| 8176 | |
Mario Limonciello | b71f4ad | 2023-11-08 13:31:57 -0600 | [diff] [blame] | 8177 | if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) |
| 8178 | return result; |
| 8179 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 8180 | cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8181 | |
| 8182 | if (!cmd.payloads) |
| 8183 | return result; |
| 8184 | |
| 8185 | cmd.number_of_payloads = num; |
| 8186 | cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; |
| 8187 | cmd.speed = 100; |
| 8188 | |
| 8189 | for (i = 0; i < num; i++) { |
| 8190 | cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); |
| 8191 | cmd.payloads[i].address = msgs[i].addr; |
| 8192 | cmd.payloads[i].length = msgs[i].len; |
| 8193 | cmd.payloads[i].data = msgs[i].buf; |
| 8194 | } |
| 8195 | |
David Francis | c85e6e5 | 2018-07-23 14:12:10 -0400 | [diff] [blame] | 8196 | if (dc_submit_i2c( |
| 8197 | ddc_service->ctx->dc, |
Fangzhi Zuo | 22676bc | 2022-06-16 15:09:01 -0400 | [diff] [blame] | 8198 | ddc_service->link->link_index, |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8199 | &cmd)) |
| 8200 | result = num; |
| 8201 | |
| 8202 | kfree(cmd.payloads); |
| 8203 | return result; |
| 8204 | } |
| 8205 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 8206 | static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8207 | { |
| 8208 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
| 8209 | } |
| 8210 | |
| 8211 | static const struct i2c_algorithm amdgpu_dm_i2c_algo = { |
| 8212 | .master_xfer = amdgpu_dm_i2c_xfer, |
| 8213 | .functionality = amdgpu_dm_i2c_func, |
| 8214 | }; |
| 8215 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 8216 | static struct amdgpu_i2c_adapter * |
| 8217 | create_i2c(struct ddc_service *ddc_service, |
| 8218 | int link_index, |
| 8219 | int *res) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8220 | { |
| 8221 | struct amdgpu_device *adev = ddc_service->ctx->driver_context; |
| 8222 | struct amdgpu_i2c_adapter *i2c; |
| 8223 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 8224 | i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); |
Ernst Sjöstrand | 2a55f09 | 2017-11-07 21:06:58 +0100 | [diff] [blame] | 8225 | if (!i2c) |
| 8226 | return NULL; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8227 | i2c->base.owner = THIS_MODULE; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8228 | i2c->base.dev.parent = &adev->pdev->dev; |
| 8229 | i2c->base.algo = &amdgpu_dm_i2c_algo; |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 8230 | snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8231 | i2c_set_adapdata(&i2c->base, i2c); |
| 8232 | i2c->ddc_service = ddc_service; |
| 8233 | |
| 8234 | return i2c; |
| 8235 | } |
| 8236 | |
Harry Wentland | 89fc8d4 | 2018-03-12 11:16:47 -0400 | [diff] [blame] | 8237 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 8238 | /* |
| 8239 | * Note: this function assumes that dc_link_detect() was called for the |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 8240 | * dc_link which will be represented by this aconnector. |
| 8241 | */ |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 8242 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
| 8243 | struct amdgpu_dm_connector *aconnector, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 8244 | u32 link_index, |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 8245 | struct amdgpu_encoder *aencoder) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8246 | { |
| 8247 | int res = 0; |
| 8248 | int connector_type; |
| 8249 | struct dc *dc = dm->dc; |
| 8250 | struct dc_link *link = dc_get_link_at_index(dc, link_index); |
| 8251 | struct amdgpu_i2c_adapter *i2c; |
Tom St Denis | 9a227d2 | 2017-10-17 10:40:08 -0400 | [diff] [blame] | 8252 | |
Harry Wentland | ff73d4c | 2023-12-01 06:25:29 -0700 | [diff] [blame] | 8253 | /* Not needed for writeback connector */ |
Tom St Denis | 9a227d2 | 2017-10-17 10:40:08 -0400 | [diff] [blame] | 8254 | link->priv = aconnector; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8255 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8256 | |
| 8257 | i2c = create_i2c(link->ddc, link->link_index, &res); |
Ernst Sjöstrand | 2a55f09 | 2017-11-07 21:06:58 +0100 | [diff] [blame] | 8258 | if (!i2c) { |
| 8259 | DRM_ERROR("Failed to create i2c adapter data\n"); |
| 8260 | return -ENOMEM; |
| 8261 | } |
| 8262 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8263 | aconnector->i2c = i2c; |
| 8264 | res = i2c_add_adapter(&i2c->base); |
| 8265 | |
| 8266 | if (res) { |
| 8267 | DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); |
| 8268 | goto out_free; |
| 8269 | } |
| 8270 | |
| 8271 | connector_type = to_drm_connector_type(link->connector_signal); |
| 8272 | |
Andrzej Pietrasiewicz | 17165de | 2019-08-26 21:25:45 +0200 | [diff] [blame] | 8273 | res = drm_connector_init_with_ddc( |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8274 | dm->ddev, |
| 8275 | &aconnector->base, |
| 8276 | &amdgpu_dm_connector_funcs, |
Andrzej Pietrasiewicz | 17165de | 2019-08-26 21:25:45 +0200 | [diff] [blame] | 8277 | connector_type, |
| 8278 | &i2c->base); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8279 | |
| 8280 | if (res) { |
| 8281 | DRM_ERROR("connector_init failed\n"); |
| 8282 | aconnector->connector_id = -1; |
| 8283 | goto out_free; |
| 8284 | } |
| 8285 | |
| 8286 | drm_connector_helper_add( |
| 8287 | &aconnector->base, |
| 8288 | &amdgpu_dm_connector_helper_funcs); |
| 8289 | |
| 8290 | amdgpu_dm_connector_init_helper( |
| 8291 | dm, |
| 8292 | aconnector, |
| 8293 | connector_type, |
| 8294 | link, |
| 8295 | link_index); |
| 8296 | |
Daniel Vetter | cde4c44 | 2018-07-09 10:40:07 +0200 | [diff] [blame] | 8297 | drm_connector_attach_encoder( |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8298 | &aconnector->base, &aencoder->base); |
| 8299 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8300 | if (connector_type == DRM_MODE_CONNECTOR_DisplayPort |
| 8301 | || connector_type == DRM_MODE_CONNECTOR_eDP) |
Alex Deucher | 7daec99 | 2020-04-16 14:44:52 -0400 | [diff] [blame] | 8302 | amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8303 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8304 | out_free: |
| 8305 | if (res) { |
| 8306 | kfree(i2c); |
| 8307 | aconnector->i2c = NULL; |
| 8308 | } |
| 8309 | return res; |
| 8310 | } |
| 8311 | |
| 8312 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) |
| 8313 | { |
| 8314 | switch (adev->mode_info.num_crtc) { |
| 8315 | case 1: |
| 8316 | return 0x1; |
| 8317 | case 2: |
| 8318 | return 0x3; |
| 8319 | case 3: |
| 8320 | return 0x7; |
| 8321 | case 4: |
| 8322 | return 0xf; |
| 8323 | case 5: |
| 8324 | return 0x1f; |
| 8325 | case 6: |
| 8326 | default: |
| 8327 | return 0x3f; |
| 8328 | } |
| 8329 | } |
| 8330 | |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 8331 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
| 8332 | struct amdgpu_encoder *aencoder, |
| 8333 | uint32_t link_index) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8334 | { |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 8335 | struct amdgpu_device *adev = drm_to_adev(dev); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8336 | |
| 8337 | int res = drm_encoder_init(dev, |
| 8338 | &aencoder->base, |
| 8339 | &amdgpu_dm_encoder_funcs, |
| 8340 | DRM_MODE_ENCODER_TMDS, |
| 8341 | NULL); |
| 8342 | |
| 8343 | aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); |
| 8344 | |
| 8345 | if (!res) |
| 8346 | aencoder->encoder_id = link_index; |
| 8347 | else |
| 8348 | aencoder->encoder_id = -1; |
| 8349 | |
| 8350 | drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); |
| 8351 | |
| 8352 | return res; |
| 8353 | } |
| 8354 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 8355 | static void manage_dm_interrupts(struct amdgpu_device *adev, |
| 8356 | struct amdgpu_crtc *acrtc, |
Hamza Mahfooz | 537ef0f | 2024-08-15 14:37:27 -0400 | [diff] [blame] | 8357 | struct dm_crtc_state *acrtc_state) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8358 | { |
| 8359 | /* |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 8360 | * We have no guarantee that the frontend index maps to the same |
| 8361 | * backend index - some even map to more than one. |
| 8362 | * |
| 8363 | * TODO: Use a different interrupt or check DC itself for the mapping. |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8364 | */ |
| 8365 | int irq_type = |
Samuel Li | 734dd01 | 2018-01-19 16:06:41 -0500 | [diff] [blame] | 8366 | amdgpu_display_crtc_idx_to_irq_type( |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8367 | adev, |
| 8368 | acrtc->crtc_id); |
Hamza Mahfooz | 537ef0f | 2024-08-15 14:37:27 -0400 | [diff] [blame] | 8369 | struct drm_vblank_crtc_config config = {0}; |
| 8370 | struct dc_crtc_timing *timing; |
| 8371 | int offdelay; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8372 | |
Hamza Mahfooz | 537ef0f | 2024-08-15 14:37:27 -0400 | [diff] [blame] | 8373 | if (acrtc_state) { |
| 8374 | if (amdgpu_ip_version(adev, DCE_HWIP, 0) < |
Hamza Mahfooz | 58a261b | 2024-08-22 11:58:22 -0400 | [diff] [blame] | 8375 | IP_VERSION(3, 5, 0) || |
| 8376 | acrtc_state->stream->link->psr_settings.psr_version < |
Aurabindo Pillai | 23d16ed | 2024-10-01 18:03:02 -0400 | [diff] [blame] | 8377 | DC_PSR_VERSION_UNSUPPORTED || |
| 8378 | !(adev->flags & AMD_IS_APU)) { |
Hamza Mahfooz | 537ef0f | 2024-08-15 14:37:27 -0400 | [diff] [blame] | 8379 | timing = &acrtc_state->stream->timing; |
| 8380 | |
| 8381 | /* at least 2 frames */ |
| 8382 | offdelay = DIV64_U64_ROUND_UP((u64)20 * |
| 8383 | timing->v_total * |
| 8384 | timing->h_total, |
| 8385 | timing->pix_clk_100hz); |
| 8386 | |
| 8387 | config.offdelay_ms = offdelay ?: 30; |
Hamza Mahfooz | e45b671 | 2024-08-20 13:53:23 -0400 | [diff] [blame] | 8388 | } else { |
| 8389 | config.disable_immediate = true; |
Hamza Mahfooz | 537ef0f | 2024-08-15 14:37:27 -0400 | [diff] [blame] | 8390 | } |
| 8391 | |
Hamza Mahfooz | 58a261b | 2024-08-22 11:58:22 -0400 | [diff] [blame] | 8392 | drm_crtc_vblank_on_config(&acrtc->base, |
| 8393 | &config); |
| 8394 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8395 | amdgpu_irq_get( |
| 8396 | adev, |
| 8397 | &adev->pageflip_irq, |
| 8398 | irq_type); |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 8399 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 8400 | amdgpu_irq_get( |
| 8401 | adev, |
| 8402 | &adev->vline0_irq, |
| 8403 | irq_type); |
| 8404 | #endif |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8405 | } else { |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 8406 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 8407 | amdgpu_irq_put( |
| 8408 | adev, |
| 8409 | &adev->vline0_irq, |
| 8410 | irq_type); |
| 8411 | #endif |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8412 | amdgpu_irq_put( |
| 8413 | adev, |
| 8414 | &adev->pageflip_irq, |
| 8415 | irq_type); |
| 8416 | drm_crtc_vblank_off(&acrtc->base); |
| 8417 | } |
| 8418 | } |
| 8419 | |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 8420 | static void dm_update_pflip_irq_state(struct amdgpu_device *adev, |
| 8421 | struct amdgpu_crtc *acrtc) |
| 8422 | { |
| 8423 | int irq_type = |
| 8424 | amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); |
| 8425 | |
| 8426 | /** |
| 8427 | * This reads the current state for the IRQ and force reapplies |
| 8428 | * the setting to hardware. |
| 8429 | */ |
| 8430 | amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); |
| 8431 | } |
| 8432 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 8433 | static bool |
| 8434 | is_scaling_state_different(const struct dm_connector_state *dm_state, |
| 8435 | const struct dm_connector_state *old_dm_state) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8436 | { |
| 8437 | if (dm_state->scaling != old_dm_state->scaling) |
| 8438 | return true; |
| 8439 | if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { |
| 8440 | if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) |
| 8441 | return true; |
| 8442 | } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { |
| 8443 | if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) |
| 8444 | return true; |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 8445 | } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || |
| 8446 | dm_state->underscan_vborder != old_dm_state->underscan_vborder) |
| 8447 | return true; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8448 | return false; |
| 8449 | } |
| 8450 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8451 | static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, |
| 8452 | struct drm_crtc_state *old_crtc_state, |
| 8453 | struct drm_connector_state *new_conn_state, |
| 8454 | struct drm_connector_state *old_conn_state, |
| 8455 | const struct drm_connector *connector, |
| 8456 | struct hdcp_workqueue *hdcp_w) |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8457 | { |
| 8458 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
Bhawanpreet Lakha | 97f6c91 | 2019-09-26 16:55:24 -0400 | [diff] [blame] | 8459 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8460 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8461 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", |
| 8462 | connector->index, connector->status, connector->dpms); |
| 8463 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", |
| 8464 | old_conn_state->content_protection, new_conn_state->content_protection); |
| 8465 | |
| 8466 | if (old_crtc_state) |
| 8467 | pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", |
| 8468 | old_crtc_state->enable, |
| 8469 | old_crtc_state->active, |
| 8470 | old_crtc_state->mode_changed, |
| 8471 | old_crtc_state->active_changed, |
| 8472 | old_crtc_state->connectors_changed); |
| 8473 | |
| 8474 | if (new_crtc_state) |
| 8475 | pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", |
| 8476 | new_crtc_state->enable, |
| 8477 | new_crtc_state->active, |
| 8478 | new_crtc_state->mode_changed, |
| 8479 | new_crtc_state->active_changed, |
| 8480 | new_crtc_state->connectors_changed); |
| 8481 | |
| 8482 | /* hdcp content type change */ |
| 8483 | if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && |
| 8484 | new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { |
| 8485 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; |
| 8486 | pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); |
Bhawanpreet Lakha | 53e108a | 2019-08-16 14:49:05 -0400 | [diff] [blame] | 8487 | return true; |
| 8488 | } |
| 8489 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8490 | /* CP is being re enabled, ignore this */ |
| 8491 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && |
| 8492 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
| 8493 | if (new_crtc_state && new_crtc_state->mode_changed) { |
| 8494 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; |
| 8495 | pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); |
| 8496 | return true; |
Yang Li | 0b8f42a | 2023-01-06 08:24:53 +0800 | [diff] [blame] | 8497 | } |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8498 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; |
| 8499 | pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8500 | return false; |
| 8501 | } |
| 8502 | |
Bhawanpreet Lakha | 31c0ed9 | 2019-09-26 17:44:50 -0400 | [diff] [blame] | 8503 | /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED |
| 8504 | * |
| 8505 | * Handles: UNDESIRED -> ENABLED |
| 8506 | */ |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8507 | if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && |
| 8508 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) |
| 8509 | new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8510 | |
Qingqing Zhuo | 0d9a947 | 2021-08-27 06:58:38 -0400 | [diff] [blame] | 8511 | /* Stream removed and re-enabled |
| 8512 | * |
| 8513 | * Can sometimes overlap with the HPD case, |
| 8514 | * thus set update_hdcp to false to avoid |
| 8515 | * setting HDCP multiple times. |
| 8516 | * |
| 8517 | * Handles: DESIRED -> DESIRED (Special case) |
| 8518 | */ |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8519 | if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && |
| 8520 | new_conn_state->crtc && new_conn_state->crtc->enabled && |
Qingqing Zhuo | 0d9a947 | 2021-08-27 06:58:38 -0400 | [diff] [blame] | 8521 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
| 8522 | dm_con_state->update_hdcp = false; |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8523 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", |
| 8524 | __func__); |
Qingqing Zhuo | 0d9a947 | 2021-08-27 06:58:38 -0400 | [diff] [blame] | 8525 | return true; |
| 8526 | } |
| 8527 | |
| 8528 | /* Hot-plug, headless s3, dpms |
| 8529 | * |
| 8530 | * Only start HDCP if the display is connected/enabled. |
| 8531 | * update_hdcp flag will be set to false until the next |
| 8532 | * HPD comes in. |
Bhawanpreet Lakha | 31c0ed9 | 2019-09-26 17:44:50 -0400 | [diff] [blame] | 8533 | * |
| 8534 | * Handles: DESIRED -> DESIRED (Special case) |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8535 | */ |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8536 | if (dm_con_state->update_hdcp && |
| 8537 | new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && |
| 8538 | connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { |
Bhawanpreet Lakha | 97f6c91 | 2019-09-26 16:55:24 -0400 | [diff] [blame] | 8539 | dm_con_state->update_hdcp = false; |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8540 | pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", |
| 8541 | __func__); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8542 | return true; |
Bhawanpreet Lakha | 97f6c91 | 2019-09-26 16:55:24 -0400 | [diff] [blame] | 8543 | } |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8544 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8545 | if (old_conn_state->content_protection == new_conn_state->content_protection) { |
| 8546 | if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
| 8547 | if (new_crtc_state && new_crtc_state->mode_changed) { |
| 8548 | pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", |
| 8549 | __func__); |
| 8550 | return true; |
Yang Li | 0b8f42a | 2023-01-06 08:24:53 +0800 | [diff] [blame] | 8551 | } |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8552 | pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", |
| 8553 | __func__); |
| 8554 | return false; |
Yang Li | 0b8f42a | 2023-01-06 08:24:53 +0800 | [diff] [blame] | 8555 | } |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8556 | |
| 8557 | pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8558 | return false; |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8559 | } |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8560 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8561 | if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { |
| 8562 | pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", |
| 8563 | __func__); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8564 | return true; |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8565 | } |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8566 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8567 | pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 8568 | return false; |
| 8569 | } |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 8570 | |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 8571 | static void remove_stream(struct amdgpu_device *adev, |
| 8572 | struct amdgpu_crtc *acrtc, |
| 8573 | struct dc_stream_state *stream) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8574 | { |
| 8575 | /* this is the update mode case */ |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8576 | |
| 8577 | acrtc->otg_inst = -1; |
| 8578 | acrtc->enabled = false; |
| 8579 | } |
| 8580 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8581 | static void prepare_flip_isr(struct amdgpu_crtc *acrtc) |
| 8582 | { |
| 8583 | |
| 8584 | assert_spin_locked(&acrtc->base.dev->event_lock); |
| 8585 | WARN_ON(acrtc->event); |
| 8586 | |
| 8587 | acrtc->event = acrtc->base.state->event; |
| 8588 | |
| 8589 | /* Set the flip status */ |
| 8590 | acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; |
| 8591 | |
| 8592 | /* Mark this event as consumed */ |
| 8593 | acrtc->base.state->event = NULL; |
| 8594 | |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 8595 | drm_dbg_state(acrtc->base.dev, |
| 8596 | "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", |
| 8597 | acrtc->crtc_id); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8598 | } |
| 8599 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8600 | static void update_freesync_state_on_stream( |
| 8601 | struct amdgpu_display_manager *dm, |
| 8602 | struct dm_crtc_state *new_crtc_state, |
Nicholas Kazlauskas | 180db30 | 2018-12-05 12:08:56 -0500 | [diff] [blame] | 8603 | struct dc_stream_state *new_stream, |
| 8604 | struct dc_plane_state *surface, |
| 8605 | u32 flip_timestamp_in_us) |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8606 | { |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8607 | struct mod_vrr_params vrr_params; |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8608 | struct dc_info_packet vrr_infopacket = {0}; |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8609 | struct amdgpu_device *adev = dm->adev; |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 8610 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8611 | unsigned long flags; |
Max.Tseng | 4cda324 | 2021-02-08 15:08:27 +0800 | [diff] [blame] | 8612 | bool pack_sdp_v1_3 = false; |
Sung Joon Kim | 5b49da0 | 2023-01-12 10:38:10 -0500 | [diff] [blame] | 8613 | struct amdgpu_dm_connector *aconn; |
| 8614 | enum vrr_packet_type packet_type = PACKET_TYPE_VRR; |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8615 | |
| 8616 | if (!new_stream) |
| 8617 | return; |
| 8618 | |
| 8619 | /* |
| 8620 | * TODO: Determine why min/max totals and vrefresh can be 0 here. |
| 8621 | * For now it's sufficient to just guard against these conditions. |
| 8622 | */ |
| 8623 | |
| 8624 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) |
| 8625 | return; |
| 8626 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 8627 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
Uwe Kleine-König | 3335a13 | 2023-03-27 18:07:54 +0200 | [diff] [blame] | 8628 | vrr_params = acrtc->dm_irq_params.vrr_params; |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8629 | |
Nicholas Kazlauskas | 180db30 | 2018-12-05 12:08:56 -0500 | [diff] [blame] | 8630 | if (surface) { |
| 8631 | mod_freesync_handle_preflip( |
| 8632 | dm->freesync_module, |
| 8633 | surface, |
| 8634 | new_stream, |
| 8635 | flip_timestamp_in_us, |
| 8636 | &vrr_params); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8637 | |
| 8638 | if (adev->family < AMDGPU_FAMILY_AI && |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 8639 | amdgpu_dm_crtc_vrr_active(new_crtc_state)) { |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8640 | mod_freesync_handle_v_update(dm->freesync_module, |
| 8641 | new_stream, &vrr_params); |
Eryk Brol | e63e249 | 2019-04-23 11:53:52 -0400 | [diff] [blame] | 8642 | |
| 8643 | /* Need to call this before the frame ends. */ |
| 8644 | dc_stream_adjust_vmin_vmax(dm->dc, |
| 8645 | new_crtc_state->stream, |
| 8646 | &vrr_params.adjust); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8647 | } |
Nicholas Kazlauskas | 180db30 | 2018-12-05 12:08:56 -0500 | [diff] [blame] | 8648 | } |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8649 | |
Sung Joon Kim | 5b49da0 | 2023-01-12 10:38:10 -0500 | [diff] [blame] | 8650 | aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; |
| 8651 | |
Bhawanpreet Lakha | 81a7be7 | 2023-06-28 11:57:51 -0400 | [diff] [blame] | 8652 | if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { |
Sung Joon Kim | 5b49da0 | 2023-01-12 10:38:10 -0500 | [diff] [blame] | 8653 | pack_sdp_v1_3 = aconn->pack_sdp_v1_3; |
| 8654 | |
| 8655 | if (aconn->vsdb_info.amd_vsdb_version == 1) |
| 8656 | packet_type = PACKET_TYPE_FS_V1; |
| 8657 | else if (aconn->vsdb_info.amd_vsdb_version == 2) |
| 8658 | packet_type = PACKET_TYPE_FS_V2; |
| 8659 | else if (aconn->vsdb_info.amd_vsdb_version == 3) |
| 8660 | packet_type = PACKET_TYPE_FS_V3; |
| 8661 | |
| 8662 | mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, |
| 8663 | &new_stream->adaptive_sync_infopacket); |
| 8664 | } |
| 8665 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8666 | mod_freesync_build_vrr_infopacket( |
| 8667 | dm->freesync_module, |
| 8668 | new_stream, |
Nicholas Kazlauskas | 180db30 | 2018-12-05 12:08:56 -0500 | [diff] [blame] | 8669 | &vrr_params, |
Sung Joon Kim | 5b49da0 | 2023-01-12 10:38:10 -0500 | [diff] [blame] | 8670 | packet_type, |
Harmanprit Tatla | ecd0136 | 2018-11-05 17:55:53 -0500 | [diff] [blame] | 8671 | TRANSFER_FUNC_UNKNOWN, |
Max.Tseng | 4cda324 | 2021-02-08 15:08:27 +0800 | [diff] [blame] | 8672 | &vrr_infopacket, |
| 8673 | pack_sdp_v1_3); |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8674 | |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 8675 | new_crtc_state->freesync_vrr_info_changed |= |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8676 | (memcmp(&new_crtc_state->vrr_infopacket, |
| 8677 | &vrr_infopacket, |
| 8678 | sizeof(vrr_infopacket)) != 0); |
| 8679 | |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 8680 | acrtc->dm_irq_params.vrr_params = vrr_params; |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8681 | new_crtc_state->vrr_infopacket = vrr_infopacket; |
| 8682 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8683 | new_stream->vrr_infopacket = vrr_infopacket; |
Aurabindo Pillai | 7eaef11 | 2023-01-05 14:21:45 -0500 | [diff] [blame] | 8684 | new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8685 | |
| 8686 | if (new_crtc_state->freesync_vrr_info_changed) |
| 8687 | DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", |
| 8688 | new_crtc_state->base.crtc->base.id, |
| 8689 | (int)new_crtc_state->base.vrr_enabled, |
Nicholas Kazlauskas | 180db30 | 2018-12-05 12:08:56 -0500 | [diff] [blame] | 8690 | (int)vrr_params.state); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8691 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 8692 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 8693 | } |
| 8694 | |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 8695 | static void update_stream_irq_parameters( |
Mario Kleiner | e854194 | 2019-03-29 13:00:53 +0100 | [diff] [blame] | 8696 | struct amdgpu_display_manager *dm, |
| 8697 | struct dm_crtc_state *new_crtc_state) |
| 8698 | { |
| 8699 | struct dc_stream_state *new_stream = new_crtc_state->stream; |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8700 | struct mod_vrr_params vrr_params; |
Mario Kleiner | e854194 | 2019-03-29 13:00:53 +0100 | [diff] [blame] | 8701 | struct mod_freesync_config config = new_crtc_state->freesync_config; |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8702 | struct amdgpu_device *adev = dm->adev; |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 8703 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8704 | unsigned long flags; |
Mario Kleiner | e854194 | 2019-03-29 13:00:53 +0100 | [diff] [blame] | 8705 | |
| 8706 | if (!new_stream) |
| 8707 | return; |
| 8708 | |
| 8709 | /* |
| 8710 | * TODO: Determine why min/max totals and vrefresh can be 0 here. |
| 8711 | * For now it's sufficient to just guard against these conditions. |
| 8712 | */ |
| 8713 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) |
| 8714 | return; |
| 8715 | |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 8716 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 8717 | vrr_params = acrtc->dm_irq_params.vrr_params; |
Mario Kleiner | 09aef2c | 2019-04-26 23:40:16 +0200 | [diff] [blame] | 8718 | |
Mario Kleiner | e854194 | 2019-03-29 13:00:53 +0100 | [diff] [blame] | 8719 | if (new_crtc_state->vrr_supported && |
| 8720 | config.min_refresh_in_uhz && |
| 8721 | config.max_refresh_in_uhz) { |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 8722 | /* |
| 8723 | * if freesync compatible mode was set, config.state will be set |
| 8724 | * in atomic check |
| 8725 | */ |
| 8726 | if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && |
| 8727 | (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || |
| 8728 | new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { |
| 8729 | vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; |
| 8730 | vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; |
| 8731 | vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; |
| 8732 | vrr_params.state = VRR_STATE_ACTIVE_FIXED; |
| 8733 | } else { |
| 8734 | config.state = new_crtc_state->base.vrr_enabled ? |
| 8735 | VRR_STATE_ACTIVE_VARIABLE : |
| 8736 | VRR_STATE_INACTIVE; |
| 8737 | } |
Mario Kleiner | e854194 | 2019-03-29 13:00:53 +0100 | [diff] [blame] | 8738 | } else { |
| 8739 | config.state = VRR_STATE_UNSUPPORTED; |
| 8740 | } |
| 8741 | |
| 8742 | mod_freesync_build_vrr_params(dm->freesync_module, |
| 8743 | new_stream, |
| 8744 | &config, &vrr_params); |
| 8745 | |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 8746 | new_crtc_state->freesync_config = config; |
| 8747 | /* Copy state for access from DM IRQ handler */ |
| 8748 | acrtc->dm_irq_params.freesync_config = config; |
| 8749 | acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; |
| 8750 | acrtc->dm_irq_params.vrr_params = vrr_params; |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 8751 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Mario Kleiner | e854194 | 2019-03-29 13:00:53 +0100 | [diff] [blame] | 8752 | } |
| 8753 | |
Mario Kleiner | 66b0c97 | 2019-03-29 13:00:54 +0100 | [diff] [blame] | 8754 | static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, |
| 8755 | struct dm_crtc_state *new_state) |
| 8756 | { |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 8757 | bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); |
| 8758 | bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); |
Mario Kleiner | 66b0c97 | 2019-03-29 13:00:54 +0100 | [diff] [blame] | 8759 | |
| 8760 | if (!old_vrr_active && new_vrr_active) { |
| 8761 | /* Transition VRR inactive -> active: |
| 8762 | * While VRR is active, we must not disable vblank irq, as a |
| 8763 | * reenable after disable would compute bogus vblank/pflip |
| 8764 | * timestamps if it likely happened inside display front-porch. |
Mario Kleiner | d2574c3 | 2019-03-29 13:00:56 +0100 | [diff] [blame] | 8765 | * |
| 8766 | * We also need vupdate irq for the actual core vblank handling |
| 8767 | * at end of vblank. |
Mario Kleiner | 66b0c97 | 2019-03-29 13:00:54 +0100 | [diff] [blame] | 8768 | */ |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 8769 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); |
Yunxiang Li | 8799c0b | 2022-09-21 17:20:19 -0400 | [diff] [blame] | 8770 | WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); |
Mario Kleiner | 66b0c97 | 2019-03-29 13:00:54 +0100 | [diff] [blame] | 8771 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", |
| 8772 | __func__, new_state->base.crtc->base.id); |
| 8773 | } else if (old_vrr_active && !new_vrr_active) { |
| 8774 | /* Transition VRR active -> inactive: |
| 8775 | * Allow vblank irq disable again for fixed refresh rate. |
| 8776 | */ |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 8777 | WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); |
Mario Kleiner | 66b0c97 | 2019-03-29 13:00:54 +0100 | [diff] [blame] | 8778 | drm_crtc_vblank_put(new_state->base.crtc); |
| 8779 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", |
| 8780 | __func__, new_state->base.crtc->base.id); |
| 8781 | } |
| 8782 | } |
| 8783 | |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 8784 | static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) |
| 8785 | { |
| 8786 | struct drm_plane *plane; |
Guenter Roeck | 5760dcb | 2021-04-21 09:18:02 -0700 | [diff] [blame] | 8787 | struct drm_plane_state *old_plane_state; |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 8788 | int i; |
| 8789 | |
| 8790 | /* |
| 8791 | * TODO: Make this per-stream so we don't issue redundant updates for |
| 8792 | * commits with multiple streams. |
| 8793 | */ |
Guenter Roeck | 5760dcb | 2021-04-21 09:18:02 -0700 | [diff] [blame] | 8794 | for_each_old_plane_in_state(state, plane, old_plane_state, i) |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 8795 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
David Tadokoro | 8bf0d9c | 2023-03-05 23:24:27 -0300 | [diff] [blame] | 8796 | amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 8797 | } |
| 8798 | |
Hamza Mahfooz | 08da182 | 2023-04-14 14:26:27 -0400 | [diff] [blame] | 8799 | static inline uint32_t get_mem_type(struct drm_framebuffer *fb) |
| 8800 | { |
| 8801 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); |
| 8802 | |
| 8803 | return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; |
| 8804 | } |
| 8805 | |
Harry Wentland | 66eba12 | 2024-03-15 13:02:00 -0400 | [diff] [blame] | 8806 | static void amdgpu_dm_update_cursor(struct drm_plane *plane, |
| 8807 | struct drm_plane_state *old_plane_state, |
| 8808 | struct dc_stream_update *update) |
| 8809 | { |
| 8810 | struct amdgpu_device *adev = drm_to_adev(plane->dev); |
| 8811 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); |
| 8812 | struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; |
| 8813 | struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; |
| 8814 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 8815 | uint64_t address = afb ? afb->address : 0; |
| 8816 | struct dc_cursor_position position = {0}; |
| 8817 | struct dc_cursor_attributes attributes; |
| 8818 | int ret; |
| 8819 | |
| 8820 | if (!plane->state->fb && !old_plane_state->fb) |
| 8821 | return; |
| 8822 | |
| 8823 | drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", |
| 8824 | amdgpu_crtc->crtc_id, plane->state->crtc_w, |
| 8825 | plane->state->crtc_h); |
| 8826 | |
| 8827 | ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); |
| 8828 | if (ret) |
| 8829 | return; |
| 8830 | |
| 8831 | if (!position.enable) { |
| 8832 | /* turn off cursor */ |
| 8833 | if (crtc_state && crtc_state->stream) { |
| 8834 | dc_stream_set_cursor_position(crtc_state->stream, |
| 8835 | &position); |
| 8836 | update->cursor_position = &crtc_state->stream->cursor_position; |
| 8837 | } |
| 8838 | return; |
| 8839 | } |
| 8840 | |
| 8841 | amdgpu_crtc->cursor_width = plane->state->crtc_w; |
| 8842 | amdgpu_crtc->cursor_height = plane->state->crtc_h; |
| 8843 | |
| 8844 | memset(&attributes, 0, sizeof(attributes)); |
| 8845 | attributes.address.high_part = upper_32_bits(address); |
| 8846 | attributes.address.low_part = lower_32_bits(address); |
| 8847 | attributes.width = plane->state->crtc_w; |
| 8848 | attributes.height = plane->state->crtc_h; |
| 8849 | attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; |
| 8850 | attributes.rotation_angle = 0; |
| 8851 | attributes.attribute_flags.value = 0; |
| 8852 | |
| 8853 | /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM |
| 8854 | * legacy gamma setup. |
| 8855 | */ |
| 8856 | if (crtc_state->cm_is_degamma_srgb && |
| 8857 | adev->dm.dc->caps.color.dpp.gamma_corr) |
| 8858 | attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; |
| 8859 | |
Srinivasan Shanmugam | 0fe2025 | 2024-08-02 12:20:36 +0530 | [diff] [blame] | 8860 | if (afb) |
| 8861 | attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; |
Harry Wentland | 66eba12 | 2024-03-15 13:02:00 -0400 | [diff] [blame] | 8862 | |
| 8863 | if (crtc_state->stream) { |
| 8864 | if (!dc_stream_set_cursor_attributes(crtc_state->stream, |
| 8865 | &attributes)) |
| 8866 | DRM_ERROR("DC failed to set cursor attributes\n"); |
| 8867 | |
| 8868 | update->cursor_attributes = &crtc_state->stream->cursor_attributes; |
| 8869 | |
| 8870 | if (!dc_stream_set_cursor_position(crtc_state->stream, |
| 8871 | &position)) |
| 8872 | DRM_ERROR("DC failed to set cursor position\n"); |
| 8873 | |
| 8874 | update->cursor_position = &crtc_state->stream->cursor_position; |
| 8875 | } |
| 8876 | } |
| 8877 | |
Tom Chung | bd8a957 | 2024-10-29 17:28:23 +0800 | [diff] [blame] | 8878 | static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, |
| 8879 | const struct dm_crtc_state *acrtc_state, |
| 8880 | const u64 current_ts) |
| 8881 | { |
| 8882 | struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; |
| 8883 | struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; |
| 8884 | struct amdgpu_dm_connector *aconn = |
| 8885 | (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; |
| 8886 | |
| 8887 | if (acrtc_state->update_type > UPDATE_TYPE_FAST) { |
| 8888 | if (pr->config.replay_supported && !pr->replay_feature_enabled) |
| 8889 | amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); |
| 8890 | else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED && |
| 8891 | !psr->psr_feature_enabled) |
| 8892 | if (!aconn->disallow_edp_enter_psr) |
| 8893 | amdgpu_dm_link_setup_psr(acrtc_state->stream); |
| 8894 | } |
| 8895 | |
| 8896 | /* Decrement skip count when SR is enabled and we're doing fast updates. */ |
| 8897 | if (acrtc_state->update_type == UPDATE_TYPE_FAST && |
| 8898 | (psr->psr_feature_enabled || pr->config.replay_supported)) { |
| 8899 | if (aconn->sr_skip_count > 0) |
| 8900 | aconn->sr_skip_count--; |
| 8901 | |
| 8902 | /* Allow SR when skip count is 0. */ |
| 8903 | acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; |
| 8904 | |
| 8905 | /* |
| 8906 | * If sink supports PSR SU/Panel Replay, there is no need to rely on |
| 8907 | * a vblank event disable request to enable PSR/RP. PSR SU/RP |
| 8908 | * can be enabled immediately once OS demonstrates an |
| 8909 | * adequate number of fast atomic commits to notify KMD |
| 8910 | * of update events. See `vblank_control_worker()`. |
| 8911 | */ |
| 8912 | if (acrtc_attach->dm_irq_params.allow_sr_entry && |
| 8913 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY |
| 8914 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && |
| 8915 | #endif |
| 8916 | (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { |
| 8917 | if (pr->replay_feature_enabled && !pr->replay_allow_active) |
| 8918 | amdgpu_dm_replay_enable(acrtc_state->stream, true); |
| 8919 | if (psr->psr_version >= DC_PSR_VERSION_SU_1 && |
| 8920 | !psr->psr_allow_active && !aconn->disallow_edp_enter_psr) |
| 8921 | amdgpu_dm_psr_enable(acrtc_state->stream); |
| 8922 | } |
| 8923 | } else { |
| 8924 | acrtc_attach->dm_irq_params.allow_sr_entry = false; |
| 8925 | } |
| 8926 | } |
| 8927 | |
Harry Wentland | 3be5262e | 2017-07-27 09:55:38 -0400 | [diff] [blame] | 8928 | static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 8929 | struct drm_device *dev, |
| 8930 | struct amdgpu_display_manager *dm, |
| 8931 | struct drm_crtc *pcrtc, |
David Francis | 420cd47 | 2019-03-01 18:15:26 -0500 | [diff] [blame] | 8932 | bool wait_for_vblank) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8933 | { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 8934 | u32 i; |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 8935 | u64 timestamp_ns = ktime_get_ns(); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8936 | struct drm_plane *plane; |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 8937 | struct drm_plane_state *old_plane_state, *new_plane_state; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8938 | struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 8939 | struct drm_crtc_state *new_pcrtc_state = |
| 8940 | drm_atomic_get_new_crtc_state(state, pcrtc); |
| 8941 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); |
Harry Wentland | 44d09c6 | 2018-03-15 14:29:24 -0400 | [diff] [blame] | 8942 | struct dm_crtc_state *dm_old_crtc_state = |
| 8943 | to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 8944 | int planes_count = 0, vpos, hpos; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8945 | unsigned long flags; |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 8946 | u32 target_vblank, last_flip_vblank; |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 8947 | bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); |
Michel Dänzer | cc79950 | 2022-07-11 16:51:31 +0200 | [diff] [blame] | 8948 | bool cursor_update = false; |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 8949 | bool pflip_present = false; |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 8950 | bool dirty_rects_changed = false; |
Harry Wentland | 66eba12 | 2024-03-15 13:02:00 -0400 | [diff] [blame] | 8951 | bool updated_planes_and_streams = false; |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 8952 | struct { |
| 8953 | struct dc_surface_update surface_updates[MAX_SURFACES]; |
| 8954 | struct dc_plane_info plane_infos[MAX_SURFACES]; |
| 8955 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 8956 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 8957 | struct dc_stream_update stream_update; |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 8958 | } *bundle; |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 8959 | |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 8960 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 8961 | |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 8962 | if (!bundle) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 8963 | drm_err(dev, "Failed to allocate update bundle\n"); |
Nicholas Kazlauskas | 4b51050 | 2019-01-28 09:00:52 -0500 | [diff] [blame] | 8964 | goto cleanup; |
| 8965 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8966 | |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 8967 | /* |
| 8968 | * Disable the cursor first if we're disabling all the planes. |
| 8969 | * It'll remain on the screen after the planes are re-enabled |
| 8970 | * if we don't. |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 8971 | * |
| 8972 | * If the cursor is transitioning from native to overlay mode, the |
| 8973 | * native cursor needs to be disabled first. |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 8974 | */ |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 8975 | if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && |
| 8976 | dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { |
| 8977 | struct dc_cursor_position cursor_position = {0}; |
| 8978 | |
| 8979 | if (!dc_stream_set_cursor_position(acrtc_state->stream, |
| 8980 | &cursor_position)) |
| 8981 | drm_err(dev, "DC failed to disable native cursor\n"); |
| 8982 | |
| 8983 | bundle->stream_update.cursor_position = |
| 8984 | &acrtc_state->stream->cursor_position; |
| 8985 | } |
| 8986 | |
| 8987 | if (acrtc_state->active_planes == 0 && |
| 8988 | dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 8989 | amdgpu_dm_commit_cursors(state); |
| 8990 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 8991 | /* update planes when needed */ |
Anson Jacob | efc8278 | 2021-02-18 19:42:57 -0500 | [diff] [blame] | 8992 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 8993 | struct drm_crtc *crtc = new_plane_state->crtc; |
Drew Davenport | f5ba60f | 2017-10-27 12:34:46 -0600 | [diff] [blame] | 8994 | struct drm_crtc_state *new_crtc_state; |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 8995 | struct drm_framebuffer *fb = new_plane_state->fb; |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 8996 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; |
David Francis | 34bafd2 | 2019-02-06 14:01:29 -0500 | [diff] [blame] | 8997 | bool plane_needs_flip; |
Nicholas Kazlauskas | c7af5f7 | 2019-01-10 09:51:54 -0500 | [diff] [blame] | 8998 | struct dc_plane_state *dc_plane; |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 8999 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9000 | |
Nicholas Kazlauskas | 80c218d56 | 2019-01-25 15:30:24 -0500 | [diff] [blame] | 9001 | /* Cursor plane is handled after stream updates */ |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 9002 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
| 9003 | acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { |
Michel Dänzer | cc79950 | 2022-07-11 16:51:31 +0200 | [diff] [blame] | 9004 | if ((fb && crtc == pcrtc) || |
Harry Wentland | 66eba12 | 2024-03-15 13:02:00 -0400 | [diff] [blame] | 9005 | (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { |
Michel Dänzer | cc79950 | 2022-07-11 16:51:31 +0200 | [diff] [blame] | 9006 | cursor_update = true; |
Harry Wentland | e582c09 | 2024-04-19 14:29:46 -0400 | [diff] [blame] | 9007 | if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) |
| 9008 | amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); |
Harry Wentland | 66eba12 | 2024-03-15 13:02:00 -0400 | [diff] [blame] | 9009 | } |
Michel Dänzer | cc79950 | 2022-07-11 16:51:31 +0200 | [diff] [blame] | 9010 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9011 | continue; |
Michel Dänzer | cc79950 | 2022-07-11 16:51:31 +0200 | [diff] [blame] | 9012 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9013 | |
Drew Davenport | f5ba60f | 2017-10-27 12:34:46 -0600 | [diff] [blame] | 9014 | if (!fb || !crtc || pcrtc != crtc) |
| 9015 | continue; |
| 9016 | |
| 9017 | new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); |
| 9018 | if (!new_crtc_state->active) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9019 | continue; |
| 9020 | |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9021 | dc_plane = dm_new_plane_state->dc_state; |
Aurabindo Pillai | da5e149 | 2023-03-24 10:42:37 -0400 | [diff] [blame] | 9022 | if (!dc_plane) |
| 9023 | continue; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9024 | |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 9025 | bundle->surface_updates[planes_count].surface = dc_plane; |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9026 | if (new_pcrtc_state->color_mgmt_changed) { |
Alvin Lee | 285a705 | 2024-03-15 17:54:20 -0400 | [diff] [blame] | 9027 | bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; |
| 9028 | bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; |
Stylon Wang | 44efb78 | 2020-03-26 23:19:44 +0800 | [diff] [blame] | 9029 | bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; |
Joshua Ashton | 4bc59dd | 2023-11-16 18:58:02 -0100 | [diff] [blame] | 9030 | bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; |
Alvin Lee | 285a705 | 2024-03-15 17:54:20 -0400 | [diff] [blame] | 9031 | bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func; |
| 9032 | bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func; |
| 9033 | bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf; |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9034 | } |
| 9035 | |
David Tadokoro | 8bf0d9c | 2023-03-05 23:24:27 -0300 | [diff] [blame] | 9036 | amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 9037 | &bundle->scaling_infos[planes_count]); |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9038 | |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 9039 | bundle->surface_updates[planes_count].scaling_info = |
| 9040 | &bundle->scaling_infos[planes_count]; |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9041 | |
David Francis | f503100 | 2019-02-13 13:20:11 -0500 | [diff] [blame] | 9042 | plane_needs_flip = old_plane_state->fb && new_plane_state->fb; |
| 9043 | |
| 9044 | pflip_present = pflip_present || plane_needs_flip; |
| 9045 | |
| 9046 | if (!plane_needs_flip) { |
| 9047 | planes_count += 1; |
| 9048 | continue; |
| 9049 | } |
| 9050 | |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 9051 | fill_dc_plane_info_and_addr( |
Nicholas Kazlauskas | 8ce5d8425 | 2020-08-06 15:48:10 -0400 | [diff] [blame] | 9052 | dm->adev, new_plane_state, |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 9053 | afb->tiling_flags, |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 9054 | &bundle->plane_infos[planes_count], |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 9055 | &bundle->flip_addrs[planes_count].address, |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 9056 | afb->tmz_surface, false); |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 9057 | |
Sean Paul | 9f07550 | 2022-03-25 00:06:19 +0000 | [diff] [blame] | 9058 | drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", |
Rodrigo Siqueira | 87b7ebc | 2020-04-22 17:43:26 -0400 | [diff] [blame] | 9059 | new_plane_state->plane->index, |
| 9060 | bundle->plane_infos[planes_count].dcc.enable); |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 9061 | |
| 9062 | bundle->surface_updates[planes_count].plane_info = |
| 9063 | &bundle->plane_infos[planes_count]; |
David Francis | f503100 | 2019-02-13 13:20:11 -0500 | [diff] [blame] | 9064 | |
Bhawanpreet Lakha | 679fc89 | 2023-08-22 10:02:46 -0400 | [diff] [blame] | 9065 | if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || |
| 9066 | acrtc_state->stream->link->replay_settings.replay_feature_enabled) { |
Hamza Mahfooz | d852871 | 2022-11-09 12:06:27 -0500 | [diff] [blame] | 9067 | fill_dc_dirty_rects(plane, old_plane_state, |
| 9068 | new_plane_state, new_crtc_state, |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 9069 | &bundle->flip_addrs[planes_count], |
Hamza Mahfooz | fc184db | 2024-02-08 16:23:29 -0500 | [diff] [blame] | 9070 | acrtc_state->stream->link->psr_settings.psr_version == |
| 9071 | DC_PSR_VERSION_SU_1, |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 9072 | &dirty_rects_changed); |
| 9073 | |
| 9074 | /* |
| 9075 | * If the dirty regions changed, PSR-SU need to be disabled temporarily |
| 9076 | * and enabled it again after dirty regions are stable to avoid video glitch. |
| 9077 | * PSR-SU will be enabled in vblank_control_worker() if user pause the video |
| 9078 | * during the PSR-SU was disabled. |
| 9079 | */ |
| 9080 | if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && |
Tom Chung | b8d9d5f | 2024-10-29 15:38:16 +0800 | [diff] [blame] | 9081 | acrtc_attach->dm_irq_params.allow_sr_entry && |
Tom Chung | d6ed6d0 | 2023-02-01 17:37:51 +0800 | [diff] [blame] | 9082 | #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY |
| 9083 | !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && |
| 9084 | #endif |
| 9085 | dirty_rects_changed) { |
| 9086 | mutex_lock(&dm->dc_lock); |
| 9087 | acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = |
| 9088 | timestamp_ns; |
| 9089 | if (acrtc_state->stream->link->psr_settings.psr_allow_active) |
| 9090 | amdgpu_dm_psr_disable(acrtc_state->stream); |
| 9091 | mutex_unlock(&dm->dc_lock); |
| 9092 | } |
| 9093 | } |
Leo Li | 7cc191e | 2022-03-30 12:45:09 -0400 | [diff] [blame] | 9094 | |
Nicholas Kazlauskas | caff0e6 | 2019-08-02 10:45:11 -0400 | [diff] [blame] | 9095 | /* |
| 9096 | * Only allow immediate flips for fast updates that don't |
Hamza Mahfooz | 08da182 | 2023-04-14 14:26:27 -0400 | [diff] [blame] | 9097 | * change memory domain, FB pitch, DCC state, rotation or |
| 9098 | * mirroring. |
Simon Ser | c1e18c4 | 2023-06-21 17:24:59 -0300 | [diff] [blame] | 9099 | * |
| 9100 | * dm_crtc_helper_atomic_check() only accepts async flips with |
| 9101 | * fast updates. |
Nicholas Kazlauskas | caff0e6 | 2019-08-02 10:45:11 -0400 | [diff] [blame] | 9102 | */ |
Simon Ser | c1e18c4 | 2023-06-21 17:24:59 -0300 | [diff] [blame] | 9103 | if (crtc->state->async_flip && |
Hamza Mahfooz | a7c0cad | 2023-08-04 11:13:04 -0400 | [diff] [blame] | 9104 | (acrtc_state->update_type != UPDATE_TYPE_FAST || |
| 9105 | get_mem_type(old_plane_state->fb) != get_mem_type(fb))) |
Simon Ser | c1e18c4 | 2023-06-21 17:24:59 -0300 | [diff] [blame] | 9106 | drm_warn_once(state->dev, |
| 9107 | "[PLANE:%d:%s] async flip with non-fast update\n", |
| 9108 | plane->base.id, plane->name); |
Hamza Mahfooz | a7c0cad | 2023-08-04 11:13:04 -0400 | [diff] [blame] | 9109 | |
David Francis | f503100 | 2019-02-13 13:20:11 -0500 | [diff] [blame] | 9110 | bundle->flip_addrs[planes_count].flip_immediate = |
Daniel Vetter | 4d85f45 | 2019-09-03 21:06:42 +0200 | [diff] [blame] | 9111 | crtc->state->async_flip && |
Hamza Mahfooz | 08da182 | 2023-04-14 14:26:27 -0400 | [diff] [blame] | 9112 | acrtc_state->update_type == UPDATE_TYPE_FAST && |
| 9113 | get_mem_type(old_plane_state->fb) == get_mem_type(fb); |
David Francis | f503100 | 2019-02-13 13:20:11 -0500 | [diff] [blame] | 9114 | |
| 9115 | timestamp_ns = ktime_get_ns(); |
| 9116 | bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); |
| 9117 | bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; |
| 9118 | bundle->surface_updates[planes_count].surface = dc_plane; |
| 9119 | |
| 9120 | if (!bundle->surface_updates[planes_count].surface) { |
| 9121 | DRM_ERROR("No surface for CRTC: id=%d\n", |
| 9122 | acrtc_attach->crtc_id); |
| 9123 | continue; |
| 9124 | } |
| 9125 | |
| 9126 | if (plane == pcrtc->primary) |
| 9127 | update_freesync_state_on_stream( |
| 9128 | dm, |
| 9129 | acrtc_state, |
| 9130 | acrtc_state->stream, |
| 9131 | dc_plane, |
| 9132 | bundle->flip_addrs[planes_count].flip_timestamp_in_us); |
| 9133 | |
Sean Paul | 9f07550 | 2022-03-25 00:06:19 +0000 | [diff] [blame] | 9134 | drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", |
David Francis | f503100 | 2019-02-13 13:20:11 -0500 | [diff] [blame] | 9135 | __func__, |
| 9136 | bundle->flip_addrs[planes_count].address.grph.addr.high_part, |
| 9137 | bundle->flip_addrs[planes_count].address.grph.addr.low_part); |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9138 | |
| 9139 | planes_count += 1; |
| 9140 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9141 | } |
| 9142 | |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 9143 | if (pflip_present) { |
Mario Kleiner | 634092b | 2019-02-09 07:52:55 +0100 | [diff] [blame] | 9144 | if (!vrr_active) { |
| 9145 | /* Use old throttling in non-vrr fixed refresh rate mode |
| 9146 | * to keep flip scheduling based on target vblank counts |
| 9147 | * working in a backwards compatible way, e.g., for |
| 9148 | * clients using the GLX_OML_sync_control extension or |
| 9149 | * DRI3/Present extension with defined target_msc. |
| 9150 | */ |
Thomas Zimmermann | e3eff4b | 2020-01-23 14:59:26 +0100 | [diff] [blame] | 9151 | last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 9152 | } else { |
Mario Kleiner | 634092b | 2019-02-09 07:52:55 +0100 | [diff] [blame] | 9153 | /* For variable refresh rate mode only: |
| 9154 | * Get vblank of last completed flip to avoid > 1 vrr |
| 9155 | * flips per video frame by use of throttling, but allow |
| 9156 | * flip programming anywhere in the possibly large |
| 9157 | * variable vrr vblank interval for fine-grained flip |
| 9158 | * timing control and more opportunity to avoid stutter |
| 9159 | * on late submission of flips. |
| 9160 | */ |
| 9161 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
Aurabindo Pillai | 5d1c59c | 2020-08-12 12:40:34 -0400 | [diff] [blame] | 9162 | last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; |
Mario Kleiner | 634092b | 2019-02-09 07:52:55 +0100 | [diff] [blame] | 9163 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
| 9164 | } |
| 9165 | |
Mario Kleiner | fdd1fe5 | 2019-04-02 17:00:06 -0500 | [diff] [blame] | 9166 | target_vblank = last_flip_vblank + wait_for_vblank; |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 9167 | |
| 9168 | /* |
| 9169 | * Wait until we're out of the vertical blank period before the one |
| 9170 | * targeted by the flip |
| 9171 | */ |
| 9172 | while ((acrtc_attach->enabled && |
| 9173 | (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, |
| 9174 | 0, &vpos, &hpos, NULL, |
| 9175 | NULL, &pcrtc->hwmode) |
| 9176 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == |
| 9177 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && |
| 9178 | (int)(target_vblank - |
Thomas Zimmermann | e3eff4b | 2020-01-23 14:59:26 +0100 | [diff] [blame] | 9179 | amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 9180 | usleep_range(1000, 1100); |
| 9181 | } |
| 9182 | |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 9183 | /** |
| 9184 | * Prepare the flip event for the pageflip interrupt to handle. |
| 9185 | * |
| 9186 | * This only works in the case where we've already turned on the |
| 9187 | * appropriate hardware blocks (eg. HUBP) so in the transition case |
| 9188 | * from 0 -> n planes we have to skip a hardware generated event |
| 9189 | * and rely on sending it from software. |
| 9190 | */ |
| 9191 | if (acrtc_attach->base.state->event && |
Wayne Lin | 10a36226 | 2022-04-13 15:52:48 +0800 | [diff] [blame] | 9192 | acrtc_state->active_planes > 0) { |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 9193 | drm_crtc_vblank_get(pcrtc); |
| 9194 | |
| 9195 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
| 9196 | |
| 9197 | WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); |
| 9198 | prepare_flip_isr(acrtc_attach); |
| 9199 | |
| 9200 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
| 9201 | } |
| 9202 | |
| 9203 | if (acrtc_state->stream) { |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 9204 | if (acrtc_state->freesync_vrr_info_changed) |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 9205 | bundle->stream_update.vrr_infopacket = |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 9206 | &acrtc_state->stream->vrr_infopacket; |
| 9207 | } |
Alex Hung | ae13c8a | 2024-04-26 10:33:47 -0600 | [diff] [blame] | 9208 | } else if (cursor_update && acrtc_state->active_planes > 0) { |
Michel Dänzer | cc79950 | 2022-07-11 16:51:31 +0200 | [diff] [blame] | 9209 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
Alex Hung | ae13c8a | 2024-04-26 10:33:47 -0600 | [diff] [blame] | 9210 | if (acrtc_attach->base.state->event) { |
| 9211 | drm_crtc_vblank_get(pcrtc); |
| 9212 | acrtc_attach->event = acrtc_attach->base.state->event; |
| 9213 | acrtc_attach->base.state->event = NULL; |
| 9214 | } |
Michel Dänzer | cc79950 | 2022-07-11 16:51:31 +0200 | [diff] [blame] | 9215 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
David Francis | 8a48b44 | 2018-12-11 15:17:15 -0500 | [diff] [blame] | 9216 | } |
| 9217 | |
Nicholas Kazlauskas | bc92c06 | 2019-04-04 11:00:53 -0400 | [diff] [blame] | 9218 | /* Update the planes if changed or disable if we don't have any. */ |
Ernst Sjöstrand | ed9656f | 2019-06-24 17:15:42 +0200 | [diff] [blame] | 9219 | if ((planes_count || acrtc_state->active_planes == 0) && |
| 9220 | acrtc_state->stream) { |
Nicholas Kazlauskas | 58aa1c5 | 2021-08-03 16:32:31 -0400 | [diff] [blame] | 9221 | /* |
| 9222 | * If PSR or idle optimizations are enabled then flush out |
| 9223 | * any pending work before hardware programming. |
| 9224 | */ |
Nicholas Kazlauskas | 06dd188 | 2021-09-07 09:53:03 -0400 | [diff] [blame] | 9225 | if (dm->vblank_control_workqueue) |
| 9226 | flush_workqueue(dm->vblank_control_workqueue); |
Nicholas Kazlauskas | 58aa1c5 | 2021-08-03 16:32:31 -0400 | [diff] [blame] | 9227 | |
Dmytro Laktyushkin | b6e881c | 2019-09-13 18:00:28 -0500 | [diff] [blame] | 9228 | bundle->stream_update.stream = acrtc_state->stream; |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9229 | if (new_pcrtc_state->mode_changed) { |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 9230 | bundle->stream_update.src = acrtc_state->stream->src; |
| 9231 | bundle->stream_update.dst = acrtc_state->stream->dst; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9232 | } |
| 9233 | |
Nicholas Kazlauskas | cf020d49 | 2019-05-09 12:14:58 -0400 | [diff] [blame] | 9234 | if (new_pcrtc_state->color_mgmt_changed) { |
| 9235 | /* |
| 9236 | * TODO: This isn't fully correct since we've actually |
| 9237 | * already modified the stream in place. |
| 9238 | */ |
| 9239 | bundle->stream_update.gamut_remap = |
| 9240 | &acrtc_state->stream->gamut_remap_matrix; |
| 9241 | bundle->stream_update.output_csc_transform = |
| 9242 | &acrtc_state->stream->csc_color_matrix; |
| 9243 | bundle->stream_update.out_transfer_func = |
Alvin Lee | 285a705 | 2024-03-15 17:54:20 -0400 | [diff] [blame] | 9244 | &acrtc_state->stream->out_transfer_func; |
Joshua Ashton | cb19dc4 | 2023-11-16 18:58:09 -0100 | [diff] [blame] | 9245 | bundle->stream_update.lut3d_func = |
| 9246 | (struct dc_3dlut *) acrtc_state->stream->lut3d_func; |
| 9247 | bundle->stream_update.func_shaper = |
| 9248 | (struct dc_transfer_func *) acrtc_state->stream->func_shaper; |
Nicholas Kazlauskas | cf020d49 | 2019-05-09 12:14:58 -0400 | [diff] [blame] | 9249 | } |
Harry Wentland | 44d09c6 | 2018-03-15 14:29:24 -0400 | [diff] [blame] | 9250 | |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9251 | acrtc_state->stream->abm_level = acrtc_state->abm_level; |
| 9252 | if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 9253 | bundle->stream_update.abm_level = &acrtc_state->abm_level; |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9254 | |
Tom Chung | f308116 | 2023-05-29 18:00:09 +0800 | [diff] [blame] | 9255 | mutex_lock(&dm->dc_lock); |
Tom Chung | bd8a957 | 2024-10-29 17:28:23 +0800 | [diff] [blame] | 9256 | if (acrtc_state->update_type > UPDATE_TYPE_FAST) { |
| 9257 | if (acrtc_state->stream->link->replay_settings.replay_allow_active) |
| 9258 | amdgpu_dm_replay_disable(acrtc_state->stream); |
| 9259 | if (acrtc_state->stream->link->psr_settings.psr_allow_active) |
| 9260 | amdgpu_dm_psr_disable(acrtc_state->stream); |
| 9261 | } |
Tom Chung | f308116 | 2023-05-29 18:00:09 +0800 | [diff] [blame] | 9262 | mutex_unlock(&dm->dc_lock); |
| 9263 | |
Eryk Brol | e63e249 | 2019-04-23 11:53:52 -0400 | [diff] [blame] | 9264 | /* |
| 9265 | * If FreeSync state on the stream has changed then we need to |
| 9266 | * re-adjust the min/max bounds now that DC doesn't handle this |
| 9267 | * as part of commit. |
| 9268 | */ |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 9269 | if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { |
Eryk Brol | e63e249 | 2019-04-23 11:53:52 -0400 | [diff] [blame] | 9270 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
| 9271 | dc_stream_adjust_vmin_vmax( |
| 9272 | dm->dc, acrtc_state->stream, |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 9273 | &acrtc_attach->dm_irq_params.vrr_params.adjust); |
Eryk Brol | e63e249 | 2019-04-23 11:53:52 -0400 | [diff] [blame] | 9274 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
| 9275 | } |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9276 | mutex_lock(&dm->dc_lock); |
Rodrigo Siqueira | 81f743a | 2023-02-23 11:36:08 -0700 | [diff] [blame] | 9277 | update_planes_and_stream_adapter(dm->dc, |
| 9278 | acrtc_state->update_type, |
| 9279 | planes_count, |
| 9280 | acrtc_state->stream, |
| 9281 | &bundle->stream_update, |
| 9282 | bundle->surface_updates); |
Harry Wentland | 66eba12 | 2024-03-15 13:02:00 -0400 | [diff] [blame] | 9283 | updated_planes_and_streams = true; |
Roman Li | 8c32230 | 2019-09-20 19:03:17 -0400 | [diff] [blame] | 9284 | |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 9285 | /** |
| 9286 | * Enable or disable the interrupts on the backend. |
| 9287 | * |
| 9288 | * Most pipes are put into power gating when unused. |
| 9289 | * |
| 9290 | * When power gating is enabled on a pipe we lose the |
| 9291 | * interrupt enablement state when power gating is disabled. |
| 9292 | * |
| 9293 | * So we need to update the IRQ control state in hardware |
| 9294 | * whenever the pipe turns on (since it could be previously |
| 9295 | * power gated) or off (since some pipes can't be power gated |
| 9296 | * on some ASICs). |
| 9297 | */ |
| 9298 | if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 9299 | dm_update_pflip_irq_state(drm_to_adev(dev), |
| 9300 | acrtc_attach); |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 9301 | |
Tom Chung | bd8a957 | 2024-10-29 17:28:23 +0800 | [diff] [blame] | 9302 | amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns); |
David Francis | bc7f670 | 2018-12-19 10:45:16 -0500 | [diff] [blame] | 9303 | mutex_unlock(&dm->dc_lock); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9304 | } |
Nicholas Kazlauskas | 4b51050 | 2019-01-28 09:00:52 -0500 | [diff] [blame] | 9305 | |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 9306 | /* |
| 9307 | * Update cursor state *after* programming all the planes. |
| 9308 | * This avoids redundant programming in the case where we're going |
| 9309 | * to be disabling a single plane - those pipes are being disabled. |
| 9310 | */ |
Harry Wentland | e582c09 | 2024-04-19 14:29:46 -0400 | [diff] [blame] | 9311 | if (acrtc_state->active_planes && |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 9312 | (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && |
| 9313 | acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) |
Nicholas Kazlauskas | 8ad2780 | 2019-04-08 10:37:44 -0400 | [diff] [blame] | 9314 | amdgpu_dm_commit_cursors(state); |
Nicholas Kazlauskas | 80c218d56 | 2019-01-25 15:30:24 -0500 | [diff] [blame] | 9315 | |
Nicholas Kazlauskas | 4b51050 | 2019-01-28 09:00:52 -0500 | [diff] [blame] | 9316 | cleanup: |
David Francis | 74aa7bd | 2019-03-01 18:22:07 -0500 | [diff] [blame] | 9317 | kfree(bundle); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9318 | } |
| 9319 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 9320 | static void amdgpu_dm_commit_audio(struct drm_device *dev, |
| 9321 | struct drm_atomic_state *state) |
| 9322 | { |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 9323 | struct amdgpu_device *adev = drm_to_adev(dev); |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 9324 | struct amdgpu_dm_connector *aconnector; |
| 9325 | struct drm_connector *connector; |
| 9326 | struct drm_connector_state *old_con_state, *new_con_state; |
| 9327 | struct drm_crtc_state *new_crtc_state; |
| 9328 | struct dm_crtc_state *new_dm_crtc_state; |
| 9329 | const struct dc_stream_status *status; |
| 9330 | int i, inst; |
| 9331 | |
| 9332 | /* Notify device removals. */ |
| 9333 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
| 9334 | if (old_con_state->crtc != new_con_state->crtc) { |
| 9335 | /* CRTC changes require notification. */ |
| 9336 | goto notify; |
| 9337 | } |
| 9338 | |
| 9339 | if (!new_con_state->crtc) |
| 9340 | continue; |
| 9341 | |
| 9342 | new_crtc_state = drm_atomic_get_new_crtc_state( |
| 9343 | state, new_con_state->crtc); |
| 9344 | |
| 9345 | if (!new_crtc_state) |
| 9346 | continue; |
| 9347 | |
| 9348 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
| 9349 | continue; |
| 9350 | |
Alex Hung | cf82a80 | 2024-03-15 21:25:25 -0600 | [diff] [blame] | 9351 | notify: |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 9352 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 9353 | continue; |
| 9354 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 9355 | aconnector = to_amdgpu_dm_connector(connector); |
| 9356 | |
| 9357 | mutex_lock(&adev->dm.audio_lock); |
| 9358 | inst = aconnector->audio_inst; |
| 9359 | aconnector->audio_inst = -1; |
| 9360 | mutex_unlock(&adev->dm.audio_lock); |
| 9361 | |
| 9362 | amdgpu_dm_audio_eld_notify(adev, inst); |
| 9363 | } |
| 9364 | |
| 9365 | /* Notify audio device additions. */ |
| 9366 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
| 9367 | if (!new_con_state->crtc) |
| 9368 | continue; |
| 9369 | |
| 9370 | new_crtc_state = drm_atomic_get_new_crtc_state( |
| 9371 | state, new_con_state->crtc); |
| 9372 | |
| 9373 | if (!new_crtc_state) |
| 9374 | continue; |
| 9375 | |
| 9376 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
| 9377 | continue; |
| 9378 | |
| 9379 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 9380 | if (!new_dm_crtc_state->stream) |
| 9381 | continue; |
| 9382 | |
| 9383 | status = dc_stream_get_status(new_dm_crtc_state->stream); |
| 9384 | if (!status) |
| 9385 | continue; |
| 9386 | |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 9387 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 9388 | continue; |
| 9389 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 9390 | aconnector = to_amdgpu_dm_connector(connector); |
| 9391 | |
| 9392 | mutex_lock(&adev->dm.audio_lock); |
| 9393 | inst = status->audio_inst; |
| 9394 | aconnector->audio_inst = inst; |
| 9395 | mutex_unlock(&adev->dm.audio_lock); |
| 9396 | |
| 9397 | amdgpu_dm_audio_eld_notify(adev, inst); |
| 9398 | } |
| 9399 | } |
| 9400 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 9401 | /* |
Leo (Sunpeng) Li | 27b3f4f | 2017-11-10 16:12:08 -0500 | [diff] [blame] | 9402 | * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC |
| 9403 | * @crtc_state: the DRM CRTC state |
| 9404 | * @stream_state: the DC stream state. |
| 9405 | * |
| 9406 | * Copy the mirrored transient state flags from DRM, to DC. It is used to bring |
| 9407 | * a dc_stream_state's flags in sync with a drm_crtc_state's flags. |
| 9408 | */ |
| 9409 | static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, |
| 9410 | struct dc_stream_state *stream_state) |
| 9411 | { |
Nicholas Kazlauskas | b9952f9 | 2019-02-08 13:21:05 -0500 | [diff] [blame] | 9412 | stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); |
Leo (Sunpeng) Li | 27b3f4f | 2017-11-10 16:12:08 -0500 | [diff] [blame] | 9413 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9414 | |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9415 | static void dm_clear_writeback(struct amdgpu_display_manager *dm, |
| 9416 | struct dm_crtc_state *crtc_state) |
| 9417 | { |
| 9418 | dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); |
| 9419 | } |
| 9420 | |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9421 | static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, |
| 9422 | struct dc_state *dc_state) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9423 | { |
| 9424 | struct drm_device *dev = state->dev; |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 9425 | struct amdgpu_device *adev = drm_to_adev(dev); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9426 | struct amdgpu_display_manager *dm = &adev->dm; |
Leo (Sunpeng) Li | 5cc6dcb | 2017-10-12 17:15:11 -0400 | [diff] [blame] | 9427 | struct drm_crtc *crtc; |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9428 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9429 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9430 | struct drm_connector_state *old_con_state; |
| 9431 | struct drm_connector *connector; |
hersen wu | 6ee90e8 | 2020-07-08 22:14:41 -0400 | [diff] [blame] | 9432 | bool mode_set_reset_required = false; |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9433 | u32 i; |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 9434 | struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; |
Tom Chung | 4f26c95 | 2024-10-09 17:09:38 +0800 | [diff] [blame] | 9435 | bool set_backlight_level = false; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9436 | |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9437 | /* Disable writeback */ |
| 9438 | for_each_old_connector_in_state(state, connector, old_con_state, i) { |
| 9439 | struct dm_connector_state *dm_old_con_state; |
| 9440 | struct amdgpu_crtc *acrtc; |
| 9441 | |
| 9442 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) |
| 9443 | continue; |
| 9444 | |
| 9445 | old_crtc_state = NULL; |
| 9446 | |
| 9447 | dm_old_con_state = to_dm_connector_state(old_con_state); |
| 9448 | if (!dm_old_con_state->base.crtc) |
| 9449 | continue; |
| 9450 | |
| 9451 | acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); |
| 9452 | if (acrtc) |
| 9453 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
| 9454 | |
Alex Hung | 1ff12bc | 2024-06-27 17:38:16 -0600 | [diff] [blame] | 9455 | if (!acrtc || !acrtc->wb_enabled) |
Alex Hung | f872e2f | 2023-12-01 06:25:36 -0700 | [diff] [blame] | 9456 | continue; |
| 9457 | |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9458 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 9459 | |
| 9460 | dm_clear_writeback(dm, dm_old_crtc_state); |
Alex Hung | f872e2f | 2023-12-01 06:25:36 -0700 | [diff] [blame] | 9461 | acrtc->wb_enabled = false; |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9462 | } |
| 9463 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 9464 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, |
| 9465 | new_crtc_state, i) { |
Aurabindo Pillai | 6d90a20 | 2020-09-11 15:10:11 -0400 | [diff] [blame] | 9466 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
| 9467 | |
| 9468 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 9469 | |
| 9470 | if (old_crtc_state->active && |
| 9471 | (!new_crtc_state->active || |
| 9472 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { |
Hamza Mahfooz | 537ef0f | 2024-08-15 14:37:27 -0400 | [diff] [blame] | 9473 | manage_dm_interrupts(adev, acrtc, NULL); |
Aurabindo Pillai | 6d90a20 | 2020-09-11 15:10:11 -0400 | [diff] [blame] | 9474 | dc_stream_release(dm_old_crtc_state->stream); |
| 9475 | } |
| 9476 | } |
| 9477 | |
Rodrigo Siqueira | 8976f73 | 2020-11-17 09:33:51 -0500 | [diff] [blame] | 9478 | drm_atomic_helper_calc_timestamping_constants(state); |
| 9479 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9480 | /* update changed items */ |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9481 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9482 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 9483 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9484 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 9485 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9486 | |
Sean Paul | 9f07550 | 2022-03-25 00:06:19 +0000 | [diff] [blame] | 9487 | drm_dbg_state(state->dev, |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 9488 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9489 | acrtc->crtc_id, |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9490 | new_crtc_state->enable, |
| 9491 | new_crtc_state->active, |
| 9492 | new_crtc_state->planes_changed, |
| 9493 | new_crtc_state->mode_changed, |
| 9494 | new_crtc_state->active_changed, |
| 9495 | new_crtc_state->connectors_changed); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9496 | |
Victor Lu | 5c68c65 | 2020-10-23 13:38:58 -0400 | [diff] [blame] | 9497 | /* Disable cursor if disabling crtc */ |
| 9498 | if (old_crtc_state->active && !new_crtc_state->active) { |
| 9499 | struct dc_cursor_position position; |
| 9500 | |
| 9501 | memset(&position, 0, sizeof(position)); |
| 9502 | mutex_lock(&dm->dc_lock); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 9503 | dc_exit_ips_for_hw_access(dm->dc); |
Harry Wentland | f63f86b | 2024-03-15 11:19:15 -0400 | [diff] [blame] | 9504 | dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); |
Victor Lu | 5c68c65 | 2020-10-23 13:38:58 -0400 | [diff] [blame] | 9505 | mutex_unlock(&dm->dc_lock); |
| 9506 | } |
| 9507 | |
Leo (Sunpeng) Li | 27b3f4f | 2017-11-10 16:12:08 -0500 | [diff] [blame] | 9508 | /* Copy all transient state flags into dc state */ |
| 9509 | if (dm_new_crtc_state->stream) { |
| 9510 | amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, |
| 9511 | dm_new_crtc_state->stream); |
| 9512 | } |
| 9513 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9514 | /* handles headless hotplug case, updating new_state and |
| 9515 | * aconnector as needed |
| 9516 | */ |
| 9517 | |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 9518 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9519 | |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 9520 | drm_dbg_atomic(dev, |
| 9521 | "Atomic commit: SET crtc id %d: [%p]\n", |
| 9522 | acrtc->crtc_id, acrtc); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9523 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9524 | if (!dm_new_crtc_state->stream) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9525 | /* |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 9526 | * this could happen because of issues with |
| 9527 | * userspace notifications delivery. |
| 9528 | * In this case userspace tries to set mode on |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 9529 | * display which is disconnected in fact. |
| 9530 | * dc_sink is NULL in this case on aconnector. |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 9531 | * We expect reset mode will come soon. |
| 9532 | * |
| 9533 | * This can also happen when unplug is done |
| 9534 | * during resume sequence ended |
| 9535 | * |
| 9536 | * In this case, we want to pretend we still |
| 9537 | * have a sink to keep the pipe running so that |
| 9538 | * hw state is consistent with the sw state |
| 9539 | */ |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 9540 | drm_dbg_atomic(dev, |
| 9541 | "Failed to create new stream for crtc %d\n", |
| 9542 | acrtc->base.base.id); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9543 | continue; |
| 9544 | } |
| 9545 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9546 | if (dm_old_crtc_state->stream) |
| 9547 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9548 | |
Lyude Paul | 9702803 | 2018-06-04 15:35:03 -0400 | [diff] [blame] | 9549 | pm_runtime_get_noresume(dev->dev); |
| 9550 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9551 | acrtc->enabled = true; |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9552 | acrtc->hw_mode = new_crtc_state->mode; |
| 9553 | crtc->hwmode = new_crtc_state->mode; |
hersen wu | 6ee90e8 | 2020-07-08 22:14:41 -0400 | [diff] [blame] | 9554 | mode_set_reset_required = true; |
Tom Chung | 4f26c95 | 2024-10-09 17:09:38 +0800 | [diff] [blame] | 9555 | set_backlight_level = true; |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9556 | } else if (modereset_required(new_crtc_state)) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 9557 | drm_dbg_atomic(dev, |
| 9558 | "Atomic commit: RESET. crtc id %d:[%p]\n", |
| 9559 | acrtc->crtc_id, acrtc); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9560 | /* i.e. reset mode */ |
hersen wu | 6ee90e8 | 2020-07-08 22:14:41 -0400 | [diff] [blame] | 9561 | if (dm_old_crtc_state->stream) |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9562 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 9563 | |
hersen wu | 6ee90e8 | 2020-07-08 22:14:41 -0400 | [diff] [blame] | 9564 | mode_set_reset_required = true; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9565 | } |
| 9566 | } /* for_each_crtc_in_state() */ |
| 9567 | |
Tom Chung | 5950efe | 2023-12-06 22:07:51 +0800 | [diff] [blame] | 9568 | /* if there mode set or reset, disable eDP PSR, Replay */ |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9569 | if (mode_set_reset_required) { |
| 9570 | if (dm->vblank_control_workqueue) |
| 9571 | flush_workqueue(dm->vblank_control_workqueue); |
Alex Hung | cae5c1a | 2022-04-25 15:12:02 -0600 | [diff] [blame] | 9572 | |
Tom Chung | 5950efe | 2023-12-06 22:07:51 +0800 | [diff] [blame] | 9573 | amdgpu_dm_replay_disable_all(dm); |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9574 | amdgpu_dm_psr_disable_all(dm); |
Mikita Lipski | fa2123d | 2017-10-17 15:29:22 -0400 | [diff] [blame] | 9575 | } |
Nikola Cornij | fe8858b | 2021-03-26 19:13:52 -0400 | [diff] [blame] | 9576 | |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9577 | dm_enable_per_frame_crtc_master_sync(dc_state); |
| 9578 | mutex_lock(&dm->dc_lock); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 9579 | dc_exit_ips_for_hw_access(dm->dc); |
Joshua Aberback | e779f45 | 2024-03-07 05:20:03 -0500 | [diff] [blame] | 9580 | WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9581 | |
| 9582 | /* Allow idle optimization when vblank count is 0 for display off */ |
| 9583 | if (dm->active_vblank_irq_count == 0) |
| 9584 | dc_allow_idle_optimizations(dm->dc, true); |
| 9585 | mutex_unlock(&dm->dc_lock); |
| 9586 | |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9587 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9588 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 9589 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9590 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9591 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9592 | if (dm_new_crtc_state->stream != NULL) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9593 | const struct dc_stream_status *status = |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9594 | dc_stream_get_status(dm_new_crtc_state->stream); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9595 | |
| 9596 | if (!status) |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 9597 | status = dc_state_get_stream_status(dc_state, |
Leo Li | 09f609c | 2018-11-27 15:05:12 -0500 | [diff] [blame] | 9598 | dm_new_crtc_state->stream); |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 9599 | if (!status) |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 9600 | drm_err(dev, |
| 9601 | "got no status for stream %p on acrtc%p\n", |
| 9602 | dm_new_crtc_state->stream, acrtc); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9603 | else |
| 9604 | acrtc->otg_inst = status->primary_otg_inst; |
| 9605 | } |
| 9606 | } |
Tom Chung | 4f26c95 | 2024-10-09 17:09:38 +0800 | [diff] [blame] | 9607 | |
| 9608 | /* During boot up and resume the DC layer will reset the panel brightness |
| 9609 | * to fix a flicker issue. |
| 9610 | * It will cause the dm->actual_brightness is not the current panel brightness |
| 9611 | * level. (the dm->brightness is the correct panel level) |
| 9612 | * So we set the backlight level with dm->brightness value after set mode |
| 9613 | */ |
| 9614 | if (set_backlight_level) { |
| 9615 | for (i = 0; i < dm->num_of_edps; i++) { |
| 9616 | if (dm->backlight_dev[i]) |
| 9617 | amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); |
| 9618 | } |
| 9619 | } |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9620 | } |
| 9621 | |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9622 | static void dm_set_writeback(struct amdgpu_display_manager *dm, |
| 9623 | struct dm_crtc_state *crtc_state, |
| 9624 | struct drm_connector *connector, |
| 9625 | struct drm_connector_state *new_con_state) |
| 9626 | { |
| 9627 | struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); |
Alex Hung | fdf43d2 | 2023-12-01 06:25:37 -0700 | [diff] [blame] | 9628 | struct amdgpu_device *adev = dm->adev; |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9629 | struct amdgpu_crtc *acrtc; |
| 9630 | struct dc_writeback_info *wb_info; |
| 9631 | struct pipe_ctx *pipe = NULL; |
| 9632 | struct amdgpu_framebuffer *afb; |
| 9633 | int i = 0; |
| 9634 | |
| 9635 | wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); |
| 9636 | if (!wb_info) { |
| 9637 | DRM_ERROR("Failed to allocate wb_info\n"); |
| 9638 | return; |
| 9639 | } |
| 9640 | |
| 9641 | acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); |
| 9642 | if (!acrtc) { |
| 9643 | DRM_ERROR("no amdgpu_crtc found\n"); |
Harshit Mogalapalli | a921071 | 2023-12-08 01:58:24 -0800 | [diff] [blame] | 9644 | kfree(wb_info); |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9645 | return; |
| 9646 | } |
| 9647 | |
| 9648 | afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); |
| 9649 | if (!afb) { |
| 9650 | DRM_ERROR("No amdgpu_framebuffer found\n"); |
Harshit Mogalapalli | a921071 | 2023-12-08 01:58:24 -0800 | [diff] [blame] | 9651 | kfree(wb_info); |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9652 | return; |
| 9653 | } |
| 9654 | |
| 9655 | for (i = 0; i < MAX_PIPES; i++) { |
| 9656 | if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { |
| 9657 | pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; |
| 9658 | break; |
| 9659 | } |
| 9660 | } |
| 9661 | |
| 9662 | /* fill in wb_info */ |
| 9663 | wb_info->wb_enabled = true; |
| 9664 | |
| 9665 | wb_info->dwb_pipe_inst = 0; |
| 9666 | wb_info->dwb_params.dwbscl_black_color = 0; |
| 9667 | wb_info->dwb_params.hdr_mult = 0x1F000; |
| 9668 | wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; |
| 9669 | wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; |
| 9670 | wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; |
| 9671 | wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; |
| 9672 | |
| 9673 | /* width & height from crtc */ |
| 9674 | wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; |
| 9675 | wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; |
| 9676 | wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; |
| 9677 | wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; |
| 9678 | |
| 9679 | wb_info->dwb_params.cnv_params.crop_en = false; |
| 9680 | wb_info->dwb_params.stereo_params.stereo_enabled = false; |
| 9681 | |
| 9682 | wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits |
| 9683 | wb_info->dwb_params.cnv_params.out_min_pix_val = 0; |
| 9684 | wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; |
| 9685 | wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; |
| 9686 | |
| 9687 | wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; |
| 9688 | |
| 9689 | wb_info->dwb_params.capture_rate = dwb_capture_rate_0; |
| 9690 | |
| 9691 | wb_info->dwb_params.scaler_taps.h_taps = 4; |
| 9692 | wb_info->dwb_params.scaler_taps.v_taps = 4; |
| 9693 | wb_info->dwb_params.scaler_taps.h_taps_c = 2; |
| 9694 | wb_info->dwb_params.scaler_taps.v_taps_c = 2; |
| 9695 | wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; |
| 9696 | |
| 9697 | wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; |
| 9698 | wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; |
| 9699 | |
| 9700 | for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { |
| 9701 | wb_info->mcif_buf_params.luma_address[i] = afb->address; |
| 9702 | wb_info->mcif_buf_params.chroma_address[i] = 0; |
| 9703 | } |
| 9704 | |
| 9705 | wb_info->mcif_buf_params.p_vmid = 1; |
Lijo Lazar | ed342a2 | 2023-12-01 17:13:46 +0530 | [diff] [blame] | 9706 | if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { |
Alex Hung | fdf43d2 | 2023-12-01 06:25:37 -0700 | [diff] [blame] | 9707 | wb_info->mcif_warmup_params.start_address.quad_part = afb->address; |
| 9708 | wb_info->mcif_warmup_params.region_size = |
| 9709 | wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; |
| 9710 | } |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 9711 | wb_info->mcif_warmup_params.p_vmid = 1; |
| 9712 | wb_info->writeback_source_plane = pipe->plane_state; |
| 9713 | |
| 9714 | dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); |
| 9715 | |
| 9716 | acrtc->wb_pending = true; |
| 9717 | acrtc->wb_conn = wb_conn; |
| 9718 | drm_writeback_queue_job(wb_conn, new_con_state); |
| 9719 | } |
| 9720 | |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 9721 | /** |
| 9722 | * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. |
| 9723 | * @state: The atomic state to commit |
| 9724 | * |
| 9725 | * This will tell DC to commit the constructed DC state from atomic_check, |
| 9726 | * programming the hardware. Any failures here implies a hardware failure, since |
| 9727 | * atomic check should have filtered anything non-kosher. |
| 9728 | */ |
| 9729 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) |
| 9730 | { |
| 9731 | struct drm_device *dev = state->dev; |
| 9732 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 9733 | struct amdgpu_display_manager *dm = &adev->dm; |
| 9734 | struct dm_atomic_state *dm_state; |
| 9735 | struct dc_state *dc_state = NULL; |
| 9736 | u32 i, j; |
| 9737 | struct drm_crtc *crtc; |
| 9738 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
| 9739 | unsigned long flags; |
| 9740 | bool wait_for_vblank = true; |
| 9741 | struct drm_connector *connector; |
| 9742 | struct drm_connector_state *old_con_state, *new_con_state; |
| 9743 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
| 9744 | int crtc_disable_count = 0; |
| 9745 | |
| 9746 | trace_amdgpu_dm_atomic_commit_tail_begin(state); |
| 9747 | |
| 9748 | drm_atomic_helper_update_legacy_modeset_state(dev, state); |
| 9749 | drm_dp_mst_atomic_wait_for_dependencies(state); |
| 9750 | |
| 9751 | dm_state = dm_atomic_get_new_state(state); |
| 9752 | if (dm_state && dm_state->context) { |
| 9753 | dc_state = dm_state->context; |
| 9754 | amdgpu_dm_commit_streams(state, dc_state); |
| 9755 | } |
| 9756 | |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 9757 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
| 9758 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
| 9759 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 9760 | struct amdgpu_dm_connector *aconnector; |
| 9761 | |
| 9762 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 9763 | continue; |
| 9764 | |
| 9765 | aconnector = to_amdgpu_dm_connector(connector); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 9766 | |
Hersen Wu | 3cf7cd3 | 2023-03-28 10:45:24 -0400 | [diff] [blame] | 9767 | if (!adev->dm.hdcp_workqueue) |
| 9768 | continue; |
| 9769 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9770 | pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 9771 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9772 | if (!connector) |
| 9773 | continue; |
| 9774 | |
| 9775 | pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", |
| 9776 | connector->index, connector->status, connector->dpms); |
| 9777 | pr_debug("[HDCP_DM] state protection old: %x new: %x\n", |
| 9778 | old_con_state->content_protection, new_con_state->content_protection); |
| 9779 | |
| 9780 | if (aconnector->dc_sink) { |
| 9781 | if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && |
| 9782 | aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { |
| 9783 | pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", |
| 9784 | aconnector->dc_sink->edid_caps.display_name); |
| 9785 | } |
| 9786 | } |
| 9787 | |
| 9788 | new_crtc_state = NULL; |
| 9789 | old_crtc_state = NULL; |
| 9790 | |
| 9791 | if (acrtc) { |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 9792 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9793 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
| 9794 | } |
| 9795 | |
| 9796 | if (old_crtc_state) |
| 9797 | pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", |
| 9798 | old_crtc_state->enable, |
| 9799 | old_crtc_state->active, |
| 9800 | old_crtc_state->mode_changed, |
| 9801 | old_crtc_state->active_changed, |
| 9802 | old_crtc_state->connectors_changed); |
| 9803 | |
| 9804 | if (new_crtc_state) |
| 9805 | pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", |
| 9806 | new_crtc_state->enable, |
| 9807 | new_crtc_state->active, |
| 9808 | new_crtc_state->mode_changed, |
| 9809 | new_crtc_state->active_changed, |
| 9810 | new_crtc_state->connectors_changed); |
| 9811 | } |
| 9812 | |
| 9813 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
| 9814 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
| 9815 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); |
| 9816 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
| 9817 | |
Hersen Wu | 3cf7cd3 | 2023-03-28 10:45:24 -0400 | [diff] [blame] | 9818 | if (!adev->dm.hdcp_workqueue) |
| 9819 | continue; |
| 9820 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9821 | new_crtc_state = NULL; |
| 9822 | old_crtc_state = NULL; |
| 9823 | |
| 9824 | if (acrtc) { |
| 9825 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
| 9826 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
| 9827 | } |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 9828 | |
| 9829 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 9830 | |
| 9831 | if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && |
| 9832 | connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { |
| 9833 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); |
| 9834 | new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; |
Bhawanpreet Lakha | 97f6c91 | 2019-09-26 16:55:24 -0400 | [diff] [blame] | 9835 | dm_new_con_state->update_hdcp = true; |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 9836 | continue; |
| 9837 | } |
| 9838 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9839 | if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, |
| 9840 | old_con_state, connector, adev->dm.hdcp_workqueue)) { |
hersen wu | 82986fd | 2022-11-15 10:39:55 -0500 | [diff] [blame] | 9841 | /* when display is unplugged from mst hub, connctor will |
| 9842 | * be destroyed within dm_dp_mst_connector_destroy. connector |
| 9843 | * hdcp perperties, like type, undesired, desired, enabled, |
| 9844 | * will be lost. So, save hdcp properties into hdcp_work within |
| 9845 | * amdgpu_dm_atomic_commit_tail. if the same display is |
| 9846 | * plugged back with same display index, its hdcp properties |
| 9847 | * will be retrieved from hdcp_work within dm_dp_mst_get_modes |
| 9848 | */ |
| 9849 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9850 | bool enable_encryption = false; |
| 9851 | |
| 9852 | if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) |
| 9853 | enable_encryption = true; |
| 9854 | |
hersen wu | 82986fd | 2022-11-15 10:39:55 -0500 | [diff] [blame] | 9855 | if (aconnector->dc_link && aconnector->dc_sink && |
| 9856 | aconnector->dc_link->type == dc_connection_mst_branch) { |
| 9857 | struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; |
| 9858 | struct hdcp_workqueue *hdcp_w = |
| 9859 | &hdcp_work[aconnector->dc_link->link_index]; |
| 9860 | |
| 9861 | hdcp_w->hdcp_content_type[connector->index] = |
| 9862 | new_con_state->hdcp_content_type; |
| 9863 | hdcp_w->content_protection[connector->index] = |
| 9864 | new_con_state->content_protection; |
| 9865 | } |
| 9866 | |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9867 | if (new_crtc_state && new_crtc_state->mode_changed && |
| 9868 | new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) |
| 9869 | enable_encryption = true; |
| 9870 | |
| 9871 | DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); |
| 9872 | |
Alex Hung | 1ff12bc | 2024-06-27 17:38:16 -0600 | [diff] [blame] | 9873 | if (aconnector->dc_link) |
| 9874 | hdcp_update_display( |
| 9875 | adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, |
| 9876 | new_con_state->hdcp_content_type, enable_encryption); |
hersen wu | e8fd3ee | 2022-11-15 14:20:56 -0500 | [diff] [blame] | 9877 | } |
Bhawanpreet Lakha | 0c8620d | 2019-09-16 15:52:58 -0500 | [diff] [blame] | 9878 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9879 | |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9880 | /* Handle connector state changes */ |
Leo (Sunpeng) Li | c2cea70 | 2017-10-12 17:15:08 -0400 | [diff] [blame] | 9881 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9882 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
| 9883 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
| 9884 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); |
Rodrigo Siqueira | 135fd1b | 2023-06-21 16:30:07 -0600 | [diff] [blame] | 9885 | struct dc_surface_update *dummy_updates; |
Nathan Chancellor | 19afd79 | 2019-02-01 13:14:28 -0700 | [diff] [blame] | 9886 | struct dc_stream_update stream_update; |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 9887 | struct dc_info_packet hdr_packet; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9888 | struct dc_stream_status *status = NULL; |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 9889 | bool abm_changed, hdr_changed, scaling_changed; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9890 | |
Nathan Chancellor | 19afd79 | 2019-02-01 13:14:28 -0700 | [diff] [blame] | 9891 | memset(&stream_update, 0, sizeof(stream_update)); |
| 9892 | |
Harry Wentland | 44d09c6 | 2018-03-15 14:29:24 -0400 | [diff] [blame] | 9893 | if (acrtc) { |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9894 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
Harry Wentland | 44d09c6 | 2018-03-15 14:29:24 -0400 | [diff] [blame] | 9895 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
| 9896 | } |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9897 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9898 | /* Skip any modesets/resets */ |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 9899 | if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9900 | continue; |
| 9901 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9902 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
David Francis | c1ee92f | 2018-11-26 15:51:09 -0500 | [diff] [blame] | 9903 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 9904 | |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 9905 | scaling_changed = is_scaling_state_different(dm_new_con_state, |
| 9906 | dm_old_con_state); |
| 9907 | |
| 9908 | abm_changed = dm_new_crtc_state->abm_level != |
| 9909 | dm_old_crtc_state->abm_level; |
| 9910 | |
| 9911 | hdr_changed = |
Maxime Ripard | 72921cd | 2021-04-30 11:44:48 +0200 | [diff] [blame] | 9912 | !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 9913 | |
| 9914 | if (!scaling_changed && !abm_changed && !hdr_changed) |
David Francis | c1ee92f | 2018-11-26 15:51:09 -0500 | [diff] [blame] | 9915 | continue; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9916 | |
Dmytro Laktyushkin | b6e881c | 2019-09-13 18:00:28 -0500 | [diff] [blame] | 9917 | stream_update.stream = dm_new_crtc_state->stream; |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 9918 | if (scaling_changed) { |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9919 | update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, |
Dmytro Laktyushkin | b6e881c | 2019-09-13 18:00:28 -0500 | [diff] [blame] | 9920 | dm_new_con_state, dm_new_crtc_state->stream); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9921 | |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9922 | stream_update.src = dm_new_crtc_state->stream->src; |
| 9923 | stream_update.dst = dm_new_crtc_state->stream->dst; |
| 9924 | } |
| 9925 | |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 9926 | if (abm_changed) { |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9927 | dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; |
| 9928 | |
| 9929 | stream_update.abm_level = &dm_new_crtc_state->abm_level; |
| 9930 | } |
Harry Wentland | 70e8ffc | 2017-11-10 11:19:02 -0500 | [diff] [blame] | 9931 | |
Nicholas Kazlauskas | b232d4ed | 2019-05-28 15:08:36 -0400 | [diff] [blame] | 9932 | if (hdr_changed) { |
| 9933 | fill_hdr_info_packet(new_con_state, &hdr_packet); |
| 9934 | stream_update.hdr_static_metadata = &hdr_packet; |
| 9935 | } |
| 9936 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 9937 | status = dc_stream_get_status(dm_new_crtc_state->stream); |
Nirmoy Das | 57738ae | 2021-05-27 14:03:33 +0200 | [diff] [blame] | 9938 | |
| 9939 | if (WARN_ON(!status)) |
| 9940 | continue; |
| 9941 | |
Harry Wentland | 3be5262e | 2017-07-27 09:55:38 -0400 | [diff] [blame] | 9942 | WARN_ON(!status->plane_count); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9943 | |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9944 | /* |
| 9945 | * TODO: DC refuses to perform stream updates without a dc_surface_update. |
| 9946 | * Here we create an empty update on each plane. |
| 9947 | * To fix this, DC should permit updating only stream properties. |
| 9948 | */ |
Rodrigo Siqueira | 135fd1b | 2023-06-21 16:30:07 -0600 | [diff] [blame] | 9949 | dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); |
Srinivasan Shanmugam | 492a1e6 | 2024-01-30 14:06:43 +0530 | [diff] [blame] | 9950 | if (!dummy_updates) { |
| 9951 | DRM_ERROR("Failed to allocate memory for dummy_updates.\n"); |
| 9952 | continue; |
| 9953 | } |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9954 | for (j = 0; j < status->plane_count; j++) |
Anson Jacob | efc8278 | 2021-02-18 19:42:57 -0500 | [diff] [blame] | 9955 | dummy_updates[j].surface = status->plane_states[0]; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 9956 | |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 9957 | sort(dummy_updates, status->plane_count, |
| 9958 | sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9959 | |
| 9960 | mutex_lock(&dm->dc_lock); |
Fangzhi Zuo | 1ff6631 | 2024-05-10 15:23:02 -0400 | [diff] [blame] | 9961 | dc_exit_ips_for_hw_access(dm->dc); |
Rodrigo Siqueira | f751128 | 2022-10-06 16:40:55 -0400 | [diff] [blame] | 9962 | dc_update_planes_and_stream(dm->dc, |
| 9963 | dummy_updates, |
| 9964 | status->plane_count, |
| 9965 | dm_new_crtc_state->stream, |
| 9966 | &stream_update); |
David Francis | 02d6a6f | 2018-12-18 15:30:19 -0500 | [diff] [blame] | 9967 | mutex_unlock(&dm->dc_lock); |
Rodrigo Siqueira | 135fd1b | 2023-06-21 16:30:07 -0600 | [diff] [blame] | 9968 | kfree(dummy_updates); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 9969 | } |
| 9970 | |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 9971 | /** |
| 9972 | * Enable interrupts for CRTCs that are newly enabled or went through |
| 9973 | * a modeset. It was intentionally deferred until after the front end |
| 9974 | * state was modified to wait until the OTG was on and so the IRQ |
| 9975 | * handlers didn't access stale or invalid state. |
| 9976 | */ |
| 9977 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
| 9978 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
Wayne Lin | 8e7b6fe | 2021-02-09 16:52:22 +0800 | [diff] [blame] | 9979 | #ifdef CONFIG_DEBUG_FS |
| 9980 | enum amdgpu_dm_pipe_crc_source cur_crc_src; |
Yunxiang Li | 8799c0b | 2022-09-21 17:20:19 -0400 | [diff] [blame] | 9981 | #endif |
| 9982 | /* Count number of newly disabled CRTCs for dropping PM refs later. */ |
| 9983 | if (old_crtc_state->active && !new_crtc_state->active) |
| 9984 | crtc_disable_count++; |
| 9985 | |
| 9986 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 9987 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 9988 | |
| 9989 | /* For freesync config update on crtc state and params for irq */ |
| 9990 | update_stream_irq_parameters(dm, dm_new_crtc_state); |
| 9991 | |
| 9992 | #ifdef CONFIG_DEBUG_FS |
Wayne Lin | d98af27 | 2021-04-27 12:00:40 +0800 | [diff] [blame] | 9993 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
| 9994 | cur_crc_src = acrtc->dm_irq_params.crc_src; |
| 9995 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Wayne Lin | 8e7b6fe | 2021-02-09 16:52:22 +0800 | [diff] [blame] | 9996 | #endif |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 9997 | |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 9998 | if (new_crtc_state->active && |
| 9999 | (!old_crtc_state->active || |
| 10000 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { |
Aurabindo Pillai | 585d450 | 2020-08-12 18:56:14 -0400 | [diff] [blame] | 10001 | dc_stream_retain(dm_new_crtc_state->stream); |
| 10002 | acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; |
Hamza Mahfooz | 537ef0f | 2024-08-15 14:37:27 -0400 | [diff] [blame] | 10003 | manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); |
Yunxiang Li | 8799c0b | 2022-09-21 17:20:19 -0400 | [diff] [blame] | 10004 | } |
| 10005 | /* Handle vrr on->off / off->on transitions */ |
| 10006 | amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); |
Rodrigo Siqueira | e2881d6 | 2021-01-07 15:09:30 -0500 | [diff] [blame] | 10007 | |
Rodrigo Siqueira | 24eb937 | 2021-01-07 14:50:51 -0500 | [diff] [blame] | 10008 | #ifdef CONFIG_DEBUG_FS |
Yunxiang Li | 8799c0b | 2022-09-21 17:20:19 -0400 | [diff] [blame] | 10009 | if (new_crtc_state->active && |
| 10010 | (!old_crtc_state->active || |
| 10011 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 10012 | /** |
| 10013 | * Frontend may have changed so reapply the CRC capture |
| 10014 | * settings for the stream. |
| 10015 | */ |
Wayne Lin | 8e7b6fe | 2021-02-09 16:52:22 +0800 | [diff] [blame] | 10016 | if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 10017 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
Wayne Lin | d98af27 | 2021-04-27 12:00:40 +0800 | [diff] [blame] | 10018 | if (amdgpu_dm_crc_window_is_activated(crtc)) { |
| 10019 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
Alan Liu | c0459bdd | 2022-10-20 11:46:42 -0400 | [diff] [blame] | 10020 | acrtc->dm_irq_params.window_param.update_win = true; |
Alan Liu | 1b11ff7 | 2022-10-19 18:15:14 +0800 | [diff] [blame] | 10021 | |
| 10022 | /** |
| 10023 | * It takes 2 frames for HW to stably generate CRC when |
| 10024 | * resuming from suspend, so we set skip_frame_cnt 2. |
| 10025 | */ |
Alan Liu | c0459bdd | 2022-10-20 11:46:42 -0400 | [diff] [blame] | 10026 | acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; |
Wayne Lin | d98af27 | 2021-04-27 12:00:40 +0800 | [diff] [blame] | 10027 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
| 10028 | } |
Wayne Lin | 86bc221 | 2021-03-02 11:52:20 +0800 | [diff] [blame] | 10029 | #endif |
Wayne Lin | bbc49fc | 2021-04-28 18:04:44 +0800 | [diff] [blame] | 10030 | if (amdgpu_dm_crtc_configure_crc_source( |
| 10031 | crtc, dm_new_crtc_state, cur_crc_src)) |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 10032 | drm_dbg_atomic(dev, "Failed to configure crc source"); |
Yunxiang Li | 8799c0b | 2022-09-21 17:20:19 -0400 | [diff] [blame] | 10033 | } |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 10034 | } |
Nathan Chancellor | 2130b87 | 2022-10-14 08:21:03 -0700 | [diff] [blame] | 10035 | #endif |
Nicholas Kazlauskas | 8fe684e9 | 2020-07-13 10:41:23 -0400 | [diff] [blame] | 10036 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10037 | |
David Francis | 420cd47 | 2019-03-01 18:15:26 -0500 | [diff] [blame] | 10038 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) |
Daniel Vetter | 4d85f45 | 2019-09-03 21:06:42 +0200 | [diff] [blame] | 10039 | if (new_crtc_state->async_flip) |
David Francis | 420cd47 | 2019-03-01 18:15:26 -0500 | [diff] [blame] | 10040 | wait_for_vblank = false; |
| 10041 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10042 | /* update planes when needed per crtc*/ |
Leo (Sunpeng) Li | 5cc6dcb | 2017-10-12 17:15:11 -0400 | [diff] [blame] | 10043 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 10044 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10045 | |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 10046 | if (dm_new_crtc_state->stream) |
Alan Liu | fff7b95 | 2023-06-27 12:21:51 +0800 | [diff] [blame] | 10047 | amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10048 | } |
| 10049 | |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 10050 | /* Enable writeback */ |
| 10051 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
| 10052 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
| 10053 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); |
| 10054 | |
| 10055 | if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) |
| 10056 | continue; |
| 10057 | |
| 10058 | if (!new_con_state->writeback_job) |
| 10059 | continue; |
| 10060 | |
Srinivasan Shanmugam | b2139c9 | 2024-01-13 14:32:27 +0530 | [diff] [blame] | 10061 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 10062 | |
Srinivasan Shanmugam | b2139c9 | 2024-01-13 14:32:27 +0530 | [diff] [blame] | 10063 | if (!new_crtc_state) |
| 10064 | continue; |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 10065 | |
Alex Hung | f872e2f | 2023-12-01 06:25:36 -0700 | [diff] [blame] | 10066 | if (acrtc->wb_enabled) |
| 10067 | continue; |
| 10068 | |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 10069 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 10070 | |
| 10071 | dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); |
Alex Hung | f872e2f | 2023-12-01 06:25:36 -0700 | [diff] [blame] | 10072 | acrtc->wb_enabled = true; |
Alex Hung | c81e13b | 2023-12-01 06:25:31 -0700 | [diff] [blame] | 10073 | } |
| 10074 | |
Nicholas Kazlauskas | 6ce8f31 | 2019-07-11 14:31:46 -0500 | [diff] [blame] | 10075 | /* Update audio instances for each connector. */ |
| 10076 | amdgpu_dm_commit_audio(dev, state); |
| 10077 | |
Alex Deucher | 7230362c | 2020-12-10 02:30:39 -0500 | [diff] [blame] | 10078 | /* restore the backlight level */ |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 10079 | for (i = 0; i < dm->num_of_edps; i++) { |
| 10080 | if (dm->backlight_dev[i] && |
Shirish S | 4052287 | 2022-03-11 20:30:17 +0530 | [diff] [blame] | 10081 | (dm->actual_brightness[i] != dm->brightness[i])) |
Alex Deucher | 7fd13ba | 2021-07-08 16:31:10 -0400 | [diff] [blame] | 10082 | amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); |
| 10083 | } |
Hans de Goede | 83a3439 | 2022-06-20 11:43:35 +0200 | [diff] [blame] | 10084 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10085 | /* |
| 10086 | * send vblank event on all events not handled in flip and |
| 10087 | * mark consumed event for drm_atomic_helper_commit_hw_done |
| 10088 | */ |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 10089 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 10090 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10091 | |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 10092 | if (new_crtc_state->event) |
| 10093 | drm_send_event_locked(dev, &new_crtc_state->event->base); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10094 | |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 10095 | new_crtc_state->event = NULL; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10096 | } |
Luben Tuikov | 4a58087 | 2020-08-24 12:29:45 -0400 | [diff] [blame] | 10097 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10098 | |
Leo Li | 29c8f23 | 2019-01-07 13:28:54 -0500 | [diff] [blame] | 10099 | /* Signal HW programming completion */ |
| 10100 | drm_atomic_helper_commit_hw_done(state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10101 | |
| 10102 | if (wait_for_vblank) |
Andrey Grodzovsky | 320a127 | 2017-11-14 20:45:52 -0500 | [diff] [blame] | 10103 | drm_atomic_helper_wait_for_flip_done(dev, state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10104 | |
| 10105 | drm_atomic_helper_cleanup_planes(dev, state); |
Lyude Paul | 9702803 | 2018-06-04 15:35:03 -0400 | [diff] [blame] | 10106 | |
Alex Deucher | e6b27cf5 | 2023-06-09 15:40:33 -0400 | [diff] [blame] | 10107 | /* Don't free the memory if we are hitting this as part of suspend. |
| 10108 | * This way we don't free any memory during suspend; see |
| 10109 | * amdgpu_bo_free_kernel(). The memory will be freed in the first |
| 10110 | * non-suspend modeset or when the driver is torn down. |
| 10111 | */ |
| 10112 | if (!adev->in_suspend) { |
| 10113 | /* return the stolen vga memory back to VRAM */ |
| 10114 | if (!adev->mman.keep_stolen_vga_memory) |
| 10115 | amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); |
| 10116 | amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); |
| 10117 | } |
Alex Deucher | 5f6fab2 | 2020-12-04 11:52:00 -0500 | [diff] [blame] | 10118 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 10119 | /* |
| 10120 | * Finally, drop a runtime PM reference for each newly disabled CRTC, |
Lyude Paul | 9702803 | 2018-06-04 15:35:03 -0400 | [diff] [blame] | 10121 | * so we can put the GPU into runtime suspend if we're not driving any |
| 10122 | * displays anymore |
| 10123 | */ |
Lyude Paul | fe2a196 | 2018-06-21 16:48:26 -0400 | [diff] [blame] | 10124 | for (i = 0; i < crtc_disable_count; i++) |
| 10125 | pm_runtime_put_autosuspend(dev->dev); |
Lyude Paul | 9702803 | 2018-06-04 15:35:03 -0400 | [diff] [blame] | 10126 | pm_runtime_mark_last_busy(dev->dev); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10127 | } |
| 10128 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10129 | static int dm_force_atomic_commit(struct drm_connector *connector) |
| 10130 | { |
| 10131 | int ret = 0; |
| 10132 | struct drm_device *ddev = connector->dev; |
| 10133 | struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); |
| 10134 | struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); |
| 10135 | struct drm_plane *plane = disconnected_acrtc->base.primary; |
| 10136 | struct drm_connector_state *conn_state; |
| 10137 | struct drm_crtc_state *crtc_state; |
| 10138 | struct drm_plane_state *plane_state; |
| 10139 | |
| 10140 | if (!state) |
| 10141 | return -ENOMEM; |
| 10142 | |
| 10143 | state->acquire_ctx = ddev->mode_config.acquire_ctx; |
| 10144 | |
| 10145 | /* Construct an atomic state to restore previous display setting */ |
| 10146 | |
| 10147 | /* |
| 10148 | * Attach connectors to drm_atomic_state |
| 10149 | */ |
| 10150 | conn_state = drm_atomic_get_connector_state(state, connector); |
| 10151 | |
| 10152 | ret = PTR_ERR_OR_ZERO(conn_state); |
| 10153 | if (ret) |
Victor Lu | 2dc3905 | 2021-01-14 16:27:07 -0500 | [diff] [blame] | 10154 | goto out; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10155 | |
| 10156 | /* Attach crtc to drm_atomic_state*/ |
| 10157 | crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); |
| 10158 | |
| 10159 | ret = PTR_ERR_OR_ZERO(crtc_state); |
| 10160 | if (ret) |
Victor Lu | 2dc3905 | 2021-01-14 16:27:07 -0500 | [diff] [blame] | 10161 | goto out; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10162 | |
| 10163 | /* force a restore */ |
| 10164 | crtc_state->mode_changed = true; |
| 10165 | |
| 10166 | /* Attach plane to drm_atomic_state */ |
| 10167 | plane_state = drm_atomic_get_plane_state(state, plane); |
| 10168 | |
| 10169 | ret = PTR_ERR_OR_ZERO(plane_state); |
| 10170 | if (ret) |
Victor Lu | 2dc3905 | 2021-01-14 16:27:07 -0500 | [diff] [blame] | 10171 | goto out; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10172 | |
| 10173 | /* Call commit internally with the state we just constructed */ |
| 10174 | ret = drm_atomic_commit(state); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10175 | |
Victor Lu | 2dc3905 | 2021-01-14 16:27:07 -0500 | [diff] [blame] | 10176 | out: |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10177 | drm_atomic_state_put(state); |
Victor Lu | 2dc3905 | 2021-01-14 16:27:07 -0500 | [diff] [blame] | 10178 | if (ret) |
| 10179 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10180 | |
| 10181 | return ret; |
| 10182 | } |
| 10183 | |
| 10184 | /* |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 10185 | * This function handles all cases when set mode does not come upon hotplug. |
| 10186 | * This includes when a display is unplugged then plugged back into the |
| 10187 | * same port and when running without usermode desktop manager supprot |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10188 | */ |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 10189 | void dm_restore_drm_connector_state(struct drm_device *dev, |
| 10190 | struct drm_connector *connector) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10191 | { |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 10192 | struct amdgpu_dm_connector *aconnector; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10193 | struct amdgpu_crtc *disconnected_acrtc; |
| 10194 | struct dm_crtc_state *acrtc_state; |
| 10195 | |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 10196 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 10197 | return; |
| 10198 | |
| 10199 | aconnector = to_amdgpu_dm_connector(connector); |
| 10200 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10201 | if (!aconnector->dc_sink || !connector->state || !connector->encoder) |
| 10202 | return; |
| 10203 | |
| 10204 | disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); |
Harry Wentland | 70e8ffc | 2017-11-10 11:19:02 -0500 | [diff] [blame] | 10205 | if (!disconnected_acrtc) |
| 10206 | return; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10207 | |
Harry Wentland | 70e8ffc | 2017-11-10 11:19:02 -0500 | [diff] [blame] | 10208 | acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); |
| 10209 | if (!acrtc_state->stream) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10210 | return; |
| 10211 | |
| 10212 | /* |
| 10213 | * If the previous sink is not released and different from the current, |
| 10214 | * we deduce we are in a state where we can not rely on usermode call |
| 10215 | * to turn on the display, so we do it here |
| 10216 | */ |
| 10217 | if (acrtc_state->stream->sink != aconnector->dc_sink) |
| 10218 | dm_force_atomic_commit(&aconnector->base); |
| 10219 | } |
| 10220 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 10221 | /* |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10222 | * Grabs all modesetting locks to serialize against any blocking commits, |
| 10223 | * Waits for completion of all non blocking commits. |
| 10224 | */ |
Alex Deucher | 3ee6b26 | 2017-10-10 17:44:52 -0400 | [diff] [blame] | 10225 | static int do_aquire_global_lock(struct drm_device *dev, |
| 10226 | struct drm_atomic_state *state) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10227 | { |
| 10228 | struct drm_crtc *crtc; |
| 10229 | struct drm_crtc_commit *commit; |
| 10230 | long ret; |
| 10231 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 10232 | /* |
| 10233 | * Adding all modeset locks to aquire_ctx will |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10234 | * ensure that when the framework release it the |
| 10235 | * extra locks we are locking here will get released to |
| 10236 | */ |
| 10237 | ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); |
| 10238 | if (ret) |
| 10239 | return ret; |
| 10240 | |
| 10241 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 10242 | spin_lock(&crtc->commit_lock); |
| 10243 | commit = list_first_entry_or_null(&crtc->commit_list, |
| 10244 | struct drm_crtc_commit, commit_entry); |
| 10245 | if (commit) |
| 10246 | drm_crtc_commit_get(commit); |
| 10247 | spin_unlock(&crtc->commit_lock); |
| 10248 | |
| 10249 | if (!commit) |
| 10250 | continue; |
| 10251 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 10252 | /* |
| 10253 | * Make sure all pending HW programming completed and |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10254 | * page flips done |
| 10255 | */ |
| 10256 | ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); |
| 10257 | |
| 10258 | if (ret > 0) |
| 10259 | ret = wait_for_completion_interruptible_timeout( |
| 10260 | &commit->flip_done, 10*HZ); |
| 10261 | |
| 10262 | if (ret == 0) |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10263 | DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", |
| 10264 | crtc->base.id, crtc->name); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10265 | |
| 10266 | drm_crtc_commit_put(commit); |
| 10267 | } |
| 10268 | |
| 10269 | return ret < 0 ? ret : 0; |
| 10270 | } |
| 10271 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 10272 | static void get_freesync_config_for_crtc( |
| 10273 | struct dm_crtc_state *new_crtc_state, |
| 10274 | struct dm_connector_state *new_con_state) |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 10275 | { |
| 10276 | struct mod_freesync_config config = {0}; |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 10277 | struct amdgpu_dm_connector *aconnector; |
Ilya Bakoulin | a057ec4 | 2019-01-17 13:40:34 -0500 | [diff] [blame] | 10278 | struct drm_display_mode *mode = &new_crtc_state->base.mode; |
Nicholas Kazlauskas | 0ab925d | 2019-03-21 11:53:45 -0400 | [diff] [blame] | 10279 | int vrefresh = drm_mode_vrefresh(mode); |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10280 | bool fs_vid_mode = false; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 10281 | |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 10282 | if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 10283 | return; |
| 10284 | |
| 10285 | aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); |
| 10286 | |
Ilya Bakoulin | a057ec4 | 2019-01-17 13:40:34 -0500 | [diff] [blame] | 10287 | new_crtc_state->vrr_supported = new_con_state->freesync_capable && |
Nicholas Kazlauskas | 0ab925d | 2019-03-21 11:53:45 -0400 | [diff] [blame] | 10288 | vrefresh >= aconnector->min_vfreq && |
| 10289 | vrefresh <= aconnector->max_vfreq; |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 10290 | |
Aurabindo Pillai | 6ffa679 | 2022-12-07 10:09:53 -0500 | [diff] [blame] | 10291 | if (new_crtc_state->vrr_supported) { |
Aurabindo Pillai | 7e5098a | 2023-01-05 14:18:09 -0500 | [diff] [blame] | 10292 | new_crtc_state->stream->ignore_msa_timing_param = true; |
Aurabindo Pillai | 6ffa679 | 2022-12-07 10:09:53 -0500 | [diff] [blame] | 10293 | fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; |
Aurabindo Pillai | 7e5098a | 2023-01-05 14:18:09 -0500 | [diff] [blame] | 10294 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10295 | config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; |
| 10296 | config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; |
Anthony Koo | 69ff884 | 2018-05-08 17:09:49 -0400 | [diff] [blame] | 10297 | config.vsif_supported = true; |
Nicholas Kazlauskas | 180db30 | 2018-12-05 12:08:56 -0500 | [diff] [blame] | 10298 | config.btr = true; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 10299 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10300 | if (fs_vid_mode) { |
| 10301 | config.state = VRR_STATE_ACTIVE_FIXED; |
| 10302 | config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; |
| 10303 | goto out; |
| 10304 | } else if (new_crtc_state->base.vrr_enabled) { |
| 10305 | config.state = VRR_STATE_ACTIVE_VARIABLE; |
| 10306 | } else { |
| 10307 | config.state = VRR_STATE_INACTIVE; |
| 10308 | } |
| 10309 | } |
| 10310 | out: |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 10311 | new_crtc_state->freesync_config = config; |
| 10312 | } |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 10313 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 10314 | static void reset_freesync_config_for_crtc( |
| 10315 | struct dm_crtc_state *new_crtc_state) |
| 10316 | { |
| 10317 | new_crtc_state->vrr_supported = false; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 10318 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 10319 | memset(&new_crtc_state->vrr_infopacket, 0, |
| 10320 | sizeof(new_crtc_state->vrr_infopacket)); |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 10321 | } |
| 10322 | |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10323 | static bool |
| 10324 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, |
| 10325 | struct drm_crtc_state *new_crtc_state) |
| 10326 | { |
Ville Syrjälä | 1cbd788 | 2022-02-18 12:03:43 +0200 | [diff] [blame] | 10327 | const struct drm_display_mode *old_mode, *new_mode; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10328 | |
| 10329 | if (!old_crtc_state || !new_crtc_state) |
| 10330 | return false; |
| 10331 | |
Ville Syrjälä | 1cbd788 | 2022-02-18 12:03:43 +0200 | [diff] [blame] | 10332 | old_mode = &old_crtc_state->mode; |
| 10333 | new_mode = &new_crtc_state->mode; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10334 | |
Ville Syrjälä | 1cbd788 | 2022-02-18 12:03:43 +0200 | [diff] [blame] | 10335 | if (old_mode->clock == new_mode->clock && |
| 10336 | old_mode->hdisplay == new_mode->hdisplay && |
| 10337 | old_mode->vdisplay == new_mode->vdisplay && |
| 10338 | old_mode->htotal == new_mode->htotal && |
| 10339 | old_mode->vtotal != new_mode->vtotal && |
| 10340 | old_mode->hsync_start == new_mode->hsync_start && |
| 10341 | old_mode->vsync_start != new_mode->vsync_start && |
| 10342 | old_mode->hsync_end == new_mode->hsync_end && |
| 10343 | old_mode->vsync_end != new_mode->vsync_end && |
| 10344 | old_mode->hskew == new_mode->hskew && |
| 10345 | old_mode->vscan == new_mode->vscan && |
| 10346 | (old_mode->vsync_end - old_mode->vsync_start) == |
| 10347 | (new_mode->vsync_end - new_mode->vsync_start)) |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10348 | return true; |
| 10349 | |
| 10350 | return false; |
| 10351 | } |
| 10352 | |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10353 | static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) |
| 10354 | { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 10355 | u64 num, den, res; |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10356 | struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; |
| 10357 | |
| 10358 | dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; |
| 10359 | |
| 10360 | num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; |
| 10361 | den = (unsigned long long)new_crtc_state->mode.htotal * |
| 10362 | (unsigned long long)new_crtc_state->mode.vtotal; |
| 10363 | |
| 10364 | res = div_u64(num, den); |
| 10365 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; |
| 10366 | } |
| 10367 | |
Maíra Canal | f11d937 | 2022-02-22 10:17:01 -0300 | [diff] [blame] | 10368 | static int dm_update_crtc_state(struct amdgpu_display_manager *dm, |
Roman Li | 17ce8a6 | 2022-01-28 12:29:01 -0500 | [diff] [blame] | 10369 | struct drm_atomic_state *state, |
| 10370 | struct drm_crtc *crtc, |
| 10371 | struct drm_crtc_state *old_crtc_state, |
| 10372 | struct drm_crtc_state *new_crtc_state, |
| 10373 | bool enable, |
| 10374 | bool *lock_and_validation_needed) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10375 | { |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 10376 | struct dm_atomic_state *dm_state = NULL; |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 10377 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
Darren Salt | 9635b75 | 2017-09-12 17:10:25 +0100 | [diff] [blame] | 10378 | struct dc_stream_state *new_stream; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10379 | int ret = 0; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10380 | |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 10381 | /* |
| 10382 | * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set |
| 10383 | * update changed items |
| 10384 | */ |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10385 | struct amdgpu_crtc *acrtc = NULL; |
Harry Wentland | 748b091 | 2023-12-01 06:25:26 -0700 | [diff] [blame] | 10386 | struct drm_connector *connector = NULL; |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10387 | struct amdgpu_dm_connector *aconnector = NULL; |
| 10388 | struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; |
| 10389 | struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 10390 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10391 | new_stream = NULL; |
Darren Salt | 9635b75 | 2017-09-12 17:10:25 +0100 | [diff] [blame] | 10392 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10393 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 10394 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 10395 | acrtc = to_amdgpu_crtc(crtc); |
Harry Wentland | 748b091 | 2023-12-01 06:25:26 -0700 | [diff] [blame] | 10396 | connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
Alex Hung | dbf5d3d | 2023-12-01 06:25:28 -0700 | [diff] [blame] | 10397 | if (connector) |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 10398 | aconnector = to_amdgpu_dm_connector(connector); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10399 | |
| 10400 | /* TODO This hack should go away */ |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 10401 | if (connector && enable) { |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10402 | /* Make sure fake sink is created in plug-in scenario */ |
| 10403 | drm_new_conn_state = drm_atomic_get_new_connector_state(state, |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 10404 | connector); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10405 | drm_old_conn_state = drm_atomic_get_old_connector_state(state, |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 10406 | connector); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10407 | |
| 10408 | if (IS_ERR(drm_new_conn_state)) { |
| 10409 | ret = PTR_ERR_OR_ZERO(drm_new_conn_state); |
| 10410 | goto fail; |
| 10411 | } |
| 10412 | |
| 10413 | dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); |
| 10414 | dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); |
| 10415 | |
Jerry (Fangzhi) Zuo | 02d35a6 | 2019-01-11 16:34:31 -0500 | [diff] [blame] | 10416 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
| 10417 | goto skip_modeset; |
| 10418 | |
Stylon Wang | cbd14ae7 | 2020-04-30 16:40:09 +0800 | [diff] [blame] | 10419 | new_stream = create_validate_stream_for_sink(aconnector, |
| 10420 | &new_crtc_state->mode, |
| 10421 | dm_new_conn_state, |
| 10422 | dm_old_crtc_state->stream); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10423 | |
| 10424 | /* |
| 10425 | * we can have no stream on ACTION_SET if a display |
| 10426 | * was disconnected during S3, in this case it is not an |
| 10427 | * error, the OS will be updated after detection, and |
| 10428 | * will do the right thing on next atomic commit |
| 10429 | */ |
| 10430 | |
| 10431 | if (!new_stream) { |
| 10432 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
| 10433 | __func__, acrtc->base.base.id); |
| 10434 | ret = -ENOMEM; |
| 10435 | goto fail; |
| 10436 | } |
| 10437 | |
Victor Lu | 3d4e52d | 2020-07-21 12:08:34 -0400 | [diff] [blame] | 10438 | /* |
| 10439 | * TODO: Check VSDB bits to decide whether this should |
| 10440 | * be enabled or not. |
| 10441 | */ |
| 10442 | new_stream->triggered_crtc_reset.enabled = |
| 10443 | dm->force_timing_sync; |
| 10444 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10445 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; |
| 10446 | |
Nicholas Kazlauskas | 88694af | 2019-05-28 15:08:35 -0400 | [diff] [blame] | 10447 | ret = fill_hdr_info_packet(drm_new_conn_state, |
| 10448 | &new_stream->hdr_static_metadata); |
| 10449 | if (ret) |
| 10450 | goto fail; |
| 10451 | |
Nicholas Kazlauskas | 7e93094 | 2019-06-11 11:54:05 -0500 | [diff] [blame] | 10452 | /* |
| 10453 | * If we already removed the old stream from the context |
| 10454 | * (and set the new stream to NULL) then we can't reuse |
| 10455 | * the old stream even if the stream and scaling are unchanged. |
| 10456 | * We'll hit the BUG_ON and black screen. |
| 10457 | * |
| 10458 | * TODO: Refactor this function to allow this check to work |
| 10459 | * in all conditions. |
| 10460 | */ |
Alex Deucher | 3c591fa | 2024-02-27 13:08:12 -0500 | [diff] [blame] | 10461 | if (amdgpu_freesync_vid_mode && |
| 10462 | dm_new_crtc_state->stream && |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10463 | is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) |
| 10464 | goto skip_modeset; |
| 10465 | |
Nicholas Kazlauskas | 7e93094 | 2019-06-11 11:54:05 -0500 | [diff] [blame] | 10466 | if (dm_new_crtc_state->stream && |
| 10467 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10468 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { |
| 10469 | new_crtc_state->mode_changed = false; |
| 10470 | DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", |
| 10471 | new_crtc_state->mode_changed); |
| 10472 | } |
| 10473 | } |
| 10474 | |
Jerry (Fangzhi) Zuo | 02d35a6 | 2019-01-11 16:34:31 -0500 | [diff] [blame] | 10475 | /* mode_changed flag may get updated above, need to check again */ |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10476 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
| 10477 | goto skip_modeset; |
| 10478 | |
Sean Paul | 9f07550 | 2022-03-25 00:06:19 +0000 | [diff] [blame] | 10479 | drm_dbg_state(state->dev, |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10480 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10481 | acrtc->crtc_id, |
| 10482 | new_crtc_state->enable, |
| 10483 | new_crtc_state->active, |
| 10484 | new_crtc_state->planes_changed, |
| 10485 | new_crtc_state->mode_changed, |
| 10486 | new_crtc_state->active_changed, |
| 10487 | new_crtc_state->connectors_changed); |
| 10488 | |
| 10489 | /* Remove stream for any changed/disabled CRTC */ |
| 10490 | if (!enable) { |
| 10491 | |
| 10492 | if (!dm_old_crtc_state->stream) |
| 10493 | goto skip_modeset; |
| 10494 | |
Aurabindo Pillai | 0f5f1ee | 2023-01-11 14:56:22 -0500 | [diff] [blame] | 10495 | /* Unset freesync video if it was active before */ |
| 10496 | if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { |
| 10497 | dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; |
| 10498 | dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; |
| 10499 | } |
| 10500 | |
| 10501 | /* Now check if we should set freesync video mode */ |
Alex Deucher | 3c591fa | 2024-02-27 13:08:12 -0500 | [diff] [blame] | 10502 | if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && |
Aurabindo Pillai | b18f05a | 2023-05-17 14:39:46 -0400 | [diff] [blame] | 10503 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && |
| 10504 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10505 | is_timing_unchanged_for_freesync(new_crtc_state, |
| 10506 | old_crtc_state)) { |
| 10507 | new_crtc_state->mode_changed = false; |
| 10508 | DRM_DEBUG_DRIVER( |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10509 | "Mode change not required for front porch change, setting mode_changed to %d", |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10510 | new_crtc_state->mode_changed); |
| 10511 | |
| 10512 | set_freesync_fixed_config(dm_new_crtc_state); |
| 10513 | |
| 10514 | goto skip_modeset; |
Alex Deucher | 3c591fa | 2024-02-27 13:08:12 -0500 | [diff] [blame] | 10515 | } else if (amdgpu_freesync_vid_mode && aconnector && |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10516 | is_freesync_video_mode(&new_crtc_state->mode, |
| 10517 | aconnector)) { |
Solomon Chiu | e88ebd8 | 2021-07-28 00:20:30 +0800 | [diff] [blame] | 10518 | struct drm_display_mode *high_mode; |
| 10519 | |
| 10520 | high_mode = get_highest_refresh_rate_mode(aconnector, false); |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10521 | if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) |
Solomon Chiu | e88ebd8 | 2021-07-28 00:20:30 +0800 | [diff] [blame] | 10522 | set_freesync_fixed_config(dm_new_crtc_state); |
Nikola Cornij | a85ba00 | 2021-03-15 19:51:37 -0400 | [diff] [blame] | 10523 | } |
| 10524 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10525 | ret = dm_atomic_get_state(state, &dm_state); |
| 10526 | if (ret) |
| 10527 | goto fail; |
| 10528 | |
| 10529 | DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", |
| 10530 | crtc->base.id); |
| 10531 | |
| 10532 | /* i.e. reset mode */ |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 10533 | if (dc_state_remove_stream( |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10534 | dm->dc, |
| 10535 | dm_state->context, |
| 10536 | dm_old_crtc_state->stream) != DC_OK) { |
Harry Wentland | f2877656 | 2018-04-16 17:28:11 -0400 | [diff] [blame] | 10537 | ret = -EINVAL; |
| 10538 | goto fail; |
| 10539 | } |
| 10540 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10541 | dc_stream_release(dm_old_crtc_state->stream); |
| 10542 | dm_new_crtc_state->stream = NULL; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10543 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10544 | reset_freesync_config_for_crtc(dm_new_crtc_state); |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10545 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10546 | *lock_and_validation_needed = true; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10547 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10548 | } else {/* Add stream for any updated/enabled CRTC */ |
| 10549 | /* |
| 10550 | * Quick fix to prevent NULL pointer on new_stream when |
| 10551 | * added MST connectors not found in existing crtc_state in the chained mode |
| 10552 | * TODO: need to dig out the root cause of that |
| 10553 | */ |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 10554 | if (!connector) |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10555 | goto skip_modeset; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10556 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10557 | if (modereset_required(new_crtc_state)) |
| 10558 | goto skip_modeset; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10559 | |
David Tadokoro | 6c5e25a | 2023-03-07 16:14:17 -0300 | [diff] [blame] | 10560 | if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10561 | dm_old_crtc_state->stream)) { |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10562 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10563 | WARN_ON(dm_new_crtc_state->stream); |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10564 | |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 10565 | ret = dm_atomic_get_state(state, &dm_state); |
| 10566 | if (ret) |
| 10567 | goto fail; |
| 10568 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10569 | dm_new_crtc_state->stream = new_stream; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10570 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10571 | dc_stream_retain(new_stream); |
| 10572 | |
Luben Tuikov | 4711c03 | 2021-03-19 23:49:38 -0400 | [diff] [blame] | 10573 | DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", |
| 10574 | crtc->base.id); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10575 | |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 10576 | if (dc_state_add_stream( |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 10577 | dm->dc, |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10578 | dm_state->context, |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10579 | dm_new_crtc_state->stream) != DC_OK) { |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10580 | ret = -EINVAL; |
Darren Salt | 9635b75 | 2017-09-12 17:10:25 +0100 | [diff] [blame] | 10581 | goto fail; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10582 | } |
Bhawanpreet Lakha | 9b690ef | 2017-07-28 13:11:00 -0400 | [diff] [blame] | 10583 | |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10584 | *lock_and_validation_needed = true; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10585 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10586 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 10587 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10588 | skip_modeset: |
| 10589 | /* Release extra reference */ |
| 10590 | if (new_stream) |
Uwe Kleine-König | 3335a13 | 2023-03-27 18:07:54 +0200 | [diff] [blame] | 10591 | dc_stream_release(new_stream); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10592 | |
| 10593 | /* |
| 10594 | * We want to do dc stream updates that do not require a |
| 10595 | * full modeset below. |
| 10596 | */ |
Harry Wentland | 3e094a2 | 2023-12-01 06:25:27 -0700 | [diff] [blame] | 10597 | if (!(enable && connector && new_crtc_state->active)) |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10598 | return 0; |
| 10599 | /* |
| 10600 | * Given above conditions, the dc state cannot be NULL because: |
| 10601 | * 1. We're in the process of enabling CRTCs (just been added |
| 10602 | * to the dc context, or already is on the context) |
| 10603 | * 2. Has a valid connector attached, and |
| 10604 | * 3. Is currently active and enabled. |
| 10605 | * => The dc stream state currently exists. |
| 10606 | */ |
| 10607 | BUG_ON(dm_new_crtc_state->stream == NULL); |
| 10608 | |
| 10609 | /* Scaling or underscan settings */ |
Roman Li | c521fc3 | 2021-05-21 10:20:25 -0400 | [diff] [blame] | 10610 | if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || |
| 10611 | drm_atomic_crtc_needs_modeset(new_crtc_state)) |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10612 | update_stream_scaling_settings( |
| 10613 | &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); |
| 10614 | |
David Francis | b05e2c5 | 2019-03-04 10:31:31 -0500 | [diff] [blame] | 10615 | /* ABM settings */ |
| 10616 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; |
| 10617 | |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10618 | /* |
| 10619 | * Color management settings. We also update color properties |
| 10620 | * when a modeset is needed, to ensure it gets reprogrammed. |
| 10621 | */ |
| 10622 | if (dm_new_crtc_state->base.color_mgmt_changed || |
Joshua Ashton | 6bd20f0 | 2023-11-16 18:57:55 -0100 | [diff] [blame] | 10623 | dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10624 | drm_atomic_crtc_needs_modeset(new_crtc_state)) { |
Nicholas Kazlauskas | cf020d49 | 2019-05-09 12:14:58 -0400 | [diff] [blame] | 10625 | ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10626 | if (ret) |
| 10627 | goto fail; |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 10628 | } |
| 10629 | |
| 10630 | /* Update Freesync settings. */ |
| 10631 | get_freesync_config_for_crtc(dm_new_crtc_state, |
| 10632 | dm_new_conn_state); |
| 10633 | |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10634 | return ret; |
Darren Salt | 9635b75 | 2017-09-12 17:10:25 +0100 | [diff] [blame] | 10635 | |
| 10636 | fail: |
| 10637 | if (new_stream) |
| 10638 | dc_stream_release(new_stream); |
| 10639 | return ret; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10640 | } |
| 10641 | |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10642 | static bool should_reset_plane(struct drm_atomic_state *state, |
| 10643 | struct drm_plane *plane, |
| 10644 | struct drm_plane_state *old_plane_state, |
| 10645 | struct drm_plane_state *new_plane_state) |
| 10646 | { |
| 10647 | struct drm_plane *other; |
| 10648 | struct drm_plane_state *old_other_state, *new_other_state; |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 10649 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
| 10650 | struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; |
Tianci Yin | 435f5b3 | 2023-11-01 09:47:13 +0800 | [diff] [blame] | 10651 | struct amdgpu_device *adev = drm_to_adev(plane->dev); |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10652 | int i; |
| 10653 | |
Nicholas Kazlauskas | 70a1efa | 2019-06-20 08:30:09 -0400 | [diff] [blame] | 10654 | /* |
Tianci Yin | 435f5b3 | 2023-11-01 09:47:13 +0800 | [diff] [blame] | 10655 | * TODO: Remove this hack for all asics once it proves that the |
| 10656 | * fast updates works fine on DCN3.2+. |
Nicholas Kazlauskas | 70a1efa | 2019-06-20 08:30:09 -0400 | [diff] [blame] | 10657 | */ |
Lijo Lazar | ed342a2 | 2023-12-01 17:13:46 +0530 | [diff] [blame] | 10658 | if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && |
| 10659 | state->allow_modeset) |
Nicholas Kazlauskas | 70a1efa | 2019-06-20 08:30:09 -0400 | [diff] [blame] | 10660 | return true; |
| 10661 | |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10662 | /* Exit early if we know that we're adding or removing the plane. */ |
| 10663 | if (old_plane_state->crtc != new_plane_state->crtc) |
| 10664 | return true; |
| 10665 | |
| 10666 | /* old crtc == new_crtc == NULL, plane not in context. */ |
| 10667 | if (!new_plane_state->crtc) |
| 10668 | return false; |
| 10669 | |
| 10670 | new_crtc_state = |
| 10671 | drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 10672 | old_crtc_state = |
| 10673 | drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10674 | |
| 10675 | if (!new_crtc_state) |
| 10676 | return true; |
| 10677 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 10678 | /* |
| 10679 | * A change in cursor mode means a new dc pipe needs to be acquired or |
| 10680 | * released from the state |
| 10681 | */ |
| 10682 | old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 10683 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 10684 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
| 10685 | old_dm_crtc_state != NULL && |
| 10686 | old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { |
| 10687 | return true; |
| 10688 | } |
| 10689 | |
Nicholas Kazlauskas | 7316c4a | 2019-05-01 10:26:09 -0400 | [diff] [blame] | 10690 | /* CRTC Degamma changes currently require us to recreate planes. */ |
| 10691 | if (new_crtc_state->color_mgmt_changed) |
| 10692 | return true; |
| 10693 | |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 10694 | /* |
| 10695 | * On zpos change, planes need to be reordered by removing and re-adding |
| 10696 | * them one by one to the dc state, in order of descending zpos. |
| 10697 | * |
| 10698 | * TODO: We can likely skip bandwidth validation if the only thing that |
| 10699 | * changed about the plane was it'z z-ordering. |
| 10700 | */ |
Leo Li | 578aab4 | 2024-09-05 18:45:04 -0400 | [diff] [blame] | 10701 | if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 10702 | return true; |
| 10703 | |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10704 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) |
| 10705 | return true; |
| 10706 | |
| 10707 | /* |
| 10708 | * If there are any new primary or overlay planes being added or |
| 10709 | * removed then the z-order can potentially change. To ensure |
| 10710 | * correct z-order and pipe acquisition the current DC architecture |
| 10711 | * requires us to remove and recreate all existing planes. |
| 10712 | * |
| 10713 | * TODO: Come up with a more elegant solution for this. |
| 10714 | */ |
| 10715 | for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 10716 | struct amdgpu_framebuffer *old_afb, *new_afb; |
Joshua Ashton | 6bed9d55 | 2023-11-16 18:57:57 -0100 | [diff] [blame] | 10717 | struct dm_plane_state *dm_new_other_state, *dm_old_other_state; |
| 10718 | |
| 10719 | dm_new_other_state = to_dm_plane_state(new_other_state); |
| 10720 | dm_old_other_state = to_dm_plane_state(old_other_state); |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10721 | |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10722 | if (other->type == DRM_PLANE_TYPE_CURSOR) |
| 10723 | continue; |
| 10724 | |
| 10725 | if (old_other_state->crtc != new_plane_state->crtc && |
| 10726 | new_other_state->crtc != new_plane_state->crtc) |
| 10727 | continue; |
| 10728 | |
| 10729 | if (old_other_state->crtc != new_other_state->crtc) |
| 10730 | return true; |
| 10731 | |
Nicholas Kazlauskas | dc4cb30 | 2020-07-28 10:48:21 -0400 | [diff] [blame] | 10732 | /* Src/dst size and scaling updates. */ |
| 10733 | if (old_other_state->src_w != new_other_state->src_w || |
| 10734 | old_other_state->src_h != new_other_state->src_h || |
| 10735 | old_other_state->crtc_w != new_other_state->crtc_w || |
| 10736 | old_other_state->crtc_h != new_other_state->crtc_h) |
| 10737 | return true; |
| 10738 | |
| 10739 | /* Rotation / mirroring updates. */ |
| 10740 | if (old_other_state->rotation != new_other_state->rotation) |
| 10741 | return true; |
| 10742 | |
| 10743 | /* Blending updates. */ |
| 10744 | if (old_other_state->pixel_blend_mode != |
| 10745 | new_other_state->pixel_blend_mode) |
| 10746 | return true; |
| 10747 | |
| 10748 | /* Alpha updates. */ |
| 10749 | if (old_other_state->alpha != new_other_state->alpha) |
| 10750 | return true; |
| 10751 | |
| 10752 | /* Colorspace changes. */ |
| 10753 | if (old_other_state->color_range != new_other_state->color_range || |
| 10754 | old_other_state->color_encoding != new_other_state->color_encoding) |
| 10755 | return true; |
| 10756 | |
Joshua Ashton | 6bed9d55 | 2023-11-16 18:57:57 -0100 | [diff] [blame] | 10757 | /* HDR/Transfer Function changes. */ |
| 10758 | if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || |
| 10759 | dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || |
| 10760 | dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || |
Melissa Wen | 3dad690 | 2023-11-16 18:58:11 -0100 | [diff] [blame] | 10761 | dm_old_other_state->ctm != dm_new_other_state->ctm || |
Joshua Ashton | 6bed9d55 | 2023-11-16 18:57:57 -0100 | [diff] [blame] | 10762 | dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || |
| 10763 | dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || |
| 10764 | dm_old_other_state->lut3d != dm_new_other_state->lut3d || |
| 10765 | dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || |
| 10766 | dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) |
| 10767 | return true; |
| 10768 | |
Nicholas Kazlauskas | 9a81cc6 | 2020-07-28 09:59:53 -0400 | [diff] [blame] | 10769 | /* Framebuffer checks fall at the end. */ |
| 10770 | if (!old_other_state->fb || !new_other_state->fb) |
| 10771 | continue; |
| 10772 | |
| 10773 | /* Pixel format changes can require bandwidth updates. */ |
| 10774 | if (old_other_state->fb->format != new_other_state->fb->format) |
| 10775 | return true; |
| 10776 | |
Bas Nieuwenhuizen | 6eed95b | 2020-09-02 14:22:38 +0200 | [diff] [blame] | 10777 | old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; |
| 10778 | new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; |
Nicholas Kazlauskas | 9a81cc6 | 2020-07-28 09:59:53 -0400 | [diff] [blame] | 10779 | |
| 10780 | /* Tiling and DCC changes also require bandwidth updates. */ |
Bas Nieuwenhuizen | 37384b3 | 2020-06-08 13:46:06 +0200 | [diff] [blame] | 10781 | if (old_afb->tiling_flags != new_afb->tiling_flags || |
| 10782 | old_afb->base.modifier != new_afb->base.modifier) |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10783 | return true; |
| 10784 | } |
| 10785 | |
| 10786 | return false; |
| 10787 | } |
| 10788 | |
Simon Ser | b0455fda6 | 2020-12-03 20:19:35 +0000 | [diff] [blame] | 10789 | static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, |
| 10790 | struct drm_plane_state *new_plane_state, |
| 10791 | struct drm_framebuffer *fb) |
| 10792 | { |
Simon Ser | e72868c | 2020-12-03 20:19:41 +0000 | [diff] [blame] | 10793 | struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); |
| 10794 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); |
Simon Ser | b0455fda6 | 2020-12-03 20:19:35 +0000 | [diff] [blame] | 10795 | unsigned int pitch; |
Simon Ser | e72868c | 2020-12-03 20:19:41 +0000 | [diff] [blame] | 10796 | bool linear; |
Simon Ser | b0455fda6 | 2020-12-03 20:19:35 +0000 | [diff] [blame] | 10797 | |
| 10798 | if (fb->width > new_acrtc->max_cursor_width || |
| 10799 | fb->height > new_acrtc->max_cursor_height) { |
| 10800 | DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", |
| 10801 | new_plane_state->fb->width, |
| 10802 | new_plane_state->fb->height); |
| 10803 | return -EINVAL; |
| 10804 | } |
| 10805 | if (new_plane_state->src_w != fb->width << 16 || |
| 10806 | new_plane_state->src_h != fb->height << 16) { |
| 10807 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); |
| 10808 | return -EINVAL; |
| 10809 | } |
| 10810 | |
| 10811 | /* Pitch in pixels */ |
| 10812 | pitch = fb->pitches[0] / fb->format->cpp[0]; |
| 10813 | |
| 10814 | if (fb->width != pitch) { |
| 10815 | DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", |
| 10816 | fb->width, pitch); |
| 10817 | return -EINVAL; |
| 10818 | } |
| 10819 | |
| 10820 | switch (pitch) { |
| 10821 | case 64: |
| 10822 | case 128: |
| 10823 | case 256: |
| 10824 | /* FB pitch is supported by cursor plane */ |
| 10825 | break; |
| 10826 | default: |
| 10827 | DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); |
| 10828 | return -EINVAL; |
| 10829 | } |
| 10830 | |
Simon Ser | e72868c | 2020-12-03 20:19:41 +0000 | [diff] [blame] | 10831 | /* Core DRM takes care of checking FB modifiers, so we only need to |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10832 | * check tiling flags when the FB doesn't have a modifier. |
| 10833 | */ |
Simon Ser | e72868c | 2020-12-03 20:19:41 +0000 | [diff] [blame] | 10834 | if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { |
Marek Olšák | f213738 | 2024-06-01 14:36:41 -0400 | [diff] [blame] | 10835 | if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { |
| 10836 | linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; |
| 10837 | } else if (adev->family >= AMDGPU_FAMILY_AI) { |
| 10838 | linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; |
| 10839 | } else { |
Simon Ser | e72868c | 2020-12-03 20:19:41 +0000 | [diff] [blame] | 10840 | linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 10841 | AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && |
Simon Ser | e72868c | 2020-12-03 20:19:41 +0000 | [diff] [blame] | 10842 | AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; |
Simon Ser | e72868c | 2020-12-03 20:19:41 +0000 | [diff] [blame] | 10843 | } |
| 10844 | if (!linear) { |
| 10845 | DRM_DEBUG_ATOMIC("Cursor FB not linear"); |
| 10846 | return -EINVAL; |
| 10847 | } |
| 10848 | } |
| 10849 | |
Simon Ser | b0455fda6 | 2020-12-03 20:19:35 +0000 | [diff] [blame] | 10850 | return 0; |
| 10851 | } |
| 10852 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 10853 | /* |
| 10854 | * Helper function for checking the cursor in native mode |
| 10855 | */ |
| 10856 | static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, |
| 10857 | struct drm_plane *plane, |
| 10858 | struct drm_plane_state *new_plane_state, |
| 10859 | bool enable) |
| 10860 | { |
| 10861 | |
| 10862 | struct amdgpu_crtc *new_acrtc; |
| 10863 | int ret; |
| 10864 | |
| 10865 | if (!enable || !new_plane_crtc || |
| 10866 | drm_atomic_plane_disabling(plane->state, new_plane_state)) |
| 10867 | return 0; |
| 10868 | |
| 10869 | new_acrtc = to_amdgpu_crtc(new_plane_crtc); |
| 10870 | |
| 10871 | if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { |
| 10872 | DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); |
| 10873 | return -EINVAL; |
| 10874 | } |
| 10875 | |
| 10876 | if (new_plane_state->fb) { |
| 10877 | ret = dm_check_cursor_fb(new_acrtc, new_plane_state, |
| 10878 | new_plane_state->fb); |
| 10879 | if (ret) |
| 10880 | return ret; |
| 10881 | } |
| 10882 | |
| 10883 | return 0; |
| 10884 | } |
| 10885 | |
| 10886 | static bool dm_should_update_native_cursor(struct drm_atomic_state *state, |
| 10887 | struct drm_crtc *old_plane_crtc, |
| 10888 | struct drm_crtc *new_plane_crtc, |
| 10889 | bool enable) |
| 10890 | { |
| 10891 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
| 10892 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
| 10893 | |
| 10894 | if (!enable) { |
| 10895 | if (old_plane_crtc == NULL) |
| 10896 | return true; |
| 10897 | |
| 10898 | old_crtc_state = drm_atomic_get_old_crtc_state( |
| 10899 | state, old_plane_crtc); |
| 10900 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 10901 | |
| 10902 | return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; |
| 10903 | } else { |
| 10904 | if (new_plane_crtc == NULL) |
| 10905 | return true; |
| 10906 | |
| 10907 | new_crtc_state = drm_atomic_get_new_crtc_state( |
| 10908 | state, new_plane_crtc); |
| 10909 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 10910 | |
| 10911 | return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; |
| 10912 | } |
| 10913 | } |
| 10914 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10915 | static int dm_update_plane_state(struct dc *dc, |
| 10916 | struct drm_atomic_state *state, |
| 10917 | struct drm_plane *plane, |
| 10918 | struct drm_plane_state *old_plane_state, |
| 10919 | struct drm_plane_state *new_plane_state, |
| 10920 | bool enable, |
Bhawanpreet Lakha | 35f3308 | 2023-01-17 14:35:41 -0500 | [diff] [blame] | 10921 | bool *lock_and_validation_needed, |
| 10922 | bool *is_top_most_overlay) |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10923 | { |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 10924 | |
| 10925 | struct dm_atomic_state *dm_state = NULL; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10926 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 10927 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 10928 | struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 10929 | struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 10930 | bool needs_reset, update_native_cursor; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10931 | int ret = 0; |
| 10932 | |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10933 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10934 | new_plane_crtc = new_plane_state->crtc; |
| 10935 | old_plane_crtc = old_plane_state->crtc; |
| 10936 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
| 10937 | dm_old_plane_state = to_dm_plane_state(old_plane_state); |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10938 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 10939 | update_native_cursor = dm_should_update_native_cursor(state, |
| 10940 | old_plane_crtc, |
| 10941 | new_plane_crtc, |
| 10942 | enable); |
Simon Ser | 626bf90f | 2020-03-30 09:23:21 +0000 | [diff] [blame] | 10943 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 10944 | if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { |
| 10945 | ret = dm_check_native_cursor_state(new_plane_crtc, plane, |
| 10946 | new_plane_state, enable); |
| 10947 | if (ret) |
| 10948 | return ret; |
Simon Ser | 24f99d2 | 2020-11-20 20:18:55 +0000 | [diff] [blame] | 10949 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10950 | return 0; |
Simon Ser | 626bf90f | 2020-03-30 09:23:21 +0000 | [diff] [blame] | 10951 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10952 | |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10953 | needs_reset = should_reset_plane(state, plane, old_plane_state, |
| 10954 | new_plane_state); |
| 10955 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10956 | /* Remove any changed/removed planes */ |
| 10957 | if (!enable) { |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 10958 | if (!needs_reset) |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10959 | return 0; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10960 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10961 | if (!old_plane_crtc) |
| 10962 | return 0; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10963 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10964 | old_crtc_state = drm_atomic_get_old_crtc_state( |
| 10965 | state, old_plane_crtc); |
| 10966 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10967 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10968 | if (!dm_old_crtc_state->stream) |
| 10969 | return 0; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10970 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10971 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
| 10972 | plane->base.id, old_plane_crtc->base.id); |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10973 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10974 | ret = dm_atomic_get_state(state, &dm_state); |
| 10975 | if (ret) |
| 10976 | return ret; |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 10977 | |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 10978 | if (!dc_state_remove_plane( |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10979 | dc, |
| 10980 | dm_old_crtc_state->stream, |
| 10981 | dm_old_plane_state->dc_state, |
| 10982 | dm_state->context)) { |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10983 | |
Tianjia Zhang | c35376137 | 2020-08-02 19:15:36 +0800 | [diff] [blame] | 10984 | return -EINVAL; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 10985 | } |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10986 | |
Aurabindo Pillai | da5e149 | 2023-03-24 10:42:37 -0400 | [diff] [blame] | 10987 | if (dm_old_plane_state->dc_state) |
| 10988 | dc_plane_state_release(dm_old_plane_state->dc_state); |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10989 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 10990 | dm_new_plane_state->dc_state = NULL; |
| 10991 | |
| 10992 | *lock_and_validation_needed = true; |
| 10993 | |
| 10994 | } else { /* Add new planes */ |
| 10995 | struct dc_plane_state *dc_new_plane_state; |
| 10996 | |
| 10997 | if (drm_atomic_plane_disabling(plane->state, new_plane_state)) |
| 10998 | return 0; |
| 10999 | |
| 11000 | if (!new_plane_crtc) |
| 11001 | return 0; |
| 11002 | |
| 11003 | new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); |
| 11004 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 11005 | |
| 11006 | if (!dm_new_crtc_state->stream) |
| 11007 | return 0; |
| 11008 | |
Nicholas Kazlauskas | f6ff2a0 | 2019-03-25 12:17:14 -0400 | [diff] [blame] | 11009 | if (!needs_reset) |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11010 | return 0; |
| 11011 | |
David Tadokoro | 8bf0d9c | 2023-03-05 23:24:27 -0300 | [diff] [blame] | 11012 | ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); |
Aurabindo Pillai | 8c44515 | 2020-06-04 15:54:39 -0400 | [diff] [blame] | 11013 | if (ret) |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11014 | goto out; |
Aurabindo Pillai | 8c44515 | 2020-06-04 15:54:39 -0400 | [diff] [blame] | 11015 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11016 | WARN_ON(dm_new_plane_state->dc_state); |
| 11017 | |
| 11018 | dc_new_plane_state = dc_create_plane_state(dc); |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11019 | if (!dc_new_plane_state) { |
| 11020 | ret = -ENOMEM; |
| 11021 | goto out; |
Bhawanpreet Lakha | 35f3308 | 2023-01-17 14:35:41 -0500 | [diff] [blame] | 11022 | } |
| 11023 | |
Luben Tuikov | 4711c03 | 2021-03-19 23:49:38 -0400 | [diff] [blame] | 11024 | DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", |
| 11025 | plane->base.id, new_plane_crtc->base.id); |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11026 | |
Nicholas Kazlauskas | 695af5f9 | 2019-03-28 14:45:19 -0400 | [diff] [blame] | 11027 | ret = fill_dc_plane_attributes( |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 11028 | drm_to_adev(new_plane_crtc->dev), |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11029 | dc_new_plane_state, |
| 11030 | new_plane_state, |
| 11031 | new_crtc_state); |
| 11032 | if (ret) { |
| 11033 | dc_plane_state_release(dc_new_plane_state); |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11034 | goto out; |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11035 | } |
| 11036 | |
| 11037 | ret = dm_atomic_get_state(state, &dm_state); |
| 11038 | if (ret) { |
| 11039 | dc_plane_state_release(dc_new_plane_state); |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11040 | goto out; |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11041 | } |
| 11042 | |
| 11043 | /* |
| 11044 | * Any atomic check errors that occur after this will |
| 11045 | * not need a release. The plane state will be attached |
| 11046 | * to the stream, and therefore part of the atomic |
| 11047 | * state. It'll be released when the atomic state is |
| 11048 | * cleaned. |
| 11049 | */ |
Dillon Varone | 09a4ec5 | 2023-11-17 16:37:50 -0500 | [diff] [blame] | 11050 | if (!dc_state_add_plane( |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11051 | dc, |
| 11052 | dm_new_crtc_state->stream, |
| 11053 | dc_new_plane_state, |
| 11054 | dm_state->context)) { |
| 11055 | |
| 11056 | dc_plane_state_release(dc_new_plane_state); |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11057 | ret = -EINVAL; |
| 11058 | goto out; |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11059 | } |
| 11060 | |
| 11061 | dm_new_plane_state->dc_state = dc_new_plane_state; |
| 11062 | |
Mikita Lipski | 214993e | 2021-12-15 11:01:45 -0500 | [diff] [blame] | 11063 | dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); |
| 11064 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11065 | /* Tell DC to do a full surface update every time there |
| 11066 | * is a plane change. Inefficient, but works for now. |
| 11067 | */ |
| 11068 | dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; |
| 11069 | |
| 11070 | *lock_and_validation_needed = true; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11071 | } |
| 11072 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11073 | out: |
| 11074 | /* If enabling cursor overlay failed, attempt fallback to native mode */ |
| 11075 | if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { |
| 11076 | ret = dm_check_native_cursor_state(new_plane_crtc, plane, |
| 11077 | new_plane_state, enable); |
| 11078 | if (ret) |
| 11079 | return ret; |
| 11080 | |
| 11081 | dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; |
| 11082 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11083 | |
| 11084 | return ret; |
| 11085 | } |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 11086 | |
Vlad Zahorodnii | 69cb562 | 2021-12-02 14:52:15 +0200 | [diff] [blame] | 11087 | static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, |
| 11088 | int *src_w, int *src_h) |
| 11089 | { |
| 11090 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { |
| 11091 | case DRM_MODE_ROTATE_90: |
| 11092 | case DRM_MODE_ROTATE_270: |
| 11093 | *src_w = plane_state->src_h >> 16; |
| 11094 | *src_h = plane_state->src_w >> 16; |
| 11095 | break; |
| 11096 | case DRM_MODE_ROTATE_0: |
| 11097 | case DRM_MODE_ROTATE_180: |
| 11098 | default: |
| 11099 | *src_w = plane_state->src_w >> 16; |
| 11100 | *src_h = plane_state->src_h >> 16; |
| 11101 | break; |
| 11102 | } |
| 11103 | } |
| 11104 | |
Michel Dänzer | ec4d770 | 2023-10-02 16:16:48 +0200 | [diff] [blame] | 11105 | static void |
| 11106 | dm_get_plane_scale(struct drm_plane_state *plane_state, |
| 11107 | int *out_plane_scale_w, int *out_plane_scale_h) |
| 11108 | { |
| 11109 | int plane_src_w, plane_src_h; |
| 11110 | |
| 11111 | dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); |
| 11112 | *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; |
| 11113 | *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; |
| 11114 | } |
| 11115 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11116 | /* |
| 11117 | * The normalized_zpos value cannot be used by this iterator directly. It's only |
| 11118 | * calculated for enabled planes, potentially causing normalized_zpos collisions |
| 11119 | * between enabled/disabled planes in the atomic state. We need a unique value |
| 11120 | * so that the iterator will not generate the same object twice, or loop |
| 11121 | * indefinitely. |
| 11122 | */ |
| 11123 | static inline struct __drm_planes_state *__get_next_zpos( |
| 11124 | struct drm_atomic_state *state, |
| 11125 | struct __drm_planes_state *prev) |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11126 | { |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11127 | unsigned int highest_zpos = 0, prev_zpos = 256; |
| 11128 | uint32_t highest_id = 0, prev_id = UINT_MAX; |
| 11129 | struct drm_plane_state *new_plane_state; |
| 11130 | struct drm_plane *plane; |
| 11131 | int i, highest_i = -1; |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11132 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11133 | if (prev != NULL) { |
| 11134 | prev_zpos = prev->new_state->zpos; |
| 11135 | prev_id = prev->ptr->base.id; |
| 11136 | } |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11137 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11138 | for_each_new_plane_in_state(state, plane, new_plane_state, i) { |
| 11139 | /* Skip planes with higher zpos than the previously returned */ |
| 11140 | if (new_plane_state->zpos > prev_zpos || |
| 11141 | (new_plane_state->zpos == prev_zpos && |
| 11142 | plane->base.id >= prev_id)) |
Michel Dänzer | bc0b79c | 2023-10-02 16:16:49 +0200 | [diff] [blame] | 11143 | continue; |
| 11144 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11145 | /* Save the index of the plane with highest zpos */ |
| 11146 | if (new_plane_state->zpos > highest_zpos || |
| 11147 | (new_plane_state->zpos == highest_zpos && |
| 11148 | plane->base.id > highest_id)) { |
| 11149 | highest_zpos = new_plane_state->zpos; |
| 11150 | highest_id = plane->base.id; |
| 11151 | highest_i = i; |
Michel Dänzer | bc0b79c | 2023-10-02 16:16:49 +0200 | [diff] [blame] | 11152 | } |
| 11153 | } |
| 11154 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11155 | if (highest_i < 0) |
| 11156 | return NULL; |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11157 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11158 | return &state->planes[highest_i]; |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11159 | } |
| 11160 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11161 | /* |
| 11162 | * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate |
| 11163 | * by descending zpos, as read from the new plane state. This is the same |
| 11164 | * ordering as defined by drm_atomic_normalize_zpos(). |
| 11165 | */ |
| 11166 | #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ |
| 11167 | for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ |
| 11168 | __i != NULL; __i = __get_next_zpos((__state), __i)) \ |
| 11169 | for_each_if(((plane) = __i->ptr, \ |
| 11170 | (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ |
| 11171 | (old_plane_state) = __i->old_state, \ |
| 11172 | (new_plane_state) = __i->new_state, 1)) |
| 11173 | |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11174 | static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) |
| 11175 | { |
| 11176 | struct drm_connector *connector; |
Roman Li | 128f8ed | 2021-12-23 17:39:57 -0500 | [diff] [blame] | 11177 | struct drm_connector_state *conn_state, *old_conn_state; |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11178 | struct amdgpu_dm_connector *aconnector = NULL; |
| 11179 | int i; |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 11180 | |
Roman Li | 128f8ed | 2021-12-23 17:39:57 -0500 | [diff] [blame] | 11181 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { |
| 11182 | if (!conn_state->crtc) |
| 11183 | conn_state = old_conn_state; |
| 11184 | |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11185 | if (conn_state->crtc != crtc) |
| 11186 | continue; |
| 11187 | |
Harry Wentland | 7db7ade | 2023-12-01 06:25:25 -0700 | [diff] [blame] | 11188 | if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) |
| 11189 | continue; |
| 11190 | |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11191 | aconnector = to_amdgpu_dm_connector(connector); |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 11192 | if (!aconnector->mst_output_port || !aconnector->mst_root) |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11193 | aconnector = NULL; |
| 11194 | else |
| 11195 | break; |
| 11196 | } |
| 11197 | |
| 11198 | if (!aconnector) |
| 11199 | return 0; |
| 11200 | |
Wayne Lin | f0127cb | 2022-12-28 19:47:12 +0800 | [diff] [blame] | 11201 | return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11202 | } |
| 11203 | |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 11204 | /** |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11205 | * DOC: Cursor Modes - Native vs Overlay |
| 11206 | * |
| 11207 | * In native mode, the cursor uses a integrated cursor pipe within each DCN hw |
| 11208 | * plane. It does not require a dedicated hw plane to enable, but it is |
| 11209 | * subjected to the same z-order and scaling as the hw plane. It also has format |
| 11210 | * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB |
| 11211 | * hw plane. |
| 11212 | * |
| 11213 | * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its |
| 11214 | * own scaling and z-pos. It also has no blending restrictions. It lends to a |
| 11215 | * cursor behavior more akin to a DRM client's expectations. However, it does |
| 11216 | * occupy an extra DCN plane, and therefore will only be used if a DCN plane is |
| 11217 | * available. |
| 11218 | */ |
| 11219 | |
| 11220 | /** |
| 11221 | * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc |
| 11222 | * @adev: amdgpu device |
| 11223 | * @state: DRM atomic state |
| 11224 | * @dm_crtc_state: amdgpu state for the CRTC containing the cursor |
| 11225 | * @cursor_mode: Returns the required cursor mode on dm_crtc_state |
| 11226 | * |
| 11227 | * Get whether the cursor should be enabled in native mode, or overlay mode, on |
| 11228 | * the dm_crtc_state. |
| 11229 | * |
| 11230 | * The cursor should be enabled in overlay mode if there exists an underlying |
| 11231 | * plane - on which the cursor may be blended - that is either YUV formatted, or |
| 11232 | * scaled differently from the cursor. |
| 11233 | * |
| 11234 | * Since zpos info is required, drm_atomic_normalize_zpos must be called before |
| 11235 | * calling this function. |
| 11236 | * |
| 11237 | * Return: 0 on success, or an error code if getting the cursor plane state |
| 11238 | * failed. |
| 11239 | */ |
| 11240 | static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, |
| 11241 | struct drm_atomic_state *state, |
| 11242 | struct dm_crtc_state *dm_crtc_state, |
| 11243 | enum amdgpu_dm_cursor_mode *cursor_mode) |
| 11244 | { |
| 11245 | struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; |
| 11246 | struct drm_crtc_state *crtc_state = &dm_crtc_state->base; |
| 11247 | struct drm_plane *plane; |
| 11248 | bool consider_mode_change = false; |
| 11249 | bool entire_crtc_covered = false; |
| 11250 | bool cursor_changed = false; |
| 11251 | int underlying_scale_w, underlying_scale_h; |
| 11252 | int cursor_scale_w, cursor_scale_h; |
| 11253 | int i; |
| 11254 | |
Aurabindo Pillai | 2ffa97c | 2024-06-10 18:22:59 +0000 | [diff] [blame] | 11255 | /* Overlay cursor not supported on HW before DCN |
| 11256 | * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions |
| 11257 | * as previous DCN generations, so enable native mode on DCN401 in addition to DCE |
| 11258 | */ |
| 11259 | if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 || |
| 11260 | amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11261 | *cursor_mode = DM_CURSOR_NATIVE_MODE; |
| 11262 | return 0; |
| 11263 | } |
| 11264 | |
| 11265 | /* Init cursor_mode to be the same as current */ |
| 11266 | *cursor_mode = dm_crtc_state->cursor_mode; |
| 11267 | |
| 11268 | /* |
| 11269 | * Cursor mode can change if a plane's format changes, scale changes, is |
| 11270 | * enabled/disabled, or z-order changes. |
| 11271 | */ |
| 11272 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { |
| 11273 | int new_scale_w, new_scale_h, old_scale_w, old_scale_h; |
| 11274 | |
| 11275 | /* Only care about planes on this CRTC */ |
| 11276 | if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) |
| 11277 | continue; |
| 11278 | |
| 11279 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
| 11280 | cursor_changed = true; |
| 11281 | |
| 11282 | if (drm_atomic_plane_enabling(old_plane_state, plane_state) || |
| 11283 | drm_atomic_plane_disabling(old_plane_state, plane_state) || |
| 11284 | old_plane_state->fb->format != plane_state->fb->format) { |
| 11285 | consider_mode_change = true; |
| 11286 | break; |
| 11287 | } |
| 11288 | |
| 11289 | dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); |
| 11290 | dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); |
| 11291 | if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { |
| 11292 | consider_mode_change = true; |
| 11293 | break; |
| 11294 | } |
| 11295 | } |
| 11296 | |
| 11297 | if (!consider_mode_change && !crtc_state->zpos_changed) |
| 11298 | return 0; |
| 11299 | |
| 11300 | /* |
| 11301 | * If no cursor change on this CRTC, and not enabled on this CRTC, then |
| 11302 | * no need to set cursor mode. This avoids needlessly locking the cursor |
| 11303 | * state. |
| 11304 | */ |
| 11305 | if (!cursor_changed && |
| 11306 | !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { |
| 11307 | return 0; |
| 11308 | } |
| 11309 | |
| 11310 | cursor_state = drm_atomic_get_plane_state(state, |
| 11311 | crtc_state->crtc->cursor); |
| 11312 | if (IS_ERR(cursor_state)) |
| 11313 | return PTR_ERR(cursor_state); |
| 11314 | |
| 11315 | /* Cursor is disabled */ |
| 11316 | if (!cursor_state->fb) |
| 11317 | return 0; |
| 11318 | |
| 11319 | /* For all planes in descending z-order (all of which are below cursor |
| 11320 | * as per zpos definitions), check their scaling and format |
| 11321 | */ |
| 11322 | for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { |
| 11323 | |
| 11324 | /* Only care about non-cursor planes on this CRTC */ |
| 11325 | if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || |
| 11326 | plane->type == DRM_PLANE_TYPE_CURSOR) |
| 11327 | continue; |
| 11328 | |
| 11329 | /* Underlying plane is YUV format - use overlay cursor */ |
| 11330 | if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { |
| 11331 | *cursor_mode = DM_CURSOR_OVERLAY_MODE; |
| 11332 | return 0; |
| 11333 | } |
| 11334 | |
| 11335 | dm_get_plane_scale(plane_state, |
| 11336 | &underlying_scale_w, &underlying_scale_h); |
| 11337 | dm_get_plane_scale(cursor_state, |
| 11338 | &cursor_scale_w, &cursor_scale_h); |
| 11339 | |
| 11340 | /* Underlying plane has different scale - use overlay cursor */ |
| 11341 | if (cursor_scale_w != underlying_scale_w && |
| 11342 | cursor_scale_h != underlying_scale_h) { |
| 11343 | *cursor_mode = DM_CURSOR_OVERLAY_MODE; |
| 11344 | return 0; |
| 11345 | } |
| 11346 | |
| 11347 | /* If this plane covers the whole CRTC, no need to check planes underneath */ |
| 11348 | if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && |
| 11349 | plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && |
| 11350 | plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { |
| 11351 | entire_crtc_covered = true; |
| 11352 | break; |
| 11353 | } |
| 11354 | } |
| 11355 | |
| 11356 | /* If planes do not cover the entire CRTC, use overlay mode to enable |
| 11357 | * cursor over holes |
| 11358 | */ |
| 11359 | if (entire_crtc_covered) |
| 11360 | *cursor_mode = DM_CURSOR_NATIVE_MODE; |
| 11361 | else |
| 11362 | *cursor_mode = DM_CURSOR_OVERLAY_MODE; |
| 11363 | |
| 11364 | return 0; |
| 11365 | } |
| 11366 | |
| 11367 | /** |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 11368 | * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. |
Rodrigo Siqueira | c620e79 | 2022-02-21 15:22:50 -0500 | [diff] [blame] | 11369 | * |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 11370 | * @dev: The DRM device |
| 11371 | * @state: The atomic state to commit |
| 11372 | * |
| 11373 | * Validate that the given atomic state is programmable by DC into hardware. |
| 11374 | * This involves constructing a &struct dc_state reflecting the new hardware |
| 11375 | * state we wish to commit, then querying DC to see if it is programmable. It's |
| 11376 | * important not to modify the existing DC state. Otherwise, atomic_check |
| 11377 | * may unexpectedly commit hardware changes. |
| 11378 | * |
| 11379 | * When validating the DC state, it's important that the right locks are |
| 11380 | * acquired. For full updates case which removes/adds/updates streams on one |
| 11381 | * CRTC while flipping on another CRTC, acquiring global lock will guarantee |
| 11382 | * that any such full update commit will wait for completion of any outstanding |
Nicholas Kazlauskas | f6d7c7f | 2020-07-28 11:08:02 -0400 | [diff] [blame] | 11383 | * flip using DRMs synchronization events. |
Leo Li | b8592b4 | 2018-09-14 11:20:08 -0400 | [diff] [blame] | 11384 | * |
| 11385 | * Note that DM adds the affected connectors for all CRTCs in state, when that |
| 11386 | * might not seem necessary. This is because DC stream creation requires the |
| 11387 | * DC sink, which is tied to the DRM connector state. Cleaning this up should |
| 11388 | * be possible but non-trivial - a possible TODO item. |
| 11389 | * |
| 11390 | * Return: -Error code if validation failed. |
| 11391 | */ |
Alex Deucher | 7578ecd | 2017-10-10 17:51:02 -0400 | [diff] [blame] | 11392 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
| 11393 | struct drm_atomic_state *state) |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11394 | { |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 11395 | struct amdgpu_device *adev = drm_to_adev(dev); |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 11396 | struct dm_atomic_state *dm_state = NULL; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11397 | struct dc *dc = adev->dm.dc; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11398 | struct drm_connector *connector; |
Leo (Sunpeng) Li | c2cea70 | 2017-10-12 17:15:08 -0400 | [diff] [blame] | 11399 | struct drm_connector_state *old_con_state, *new_con_state; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11400 | struct drm_crtc *crtc; |
Shirish S | fc9e992 | 2017-09-27 15:15:38 +0530 | [diff] [blame] | 11401 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11402 | struct drm_plane *plane; |
Aurabindo Pillai | 2ffa97c | 2024-06-10 18:22:59 +0000 | [diff] [blame] | 11403 | struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; |
Rodrigo Siqueira | 74a1667 | 2020-05-26 16:53:38 -0400 | [diff] [blame] | 11404 | enum dc_status status; |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11405 | int ret, i; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11406 | bool lock_and_validation_needed = false; |
Bhawanpreet Lakha | 35f3308 | 2023-01-17 14:35:41 -0500 | [diff] [blame] | 11407 | bool is_top_most_overlay = true; |
Mikita Lipski | 214993e | 2021-12-15 11:01:45 -0500 | [diff] [blame] | 11408 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
Dave Airlie | cdf657f | 2023-01-27 12:15:13 +1000 | [diff] [blame] | 11409 | struct drm_dp_mst_topology_mgr *mgr; |
| 11410 | struct drm_dp_mst_topology_state *mst_state; |
Alex Hung | f95bcb0 | 2024-04-15 19:02:56 -0600 | [diff] [blame] | 11411 | struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11412 | |
Rodrigo Siqueira | e8a9823 | 2020-09-04 14:37:53 -0400 | [diff] [blame] | 11413 | trace_amdgpu_dm_atomic_check_begin(state); |
Eryk Brol | c44a22b | 2020-08-27 17:13:57 -0400 | [diff] [blame] | 11414 | |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11415 | ret = drm_atomic_helper_check_modeset(dev, state); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11416 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11417 | drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n"); |
Michel Dänzer | 01e28f9 | 2017-11-09 18:38:09 +0100 | [diff] [blame] | 11418 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11419 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11420 | |
Stylon Wang | c5892a1 | 2020-06-30 17:55:29 +0800 | [diff] [blame] | 11421 | /* Check connector changes */ |
| 11422 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
| 11423 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
| 11424 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
| 11425 | |
| 11426 | /* Skip connectors that are disabled or part of modeset already. */ |
Stylon Wang | c5892a1 | 2020-06-30 17:55:29 +0800 | [diff] [blame] | 11427 | if (!new_con_state->crtc) |
| 11428 | continue; |
| 11429 | |
| 11430 | new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); |
| 11431 | if (IS_ERR(new_crtc_state)) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11432 | drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n"); |
Stylon Wang | c5892a1 | 2020-06-30 17:55:29 +0800 | [diff] [blame] | 11433 | ret = PTR_ERR(new_crtc_state); |
| 11434 | goto fail; |
| 11435 | } |
| 11436 | |
hongao | 3c6d1ae | 2022-11-22 19:20:34 +0800 | [diff] [blame] | 11437 | if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || |
| 11438 | dm_old_con_state->scaling != dm_new_con_state->scaling) |
Stylon Wang | c5892a1 | 2020-06-30 17:55:29 +0800 | [diff] [blame] | 11439 | new_crtc_state->connectors_changed = true; |
| 11440 | } |
| 11441 | |
Eryk Brol | 349a19b | 2021-02-09 17:09:52 -0500 | [diff] [blame] | 11442 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11443 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
| 11444 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { |
| 11445 | ret = add_affected_mst_dsc_crtcs(state, crtc); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11446 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11447 | drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n"); |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11448 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11449 | } |
Mikita Lipski | 44be939 | 2019-11-12 09:14:15 -0500 | [diff] [blame] | 11450 | } |
| 11451 | } |
| 11452 | } |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11453 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
Eryk Brol | 886876e | 2020-10-15 13:07:09 -0400 | [diff] [blame] | 11454 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
| 11455 | |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11456 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 11457 | !new_crtc_state->color_mgmt_changed && |
Eryk Brol | 886876e | 2020-10-15 13:07:09 -0400 | [diff] [blame] | 11458 | old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && |
| 11459 | dm_old_crtc_state->dsc_force_changed == false) |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11460 | continue; |
Shirish S | 7bef1af | 2017-10-27 03:25:55 +0000 | [diff] [blame] | 11461 | |
Mark Yacoub | 03fc4cf | 2021-06-04 13:01:07 -0400 | [diff] [blame] | 11462 | ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11463 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11464 | drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n"); |
Mark Yacoub | 03fc4cf | 2021-06-04 13:01:07 -0400 | [diff] [blame] | 11465 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11466 | } |
Mark Yacoub | 03fc4cf | 2021-06-04 13:01:07 -0400 | [diff] [blame] | 11467 | |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11468 | if (!new_crtc_state->enable) |
| 11469 | continue; |
Shirish S | fc9e992 | 2017-09-27 15:15:38 +0530 | [diff] [blame] | 11470 | |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11471 | ret = drm_atomic_add_affected_connectors(state, crtc); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11472 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11473 | drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n"); |
Shirish S | 706bc8c | 2021-11-08 19:21:46 +0530 | [diff] [blame] | 11474 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11475 | } |
Shirish S | fc9e992 | 2017-09-27 15:15:38 +0530 | [diff] [blame] | 11476 | |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11477 | ret = drm_atomic_add_affected_planes(state, crtc); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11478 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11479 | drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n"); |
Shirish S | 1e88ad0 | 2017-12-01 01:27:04 -0500 | [diff] [blame] | 11480 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11481 | } |
Eryk Brol | 115a385 | 2020-11-19 16:48:57 -0500 | [diff] [blame] | 11482 | |
Eryk Brol | cbac53f | 2020-12-08 12:52:36 -0500 | [diff] [blame] | 11483 | if (dm_old_crtc_state->dsc_force_changed) |
Eryk Brol | 115a385 | 2020-11-19 16:48:57 -0500 | [diff] [blame] | 11484 | new_crtc_state->mode_changed = true; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11485 | } |
| 11486 | |
Nicholas Kazlauskas | 2d9e643 | 2019-01-18 13:17:55 -0500 | [diff] [blame] | 11487 | /* |
| 11488 | * Add all primary and overlay planes on the CRTC to the state |
| 11489 | * whenever a plane is enabled to maintain correct z-ordering |
| 11490 | * and to enable fast surface updates. |
| 11491 | */ |
| 11492 | drm_for_each_crtc(crtc, dev) { |
| 11493 | bool modified = false; |
| 11494 | |
| 11495 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
| 11496 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
| 11497 | continue; |
| 11498 | |
| 11499 | if (new_plane_state->crtc == crtc || |
| 11500 | old_plane_state->crtc == crtc) { |
| 11501 | modified = true; |
| 11502 | break; |
| 11503 | } |
| 11504 | } |
| 11505 | |
| 11506 | if (!modified) |
| 11507 | continue; |
| 11508 | |
| 11509 | drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { |
| 11510 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
| 11511 | continue; |
| 11512 | |
| 11513 | new_plane_state = |
| 11514 | drm_atomic_get_plane_state(state, plane); |
| 11515 | |
| 11516 | if (IS_ERR(new_plane_state)) { |
| 11517 | ret = PTR_ERR(new_plane_state); |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11518 | drm_dbg_atomic(dev, "new_plane_state is BAD\n"); |
Nicholas Kazlauskas | 2d9e643 | 2019-01-18 13:17:55 -0500 | [diff] [blame] | 11519 | goto fail; |
| 11520 | } |
| 11521 | } |
| 11522 | } |
| 11523 | |
Leo Li | 22c42b0 | 2022-08-30 16:38:16 -0400 | [diff] [blame] | 11524 | /* |
| 11525 | * DC consults the zpos (layer_index in DC terminology) to determine the |
| 11526 | * hw plane on which to enable the hw cursor (see |
| 11527 | * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in |
| 11528 | * atomic state, so call drm helper to normalize zpos. |
| 11529 | */ |
Leo Li | ac0bb08 | 2023-02-09 12:15:21 -0500 | [diff] [blame] | 11530 | ret = drm_atomic_normalize_zpos(dev, state); |
| 11531 | if (ret) { |
| 11532 | drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); |
| 11533 | goto fail; |
| 11534 | } |
Leo Li | 22c42b0 | 2022-08-30 16:38:16 -0400 | [diff] [blame] | 11535 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11536 | /* |
| 11537 | * Determine whether cursors on each CRTC should be enabled in native or |
| 11538 | * overlay mode. |
| 11539 | */ |
| 11540 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
| 11541 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 11542 | |
| 11543 | ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, |
| 11544 | &dm_new_crtc_state->cursor_mode); |
| 11545 | if (ret) { |
| 11546 | drm_dbg(dev, "Failed to determine cursor mode\n"); |
| 11547 | goto fail; |
| 11548 | } |
Leo Li | 0c8c5bd | 2024-09-11 09:06:50 -0400 | [diff] [blame] | 11549 | |
| 11550 | /* |
| 11551 | * If overlay cursor is needed, DC cannot go through the |
| 11552 | * native cursor update path. All enabled planes on the CRTC |
| 11553 | * need to be added for DC to not disable a plane by mistake |
| 11554 | */ |
| 11555 | if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { |
| 11556 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 11557 | if (ret) |
| 11558 | goto fail; |
| 11559 | } |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11560 | } |
| 11561 | |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11562 | /* Remove exiting planes if they are modified */ |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 11563 | for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { |
Hamza Mahfooz | a7c0cad | 2023-08-04 11:13:04 -0400 | [diff] [blame] | 11564 | if (old_plane_state->fb && new_plane_state->fb && |
| 11565 | get_mem_type(old_plane_state->fb) != |
| 11566 | get_mem_type(new_plane_state->fb)) |
| 11567 | lock_and_validation_needed = true; |
| 11568 | |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11569 | ret = dm_update_plane_state(dc, state, plane, |
| 11570 | old_plane_state, |
| 11571 | new_plane_state, |
| 11572 | false, |
Bhawanpreet Lakha | 35f3308 | 2023-01-17 14:35:41 -0500 | [diff] [blame] | 11573 | &lock_and_validation_needed, |
| 11574 | &is_top_most_overlay); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11575 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11576 | drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11577 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11578 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11579 | } |
| 11580 | |
| 11581 | /* Disable all crtcs which require disable */ |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 11582 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
| 11583 | ret = dm_update_crtc_state(&adev->dm, state, crtc, |
| 11584 | old_crtc_state, |
| 11585 | new_crtc_state, |
| 11586 | false, |
| 11587 | &lock_and_validation_needed); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11588 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11589 | drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n"); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 11590 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11591 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11592 | } |
| 11593 | |
| 11594 | /* Enable all crtcs which require enable */ |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 11595 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
| 11596 | ret = dm_update_crtc_state(&adev->dm, state, crtc, |
| 11597 | old_crtc_state, |
| 11598 | new_crtc_state, |
| 11599 | true, |
| 11600 | &lock_and_validation_needed); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11601 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11602 | drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n"); |
Leo Li | 4b9674e | 2018-11-11 11:35:13 -0500 | [diff] [blame] | 11603 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11604 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11605 | } |
| 11606 | |
| 11607 | /* Add new/modified planes */ |
Leo Li | 38e0c3df | 2024-02-26 16:56:49 -0500 | [diff] [blame] | 11608 | for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11609 | ret = dm_update_plane_state(dc, state, plane, |
| 11610 | old_plane_state, |
| 11611 | new_plane_state, |
| 11612 | true, |
Bhawanpreet Lakha | 35f3308 | 2023-01-17 14:35:41 -0500 | [diff] [blame] | 11613 | &lock_and_validation_needed, |
| 11614 | &is_top_most_overlay); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11615 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11616 | drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); |
Leo Li | 9e86906 | 2018-11-11 11:11:52 -0500 | [diff] [blame] | 11617 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11618 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11619 | } |
| 11620 | |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 11621 | #if defined(CONFIG_DRM_AMD_DC_FP) |
Fangzhi Zuo | 876fcc4 | 2022-08-30 12:12:53 -0400 | [diff] [blame] | 11622 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
Lyude Paul | 7cce4cd6 | 2022-11-14 17:17:52 -0500 | [diff] [blame] | 11623 | ret = pre_validate_dsc(state, &dm_state, vars); |
| 11624 | if (ret != 0) |
Fangzhi Zuo | 876fcc4 | 2022-08-30 12:12:53 -0400 | [diff] [blame] | 11625 | goto fail; |
Fangzhi Zuo | 876fcc4 | 2022-08-30 12:12:53 -0400 | [diff] [blame] | 11626 | } |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 11627 | #endif |
Fangzhi Zuo | 876fcc4 | 2022-08-30 12:12:53 -0400 | [diff] [blame] | 11628 | |
Ernst Sjöstrand | b349f76 | 2017-11-07 21:06:57 +0100 | [diff] [blame] | 11629 | /* Run this here since we want to validate the streams we created */ |
| 11630 | ret = drm_atomic_helper_check_planes(dev, state); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11631 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11632 | drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n"); |
Ernst Sjöstrand | b349f76 | 2017-11-07 21:06:57 +0100 | [diff] [blame] | 11633 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11634 | } |
Andrey Grodzovsky | 62f5553 | 2017-08-18 10:52:20 -0400 | [diff] [blame] | 11635 | |
Mikita Lipski | 214993e | 2021-12-15 11:01:45 -0500 | [diff] [blame] | 11636 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
| 11637 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 11638 | if (dm_new_crtc_state->mpo_requested) |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11639 | drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); |
Mikita Lipski | 214993e | 2021-12-15 11:01:45 -0500 | [diff] [blame] | 11640 | } |
| 11641 | |
Aurabindo Pillai | 2ffa97c | 2024-06-10 18:22:59 +0000 | [diff] [blame] | 11642 | /* Check cursor restrictions */ |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11643 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11644 | enum amdgpu_dm_cursor_mode required_cursor_mode; |
Aurabindo Pillai | 2ffa97c | 2024-06-10 18:22:59 +0000 | [diff] [blame] | 11645 | int is_rotated, is_scaled; |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11646 | |
| 11647 | /* Overlay cusor not subject to native cursor restrictions */ |
| 11648 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
| 11649 | if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) |
| 11650 | continue; |
| 11651 | |
Aurabindo Pillai | 2ffa97c | 2024-06-10 18:22:59 +0000 | [diff] [blame] | 11652 | /* Check if rotation or scaling is enabled on DCN401 */ |
| 11653 | if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && |
| 11654 | amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { |
| 11655 | new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); |
| 11656 | |
| 11657 | is_rotated = new_cursor_state && |
| 11658 | ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); |
| 11659 | is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || |
| 11660 | (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); |
| 11661 | |
| 11662 | if (is_rotated || is_scaled) { |
| 11663 | drm_dbg_driver( |
| 11664 | crtc->dev, |
| 11665 | "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", |
| 11666 | crtc->base.id, crtc->name); |
| 11667 | ret = -EINVAL; |
| 11668 | goto fail; |
| 11669 | } |
| 11670 | } |
| 11671 | |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11672 | /* If HW can only do native cursor, check restrictions again */ |
| 11673 | ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, |
| 11674 | &required_cursor_mode); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11675 | if (ret) { |
Leo Li | 1b04dcc | 2024-01-18 16:29:49 -0500 | [diff] [blame] | 11676 | drm_dbg_driver(crtc->dev, |
| 11677 | "[CRTC:%d:%s] Checking cursor mode failed\n", |
| 11678 | crtc->base.id, crtc->name); |
| 11679 | goto fail; |
| 11680 | } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { |
| 11681 | drm_dbg_driver(crtc->dev, |
| 11682 | "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n", |
| 11683 | crtc->base.id, crtc->name); |
| 11684 | ret = -EINVAL; |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11685 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11686 | } |
Simon Ser | 12f4849 | 2020-11-20 20:18:59 +0000 | [diff] [blame] | 11687 | } |
| 11688 | |
Nicholas Kazlauskas | 43d10d3 | 2019-07-31 09:45:16 -0400 | [diff] [blame] | 11689 | if (state->legacy_cursor_update) { |
| 11690 | /* |
| 11691 | * This is a fast cursor update coming from the plane update |
| 11692 | * helper, check if it can be done asynchronously for better |
| 11693 | * performance. |
| 11694 | */ |
| 11695 | state->async_update = |
| 11696 | !drm_atomic_helper_async_check(dev, state); |
| 11697 | |
| 11698 | /* |
| 11699 | * Skip the remaining global validation if this is an async |
| 11700 | * update. Cursor updates can be done without affecting |
| 11701 | * state or bandwidth calcs and this avoids the performance |
| 11702 | * penalty of locking the private state object and |
| 11703 | * allocating a new dc_state. |
| 11704 | */ |
| 11705 | if (state->async_update) |
| 11706 | return 0; |
| 11707 | } |
| 11708 | |
Leo (Sunpeng) Li | ebdd27e | 2017-10-12 17:15:10 -0400 | [diff] [blame] | 11709 | /* Check scaling and underscan changes*/ |
David Francis | 1f6010a | 2018-08-15 14:38:30 -0400 | [diff] [blame] | 11710 | /* TODO Removed scaling changes validation due to inability to commit |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11711 | * new stream into context w\o causing full reset. Need to |
| 11712 | * decide how to handle. |
| 11713 | */ |
Leo (Sunpeng) Li | c2cea70 | 2017-10-12 17:15:08 -0400 | [diff] [blame] | 11714 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 11715 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
| 11716 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
| 11717 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11718 | |
| 11719 | /* Skip any modesets/resets */ |
Leo (Sunpeng) Li | 0bc9706 | 2017-10-12 17:15:07 -0400 | [diff] [blame] | 11720 | if (!acrtc || drm_atomic_crtc_needs_modeset( |
| 11721 | drm_atomic_get_new_crtc_state(state, &acrtc->base))) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11722 | continue; |
| 11723 | |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 11724 | /* Skip any thing not scale or underscan changes */ |
Leo (Sunpeng) Li | 54d7657 | 2017-10-12 17:15:09 -0400 | [diff] [blame] | 11725 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11726 | continue; |
| 11727 | |
| 11728 | lock_and_validation_needed = true; |
| 11729 | } |
| 11730 | |
Lyude Paul | c689e1e | 2022-11-23 14:50:16 -0500 | [diff] [blame] | 11731 | /* set the slot info for each mst_state based on the link encoding format */ |
| 11732 | for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { |
| 11733 | struct amdgpu_dm_connector *aconnector; |
| 11734 | struct drm_connector *connector; |
| 11735 | struct drm_connector_list_iter iter; |
| 11736 | u8 link_coding_cap; |
| 11737 | |
| 11738 | drm_connector_list_iter_begin(dev, &iter); |
| 11739 | drm_for_each_connector_iter(connector, &iter) { |
| 11740 | if (connector->index == mst_state->mgr->conn_base_id) { |
| 11741 | aconnector = to_amdgpu_dm_connector(connector); |
| 11742 | link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); |
| 11743 | drm_dp_mst_update_slots(mst_state, link_coding_cap); |
| 11744 | |
| 11745 | break; |
| 11746 | } |
| 11747 | } |
| 11748 | drm_connector_list_iter_end(&iter); |
| 11749 | } |
Lyude Paul | c689e1e | 2022-11-23 14:50:16 -0500 | [diff] [blame] | 11750 | |
Nicholas Kazlauskas | f6d7c7f | 2020-07-28 11:08:02 -0400 | [diff] [blame] | 11751 | /** |
| 11752 | * Streams and planes are reset when there are changes that affect |
| 11753 | * bandwidth. Anything that affects bandwidth needs to go through |
| 11754 | * DC global validation to ensure that the configuration can be applied |
| 11755 | * to hardware. |
| 11756 | * |
| 11757 | * We have to currently stall out here in atomic_check for outstanding |
| 11758 | * commits to finish in this case because our IRQ handlers reference |
| 11759 | * DRM state directly - we can end up disabling interrupts too early |
| 11760 | * if we don't. |
| 11761 | * |
| 11762 | * TODO: Remove this stall and drop DM state private objects. |
Bhawanpreet Lakha | a87fa99 | 2018-08-20 13:32:07 -0400 | [diff] [blame] | 11763 | */ |
Nicholas Kazlauskas | f6d7c7f | 2020-07-28 11:08:02 -0400 | [diff] [blame] | 11764 | if (lock_and_validation_needed) { |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 11765 | ret = dm_atomic_get_state(state, &dm_state); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11766 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11767 | drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); |
Nicholas Kazlauskas | eb3dc89 | 2018-11-22 12:34:36 -0500 | [diff] [blame] | 11768 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11769 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11770 | |
| 11771 | ret = do_aquire_global_lock(dev, state); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11772 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11773 | drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n"); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11774 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11775 | } |
Andrey Grodzovsky | 1dc9049 | 2017-07-31 11:29:25 -0400 | [diff] [blame] | 11776 | |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 11777 | #if defined(CONFIG_DRM_AMD_DC_FP) |
Fangzhi Zuo | 1b5b72b | 2024-01-22 13:43:46 -0500 | [diff] [blame] | 11778 | if (dc_resource_is_dsc_encoding_supported(dc)) { |
| 11779 | ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); |
| 11780 | if (ret) { |
Fangzhi Zuo | 3715112 | 2024-08-02 15:03:39 -0400 | [diff] [blame] | 11781 | drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n"); |
Fangzhi Zuo | 1b5b72b | 2024-01-22 13:43:46 -0500 | [diff] [blame] | 11782 | ret = -EINVAL; |
| 11783 | goto fail; |
| 11784 | } |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11785 | } |
Aurabindo Pillai | 00c3911 | 2024-03-20 13:56:16 -0400 | [diff] [blame] | 11786 | #endif |
David Francis | 8c20a1e | 2019-06-19 14:49:19 -0400 | [diff] [blame] | 11787 | |
Hersen Wu | 6513104b | 2021-08-25 16:27:47 -0400 | [diff] [blame] | 11788 | ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11789 | if (ret) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11790 | drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 11791 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11792 | } |
Mikita Lipski | 29b9ba7 | 2019-11-12 14:52:14 -0500 | [diff] [blame] | 11793 | |
Zhan Liu | ded58c7 | 2020-01-28 16:38:53 -0500 | [diff] [blame] | 11794 | /* |
| 11795 | * Perform validation of MST topology in the state: |
| 11796 | * We need to perform MST atomic check before calling |
| 11797 | * dc_validate_global_state(), or there is a chance |
| 11798 | * to get stuck in an infinite loop and hang eventually. |
| 11799 | */ |
| 11800 | ret = drm_dp_mst_atomic_check(state); |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11801 | if (ret) { |
Fangzhi Zuo | 3715112 | 2024-08-02 15:03:39 -0400 | [diff] [blame] | 11802 | drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); |
Zhan Liu | ded58c7 | 2020-01-28 16:38:53 -0500 | [diff] [blame] | 11803 | goto fail; |
Shirish S | 68ca1c3 | 2021-11-09 10:41:26 +0530 | [diff] [blame] | 11804 | } |
Ivan Lipski | c2ab9ce | 2024-01-05 19:40:50 -0500 | [diff] [blame] | 11805 | status = dc_validate_global_state(dc, dm_state->context, true); |
Rodrigo Siqueira | 74a1667 | 2020-05-26 16:53:38 -0400 | [diff] [blame] | 11806 | if (status != DC_OK) { |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11807 | drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", |
Rodrigo Siqueira | 74a1667 | 2020-05-26 16:53:38 -0400 | [diff] [blame] | 11808 | dc_status_to_str(status), status); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11809 | ret = -EINVAL; |
| 11810 | goto fail; |
| 11811 | } |
Nicholas Kazlauskas | bd200d1 | 2019-07-31 10:33:54 -0400 | [diff] [blame] | 11812 | } else { |
Nicholas Kazlauskas | 674e78a | 2018-12-05 14:59:07 -0500 | [diff] [blame] | 11813 | /* |
Nicholas Kazlauskas | bd200d1 | 2019-07-31 10:33:54 -0400 | [diff] [blame] | 11814 | * The commit is a fast update. Fast updates shouldn't change |
| 11815 | * the DC context, affect global validation, and can have their |
| 11816 | * commit work done in parallel with other commits not touching |
| 11817 | * the same resource. If we have a new DC context as part of |
| 11818 | * the DM atomic state from validation we need to free it and |
| 11819 | * retain the existing one instead. |
Mazin Rezk | fde9f39 | 2020-07-27 05:40:46 +0000 | [diff] [blame] | 11820 | * |
| 11821 | * Furthermore, since the DM atomic state only contains the DC |
| 11822 | * context and can safely be annulled, we can free the state |
| 11823 | * and clear the associated private object now to free |
| 11824 | * some memory and avoid a possible use-after-free later. |
Nicholas Kazlauskas | 674e78a | 2018-12-05 14:59:07 -0500 | [diff] [blame] | 11825 | */ |
Nicholas Kazlauskas | bd200d1 | 2019-07-31 10:33:54 -0400 | [diff] [blame] | 11826 | |
Mazin Rezk | fde9f39 | 2020-07-27 05:40:46 +0000 | [diff] [blame] | 11827 | for (i = 0; i < state->num_private_objs; i++) { |
| 11828 | struct drm_private_obj *obj = state->private_objs[i].ptr; |
Nicholas Kazlauskas | bd200d1 | 2019-07-31 10:33:54 -0400 | [diff] [blame] | 11829 | |
Mazin Rezk | fde9f39 | 2020-07-27 05:40:46 +0000 | [diff] [blame] | 11830 | if (obj->funcs == adev->dm.atomic_obj.funcs) { |
| 11831 | int j = state->num_private_objs-1; |
Nicholas Kazlauskas | bd200d1 | 2019-07-31 10:33:54 -0400 | [diff] [blame] | 11832 | |
Mazin Rezk | fde9f39 | 2020-07-27 05:40:46 +0000 | [diff] [blame] | 11833 | dm_atomic_destroy_state(obj, |
| 11834 | state->private_objs[i].state); |
Nicholas Kazlauskas | bd200d1 | 2019-07-31 10:33:54 -0400 | [diff] [blame] | 11835 | |
Mazin Rezk | fde9f39 | 2020-07-27 05:40:46 +0000 | [diff] [blame] | 11836 | /* If i is not at the end of the array then the |
| 11837 | * last element needs to be moved to where i was |
| 11838 | * before the array can safely be truncated. |
| 11839 | */ |
| 11840 | if (i != j) |
| 11841 | state->private_objs[i] = |
| 11842 | state->private_objs[j]; |
| 11843 | |
| 11844 | state->private_objs[j].ptr = NULL; |
| 11845 | state->private_objs[j].state = NULL; |
| 11846 | state->private_objs[j].old_state = NULL; |
| 11847 | state->private_objs[j].new_state = NULL; |
| 11848 | |
| 11849 | state->num_private_objs = j; |
| 11850 | break; |
| 11851 | } |
Nicholas Kazlauskas | bd200d1 | 2019-07-31 10:33:54 -0400 | [diff] [blame] | 11852 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11853 | } |
| 11854 | |
Nicholas Kazlauskas | caff0e6 | 2019-08-02 10:45:11 -0400 | [diff] [blame] | 11855 | /* Store the overall update type for use later in atomic check. */ |
Srinivasan Shanmugam | c82eddf | 2023-06-17 21:09:46 +0530 | [diff] [blame] | 11856 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
Nicholas Kazlauskas | caff0e6 | 2019-08-02 10:45:11 -0400 | [diff] [blame] | 11857 | struct dm_crtc_state *dm_new_crtc_state = |
| 11858 | to_dm_crtc_state(new_crtc_state); |
| 11859 | |
Hamza Mahfooz | a7c0cad | 2023-08-04 11:13:04 -0400 | [diff] [blame] | 11860 | /* |
| 11861 | * Only allow async flips for fast updates that don't change |
| 11862 | * the FB pitch, the DCC state, rotation, etc. |
| 11863 | */ |
| 11864 | if (new_crtc_state->async_flip && lock_and_validation_needed) { |
| 11865 | drm_dbg_atomic(crtc->dev, |
| 11866 | "[CRTC:%d:%s] async flips are only supported for fast updates\n", |
| 11867 | crtc->base.id, crtc->name); |
| 11868 | ret = -EINVAL; |
| 11869 | goto fail; |
| 11870 | } |
| 11871 | |
Nicholas Kazlauskas | f6d7c7f | 2020-07-28 11:08:02 -0400 | [diff] [blame] | 11872 | dm_new_crtc_state->update_type = lock_and_validation_needed ? |
Hamza Mahfooz | a7c0cad | 2023-08-04 11:13:04 -0400 | [diff] [blame] | 11873 | UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11874 | } |
| 11875 | |
| 11876 | /* Must be success */ |
| 11877 | WARN_ON(ret); |
Rodrigo Siqueira | e8a9823 | 2020-09-04 14:37:53 -0400 | [diff] [blame] | 11878 | |
| 11879 | trace_amdgpu_dm_atomic_check_finish(state, ret); |
| 11880 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11881 | return ret; |
| 11882 | |
| 11883 | fail: |
| 11884 | if (ret == -EDEADLK) |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11885 | drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11886 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11887 | drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11888 | else |
Tvrtko Ursulin | 730ac57 | 2024-05-28 13:57:11 +0100 | [diff] [blame] | 11889 | drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11890 | |
Rodrigo Siqueira | e8a9823 | 2020-09-04 14:37:53 -0400 | [diff] [blame] | 11891 | trace_amdgpu_dm_atomic_check_finish(state, ret); |
| 11892 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 11893 | return ret; |
| 11894 | } |
| 11895 | |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11896 | static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, |
| 11897 | unsigned int offset, |
| 11898 | unsigned int total_length, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 11899 | u8 *data, |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11900 | unsigned int length, |
| 11901 | struct amdgpu_hdmi_vsdb_info *vsdb) |
| 11902 | { |
| 11903 | bool res; |
| 11904 | union dmub_rb_cmd cmd; |
| 11905 | struct dmub_cmd_send_edid_cea *input; |
| 11906 | struct dmub_cmd_edid_cea_output *output; |
| 11907 | |
| 11908 | if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) |
| 11909 | return false; |
| 11910 | |
| 11911 | memset(&cmd, 0, sizeof(cmd)); |
| 11912 | |
| 11913 | input = &cmd.edid_cea.data.input; |
| 11914 | |
| 11915 | cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; |
| 11916 | cmd.edid_cea.header.sub_type = 0; |
| 11917 | cmd.edid_cea.header.payload_bytes = |
| 11918 | sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); |
| 11919 | input->offset = offset; |
| 11920 | input->length = length; |
Oliver Logush | eb9e59e | 2021-11-24 17:24:05 -0500 | [diff] [blame] | 11921 | input->cea_total_length = total_length; |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11922 | memcpy(input->payload, data, length); |
| 11923 | |
Nicholas Kazlauskas | 8892780 | 2023-12-04 16:35:04 -0500 | [diff] [blame] | 11924 | res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11925 | if (!res) { |
| 11926 | DRM_ERROR("EDID CEA parser failed\n"); |
| 11927 | return false; |
| 11928 | } |
| 11929 | |
| 11930 | output = &cmd.edid_cea.data.output; |
| 11931 | |
| 11932 | if (output->type == DMUB_CMD__EDID_CEA_ACK) { |
| 11933 | if (!output->ack.success) { |
| 11934 | DRM_ERROR("EDID CEA ack failed at offset %d\n", |
| 11935 | output->ack.offset); |
| 11936 | } |
| 11937 | } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { |
| 11938 | if (!output->amd_vsdb.vsdb_found) |
| 11939 | return false; |
| 11940 | |
| 11941 | vsdb->freesync_supported = output->amd_vsdb.freesync_supported; |
| 11942 | vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; |
| 11943 | vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; |
| 11944 | vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; |
| 11945 | } else { |
Guchun Chen | b76a806 | 2021-07-13 13:44:46 +0800 | [diff] [blame] | 11946 | DRM_WARN("Unknown EDID CEA parser results\n"); |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11947 | return false; |
| 11948 | } |
| 11949 | |
| 11950 | return true; |
| 11951 | } |
| 11952 | |
| 11953 | static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 11954 | u8 *edid_ext, int len, |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 11955 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
| 11956 | { |
| 11957 | int i; |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 11958 | |
| 11959 | /* send extension block to DMCU for parsing */ |
| 11960 | for (i = 0; i < len; i += 8) { |
| 11961 | bool res; |
| 11962 | int offset; |
| 11963 | |
| 11964 | /* send 8 bytes a time */ |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11965 | if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 11966 | return false; |
| 11967 | |
| 11968 | if (i+8 == len) { |
| 11969 | /* EDID block sent completed, expect result */ |
| 11970 | int version, min_rate, max_rate; |
| 11971 | |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11972 | res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 11973 | if (res) { |
| 11974 | /* amd vsdb found */ |
| 11975 | vsdb_info->freesync_supported = 1; |
| 11976 | vsdb_info->amd_vsdb_version = version; |
| 11977 | vsdb_info->min_refresh_rate_hz = min_rate; |
| 11978 | vsdb_info->max_refresh_rate_hz = max_rate; |
| 11979 | return true; |
| 11980 | } |
| 11981 | /* not amd vsdb */ |
| 11982 | return false; |
| 11983 | } |
| 11984 | |
| 11985 | /* check for ack*/ |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11986 | res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 11987 | if (!res) |
| 11988 | return false; |
| 11989 | } |
| 11990 | |
| 11991 | return false; |
| 11992 | } |
| 11993 | |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11994 | static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 11995 | u8 *edid_ext, int len, |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 11996 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
| 11997 | { |
| 11998 | int i; |
| 11999 | |
| 12000 | /* send extension block to DMCU for parsing */ |
| 12001 | for (i = 0; i < len; i += 8) { |
| 12002 | /* send 8 bytes a time */ |
| 12003 | if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) |
| 12004 | return false; |
| 12005 | } |
| 12006 | |
| 12007 | return vsdb_info->freesync_supported; |
| 12008 | } |
| 12009 | |
| 12010 | static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 12011 | u8 *edid_ext, int len, |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 12012 | struct amdgpu_hdmi_vsdb_info *vsdb_info) |
| 12013 | { |
| 12014 | struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); |
Stylon Wang | 53f4da7 | 2022-12-21 19:28:16 +0800 | [diff] [blame] | 12015 | bool ret; |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 12016 | |
Stylon Wang | 53f4da7 | 2022-12-21 19:28:16 +0800 | [diff] [blame] | 12017 | mutex_lock(&adev->dm.dc_lock); |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 12018 | if (adev->dm.dmub_srv) |
Stylon Wang | 53f4da7 | 2022-12-21 19:28:16 +0800 | [diff] [blame] | 12019 | ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 12020 | else |
Stylon Wang | 53f4da7 | 2022-12-21 19:28:16 +0800 | [diff] [blame] | 12021 | ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); |
| 12022 | mutex_unlock(&adev->dm.dc_lock); |
| 12023 | return ret; |
Stylon Wang | 46db138 | 2021-05-29 14:19:20 +0800 | [diff] [blame] | 12024 | } |
| 12025 | |
Tom Chung | a638b83 | 2024-06-14 15:38:56 +0800 | [diff] [blame] | 12026 | static void parse_edid_displayid_vrr(struct drm_connector *connector, |
| 12027 | struct edid *edid) |
| 12028 | { |
| 12029 | u8 *edid_ext = NULL; |
| 12030 | int i; |
| 12031 | int j = 0; |
| 12032 | u16 min_vfreq; |
| 12033 | u16 max_vfreq; |
| 12034 | |
| 12035 | if (edid == NULL || edid->extensions == 0) |
| 12036 | return; |
| 12037 | |
| 12038 | /* Find DisplayID extension */ |
| 12039 | for (i = 0; i < edid->extensions; i++) { |
| 12040 | edid_ext = (void *)(edid + (i + 1)); |
| 12041 | if (edid_ext[0] == DISPLAYID_EXT) |
| 12042 | break; |
| 12043 | } |
| 12044 | |
| 12045 | if (edid_ext == NULL) |
| 12046 | return; |
| 12047 | |
| 12048 | while (j < EDID_LENGTH) { |
| 12049 | /* Get dynamic video timing range from DisplayID if available */ |
| 12050 | if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 && |
| 12051 | (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) { |
| 12052 | min_vfreq = edid_ext[j+9]; |
| 12053 | if (edid_ext[j+1] & 7) |
| 12054 | max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8); |
| 12055 | else |
| 12056 | max_vfreq = edid_ext[j+10]; |
| 12057 | |
| 12058 | if (max_vfreq && min_vfreq) { |
| 12059 | connector->display_info.monitor_range.max_vfreq = max_vfreq; |
| 12060 | connector->display_info.monitor_range.min_vfreq = min_vfreq; |
| 12061 | |
| 12062 | return; |
| 12063 | } |
| 12064 | } |
| 12065 | j++; |
| 12066 | } |
| 12067 | } |
| 12068 | |
Bhawanpreet Lakha | ec8e59c | 2023-06-12 14:06:39 -0400 | [diff] [blame] | 12069 | static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
| 12070 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) |
| 12071 | { |
| 12072 | u8 *edid_ext = NULL; |
| 12073 | int i; |
| 12074 | int j = 0; |
| 12075 | |
| 12076 | if (edid == NULL || edid->extensions == 0) |
| 12077 | return -ENODEV; |
| 12078 | |
| 12079 | /* Find DisplayID extension */ |
| 12080 | for (i = 0; i < edid->extensions; i++) { |
| 12081 | edid_ext = (void *)(edid + (i + 1)); |
| 12082 | if (edid_ext[0] == DISPLAYID_EXT) |
| 12083 | break; |
| 12084 | } |
| 12085 | |
Rodrigo Siqueira | 16dd282 | 2024-11-05 08:40:23 -0700 | [diff] [blame] | 12086 | while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) { |
Bhawanpreet Lakha | ec8e59c | 2023-06-12 14:06:39 -0400 | [diff] [blame] | 12087 | struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; |
| 12088 | unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); |
| 12089 | |
| 12090 | if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && |
| 12091 | amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { |
| 12092 | vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; |
| 12093 | vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; |
| 12094 | DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); |
| 12095 | |
| 12096 | return true; |
| 12097 | } |
| 12098 | j++; |
| 12099 | } |
| 12100 | |
| 12101 | return false; |
| 12102 | } |
| 12103 | |
Arnd Bergmann | 7c7dd77 | 2021-02-25 16:01:02 +0100 | [diff] [blame] | 12104 | static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12105 | struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) |
| 12106 | { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 12107 | u8 *edid_ext = NULL; |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12108 | int i; |
| 12109 | bool valid_vsdb_found = false; |
| 12110 | |
| 12111 | /*----- drm_find_cea_extension() -----*/ |
| 12112 | /* No EDID or EDID extensions */ |
| 12113 | if (edid == NULL || edid->extensions == 0) |
Arnd Bergmann | 7c7dd77 | 2021-02-25 16:01:02 +0100 | [diff] [blame] | 12114 | return -ENODEV; |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12115 | |
| 12116 | /* Find CEA extension */ |
| 12117 | for (i = 0; i < edid->extensions; i++) { |
| 12118 | edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); |
| 12119 | if (edid_ext[0] == CEA_EXT) |
| 12120 | break; |
| 12121 | } |
| 12122 | |
| 12123 | if (i == edid->extensions) |
Arnd Bergmann | 7c7dd77 | 2021-02-25 16:01:02 +0100 | [diff] [blame] | 12124 | return -ENODEV; |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12125 | |
| 12126 | /*----- cea_db_offsets() -----*/ |
| 12127 | if (edid_ext[0] != CEA_EXT) |
Arnd Bergmann | 7c7dd77 | 2021-02-25 16:01:02 +0100 | [diff] [blame] | 12128 | return -ENODEV; |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12129 | |
| 12130 | valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); |
Arnd Bergmann | 7c7dd77 | 2021-02-25 16:01:02 +0100 | [diff] [blame] | 12131 | |
| 12132 | return valid_vsdb_found ? i : -ENODEV; |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12133 | } |
| 12134 | |
Rodrigo Siqueira | c620e79 | 2022-02-21 15:22:50 -0500 | [diff] [blame] | 12135 | /** |
| 12136 | * amdgpu_dm_update_freesync_caps - Update Freesync capabilities |
| 12137 | * |
Alex Deucher | 41ee1f1 | 2022-08-30 17:57:52 -0400 | [diff] [blame] | 12138 | * @connector: Connector to query. |
| 12139 | * @edid: EDID from monitor |
Rodrigo Siqueira | c620e79 | 2022-02-21 15:22:50 -0500 | [diff] [blame] | 12140 | * |
| 12141 | * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep |
| 12142 | * track of some of the display information in the internal data struct used by |
| 12143 | * amdgpu_dm. This function checks which type of connector we need to set the |
| 12144 | * FreeSync parameters. |
| 12145 | */ |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 12146 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
Rodrigo Siqueira | c620e79 | 2022-02-21 15:22:50 -0500 | [diff] [blame] | 12147 | struct edid *edid) |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12148 | { |
Souptick Joarder | eb0709b | 2021-02-23 00:55:31 +0530 | [diff] [blame] | 12149 | int i = 0; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12150 | struct detailed_timing *timing; |
| 12151 | struct detailed_non_pixel *data; |
| 12152 | struct detailed_data_monitor_range *range; |
Harry Wentland | c84dec2 | 2017-09-05 14:16:09 -0400 | [diff] [blame] | 12153 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
| 12154 | to_amdgpu_dm_connector(connector); |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 12155 | struct dm_connector_state *dm_con_state = NULL; |
Colin Ian King | 9ad5446 | 2021-08-29 17:46:24 +0100 | [diff] [blame] | 12156 | struct dc_sink *sink; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12157 | |
Srinivasan Shanmugam | 534eee8 | 2023-11-12 09:30:51 +0530 | [diff] [blame] | 12158 | struct amdgpu_device *adev = drm_to_adev(connector->dev); |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12159 | struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; |
Rodrigo Siqueira | c620e79 | 2022-02-21 15:22:50 -0500 | [diff] [blame] | 12160 | bool freesync_capable = false; |
Sung Joon Kim | 5b49da0 | 2023-01-12 10:38:10 -0500 | [diff] [blame] | 12161 | enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; |
Harry Wentland | b830ebc | 2017-07-26 21:03:22 -0400 | [diff] [blame] | 12162 | |
Harry Wentland | 8218d7f | 2017-10-17 12:02:01 -0400 | [diff] [blame] | 12163 | if (!connector->state) { |
| 12164 | DRM_ERROR("%s - Connector has no state", __func__); |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 12165 | goto update; |
Harry Wentland | 8218d7f | 2017-10-17 12:02:01 -0400 | [diff] [blame] | 12166 | } |
| 12167 | |
Aurabindo Pillai | 9b2fdc3 | 2021-08-11 14:38:44 -0400 | [diff] [blame] | 12168 | sink = amdgpu_dm_connector->dc_sink ? |
| 12169 | amdgpu_dm_connector->dc_sink : |
| 12170 | amdgpu_dm_connector->dc_em_sink; |
| 12171 | |
| 12172 | if (!edid || !sink) { |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 12173 | dm_con_state = to_dm_connector_state(connector->state); |
| 12174 | |
| 12175 | amdgpu_dm_connector->min_vfreq = 0; |
| 12176 | amdgpu_dm_connector->max_vfreq = 0; |
Aurabindo Pillai | 9b2fdc3 | 2021-08-11 14:38:44 -0400 | [diff] [blame] | 12177 | connector->display_info.monitor_range.min_vfreq = 0; |
| 12178 | connector->display_info.monitor_range.max_vfreq = 0; |
| 12179 | freesync_capable = false; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 12180 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 12181 | goto update; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 12182 | } |
| 12183 | |
Harry Wentland | 8218d7f | 2017-10-17 12:02:01 -0400 | [diff] [blame] | 12184 | dm_con_state = to_dm_connector_state(connector->state); |
| 12185 | |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12186 | if (!adev->dm.freesync_module) |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 12187 | goto update; |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12188 | |
Tom Chung | a638b83 | 2024-06-14 15:38:56 +0800 | [diff] [blame] | 12189 | /* Some eDP panels only have the refresh rate range info in DisplayID */ |
| 12190 | if ((connector->display_info.monitor_range.min_vfreq == 0 || |
| 12191 | connector->display_info.monitor_range.max_vfreq == 0)) |
| 12192 | parse_edid_displayid_vrr(connector, edid); |
| 12193 | |
Mario Limonciello | 2f14c0c | 2024-03-05 14:34:24 -0600 | [diff] [blame] | 12194 | if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || |
| 12195 | sink->sink_signal == SIGNAL_TYPE_EDP)) { |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12196 | bool edid_check_required = false; |
| 12197 | |
Tom Chung | f91a9af | 2024-07-03 16:47:57 +0800 | [diff] [blame] | 12198 | if (amdgpu_dm_connector->dc_link && |
| 12199 | amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { |
Mario Limonciello | 2f14c0c | 2024-03-05 14:34:24 -0600 | [diff] [blame] | 12200 | if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) { |
Mario Limonciello | 2f14c0c | 2024-03-05 14:34:24 -0600 | [diff] [blame] | 12201 | amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; |
| 12202 | amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; |
Tom Chung | 9023ec5 | 2024-06-19 14:03:55 +0800 | [diff] [blame] | 12203 | if (amdgpu_dm_connector->max_vfreq - |
| 12204 | amdgpu_dm_connector->min_vfreq > 10) |
| 12205 | freesync_capable = true; |
Mario Limonciello | 2f14c0c | 2024-03-05 14:34:24 -0600 | [diff] [blame] | 12206 | } else { |
| 12207 | edid_check_required = edid->version > 1 || |
| 12208 | (edid->version == 1 && |
| 12209 | edid->revision > 1); |
| 12210 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12211 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12212 | |
Mario Limonciello | 2f14c0c | 2024-03-05 14:34:24 -0600 | [diff] [blame] | 12213 | if (edid_check_required) { |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12214 | for (i = 0; i < 4; i++) { |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12215 | |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12216 | timing = &edid->detailed_timings[i]; |
| 12217 | data = &timing->data.other_data; |
| 12218 | range = &data->data.range; |
| 12219 | /* |
| 12220 | * Check if monitor has continuous frequency mode |
| 12221 | */ |
| 12222 | if (data->type != EDID_DETAIL_MONITOR_RANGE) |
| 12223 | continue; |
| 12224 | /* |
| 12225 | * Check for flag range limits only. If flag == 1 then |
| 12226 | * no additional timing information provided. |
| 12227 | * Default GTF, GTF Secondary curve and CVT are not |
| 12228 | * supported |
| 12229 | */ |
| 12230 | if (range->flags != 1) |
| 12231 | continue; |
Stylon Wang | a0ffc3f | 2021-01-05 14:07:51 +0800 | [diff] [blame] | 12232 | |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12233 | connector->display_info.monitor_range.min_vfreq = range->min_vfreq; |
| 12234 | connector->display_info.monitor_range.max_vfreq = range->max_vfreq; |
| 12235 | |
Alex Deucher | 68e05b9 | 2024-02-28 15:59:22 -0500 | [diff] [blame] | 12236 | if (edid->revision >= 4) { |
| 12237 | if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) |
| 12238 | connector->display_info.monitor_range.min_vfreq += 255; |
| 12239 | if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) |
| 12240 | connector->display_info.monitor_range.max_vfreq += 255; |
| 12241 | } |
| 12242 | |
| 12243 | amdgpu_dm_connector->min_vfreq = |
| 12244 | connector->display_info.monitor_range.min_vfreq; |
| 12245 | amdgpu_dm_connector->max_vfreq = |
| 12246 | connector->display_info.monitor_range.max_vfreq; |
Alex Deucher | 68e05b9 | 2024-02-28 15:59:22 -0500 | [diff] [blame] | 12247 | |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12248 | break; |
| 12249 | } |
| 12250 | |
| 12251 | if (amdgpu_dm_connector->max_vfreq - |
| 12252 | amdgpu_dm_connector->min_vfreq > 10) { |
| 12253 | |
| 12254 | freesync_capable = true; |
| 12255 | } |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12256 | } |
Bhawanpreet Lakha | ec8e59c | 2023-06-12 14:06:39 -0400 | [diff] [blame] | 12257 | parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
| 12258 | |
| 12259 | if (vsdb_info.replay_mode) { |
| 12260 | amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; |
| 12261 | amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; |
| 12262 | amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; |
| 12263 | } |
| 12264 | |
Aurabindo Pillai | 9b2fdc3 | 2021-08-11 14:38:44 -0400 | [diff] [blame] | 12265 | } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
Arnd Bergmann | 7c7dd77 | 2021-02-25 16:01:02 +0100 | [diff] [blame] | 12266 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
| 12267 | if (i >= 0 && vsdb_info.freesync_supported) { |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12268 | timing = &edid->detailed_timings[i]; |
| 12269 | data = &timing->data.other_data; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12270 | |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12271 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; |
| 12272 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
| 12273 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) |
| 12274 | freesync_capable = true; |
Anthony Koo | 98e6436 | 2018-08-21 14:40:28 -0500 | [diff] [blame] | 12275 | |
Stylon Wang | f9b4f20 | 2020-12-04 12:08:31 +0800 | [diff] [blame] | 12276 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; |
| 12277 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12278 | } |
| 12279 | } |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 12280 | |
Alex Hung | 722e96c | 2024-07-15 10:24:58 -0600 | [diff] [blame] | 12281 | if (amdgpu_dm_connector->dc_link) |
| 12282 | as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); |
Sung Joon Kim | 5b49da0 | 2023-01-12 10:38:10 -0500 | [diff] [blame] | 12283 | |
| 12284 | if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { |
| 12285 | i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); |
| 12286 | if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { |
| 12287 | |
| 12288 | amdgpu_dm_connector->pack_sdp_v1_3 = true; |
| 12289 | amdgpu_dm_connector->as_type = as_type; |
| 12290 | amdgpu_dm_connector->vsdb_info = vsdb_info; |
| 12291 | |
| 12292 | amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; |
| 12293 | amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; |
| 12294 | if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) |
| 12295 | freesync_capable = true; |
| 12296 | |
| 12297 | connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; |
| 12298 | connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; |
| 12299 | } |
| 12300 | } |
| 12301 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 12302 | update: |
| 12303 | if (dm_con_state) |
| 12304 | dm_con_state->freesync_capable = freesync_capable; |
| 12305 | |
Tom Chung | b684176 | 2024-06-26 16:14:24 +0800 | [diff] [blame] | 12306 | if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable && |
| 12307 | amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) { |
| 12308 | amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false; |
| 12309 | amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false; |
| 12310 | } |
| 12311 | |
Nicholas Kazlauskas | bb47de7 | 2018-10-04 13:03:30 -0400 | [diff] [blame] | 12312 | if (connector->vrr_capable_property) |
| 12313 | drm_connector_set_vrr_capable_property(connector, |
| 12314 | freesync_capable); |
Harry Wentland | e7b07ce | 2017-08-10 13:29:07 -0400 | [diff] [blame] | 12315 | } |
| 12316 | |
Victor Lu | 3d4e52d | 2020-07-21 12:08:34 -0400 | [diff] [blame] | 12317 | void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) |
| 12318 | { |
Luben Tuikov | 1348969 | 2020-08-24 12:27:47 -0400 | [diff] [blame] | 12319 | struct amdgpu_device *adev = drm_to_adev(dev); |
Victor Lu | 3d4e52d | 2020-07-21 12:08:34 -0400 | [diff] [blame] | 12320 | struct dc *dc = adev->dm.dc; |
| 12321 | int i; |
| 12322 | |
| 12323 | mutex_lock(&adev->dm.dc_lock); |
| 12324 | if (dc->current_state) { |
| 12325 | for (i = 0; i < dc->current_state->stream_count; ++i) |
| 12326 | dc->current_state->streams[i] |
| 12327 | ->triggered_crtc_reset.enabled = |
| 12328 | adev->dm.force_timing_sync; |
| 12329 | |
| 12330 | dm_enable_per_frame_crtc_master_sync(dc->current_state); |
| 12331 | dc_trigger_sync(dc, dc->current_state); |
| 12332 | } |
| 12333 | mutex_unlock(&adev->dm.dc_lock); |
| 12334 | } |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12335 | |
Hamza Mahfooz | 0259324 | 2024-06-03 10:16:45 -0400 | [diff] [blame] | 12336 | static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) |
| 12337 | { |
| 12338 | if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) |
| 12339 | dc_exit_ips_for_hw_access(dc); |
| 12340 | } |
| 12341 | |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12342 | void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 12343 | u32 value, const char *func_name) |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12344 | { |
| 12345 | #ifdef DM_CHECK_ADDR_0 |
| 12346 | if (address == 0) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 12347 | drm_err(adev_to_drm(ctx->driver_context), |
| 12348 | "invalid register write. address = 0"); |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12349 | return; |
| 12350 | } |
| 12351 | #endif |
Hamza Mahfooz | 0259324 | 2024-06-03 10:16:45 -0400 | [diff] [blame] | 12352 | |
| 12353 | amdgpu_dm_exit_ips_for_hw_access(ctx->dc); |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12354 | cgs_write_register(ctx->cgs_device, address, value); |
| 12355 | trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); |
| 12356 | } |
| 12357 | |
| 12358 | uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, |
| 12359 | const char *func_name) |
| 12360 | { |
Srinivasan Shanmugam | ae67558 | 2022-12-19 17:20:39 +0530 | [diff] [blame] | 12361 | u32 value; |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12362 | #ifdef DM_CHECK_ADDR_0 |
| 12363 | if (address == 0) { |
Hamza Mahfooz | 5d72e24 | 2023-09-20 13:38:11 -0400 | [diff] [blame] | 12364 | drm_err(adev_to_drm(ctx->driver_context), |
| 12365 | "invalid register read; address = 0\n"); |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12366 | return 0; |
| 12367 | } |
| 12368 | #endif |
| 12369 | |
| 12370 | if (ctx->dmub_srv && |
| 12371 | ctx->dmub_srv->reg_helper_offload.gather_in_progress && |
| 12372 | !ctx->dmub_srv->reg_helper_offload.should_burst_write) { |
| 12373 | ASSERT(false); |
| 12374 | return 0; |
| 12375 | } |
| 12376 | |
Hamza Mahfooz | 0259324 | 2024-06-03 10:16:45 -0400 | [diff] [blame] | 12377 | amdgpu_dm_exit_ips_for_hw_access(ctx->dc); |
| 12378 | |
Rodrigo Siqueira | 9d83722 | 2020-09-15 12:33:43 -0400 | [diff] [blame] | 12379 | value = cgs_read_register(ctx->cgs_device, address); |
| 12380 | |
| 12381 | trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); |
| 12382 | |
| 12383 | return value; |
| 12384 | } |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 12385 | |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12386 | int amdgpu_dm_process_dmub_aux_transfer_sync( |
| 12387 | struct dc_context *ctx, |
| 12388 | unsigned int link_index, |
| 12389 | struct aux_payload *payload, |
| 12390 | enum aux_return_code_type *operation_result) |
Jude Shih | 88f52b1 | 2021-08-11 14:41:34 +0800 | [diff] [blame] | 12391 | { |
| 12392 | struct amdgpu_device *adev = ctx->driver_context; |
Jude Shih | 88f52b1 | 2021-08-11 14:41:34 +0800 | [diff] [blame] | 12393 | struct dmub_notification *p_notify = adev->dm.dmub_notify; |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12394 | int ret = -1; |
Jude Shih | 88f52b1 | 2021-08-11 14:41:34 +0800 | [diff] [blame] | 12395 | |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12396 | mutex_lock(&adev->dm.dpia_aux_lock); |
| 12397 | if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { |
| 12398 | *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; |
| 12399 | goto out; |
Uwe Kleine-König | 3335a13 | 2023-03-27 18:07:54 +0200 | [diff] [blame] | 12400 | } |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12401 | |
| 12402 | if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { |
| 12403 | DRM_ERROR("wait_for_completion_timeout timeout!"); |
| 12404 | *operation_result = AUX_RET_ERROR_TIMEOUT; |
| 12405 | goto out; |
Jude Shih | 88f52b1 | 2021-08-11 14:41:34 +0800 | [diff] [blame] | 12406 | } |
| 12407 | |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12408 | if (p_notify->result != AUX_RET_SUCCESS) { |
| 12409 | /* |
| 12410 | * Transient states before tunneling is enabled could |
| 12411 | * lead to this error. We can ignore this for now. |
| 12412 | */ |
| 12413 | if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { |
| 12414 | DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", |
| 12415 | payload->address, payload->length, |
| 12416 | p_notify->result); |
| 12417 | } |
| 12418 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; |
| 12419 | goto out; |
| 12420 | } |
| 12421 | |
| 12422 | |
| 12423 | payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; |
| 12424 | if (!payload->write && p_notify->aux_reply.length && |
| 12425 | (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { |
| 12426 | |
| 12427 | if (payload->length != p_notify->aux_reply.length) { |
| 12428 | DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", |
| 12429 | p_notify->aux_reply.length, |
| 12430 | payload->address, payload->length); |
| 12431 | *operation_result = AUX_RET_ERROR_INVALID_REPLY; |
| 12432 | goto out; |
| 12433 | } |
| 12434 | |
| 12435 | memcpy(payload->data, p_notify->aux_reply.data, |
| 12436 | p_notify->aux_reply.length); |
| 12437 | } |
| 12438 | |
| 12439 | /* success */ |
| 12440 | ret = p_notify->aux_reply.length; |
| 12441 | *operation_result = p_notify->result; |
| 12442 | out: |
Stylon Wang | 0cf8307 | 2023-01-10 14:38:33 +0800 | [diff] [blame] | 12443 | reinit_completion(&adev->dm.dmub_aux_transfer_done); |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12444 | mutex_unlock(&adev->dm.dpia_aux_lock); |
| 12445 | return ret; |
Jude Shih | 88f52b1 | 2021-08-11 14:41:34 +0800 | [diff] [blame] | 12446 | } |
| 12447 | |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12448 | int amdgpu_dm_process_dmub_set_config_sync( |
| 12449 | struct dc_context *ctx, |
| 12450 | unsigned int link_index, |
| 12451 | struct set_config_cmd_payload *payload, |
| 12452 | enum set_config_status *operation_result) |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 12453 | { |
| 12454 | struct amdgpu_device *adev = ctx->driver_context; |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12455 | bool is_cmd_complete; |
| 12456 | int ret; |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 12457 | |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12458 | mutex_lock(&adev->dm.dpia_aux_lock); |
| 12459 | is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, |
| 12460 | link_index, payload, adev->dm.dmub_notify); |
Jude Shih | 88f52b1 | 2021-08-11 14:41:34 +0800 | [diff] [blame] | 12461 | |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12462 | if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { |
| 12463 | ret = 0; |
| 12464 | *operation_result = adev->dm.dmub_notify->sc_status; |
| 12465 | } else { |
Jude Shih | 9e3a50d | 2021-09-29 11:13:56 +0800 | [diff] [blame] | 12466 | DRM_ERROR("wait_for_completion_timeout timeout!"); |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12467 | ret = -1; |
| 12468 | *operation_result = SET_CONFIG_UNKNOWN_ERROR; |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 12469 | } |
| 12470 | |
Stylon Wang | 0cf8307 | 2023-01-10 14:38:33 +0800 | [diff] [blame] | 12471 | if (!is_cmd_complete) |
| 12472 | reinit_completion(&adev->dm.dmub_aux_transfer_done); |
Stylon Wang | ead08b9 | 2022-11-10 21:53:01 +0800 | [diff] [blame] | 12473 | mutex_unlock(&adev->dm.dpia_aux_lock); |
| 12474 | return ret; |
Jude Shih | 81927e2 | 2021-04-20 10:19:37 +0800 | [diff] [blame] | 12475 | } |
Zhan Liu | 1edf5ae | 2021-11-08 19:31:00 -0500 | [diff] [blame] | 12476 | |
Josip Pavic | e97cc04 | 2023-02-15 15:47:59 -0500 | [diff] [blame] | 12477 | bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) |
| 12478 | { |
| 12479 | return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); |
| 12480 | } |
| 12481 | |
| 12482 | bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) |
| 12483 | { |
| 12484 | return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); |
| 12485 | } |