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Arvind Bhushand69630e2013-03-14 05:09:07 +00001/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef __CSIO_HW_CHIP_H__
35#define __CSIO_HW_CHIP_H__
36
37#include "csio_defs.h"
38
Arvind Bhushand69630e2013-03-14 05:09:07 +000039/* Define MACRO values */
Arvind Bhushand69630e2013-03-14 05:09:07 +000040#define CSIO_HW_T5 0x5000
41#define CSIO_T5_FCOE_ASIC 0x5600
Varun Prakash4bbd4582017-05-18 20:17:38 +053042#define CSIO_HW_T6 0x6000
43#define CSIO_T6_FCOE_ASIC 0x6600
Arvind Bhushand69630e2013-03-14 05:09:07 +000044#define CSIO_HW_CHIP_MASK 0xF000
Hariprasad Shenai3fedeab2014-11-25 08:33:58 +053045
Arvind Bhushand69630e2013-03-14 05:09:07 +000046#define T5_REGMAP_SIZE (332 * 1024)
Arvind Bhushand69630e2013-03-14 05:09:07 +000047#define FW_FNAME_T5 "cxgb4/t5fw.bin"
Arvind Bhushand69630e2013-03-14 05:09:07 +000048#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
Varun Prakash4bbd4582017-05-18 20:17:38 +053049#define FW_FNAME_T6 "cxgb4/t6fw.bin"
50#define FW_CFG_NAME_T6 "cxgb4/t6-config.txt"
Arvind Bhushand69630e2013-03-14 05:09:07 +000051
Praveen Madhavanf40e74f2015-01-07 19:16:28 +053052#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
53#define CHELSIO_CHIP_FPGA 0x100
54#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
55#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
56
Praveen Madhavanf40e74f2015-01-07 19:16:28 +053057#define CHELSIO_T5 0x5
Varun Prakash4bbd4582017-05-18 20:17:38 +053058#define CHELSIO_T6 0x6
Praveen Madhavanf40e74f2015-01-07 19:16:28 +053059
60enum chip_type {
Praveen Madhavanf40e74f2015-01-07 19:16:28 +053061 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
62 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
63 T5_FIRST_REV = T5_A0,
64 T5_LAST_REV = T5_A1,
Varun Prakash4bbd4582017-05-18 20:17:38 +053065
66 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
67 T6_FIRST_REV = T6_A0,
68 T6_LAST_REV = T6_A0,
Praveen Madhavanf40e74f2015-01-07 19:16:28 +053069};
70
Arvind Bhushand69630e2013-03-14 05:09:07 +000071static inline int csio_is_t5(uint16_t chip)
72{
73 return (chip == CSIO_HW_T5);
74}
75
Varun Prakash4bbd4582017-05-18 20:17:38 +053076static inline int csio_is_t6(uint16_t chip)
77{
78 return (chip == CSIO_HW_T6);
79}
80
Arvind Bhushand69630e2013-03-14 05:09:07 +000081/* Define MACRO DEFINITIONS */
82#define CSIO_DEVICE(devid, idx) \
83 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
84
Praveen Madhavanf40e74f2015-01-07 19:16:28 +053085#include "t4fw_api.h"
Praveen Madhavan541c5712015-02-03 17:18:26 +053086#include "t4fw_version.h"
Arvind Bhushand69630e2013-03-14 05:09:07 +000087
Praveen Madhavanf40e74f2015-01-07 19:16:28 +053088#define FW_VERSION(chip) ( \
89 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
90 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
91 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
92 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
93#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
94
95struct fw_info {
96 u8 chip;
97 char *fs_name;
98 char *fw_mod_name;
99 struct fw_hdr fw_hdr;
100};
Arvind Bhushand69630e2013-03-14 05:09:07 +0000101
102/* Declare ENUMS */
103enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
104
105enum {
106 MEMWIN_APERTURE = 2048,
107 MEMWIN_BASE = 0x1b800,
Arvind Bhushand69630e2013-03-14 05:09:07 +0000108};
109
110/* Slow path handlers */
111struct intr_info {
112 unsigned int mask; /* bits to check in interrupt status */
113 const char *msg; /* message to print or NULL */
114 short stat_idx; /* stat counter to increment or -1 */
115 unsigned short fatal; /* whether the condition reported is fatal */
116};
117
118/* T4/T5 Chip specific ops */
119struct csio_hw;
120struct csio_hw_chip_ops {
121 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
122 void (*chip_pcie_intr_handler)(struct csio_hw *);
123 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
124 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
125 __be32 *, uint64_t *);
126 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
127 __be32 *, uint64_t *);
128 int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
129 u32, uint32_t *, int);
130 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
131};
132
Arvind Bhushand69630e2013-03-14 05:09:07 +0000133extern struct csio_hw_chip_ops t5_ops;
134
135#endif /* #ifndef __CSIO_HW_CHIP_H__ */