Ingo Molnar | 5c167b8 | 2008-12-17 09:02:19 +0100 | [diff] [blame] | 1 | #ifndef _ASM_X86_PERF_COUNTER_H |
| 2 | #define _ASM_X86_PERF_COUNTER_H |
Thomas Gleixner | 003a46c | 2007-10-15 13:57:47 +0200 | [diff] [blame] | 3 | |
Ingo Molnar | eb2b861 | 2008-12-17 09:09:13 +0100 | [diff] [blame] | 4 | /* |
| 5 | * Performance counter hw details: |
| 6 | */ |
| 7 | |
| 8 | #define X86_PMC_MAX_GENERIC 8 |
| 9 | #define X86_PMC_MAX_FIXED 3 |
| 10 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 11 | #define X86_PMC_IDX_GENERIC 0 |
| 12 | #define X86_PMC_IDX_FIXED 32 |
| 13 | #define X86_PMC_IDX_MAX 64 |
| 14 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 15 | #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 |
| 16 | #define MSR_ARCH_PERFMON_PERFCTR1 0xc2 |
Thomas Gleixner | 003a46c | 2007-10-15 13:57:47 +0200 | [diff] [blame] | 17 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 18 | #define MSR_ARCH_PERFMON_EVENTSEL0 0x186 |
| 19 | #define MSR_ARCH_PERFMON_EVENTSEL1 0x187 |
Thomas Gleixner | 003a46c | 2007-10-15 13:57:47 +0200 | [diff] [blame] | 20 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 21 | #define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22) |
| 22 | #define ARCH_PERFMON_EVENTSEL_INT (1 << 20) |
| 23 | #define ARCH_PERFMON_EVENTSEL_OS (1 << 17) |
| 24 | #define ARCH_PERFMON_EVENTSEL_USR (1 << 16) |
Thomas Gleixner | 003a46c | 2007-10-15 13:57:47 +0200 | [diff] [blame] | 25 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 26 | /* |
| 27 | * Includes eventsel and unit mask as well: |
| 28 | */ |
| 29 | #define ARCH_PERFMON_EVENT_MASK 0xffff |
| 30 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 31 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c |
| 32 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) |
| 33 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 |
Thomas Gleixner | 003a46c | 2007-10-15 13:57:47 +0200 | [diff] [blame] | 34 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 35 | (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) |
| 36 | |
| 37 | #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 |
Thomas Gleixner | 003a46c | 2007-10-15 13:57:47 +0200 | [diff] [blame] | 38 | |
Ingo Molnar | eb2b861 | 2008-12-17 09:09:13 +0100 | [diff] [blame] | 39 | /* |
| 40 | * Intel "Architectural Performance Monitoring" CPUID |
| 41 | * detection/enumeration details: |
| 42 | */ |
Thomas Gleixner | 003a46c | 2007-10-15 13:57:47 +0200 | [diff] [blame] | 43 | union cpuid10_eax { |
| 44 | struct { |
| 45 | unsigned int version_id:8; |
| 46 | unsigned int num_counters:8; |
| 47 | unsigned int bit_width:8; |
| 48 | unsigned int mask_length:8; |
| 49 | } split; |
| 50 | unsigned int full; |
| 51 | }; |
| 52 | |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 53 | union cpuid10_edx { |
| 54 | struct { |
| 55 | unsigned int num_counters_fixed:4; |
| 56 | unsigned int reserved:28; |
| 57 | } split; |
| 58 | unsigned int full; |
| 59 | }; |
| 60 | |
| 61 | |
| 62 | /* |
| 63 | * Fixed-purpose performance counters: |
| 64 | */ |
| 65 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 66 | /* |
| 67 | * All 3 fixed-mode PMCs are configured via this single MSR: |
| 68 | */ |
| 69 | #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d |
| 70 | |
| 71 | /* |
| 72 | * The counts are available in three separate MSRs: |
| 73 | */ |
| 74 | |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 75 | /* Instr_Retired.Any: */ |
| 76 | #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 77 | #define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0) |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 78 | |
| 79 | /* CPU_CLK_Unhalted.Core: */ |
| 80 | #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 81 | #define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1) |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 82 | |
| 83 | /* CPU_CLK_Unhalted.Ref: */ |
| 84 | #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 85 | #define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2) |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 86 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 87 | #ifdef CONFIG_PERF_COUNTERS |
| 88 | extern void init_hw_perf_counters(void); |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 89 | extern void perf_counters_lapic_init(void); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 90 | |
| 91 | #define PERF_COUNTER_INDEX_OFFSET 0 |
| 92 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 93 | #else |
| 94 | static inline void init_hw_perf_counters(void) { } |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 95 | static inline void perf_counters_lapic_init(void) { } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 96 | #endif |
| 97 | |
Ingo Molnar | 5c167b8 | 2008-12-17 09:02:19 +0100 | [diff] [blame] | 98 | #endif /* _ASM_X86_PERF_COUNTER_H */ |