Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Paul Mackerras | a7fdd90 | 2006-01-15 17:30:44 +1100 | [diff] [blame] | 2 | * Common prep/chrp pci routines. -- Cort |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | */ |
| 4 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | #include <linux/kernel.h> |
| 6 | #include <linux/pci.h> |
| 7 | #include <linux/delay.h> |
| 8 | #include <linux/string.h> |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/capability.h> |
| 11 | #include <linux/sched.h> |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/bootmem.h> |
| 14 | |
| 15 | #include <asm/processor.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <asm/prom.h> |
| 18 | #include <asm/sections.h> |
| 19 | #include <asm/pci-bridge.h> |
| 20 | #include <asm/byteorder.h> |
| 21 | #include <asm/irq.h> |
| 22 | #include <asm/uaccess.h> |
Paul Mackerras | b60fc8bb | 2005-10-10 14:14:55 +1000 | [diff] [blame] | 23 | #include <asm/machdep.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | |
| 25 | #undef DEBUG |
| 26 | |
| 27 | #ifdef DEBUG |
| 28 | #define DBG(x...) printk(x) |
| 29 | #else |
| 30 | #define DBG(x...) |
| 31 | #endif |
| 32 | |
| 33 | unsigned long isa_io_base = 0; |
| 34 | unsigned long isa_mem_base = 0; |
| 35 | unsigned long pci_dram_offset = 0; |
| 36 | int pcibios_assign_bus_offset = 1; |
| 37 | |
| 38 | void pcibios_make_OF_bus_map(void); |
| 39 | |
| 40 | static int pci_relocate_bridge_resource(struct pci_bus *bus, int i); |
| 41 | static int probe_resource(struct pci_bus *parent, struct resource *pr, |
| 42 | struct resource *res, struct resource **conflict); |
| 43 | static void update_bridge_base(struct pci_bus *bus, int i); |
| 44 | static void pcibios_fixup_resources(struct pci_dev* dev); |
| 45 | static void fixup_broken_pcnet32(struct pci_dev* dev); |
| 46 | static int reparent_resources(struct resource *parent, struct resource *res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | static void fixup_cpc710_pci64(struct pci_dev* dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
Paul Mackerras | a7fdd90 | 2006-01-15 17:30:44 +1100 | [diff] [blame] | 49 | /* By default, we don't re-assign bus numbers. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | */ |
Paul Mackerras | 399fe2b | 2005-10-20 20:57:05 +1000 | [diff] [blame] | 51 | int pci_assign_all_buses; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | |
| 53 | struct pci_controller* hose_head; |
| 54 | struct pci_controller** hose_tail = &hose_head; |
| 55 | |
| 56 | static int pci_bus_count; |
| 57 | |
| 58 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | fixup_broken_pcnet32(struct pci_dev* dev) |
| 60 | { |
| 61 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { |
| 62 | dev->vendor = PCI_VENDOR_ID_AMD; |
| 63 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | } |
| 65 | } |
| 66 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); |
| 67 | |
| 68 | static void |
| 69 | fixup_cpc710_pci64(struct pci_dev* dev) |
| 70 | { |
| 71 | /* Hide the PCI64 BARs from the kernel as their content doesn't |
| 72 | * fit well in the resource management |
| 73 | */ |
| 74 | dev->resource[0].start = dev->resource[0].end = 0; |
| 75 | dev->resource[0].flags = 0; |
| 76 | dev->resource[1].start = dev->resource[1].end = 0; |
| 77 | dev->resource[1].flags = 0; |
| 78 | } |
| 79 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64); |
| 80 | |
| 81 | static void |
| 82 | pcibios_fixup_resources(struct pci_dev *dev) |
| 83 | { |
| 84 | struct pci_controller* hose = (struct pci_controller *)dev->sysdata; |
| 85 | int i; |
| 86 | unsigned long offset; |
| 87 | |
| 88 | if (!hose) { |
| 89 | printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev)); |
| 90 | return; |
| 91 | } |
| 92 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 93 | struct resource *res = dev->resource + i; |
| 94 | if (!res->flags) |
| 95 | continue; |
| 96 | if (res->end == 0xffffffff) { |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 97 | DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n", |
| 98 | pci_name(dev), i, |
| 99 | (unsigned long long)res->start, |
| 100 | (unsigned long long)res->end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | res->end -= res->start; |
| 102 | res->start = 0; |
| 103 | res->flags |= IORESOURCE_UNSET; |
| 104 | continue; |
| 105 | } |
| 106 | offset = 0; |
| 107 | if (res->flags & IORESOURCE_MEM) { |
| 108 | offset = hose->pci_mem_offset; |
| 109 | } else if (res->flags & IORESOURCE_IO) { |
| 110 | offset = (unsigned long) hose->io_base_virt |
| 111 | - isa_io_base; |
| 112 | } |
| 113 | if (offset != 0) { |
| 114 | res->start += offset; |
| 115 | res->end += offset; |
| 116 | #ifdef DEBUG |
| 117 | printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n", |
| 118 | i, res->flags, pci_name(dev), |
| 119 | res->start - offset, res->start); |
| 120 | #endif |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | /* Call machine specific resource fixup */ |
| 125 | if (ppc_md.pcibios_fixup_resources) |
| 126 | ppc_md.pcibios_fixup_resources(dev); |
| 127 | } |
| 128 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); |
| 129 | |
| 130 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
| 131 | struct resource *res) |
| 132 | { |
| 133 | unsigned long offset = 0; |
| 134 | struct pci_controller *hose = dev->sysdata; |
| 135 | |
| 136 | if (hose && res->flags & IORESOURCE_IO) |
| 137 | offset = (unsigned long)hose->io_base_virt - isa_io_base; |
| 138 | else if (hose && res->flags & IORESOURCE_MEM) |
| 139 | offset = hose->pci_mem_offset; |
| 140 | region->start = res->start - offset; |
| 141 | region->end = res->end - offset; |
| 142 | } |
| 143 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
| 144 | |
Dominik Brodowski | 43c3473 | 2005-08-04 18:06:21 -0700 | [diff] [blame] | 145 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
| 146 | struct pci_bus_region *region) |
| 147 | { |
| 148 | unsigned long offset = 0; |
| 149 | struct pci_controller *hose = dev->sysdata; |
| 150 | |
| 151 | if (hose && res->flags & IORESOURCE_IO) |
| 152 | offset = (unsigned long)hose->io_base_virt - isa_io_base; |
| 153 | else if (hose && res->flags & IORESOURCE_MEM) |
| 154 | offset = hose->pci_mem_offset; |
| 155 | res->start = region->start + offset; |
| 156 | res->end = region->end + offset; |
| 157 | } |
| 158 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
| 159 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | /* |
| 161 | * We need to avoid collisions with `mirrored' VGA ports |
| 162 | * and other strange ISA hardware, so we always want the |
| 163 | * addresses to be allocated in the 0x000-0x0ff region |
| 164 | * modulo 0x400. |
| 165 | * |
| 166 | * Why? Because some silly external IO cards only decode |
| 167 | * the low 10 bits of the IO address. The 0x00-0xff region |
| 168 | * is reserved for motherboard devices that decode all 16 |
| 169 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, |
| 170 | * but we want to try to avoid allocating at 0x2900-0x2bff |
| 171 | * which might have be mirrored at 0x0100-0x03ff.. |
| 172 | */ |
Greg Kroah-Hartman | e31dd6e | 2006-06-12 17:06:02 -0700 | [diff] [blame] | 173 | void pcibios_align_resource(void *data, struct resource *res, |
| 174 | resource_size_t size, resource_size_t align) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | { |
| 176 | struct pci_dev *dev = data; |
| 177 | |
| 178 | if (res->flags & IORESOURCE_IO) { |
Greg Kroah-Hartman | e31dd6e | 2006-06-12 17:06:02 -0700 | [diff] [blame] | 179 | resource_size_t start = res->start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | |
| 181 | if (size > 0x100) { |
| 182 | printk(KERN_ERR "PCI: I/O Region %s/%d too large" |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 183 | " (%lld bytes)\n", pci_name(dev), |
| 184 | dev->resource - res, (unsigned long long)size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | if (start & 0x300) { |
| 188 | start = (start + 0x3ff) & ~0x3ff; |
| 189 | res->start = start; |
| 190 | } |
| 191 | } |
| 192 | } |
| 193 | EXPORT_SYMBOL(pcibios_align_resource); |
| 194 | |
| 195 | /* |
| 196 | * Handle resources of PCI devices. If the world were perfect, we could |
| 197 | * just allocate all the resource regions and do nothing more. It isn't. |
| 198 | * On the other hand, we cannot just re-allocate all devices, as it would |
| 199 | * require us to know lots of host bridge internals. So we attempt to |
| 200 | * keep as much of the original configuration as possible, but tweak it |
| 201 | * when it's found to be wrong. |
| 202 | * |
| 203 | * Known BIOS problems we have to work around: |
| 204 | * - I/O or memory regions not configured |
| 205 | * - regions configured, but not enabled in the command register |
| 206 | * - bogus I/O addresses above 64K used |
| 207 | * - expansion ROMs left enabled (this may sound harmless, but given |
| 208 | * the fact the PCI specs explicitly allow address decoders to be |
| 209 | * shared between expansion ROMs and other resource regions, it's |
| 210 | * at least dangerous) |
| 211 | * |
| 212 | * Our solution: |
| 213 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. |
| 214 | * This gives us fixed barriers on where we can allocate. |
| 215 | * (2) Allocate resources for all enabled devices. If there is |
| 216 | * a collision, just mark the resource as unallocated. Also |
| 217 | * disable expansion ROMs during this step. |
| 218 | * (3) Try to allocate resources for disabled devices. If the |
| 219 | * resources were assigned correctly, everything goes well, |
| 220 | * if they weren't, they won't disturb allocation of other |
| 221 | * resources. |
| 222 | * (4) Assign new addresses to resources which were either |
| 223 | * not configured at all or misconfigured. If explicitly |
| 224 | * requested by the user, configure expansion ROM address |
| 225 | * as well. |
| 226 | */ |
| 227 | |
| 228 | static void __init |
| 229 | pcibios_allocate_bus_resources(struct list_head *bus_list) |
| 230 | { |
| 231 | struct pci_bus *bus; |
| 232 | int i; |
| 233 | struct resource *res, *pr; |
| 234 | |
| 235 | /* Depth-First Search on bus tree */ |
| 236 | list_for_each_entry(bus, bus_list, node) { |
| 237 | for (i = 0; i < 4; ++i) { |
| 238 | if ((res = bus->resource[i]) == NULL || !res->flags |
| 239 | || res->start > res->end) |
| 240 | continue; |
| 241 | if (bus->parent == NULL) |
| 242 | pr = (res->flags & IORESOURCE_IO)? |
| 243 | &ioport_resource: &iomem_resource; |
| 244 | else { |
| 245 | pr = pci_find_parent_resource(bus->self, res); |
| 246 | if (pr == res) { |
| 247 | /* this happens when the generic PCI |
| 248 | * code (wrongly) decides that this |
| 249 | * bridge is transparent -- paulus |
| 250 | */ |
| 251 | continue; |
| 252 | } |
| 253 | } |
| 254 | |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 255 | DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n", |
| 256 | (unsigned long long)res->start, |
| 257 | (unsigned long long)res->end, res->flags, pr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | if (pr) { |
| 259 | if (request_resource(pr, res) == 0) |
| 260 | continue; |
| 261 | /* |
| 262 | * Must be a conflict with an existing entry. |
| 263 | * Move that entry (or entries) under the |
| 264 | * bridge resource and try again. |
| 265 | */ |
| 266 | if (reparent_resources(pr, res) == 0) |
| 267 | continue; |
| 268 | } |
| 269 | printk(KERN_ERR "PCI: Cannot allocate resource region " |
| 270 | "%d of PCI bridge %d\n", i, bus->number); |
| 271 | if (pci_relocate_bridge_resource(bus, i)) |
| 272 | bus->resource[i] = NULL; |
| 273 | } |
| 274 | pcibios_allocate_bus_resources(&bus->children); |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | /* |
| 279 | * Reparent resource children of pr that conflict with res |
| 280 | * under res, and make res replace those children. |
| 281 | */ |
| 282 | static int __init |
| 283 | reparent_resources(struct resource *parent, struct resource *res) |
| 284 | { |
| 285 | struct resource *p, **pp; |
| 286 | struct resource **firstpp = NULL; |
| 287 | |
| 288 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { |
| 289 | if (p->end < res->start) |
| 290 | continue; |
| 291 | if (res->end < p->start) |
| 292 | break; |
| 293 | if (p->start < res->start || p->end > res->end) |
| 294 | return -1; /* not completely contained */ |
| 295 | if (firstpp == NULL) |
| 296 | firstpp = pp; |
| 297 | } |
| 298 | if (firstpp == NULL) |
| 299 | return -1; /* didn't find any conflicting entries? */ |
| 300 | res->parent = parent; |
| 301 | res->child = *firstpp; |
| 302 | res->sibling = *pp; |
| 303 | *firstpp = res; |
| 304 | *pp = NULL; |
| 305 | for (p = res->child; p != NULL; p = p->sibling) { |
| 306 | p->parent = res; |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 307 | DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", |
| 308 | p->name, (unsigned long long)p->start, |
| 309 | (unsigned long long)p->end, res->name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | } |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | /* |
| 315 | * A bridge has been allocated a range which is outside the range |
| 316 | * of its parent bridge, so it needs to be moved. |
| 317 | */ |
| 318 | static int __init |
| 319 | pci_relocate_bridge_resource(struct pci_bus *bus, int i) |
| 320 | { |
| 321 | struct resource *res, *pr, *conflict; |
| 322 | unsigned long try, size; |
| 323 | int j; |
| 324 | struct pci_bus *parent = bus->parent; |
| 325 | |
| 326 | if (parent == NULL) { |
| 327 | /* shouldn't ever happen */ |
| 328 | printk(KERN_ERR "PCI: can't move host bridge resource\n"); |
| 329 | return -1; |
| 330 | } |
| 331 | res = bus->resource[i]; |
| 332 | if (res == NULL) |
| 333 | return -1; |
| 334 | pr = NULL; |
| 335 | for (j = 0; j < 4; j++) { |
| 336 | struct resource *r = parent->resource[j]; |
| 337 | if (!r) |
| 338 | continue; |
| 339 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) |
| 340 | continue; |
| 341 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) { |
| 342 | pr = r; |
| 343 | break; |
| 344 | } |
| 345 | if (res->flags & IORESOURCE_PREFETCH) |
| 346 | pr = r; |
| 347 | } |
| 348 | if (pr == NULL) |
| 349 | return -1; |
| 350 | size = res->end - res->start; |
| 351 | if (pr->start > pr->end || size > pr->end - pr->start) |
| 352 | return -1; |
| 353 | try = pr->end; |
| 354 | for (;;) { |
| 355 | res->start = try - size; |
| 356 | res->end = try; |
| 357 | if (probe_resource(bus->parent, pr, res, &conflict) == 0) |
| 358 | break; |
| 359 | if (conflict->start <= pr->start + size) |
| 360 | return -1; |
| 361 | try = conflict->start - 1; |
| 362 | } |
| 363 | if (request_resource(pr, res)) { |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 364 | DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n", |
| 365 | (unsigned long long)res->start, |
| 366 | (unsigned long long)res->end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | return -1; /* "can't happen" */ |
| 368 | } |
| 369 | update_bridge_base(bus, i); |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 370 | printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n", |
| 371 | bus->number, i, (unsigned long long)res->start, |
| 372 | (unsigned long long)res->end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | static int __init |
| 377 | probe_resource(struct pci_bus *parent, struct resource *pr, |
| 378 | struct resource *res, struct resource **conflict) |
| 379 | { |
| 380 | struct pci_bus *bus; |
| 381 | struct pci_dev *dev; |
| 382 | struct resource *r; |
| 383 | int i; |
| 384 | |
| 385 | for (r = pr->child; r != NULL; r = r->sibling) { |
| 386 | if (r->end >= res->start && res->end >= r->start) { |
| 387 | *conflict = r; |
| 388 | return 1; |
| 389 | } |
| 390 | } |
| 391 | list_for_each_entry(bus, &parent->children, node) { |
| 392 | for (i = 0; i < 4; ++i) { |
| 393 | if ((r = bus->resource[i]) == NULL) |
| 394 | continue; |
| 395 | if (!r->flags || r->start > r->end || r == res) |
| 396 | continue; |
| 397 | if (pci_find_parent_resource(bus->self, r) != pr) |
| 398 | continue; |
| 399 | if (r->end >= res->start && res->end >= r->start) { |
| 400 | *conflict = r; |
| 401 | return 1; |
| 402 | } |
| 403 | } |
| 404 | } |
| 405 | list_for_each_entry(dev, &parent->devices, bus_list) { |
| 406 | for (i = 0; i < 6; ++i) { |
| 407 | r = &dev->resource[i]; |
| 408 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) |
| 409 | continue; |
| 410 | if (pci_find_parent_resource(dev, r) != pr) |
| 411 | continue; |
| 412 | if (r->end >= res->start && res->end >= r->start) { |
| 413 | *conflict = r; |
| 414 | return 1; |
| 415 | } |
| 416 | } |
| 417 | } |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static void __init |
| 422 | update_bridge_base(struct pci_bus *bus, int i) |
| 423 | { |
| 424 | struct resource *res = bus->resource[i]; |
| 425 | u8 io_base_lo, io_limit_lo; |
| 426 | u16 mem_base, mem_limit; |
| 427 | u16 cmd; |
| 428 | unsigned long start, end, off; |
| 429 | struct pci_dev *dev = bus->self; |
| 430 | struct pci_controller *hose = dev->sysdata; |
| 431 | |
| 432 | if (!hose) { |
| 433 | printk("update_bridge_base: no hose?\n"); |
| 434 | return; |
| 435 | } |
| 436 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 437 | pci_write_config_word(dev, PCI_COMMAND, |
| 438 | cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); |
| 439 | if (res->flags & IORESOURCE_IO) { |
| 440 | off = (unsigned long) hose->io_base_virt - isa_io_base; |
| 441 | start = res->start - off; |
| 442 | end = res->end - off; |
| 443 | io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK; |
| 444 | io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK; |
| 445 | if (end > 0xffff) { |
| 446 | pci_write_config_word(dev, PCI_IO_BASE_UPPER16, |
| 447 | start >> 16); |
| 448 | pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, |
| 449 | end >> 16); |
| 450 | io_base_lo |= PCI_IO_RANGE_TYPE_32; |
| 451 | } else |
| 452 | io_base_lo |= PCI_IO_RANGE_TYPE_16; |
| 453 | pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo); |
| 454 | pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo); |
| 455 | |
| 456 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) |
| 457 | == IORESOURCE_MEM) { |
| 458 | off = hose->pci_mem_offset; |
| 459 | mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK; |
| 460 | mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK; |
| 461 | pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); |
| 462 | pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); |
| 463 | |
| 464 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) |
| 465 | == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) { |
| 466 | off = hose->pci_mem_offset; |
| 467 | mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK; |
| 468 | mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK; |
| 469 | pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base); |
| 470 | pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); |
| 471 | |
| 472 | } else { |
| 473 | DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", |
| 474 | pci_name(dev), i, res->flags); |
| 475 | } |
| 476 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 477 | } |
| 478 | |
| 479 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
| 480 | { |
| 481 | struct resource *pr, *r = &dev->resource[idx]; |
| 482 | |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 483 | DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n", |
| 484 | pci_name(dev), idx, (unsigned long long)r->start, |
| 485 | (unsigned long long)r->end, r->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 486 | pr = pci_find_parent_resource(dev, r); |
| 487 | if (!pr || request_resource(pr, r) < 0) { |
| 488 | printk(KERN_ERR "PCI: Cannot allocate resource region %d" |
| 489 | " of device %s\n", idx, pci_name(dev)); |
| 490 | if (pr) |
Greg Kroah-Hartman | 685143ac | 2006-06-12 15:18:31 -0700 | [diff] [blame] | 491 | DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n", |
| 492 | pr, (unsigned long long)pr->start, |
| 493 | (unsigned long long)pr->end, pr->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | /* We'll assign a new address later */ |
| 495 | r->flags |= IORESOURCE_UNSET; |
| 496 | r->end -= r->start; |
| 497 | r->start = 0; |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | static void __init |
| 502 | pcibios_allocate_resources(int pass) |
| 503 | { |
| 504 | struct pci_dev *dev = NULL; |
| 505 | int idx, disabled; |
| 506 | u16 command; |
| 507 | struct resource *r; |
| 508 | |
Jiri Slaby | cee0295 | 2005-11-06 23:39:34 -0800 | [diff] [blame] | 509 | for_each_pci_dev(dev) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | pci_read_config_word(dev, PCI_COMMAND, &command); |
| 511 | for (idx = 0; idx < 6; idx++) { |
| 512 | r = &dev->resource[idx]; |
| 513 | if (r->parent) /* Already allocated */ |
| 514 | continue; |
| 515 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) |
| 516 | continue; /* Not assigned at all */ |
| 517 | if (r->flags & IORESOURCE_IO) |
| 518 | disabled = !(command & PCI_COMMAND_IO); |
| 519 | else |
| 520 | disabled = !(command & PCI_COMMAND_MEMORY); |
| 521 | if (pass == disabled) |
| 522 | alloc_resource(dev, idx); |
| 523 | } |
| 524 | if (pass) |
| 525 | continue; |
| 526 | r = &dev->resource[PCI_ROM_RESOURCE]; |
| 527 | if (r->flags & IORESOURCE_ROM_ENABLE) { |
| 528 | /* Turn the ROM off, leave the resource region, but keep it unregistered. */ |
| 529 | u32 reg; |
| 530 | DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); |
| 531 | r->flags &= ~IORESOURCE_ROM_ENABLE; |
| 532 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
| 533 | pci_write_config_dword(dev, dev->rom_base_reg, |
| 534 | reg & ~PCI_ROM_ADDRESS_ENABLE); |
| 535 | } |
| 536 | } |
| 537 | } |
| 538 | |
| 539 | static void __init |
| 540 | pcibios_assign_resources(void) |
| 541 | { |
| 542 | struct pci_dev *dev = NULL; |
| 543 | int idx; |
| 544 | struct resource *r; |
| 545 | |
Jiri Slaby | cee0295 | 2005-11-06 23:39:34 -0800 | [diff] [blame] | 546 | for_each_pci_dev(dev) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | int class = dev->class >> 8; |
| 548 | |
| 549 | /* Don't touch classless devices and host bridges */ |
| 550 | if (!class || class == PCI_CLASS_BRIDGE_HOST) |
| 551 | continue; |
| 552 | |
| 553 | for (idx = 0; idx < 6; idx++) { |
| 554 | r = &dev->resource[idx]; |
| 555 | |
| 556 | /* |
| 557 | * We shall assign a new address to this resource, |
| 558 | * either because the BIOS (sic) forgot to do so |
| 559 | * or because we have decided the old address was |
| 560 | * unusable for some reason. |
| 561 | */ |
| 562 | if ((r->flags & IORESOURCE_UNSET) && r->end && |
| 563 | (!ppc_md.pcibios_enable_device_hook || |
| 564 | !ppc_md.pcibios_enable_device_hook(dev, 1))) { |
| 565 | r->flags &= ~IORESOURCE_UNSET; |
| 566 | pci_assign_resource(dev, idx); |
| 567 | } |
| 568 | } |
| 569 | |
| 570 | #if 0 /* don't assign ROMs */ |
| 571 | r = &dev->resource[PCI_ROM_RESOURCE]; |
| 572 | r->end -= r->start; |
| 573 | r->start = 0; |
| 574 | if (r->end) |
| 575 | pci_assign_resource(dev, PCI_ROM_RESOURCE); |
| 576 | #endif |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | |
| 581 | int |
| 582 | pcibios_enable_resources(struct pci_dev *dev, int mask) |
| 583 | { |
| 584 | u16 cmd, old_cmd; |
| 585 | int idx; |
| 586 | struct resource *r; |
| 587 | |
| 588 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 589 | old_cmd = cmd; |
| 590 | for (idx=0; idx<6; idx++) { |
| 591 | /* Only set up the requested stuff */ |
| 592 | if (!(mask & (1<<idx))) |
| 593 | continue; |
| 594 | |
| 595 | r = &dev->resource[idx]; |
| 596 | if (r->flags & IORESOURCE_UNSET) { |
| 597 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); |
| 598 | return -EINVAL; |
| 599 | } |
| 600 | if (r->flags & IORESOURCE_IO) |
| 601 | cmd |= PCI_COMMAND_IO; |
| 602 | if (r->flags & IORESOURCE_MEM) |
| 603 | cmd |= PCI_COMMAND_MEMORY; |
| 604 | } |
| 605 | if (dev->resource[PCI_ROM_RESOURCE].start) |
| 606 | cmd |= PCI_COMMAND_MEMORY; |
| 607 | if (cmd != old_cmd) { |
| 608 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); |
| 609 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 610 | } |
| 611 | return 0; |
| 612 | } |
| 613 | |
| 614 | static int next_controller_index; |
| 615 | |
| 616 | struct pci_controller * __init |
| 617 | pcibios_alloc_controller(void) |
| 618 | { |
| 619 | struct pci_controller *hose; |
| 620 | |
| 621 | hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose)); |
| 622 | memset(hose, 0, sizeof(struct pci_controller)); |
| 623 | |
| 624 | *hose_tail = hose; |
| 625 | hose_tail = &hose->next; |
| 626 | |
| 627 | hose->index = next_controller_index++; |
| 628 | |
| 629 | return hose; |
| 630 | } |
| 631 | |
Paul Mackerras | fd582ec | 2005-10-11 22:08:12 +1000 | [diff] [blame] | 632 | void pcibios_make_OF_bus_map(void) |
| 633 | { |
| 634 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | |
| 636 | /* Add sysfs properties */ |
| 637 | void pcibios_add_platform_entries(struct pci_dev *pdev) |
| 638 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | static int __init |
| 643 | pcibios_init(void) |
| 644 | { |
| 645 | struct pci_controller *hose; |
| 646 | struct pci_bus *bus; |
| 647 | int next_busno; |
| 648 | |
| 649 | printk(KERN_INFO "PCI: Probing PCI hardware\n"); |
| 650 | |
| 651 | /* Scan all of the recorded PCI controllers. */ |
| 652 | for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { |
Paul Mackerras | 399fe2b | 2005-10-20 20:57:05 +1000 | [diff] [blame] | 653 | if (pci_assign_all_buses) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 654 | hose->first_busno = next_busno; |
| 655 | hose->last_busno = 0xff; |
| 656 | bus = pci_scan_bus(hose->first_busno, hose->ops, hose); |
| 657 | hose->last_busno = bus->subordinate; |
Paul Mackerras | 399fe2b | 2005-10-20 20:57:05 +1000 | [diff] [blame] | 658 | if (pci_assign_all_buses || next_busno <= hose->last_busno) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 659 | next_busno = hose->last_busno + pcibios_assign_bus_offset; |
| 660 | } |
| 661 | pci_bus_count = next_busno; |
| 662 | |
| 663 | /* OpenFirmware based machines need a map of OF bus |
| 664 | * numbers vs. kernel bus numbers since we may have to |
| 665 | * remap them. |
| 666 | */ |
Paul Mackerras | 399fe2b | 2005-10-20 20:57:05 +1000 | [diff] [blame] | 667 | if (pci_assign_all_buses && have_of) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 668 | pcibios_make_OF_bus_map(); |
| 669 | |
| 670 | /* Do machine dependent PCI interrupt routing */ |
| 671 | if (ppc_md.pci_swizzle && ppc_md.pci_map_irq) |
| 672 | pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq); |
| 673 | |
| 674 | /* Call machine dependent fixup */ |
| 675 | if (ppc_md.pcibios_fixup) |
| 676 | ppc_md.pcibios_fixup(); |
| 677 | |
| 678 | /* Allocate and assign resources */ |
| 679 | pcibios_allocate_bus_resources(&pci_root_buses); |
| 680 | pcibios_allocate_resources(0); |
| 681 | pcibios_allocate_resources(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | pcibios_assign_resources(); |
| 683 | |
| 684 | /* Call machine dependent post-init code */ |
| 685 | if (ppc_md.pcibios_after_init) |
| 686 | ppc_md.pcibios_after_init(); |
| 687 | |
| 688 | return 0; |
| 689 | } |
| 690 | |
| 691 | subsys_initcall(pcibios_init); |
| 692 | |
| 693 | unsigned char __init |
| 694 | common_swizzle(struct pci_dev *dev, unsigned char *pinp) |
| 695 | { |
| 696 | struct pci_controller *hose = dev->sysdata; |
| 697 | |
| 698 | if (dev->bus->number != hose->first_busno) { |
| 699 | u8 pin = *pinp; |
| 700 | do { |
| 701 | pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); |
| 702 | /* Move up the chain of bridges. */ |
| 703 | dev = dev->bus->self; |
| 704 | } while (dev->bus->self); |
| 705 | *pinp = pin; |
| 706 | |
| 707 | /* The slot is the idsel of the last bridge. */ |
| 708 | } |
| 709 | return PCI_SLOT(dev->devfn); |
| 710 | } |
| 711 | |
| 712 | unsigned long resource_fixup(struct pci_dev * dev, struct resource * res, |
| 713 | unsigned long start, unsigned long size) |
| 714 | { |
| 715 | return start; |
| 716 | } |
| 717 | |
| 718 | void __init pcibios_fixup_bus(struct pci_bus *bus) |
| 719 | { |
| 720 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; |
| 721 | unsigned long io_offset; |
| 722 | struct resource *res; |
| 723 | int i; |
| 724 | |
| 725 | io_offset = (unsigned long)hose->io_base_virt - isa_io_base; |
| 726 | if (bus->parent == NULL) { |
| 727 | /* This is a host bridge - fill in its resources */ |
| 728 | hose->bus = bus; |
| 729 | |
| 730 | bus->resource[0] = res = &hose->io_resource; |
| 731 | if (!res->flags) { |
| 732 | if (io_offset) |
| 733 | printk(KERN_ERR "I/O resource not set for host" |
| 734 | " bridge %d\n", hose->index); |
| 735 | res->start = 0; |
| 736 | res->end = IO_SPACE_LIMIT; |
| 737 | res->flags = IORESOURCE_IO; |
| 738 | } |
| 739 | res->start += io_offset; |
| 740 | res->end += io_offset; |
| 741 | |
| 742 | for (i = 0; i < 3; ++i) { |
| 743 | res = &hose->mem_resources[i]; |
| 744 | if (!res->flags) { |
| 745 | if (i > 0) |
| 746 | continue; |
| 747 | printk(KERN_ERR "Memory resource not set for " |
| 748 | "host bridge %d\n", hose->index); |
| 749 | res->start = hose->pci_mem_offset; |
| 750 | res->end = ~0U; |
| 751 | res->flags = IORESOURCE_MEM; |
| 752 | } |
| 753 | bus->resource[i+1] = res; |
| 754 | } |
| 755 | } else { |
| 756 | /* This is a subordinate bridge */ |
| 757 | pci_read_bridge_bases(bus); |
| 758 | |
| 759 | for (i = 0; i < 4; ++i) { |
| 760 | if ((res = bus->resource[i]) == NULL) |
| 761 | continue; |
| 762 | if (!res->flags) |
| 763 | continue; |
| 764 | if (io_offset && (res->flags & IORESOURCE_IO)) { |
| 765 | res->start += io_offset; |
| 766 | res->end += io_offset; |
| 767 | } else if (hose->pci_mem_offset |
| 768 | && (res->flags & IORESOURCE_MEM)) { |
| 769 | res->start += hose->pci_mem_offset; |
| 770 | res->end += hose->pci_mem_offset; |
| 771 | } |
| 772 | } |
| 773 | } |
| 774 | |
| 775 | if (ppc_md.pcibios_fixup_bus) |
| 776 | ppc_md.pcibios_fixup_bus(bus); |
| 777 | } |
| 778 | |
| 779 | char __init *pcibios_setup(char *str) |
| 780 | { |
| 781 | return str; |
| 782 | } |
| 783 | |
| 784 | /* the next one is stolen from the alpha port... */ |
| 785 | void __init |
| 786 | pcibios_update_irq(struct pci_dev *dev, int irq) |
| 787 | { |
| 788 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); |
| 789 | /* XXX FIXME - update OF device tree node interrupt property */ |
| 790 | } |
| 791 | |
| 792 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
| 793 | { |
| 794 | u16 cmd, old_cmd; |
| 795 | int idx; |
| 796 | struct resource *r; |
| 797 | |
| 798 | if (ppc_md.pcibios_enable_device_hook) |
| 799 | if (ppc_md.pcibios_enable_device_hook(dev, 0)) |
| 800 | return -EINVAL; |
| 801 | |
| 802 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
| 803 | old_cmd = cmd; |
| 804 | for (idx=0; idx<6; idx++) { |
| 805 | r = &dev->resource[idx]; |
| 806 | if (r->flags & IORESOURCE_UNSET) { |
| 807 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); |
| 808 | return -EINVAL; |
| 809 | } |
| 810 | if (r->flags & IORESOURCE_IO) |
| 811 | cmd |= PCI_COMMAND_IO; |
| 812 | if (r->flags & IORESOURCE_MEM) |
| 813 | cmd |= PCI_COMMAND_MEMORY; |
| 814 | } |
| 815 | if (cmd != old_cmd) { |
| 816 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
| 817 | pci_name(dev), old_cmd, cmd); |
| 818 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
| 819 | } |
| 820 | return 0; |
| 821 | } |
| 822 | |
| 823 | struct pci_controller* |
| 824 | pci_bus_to_hose(int bus) |
| 825 | { |
| 826 | struct pci_controller* hose = hose_head; |
| 827 | |
| 828 | for (; hose; hose = hose->next) |
| 829 | if (bus >= hose->first_busno && bus <= hose->last_busno) |
| 830 | return hose; |
| 831 | return NULL; |
| 832 | } |
| 833 | |
Al Viro | 92a11f9 | 2005-04-25 07:55:57 -0700 | [diff] [blame] | 834 | void __iomem * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 835 | pci_bus_io_base(unsigned int bus) |
| 836 | { |
| 837 | struct pci_controller *hose; |
| 838 | |
| 839 | hose = pci_bus_to_hose(bus); |
| 840 | if (!hose) |
| 841 | return NULL; |
| 842 | return hose->io_base_virt; |
| 843 | } |
| 844 | |
| 845 | unsigned long |
| 846 | pci_bus_io_base_phys(unsigned int bus) |
| 847 | { |
| 848 | struct pci_controller *hose; |
| 849 | |
| 850 | hose = pci_bus_to_hose(bus); |
| 851 | if (!hose) |
| 852 | return 0; |
| 853 | return hose->io_base_phys; |
| 854 | } |
| 855 | |
| 856 | unsigned long |
| 857 | pci_bus_mem_base_phys(unsigned int bus) |
| 858 | { |
| 859 | struct pci_controller *hose; |
| 860 | |
| 861 | hose = pci_bus_to_hose(bus); |
| 862 | if (!hose) |
| 863 | return 0; |
| 864 | return hose->pci_mem_offset; |
| 865 | } |
| 866 | |
| 867 | unsigned long |
| 868 | pci_resource_to_bus(struct pci_dev *pdev, struct resource *res) |
| 869 | { |
| 870 | /* Hack alert again ! See comments in chrp_pci.c |
| 871 | */ |
| 872 | struct pci_controller* hose = |
| 873 | (struct pci_controller *)pdev->sysdata; |
| 874 | if (hose && res->flags & IORESOURCE_MEM) |
| 875 | return res->start - hose->pci_mem_offset; |
| 876 | /* We may want to do something with IOs here... */ |
| 877 | return res->start; |
| 878 | } |
| 879 | |
| 880 | |
| 881 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, |
| 882 | unsigned long *offset, |
| 883 | enum pci_mmap_state mmap_state) |
| 884 | { |
| 885 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); |
| 886 | unsigned long io_offset = 0; |
| 887 | int i, res_bit; |
| 888 | |
| 889 | if (hose == 0) |
| 890 | return NULL; /* should never happen */ |
| 891 | |
| 892 | /* If memory, add on the PCI bridge address offset */ |
| 893 | if (mmap_state == pci_mmap_mem) { |
| 894 | *offset += hose->pci_mem_offset; |
| 895 | res_bit = IORESOURCE_MEM; |
| 896 | } else { |
Michael Ellerman | 2311b1f | 2005-05-13 17:44:10 +1000 | [diff] [blame] | 897 | io_offset = hose->io_base_virt - ___IO_BASE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 898 | *offset += io_offset; |
| 899 | res_bit = IORESOURCE_IO; |
| 900 | } |
| 901 | |
| 902 | /* |
| 903 | * Check that the offset requested corresponds to one of the |
| 904 | * resources of the device. |
| 905 | */ |
| 906 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 907 | struct resource *rp = &dev->resource[i]; |
| 908 | int flags = rp->flags; |
| 909 | |
| 910 | /* treat ROM as memory (should be already) */ |
| 911 | if (i == PCI_ROM_RESOURCE) |
| 912 | flags |= IORESOURCE_MEM; |
| 913 | |
| 914 | /* Active and same type? */ |
| 915 | if ((flags & res_bit) == 0) |
| 916 | continue; |
| 917 | |
| 918 | /* In the range of this resource? */ |
| 919 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) |
| 920 | continue; |
| 921 | |
| 922 | /* found it! construct the final physical address */ |
| 923 | if (mmap_state == pci_mmap_io) |
Michael Ellerman | 2311b1f | 2005-05-13 17:44:10 +1000 | [diff] [blame] | 924 | *offset += hose->io_base_phys - io_offset; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 925 | return rp; |
| 926 | } |
| 927 | |
| 928 | return NULL; |
| 929 | } |
| 930 | |
| 931 | /* |
| 932 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci |
| 933 | * device mapping. |
| 934 | */ |
| 935 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, |
| 936 | pgprot_t protection, |
| 937 | enum pci_mmap_state mmap_state, |
| 938 | int write_combine) |
| 939 | { |
| 940 | unsigned long prot = pgprot_val(protection); |
| 941 | |
| 942 | /* Write combine is always 0 on non-memory space mappings. On |
| 943 | * memory space, if the user didn't pass 1, we check for a |
| 944 | * "prefetchable" resource. This is a bit hackish, but we use |
| 945 | * this to workaround the inability of /sysfs to provide a write |
| 946 | * combine bit |
| 947 | */ |
| 948 | if (mmap_state != pci_mmap_mem) |
| 949 | write_combine = 0; |
| 950 | else if (write_combine == 0) { |
| 951 | if (rp->flags & IORESOURCE_PREFETCH) |
| 952 | write_combine = 1; |
| 953 | } |
| 954 | |
| 955 | /* XXX would be nice to have a way to ask for write-through */ |
| 956 | prot |= _PAGE_NO_CACHE; |
| 957 | if (write_combine) |
| 958 | prot &= ~_PAGE_GUARDED; |
| 959 | else |
| 960 | prot |= _PAGE_GUARDED; |
| 961 | |
Greg Kroah-Hartman | e31dd6e | 2006-06-12 17:06:02 -0700 | [diff] [blame] | 962 | printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev), |
| 963 | (unsigned long long)rp->start, prot); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | |
| 965 | return __pgprot(prot); |
| 966 | } |
| 967 | |
| 968 | /* |
| 969 | * This one is used by /dev/mem and fbdev who have no clue about the |
| 970 | * PCI device, it tries to find the PCI device first and calls the |
| 971 | * above routine |
| 972 | */ |
| 973 | pgprot_t pci_phys_mem_access_prot(struct file *file, |
Roland Dreier | 8b15047 | 2005-10-28 17:46:18 -0700 | [diff] [blame] | 974 | unsigned long pfn, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | unsigned long size, |
| 976 | pgprot_t protection) |
| 977 | { |
| 978 | struct pci_dev *pdev = NULL; |
| 979 | struct resource *found = NULL; |
| 980 | unsigned long prot = pgprot_val(protection); |
Roland Dreier | 8b15047 | 2005-10-28 17:46:18 -0700 | [diff] [blame] | 981 | unsigned long offset = pfn << PAGE_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 982 | int i; |
| 983 | |
Roland Dreier | 8b15047 | 2005-10-28 17:46:18 -0700 | [diff] [blame] | 984 | if (page_is_ram(pfn)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | return prot; |
| 986 | |
| 987 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; |
| 988 | |
| 989 | for_each_pci_dev(pdev) { |
| 990 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 991 | struct resource *rp = &pdev->resource[i]; |
| 992 | int flags = rp->flags; |
| 993 | |
| 994 | /* Active and same type? */ |
| 995 | if ((flags & IORESOURCE_MEM) == 0) |
| 996 | continue; |
| 997 | /* In the range of this resource? */ |
| 998 | if (offset < (rp->start & PAGE_MASK) || |
| 999 | offset > rp->end) |
| 1000 | continue; |
| 1001 | found = rp; |
| 1002 | break; |
| 1003 | } |
| 1004 | if (found) |
| 1005 | break; |
| 1006 | } |
| 1007 | if (found) { |
| 1008 | if (found->flags & IORESOURCE_PREFETCH) |
| 1009 | prot &= ~_PAGE_GUARDED; |
| 1010 | pci_dev_put(pdev); |
| 1011 | } |
| 1012 | |
| 1013 | DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); |
| 1014 | |
| 1015 | return __pgprot(prot); |
| 1016 | } |
| 1017 | |
| 1018 | |
| 1019 | /* |
| 1020 | * Perform the actual remap of the pages for a PCI device mapping, as |
| 1021 | * appropriate for this architecture. The region in the process to map |
| 1022 | * is described by vm_start and vm_end members of VMA, the base physical |
| 1023 | * address is found in vm_pgoff. |
| 1024 | * The pci device structure is provided so that architectures may make mapping |
| 1025 | * decisions on a per-device or per-bus basis. |
| 1026 | * |
| 1027 | * Returns a negative error code on failure, zero on success. |
| 1028 | */ |
| 1029 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
| 1030 | enum pci_mmap_state mmap_state, |
| 1031 | int write_combine) |
| 1032 | { |
| 1033 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; |
| 1034 | struct resource *rp; |
| 1035 | int ret; |
| 1036 | |
| 1037 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); |
| 1038 | if (rp == NULL) |
| 1039 | return -EINVAL; |
| 1040 | |
| 1041 | vma->vm_pgoff = offset >> PAGE_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1042 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, |
| 1043 | vma->vm_page_prot, |
| 1044 | mmap_state, write_combine); |
| 1045 | |
| 1046 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
| 1047 | vma->vm_end - vma->vm_start, vma->vm_page_prot); |
| 1048 | |
| 1049 | return ret; |
| 1050 | } |
| 1051 | |
| 1052 | /* Obsolete functions. Should be removed once the symbios driver |
| 1053 | * is fixed |
| 1054 | */ |
| 1055 | unsigned long |
| 1056 | phys_to_bus(unsigned long pa) |
| 1057 | { |
| 1058 | struct pci_controller *hose; |
| 1059 | int i; |
| 1060 | |
| 1061 | for (hose = hose_head; hose; hose = hose->next) { |
| 1062 | for (i = 0; i < 3; ++i) { |
| 1063 | if (pa >= hose->mem_resources[i].start |
| 1064 | && pa <= hose->mem_resources[i].end) { |
| 1065 | /* |
| 1066 | * XXX the hose->pci_mem_offset really |
| 1067 | * only applies to mem_resources[0]. |
| 1068 | * We need a way to store an offset for |
| 1069 | * the others. -- paulus |
| 1070 | */ |
| 1071 | if (i == 0) |
| 1072 | pa -= hose->pci_mem_offset; |
| 1073 | return pa; |
| 1074 | } |
| 1075 | } |
| 1076 | } |
| 1077 | /* hmmm, didn't find it */ |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
| 1081 | unsigned long |
| 1082 | pci_phys_to_bus(unsigned long pa, int busnr) |
| 1083 | { |
| 1084 | struct pci_controller* hose = pci_bus_to_hose(busnr); |
| 1085 | if (!hose) |
| 1086 | return pa; |
| 1087 | return pa - hose->pci_mem_offset; |
| 1088 | } |
| 1089 | |
| 1090 | unsigned long |
| 1091 | pci_bus_to_phys(unsigned int ba, int busnr) |
| 1092 | { |
| 1093 | struct pci_controller* hose = pci_bus_to_hose(busnr); |
| 1094 | if (!hose) |
| 1095 | return ba; |
| 1096 | return ba + hose->pci_mem_offset; |
| 1097 | } |
| 1098 | |
| 1099 | /* Provide information on locations of various I/O regions in physical |
| 1100 | * memory. Do this on a per-card basis so that we choose the right |
| 1101 | * root bridge. |
| 1102 | * Note that the returned IO or memory base is a physical address |
| 1103 | */ |
| 1104 | |
| 1105 | long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) |
| 1106 | { |
| 1107 | struct pci_controller* hose; |
| 1108 | long result = -EOPNOTSUPP; |
| 1109 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1110 | hose = pci_bus_to_hose(bus); |
| 1111 | if (!hose) |
| 1112 | return -ENODEV; |
| 1113 | |
| 1114 | switch (which) { |
| 1115 | case IOBASE_BRIDGE_NUMBER: |
| 1116 | return (long)hose->first_busno; |
| 1117 | case IOBASE_MEMORY: |
| 1118 | return (long)hose->pci_mem_offset; |
| 1119 | case IOBASE_IO: |
| 1120 | return (long)hose->io_base_phys; |
| 1121 | case IOBASE_ISA_IO: |
| 1122 | return (long)isa_io_base; |
| 1123 | case IOBASE_ISA_MEM: |
| 1124 | return (long)isa_mem_base; |
| 1125 | } |
| 1126 | |
| 1127 | return result; |
| 1128 | } |
| 1129 | |
Michael Ellerman | 2311b1f | 2005-05-13 17:44:10 +1000 | [diff] [blame] | 1130 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
| 1131 | const struct resource *rsrc, |
Greg Kroah-Hartman | e31dd6e | 2006-06-12 17:06:02 -0700 | [diff] [blame] | 1132 | resource_size_t *start, resource_size_t *end) |
Michael Ellerman | 2311b1f | 2005-05-13 17:44:10 +1000 | [diff] [blame] | 1133 | { |
| 1134 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); |
| 1135 | unsigned long offset = 0; |
| 1136 | |
| 1137 | if (hose == NULL) |
| 1138 | return; |
| 1139 | |
| 1140 | if (rsrc->flags & IORESOURCE_IO) |
| 1141 | offset = ___IO_BASE - hose->io_base_virt + hose->io_base_phys; |
| 1142 | |
| 1143 | *start = rsrc->start + offset; |
| 1144 | *end = rsrc->end + offset; |
| 1145 | } |
| 1146 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1147 | void __init |
| 1148 | pci_init_resource(struct resource *res, unsigned long start, unsigned long end, |
| 1149 | int flags, char *name) |
| 1150 | { |
| 1151 | res->start = start; |
| 1152 | res->end = end; |
| 1153 | res->flags = flags; |
| 1154 | res->name = name; |
| 1155 | res->parent = NULL; |
| 1156 | res->sibling = NULL; |
| 1157 | res->child = NULL; |
| 1158 | } |
| 1159 | |
| 1160 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max) |
| 1161 | { |
| 1162 | unsigned long start = pci_resource_start(dev, bar); |
| 1163 | unsigned long len = pci_resource_len(dev, bar); |
| 1164 | unsigned long flags = pci_resource_flags(dev, bar); |
| 1165 | |
| 1166 | if (!len) |
| 1167 | return NULL; |
| 1168 | if (max && len > max) |
| 1169 | len = max; |
| 1170 | if (flags & IORESOURCE_IO) |
| 1171 | return ioport_map(start, len); |
| 1172 | if (flags & IORESOURCE_MEM) |
| 1173 | /* Not checking IORESOURCE_CACHEABLE because PPC does |
| 1174 | * not currently distinguish between ioremap and |
| 1175 | * ioremap_nocache. |
| 1176 | */ |
| 1177 | return ioremap(start, len); |
| 1178 | /* What? */ |
| 1179 | return NULL; |
| 1180 | } |
| 1181 | |
| 1182 | void pci_iounmap(struct pci_dev *dev, void __iomem *addr) |
| 1183 | { |
| 1184 | /* Nothing to do */ |
| 1185 | } |
| 1186 | EXPORT_SYMBOL(pci_iomap); |
| 1187 | EXPORT_SYMBOL(pci_iounmap); |
| 1188 | |
Benjamin Herrenschmidt | f2c4583 | 2005-12-15 15:00:57 +1100 | [diff] [blame] | 1189 | unsigned long pci_address_to_pio(phys_addr_t address) |
Benjamin Herrenschmidt | d2dd482 | 2005-11-30 16:57:28 +1100 | [diff] [blame] | 1190 | { |
| 1191 | struct pci_controller* hose = hose_head; |
| 1192 | |
| 1193 | for (; hose; hose = hose->next) { |
| 1194 | unsigned int size = hose->io_resource.end - |
| 1195 | hose->io_resource.start + 1; |
| 1196 | if (address >= hose->io_base_phys && |
Benjamin Herrenschmidt | f2c4583 | 2005-12-15 15:00:57 +1100 | [diff] [blame] | 1197 | address < (hose->io_base_phys + size)) { |
| 1198 | unsigned long base = |
| 1199 | (unsigned long)hose->io_base_virt - _IO_BASE; |
| 1200 | return base + (address - hose->io_base_phys); |
Kumar Gala | e5cd040 | 2005-12-19 15:49:07 -0600 | [diff] [blame] | 1201 | } |
Benjamin Herrenschmidt | d2dd482 | 2005-11-30 16:57:28 +1100 | [diff] [blame] | 1202 | } |
| 1203 | return (unsigned int)-1; |
| 1204 | } |
| 1205 | EXPORT_SYMBOL(pci_address_to_pio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1206 | |
| 1207 | /* |
| 1208 | * Null PCI config access functions, for the case when we can't |
| 1209 | * find a hose. |
| 1210 | */ |
| 1211 | #define NULL_PCI_OP(rw, size, type) \ |
| 1212 | static int \ |
| 1213 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ |
| 1214 | { \ |
| 1215 | return PCIBIOS_DEVICE_NOT_FOUND; \ |
| 1216 | } |
| 1217 | |
| 1218 | static int |
| 1219 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 1220 | int len, u32 *val) |
| 1221 | { |
| 1222 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 1223 | } |
| 1224 | |
| 1225 | static int |
| 1226 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, |
| 1227 | int len, u32 val) |
| 1228 | { |
| 1229 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 1230 | } |
| 1231 | |
| 1232 | static struct pci_ops null_pci_ops = |
| 1233 | { |
| 1234 | null_read_config, |
| 1235 | null_write_config |
| 1236 | }; |
| 1237 | |
| 1238 | /* |
| 1239 | * These functions are used early on before PCI scanning is done |
| 1240 | * and all of the pci_dev and pci_bus structures have been created. |
| 1241 | */ |
| 1242 | static struct pci_bus * |
| 1243 | fake_pci_bus(struct pci_controller *hose, int busnr) |
| 1244 | { |
| 1245 | static struct pci_bus bus; |
| 1246 | |
| 1247 | if (hose == 0) { |
| 1248 | hose = pci_bus_to_hose(busnr); |
| 1249 | if (hose == 0) |
| 1250 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); |
| 1251 | } |
| 1252 | bus.number = busnr; |
| 1253 | bus.sysdata = hose; |
| 1254 | bus.ops = hose? hose->ops: &null_pci_ops; |
| 1255 | return &bus; |
| 1256 | } |
| 1257 | |
| 1258 | #define EARLY_PCI_OP(rw, size, type) \ |
| 1259 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ |
| 1260 | int devfn, int offset, type value) \ |
| 1261 | { \ |
| 1262 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ |
| 1263 | devfn, offset, value); \ |
| 1264 | } |
| 1265 | |
| 1266 | EARLY_PCI_OP(read, byte, u8 *) |
| 1267 | EARLY_PCI_OP(read, word, u16 *) |
| 1268 | EARLY_PCI_OP(read, dword, u32 *) |
| 1269 | EARLY_PCI_OP(write, byte, u8) |
| 1270 | EARLY_PCI_OP(write, word, u16) |
| 1271 | EARLY_PCI_OP(write, dword, u32) |