Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * PCIe driver for Renesas R-Car SoCs |
| 4 | * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd |
| 5 | * |
| 6 | * Author: Phil Edworthy <phil.edworthy@renesas.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef _PCIE_RCAR_H |
| 10 | #define _PCIE_RCAR_H |
| 11 | |
| 12 | #define PCIECAR 0x000010 |
| 13 | #define PCIECCTLR 0x000018 |
Lukas Bulwahn | 727de4c | 2023-01-13 09:45:16 +0100 | [diff] [blame] | 14 | #define PCIECCTLR_CCIE BIT(31) |
Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 15 | #define TYPE0 (0 << 8) |
| 16 | #define TYPE1 BIT(8) |
| 17 | #define PCIECDR 0x000020 |
| 18 | #define PCIEMSR 0x000028 |
| 19 | #define PCIEINTXR 0x000400 |
Lad Prabhakar | 2a6d0d6 | 2020-05-07 13:33:18 +0100 | [diff] [blame] | 20 | #define ASTINTX BIT(16) |
Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 21 | #define PCIEPHYSR 0x0007f0 |
| 22 | #define PHYRDY BIT(0) |
| 23 | #define PCIEMSITXR 0x000840 |
| 24 | |
| 25 | /* Transfer control */ |
| 26 | #define PCIETCTLR 0x02000 |
| 27 | #define DL_DOWN BIT(3) |
| 28 | #define CFINIT BIT(0) |
| 29 | #define PCIETSTR 0x02004 |
| 30 | #define DATA_LINK_ACTIVE BIT(0) |
| 31 | #define PCIEERRFR 0x02020 |
| 32 | #define UNSUPPORTED_REQUEST BIT(4) |
| 33 | #define PCIEMSIFR 0x02044 |
| 34 | #define PCIEMSIALR 0x02048 |
| 35 | #define MSIFE BIT(0) |
| 36 | #define PCIEMSIAUR 0x0204c |
| 37 | #define PCIEMSIIER 0x02050 |
| 38 | |
| 39 | /* root port address */ |
| 40 | #define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) |
| 41 | |
| 42 | /* local address reg & mask */ |
| 43 | #define PCIELAR(x) (0x02200 + ((x) * 0x20)) |
| 44 | #define PCIELAMR(x) (0x02208 + ((x) * 0x20)) |
| 45 | #define LAM_PREFETCH BIT(3) |
| 46 | #define LAM_64BIT BIT(2) |
| 47 | #define LAR_ENABLE BIT(1) |
| 48 | |
| 49 | /* PCIe address reg & mask */ |
| 50 | #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) |
| 51 | #define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) |
| 52 | #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) |
| 53 | #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) |
| 54 | #define PAR_ENABLE BIT(31) |
| 55 | #define IO_SPACE BIT(8) |
| 56 | |
| 57 | /* Configuration */ |
| 58 | #define PCICONF(x) (0x010000 + ((x) * 0x4)) |
Lad Prabhakar | 2a6d0d6 | 2020-05-07 13:33:18 +0100 | [diff] [blame] | 59 | #define INTDIS BIT(10) |
Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 60 | #define PMCAP(x) (0x010040 + ((x) * 0x4)) |
Lad Prabhakar | 2a6d0d6 | 2020-05-07 13:33:18 +0100 | [diff] [blame] | 61 | #define MSICAP(x) (0x010050 + ((x) * 0x4)) |
| 62 | #define MSICAP0_MSIE BIT(16) |
| 63 | #define MSICAP0_MMESCAP_OFFSET 17 |
| 64 | #define MSICAP0_MMESE_OFFSET 20 |
| 65 | #define MSICAP0_MMESE_MASK GENMASK(22, 20) |
Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 66 | #define EXPCAP(x) (0x010070 + ((x) * 0x4)) |
| 67 | #define VCCAP(x) (0x010100 + ((x) * 0x4)) |
| 68 | |
| 69 | /* link layer */ |
Lad Prabhakar | 2a6d0d6 | 2020-05-07 13:33:18 +0100 | [diff] [blame] | 70 | #define IDSETR0 0x011000 |
Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 71 | #define IDSETR1 0x011004 |
Lad Prabhakar | 2a6d0d6 | 2020-05-07 13:33:18 +0100 | [diff] [blame] | 72 | #define SUBIDSETR 0x011024 |
Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 73 | #define TLCTLR 0x011048 |
| 74 | #define MACSR 0x011054 |
| 75 | #define SPCHGFIN BIT(4) |
| 76 | #define SPCHGFAIL BIT(6) |
| 77 | #define SPCHGSUC BIT(7) |
| 78 | #define LINK_SPEED (0xf << 16) |
| 79 | #define LINK_SPEED_2_5GTS (1 << 16) |
| 80 | #define LINK_SPEED_5_0GTS (2 << 16) |
| 81 | #define MACCTLR 0x011058 |
| 82 | #define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */ |
| 83 | #define SPEED_CHANGE BIT(24) |
| 84 | #define SCRAMBLE_DISABLE BIT(27) |
| 85 | #define LTSMDIS BIT(31) |
| 86 | #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK) |
| 87 | #define PMSR 0x01105c |
Marek Vasut | a115b1b | 2021-08-15 20:16:50 +0200 | [diff] [blame] | 88 | #define L1FAEG BIT(31) |
| 89 | #define PMEL1RX BIT(23) |
| 90 | #define PMSTATE GENMASK(18, 16) |
| 91 | #define PMSTATE_L1 (3 << 16) |
| 92 | #define PMCTLR 0x011060 |
| 93 | #define L1IATN BIT(31) |
| 94 | |
Lad Prabhakar | 78a0d7f | 2020-05-07 13:33:13 +0100 | [diff] [blame] | 95 | #define MACS2R 0x011078 |
| 96 | #define MACCGSPSETR 0x011084 |
| 97 | #define SPCNGRSN BIT(31) |
| 98 | |
| 99 | /* R-Car H1 PHY */ |
| 100 | #define H1_PCIEPHYADRR 0x04000c |
| 101 | #define WRITE_CMD BIT(16) |
| 102 | #define PHY_ACK BIT(24) |
| 103 | #define RATE_POS 12 |
| 104 | #define LANE_POS 8 |
| 105 | #define ADR_POS 0 |
| 106 | #define H1_PCIEPHYDOUTR 0x040014 |
| 107 | |
| 108 | /* R-Car Gen2 PHY */ |
| 109 | #define GEN2_PCIEPHYADDR 0x780 |
| 110 | #define GEN2_PCIEPHYDATA 0x784 |
| 111 | #define GEN2_PCIEPHYCTRL 0x78c |
| 112 | |
| 113 | #define INT_PCI_MSI_NR 32 |
| 114 | |
| 115 | #define RCONF(x) (PCICONF(0) + (x)) |
| 116 | #define RPMCAP(x) (PMCAP(0) + (x)) |
| 117 | #define REXPCAP(x) (EXPCAP(0) + (x)) |
| 118 | #define RVCCAP(x) (VCCAP(0) + (x)) |
| 119 | |
| 120 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24) |
| 121 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19) |
| 122 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16) |
| 123 | |
| 124 | #define RCAR_PCI_MAX_RESOURCES 4 |
| 125 | #define MAX_NR_INBOUND_MAPS 6 |
| 126 | |
| 127 | struct rcar_pcie { |
| 128 | struct device *dev; |
| 129 | void __iomem *base; |
| 130 | }; |
| 131 | |
| 132 | enum { |
| 133 | RCAR_PCI_ACCESS_READ, |
| 134 | RCAR_PCI_ACCESS_WRITE, |
| 135 | }; |
| 136 | |
| 137 | void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg); |
| 138 | u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg); |
| 139 | void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data); |
| 140 | int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie); |
| 141 | int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie); |
| 142 | void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win, |
| 143 | struct resource_entry *window); |
| 144 | void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr, |
| 145 | u64 pci_addr, u64 flags, int idx, bool host); |
| 146 | |
| 147 | #endif |