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Krzysztof Kozlowski347863d2017-12-25 20:54:31 +01001// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2014 Samsung Electronics Co., Ltd.
3// http://www.samsung.com
4//
5// Based on arch/arm/mach-vexpress/dcscb.c
Abhilash Kesavanccf55112014-05-16 04:26:30 +09006
7#include <linux/arm-cci.h>
8#include <linux/delay.h>
9#include <linux/io.h>
10#include <linux/of_address.h>
Abhilash Kesavanadc548d2014-11-07 09:20:16 +090011#include <linux/syscore_ops.h>
Pankaj Dubey2262d6e2015-12-18 09:02:11 +053012#include <linux/soc/samsung/exynos-regs-pmu.h>
Abhilash Kesavanccf55112014-05-16 04:26:30 +090013
14#include <asm/cputype.h>
15#include <asm/cp15.h>
16#include <asm/mcpm.h>
Chanho Park833b5792015-09-01 23:17:03 +090017#include <asm/smp_plat.h>
Abhilash Kesavanccf55112014-05-16 04:26:30 +090018
Abhilash Kesavanccf55112014-05-16 04:26:30 +090019#include "common.h"
20
21#define EXYNOS5420_CPUS_PER_CLUSTER 4
22#define EXYNOS5420_NR_CLUSTERS 2
Abhilash Kesavanccf55112014-05-16 04:26:30 +090023
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +090024#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
25#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
26#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
27
Krzysztof Kozlowski731d97c2016-12-10 15:47:33 +020028static void __iomem *ns_sram_base_addr __ro_after_init;
Marek Szyprowskiea9dd8f2020-06-29 12:02:18 +020029static bool secure_firmware __ro_after_init;
Abhilash Kesavanadc548d2014-11-07 09:20:16 +090030
Abhilash Kesavanccf55112014-05-16 04:26:30 +090031/*
32 * The common v7_exit_coherency_flush API could not be used because of the
33 * Erratum 799270 workaround. This macro is the same as the common one (in
34 * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
35 */
36#define exynos_v7_exit_coherency_flush(level) \
37 asm volatile( \
38 "stmfd sp!, {fp, ip}\n\t"\
39 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
40 "bic r0, r0, #"__stringify(CR_C)"\n\t" \
41 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
42 "isb\n\t"\
43 "bl v7_flush_dcache_"__stringify(level)"\n\t" \
Abhilash Kesavanccf55112014-05-16 04:26:30 +090044 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
45 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
46 /* Dummy Load of a device register to avoid Erratum 799270 */ \
47 "ldr r4, [%0]\n\t" \
48 "and r4, r4, #0\n\t" \
49 "orr r0, r0, r4\n\t" \
50 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \
51 "isb\n\t" \
52 "dsb\n\t" \
53 "ldmfd sp!, {fp, ip}" \
54 : \
Pankaj Dubey2e94ac42014-07-19 03:43:22 +090055 : "Ir" (pmu_base_addr + S5P_INFORM0) \
Abhilash Kesavanccf55112014-05-16 04:26:30 +090056 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
57 "r9", "r10", "lr", "memory")
58
Nicolas Pitre5f493ac2015-03-16 17:16:07 -040059static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
Abhilash Kesavanccf55112014-05-16 04:26:30 +090060{
61 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
Marek Szyprowskiea9dd8f2020-06-29 12:02:18 +020062 bool state;
Abhilash Kesavanccf55112014-05-16 04:26:30 +090063
64 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
65 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
66 cluster >= EXYNOS5420_NR_CLUSTERS)
67 return -EINVAL;
68
Marek Szyprowskiea9dd8f2020-06-29 12:02:18 +020069 state = exynos_cpu_power_state(cpunr);
70 exynos_cpu_power_up(cpunr);
71 if (!state && secure_firmware) {
Chanho Park833b5792015-09-01 23:17:03 +090072 /*
73 * This assumes the cluster number of the big cores(Cortex A15)
74 * is 0 and the Little cores(Cortex A7) is 1.
75 * When the system was booted from the Little core,
76 * they should be reset during power up cpu.
77 */
78 if (cluster &&
79 cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
Marek Szyprowski98a33082019-03-26 15:03:59 +010080 unsigned int timeout = 16;
81
Chanho Park833b5792015-09-01 23:17:03 +090082 /*
83 * Before we reset the Little cores, we should wait
84 * the SPARE2 register is set to 1 because the init
85 * codes of the iROM will set the register after
86 * initialization.
87 */
Marek Szyprowski98a33082019-03-26 15:03:59 +010088 while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
89 timeout--;
Chanho Park833b5792015-09-01 23:17:03 +090090 udelay(10);
Marek Szyprowski98a33082019-03-26 15:03:59 +010091 }
92
93 if (timeout == 0) {
94 pr_err("cpu %u cluster %u powerup failed\n",
95 cpu, cluster);
96 exynos_cpu_power_down(cpunr);
97 return -ETIMEDOUT;
98 }
Chanho Park833b5792015-09-01 23:17:03 +090099
100 pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
101 EXYNOS_SWRESET);
102 }
103 }
104
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900105 return 0;
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900106}
107
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400108static int exynos_cluster_powerup(unsigned int cluster)
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900109{
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400110 pr_debug("%s: cluster %u\n", __func__, cluster);
111 if (cluster >= EXYNOS5420_NR_CLUSTERS)
112 return -EINVAL;
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900113
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400114 exynos_cluster_power_up(cluster);
115 return 0;
116}
117
118static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
119{
120 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900121
122 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
123 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
124 cluster >= EXYNOS5420_NR_CLUSTERS);
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400125 exynos_cpu_power_down(cpunr);
126}
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900127
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400128static void exynos_cluster_powerdown_prepare(unsigned int cluster)
129{
130 pr_debug("%s: cluster %u\n", __func__, cluster);
131 BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
132 exynos_cluster_power_down(cluster);
133}
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900134
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400135static void exynos_cpu_cache_disable(void)
136{
137 /* Disable and flush the local CPU cache. */
138 exynos_v7_exit_coherency_flush(louis);
139}
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900140
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400141static void exynos_cluster_cache_disable(void)
142{
143 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900144 /*
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400145 * On the Cortex-A15 we need to disable
146 * L2 prefetching before flushing the cache.
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900147 */
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400148 asm volatile(
149 "mcr p15, 1, %0, c15, c0, 3\n\t"
150 "isb\n\t"
151 "dsb"
152 : : "r" (0x400));
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900153 }
154
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400155 /* Flush all cache levels for this cluster. */
156 exynos_v7_exit_coherency_flush(all);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900157
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400158 /*
159 * Disable cluster-level coherency by masking
160 * incoming snoops and DVM messages:
161 */
162 cci_disable_port_by_cpu(read_cpuid_mpidr());
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900163}
164
Kukjin Kim7c5688e2014-05-28 00:04:34 +0900165static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900166{
167 unsigned int tries = 100;
168 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
169
170 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
171 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
172 cluster >= EXYNOS5420_NR_CLUSTERS);
173
174 /* Wait for the core state to be OFF */
175 while (tries--) {
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400176 if ((exynos_cpu_power_state(cpunr) == 0))
177 return 0; /* success: the CPU is halted */
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900178
179 /* Otherwise, wait and retry: */
180 msleep(1);
181 }
182
183 return -ETIMEDOUT; /* timeout */
184}
185
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400186static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
Chander Kashyapfc2cac42014-07-05 06:24:35 +0900187{
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400188 /* especially when resuming: make sure power control is set */
189 exynos_cpu_powerup(cpu, cluster);
Chander Kashyapfc2cac42014-07-05 06:24:35 +0900190}
191
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900192static const struct mcpm_platform_ops exynos_power_ops = {
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400193 .cpu_powerup = exynos_cpu_powerup,
194 .cluster_powerup = exynos_cluster_powerup,
195 .cpu_powerdown_prepare = exynos_cpu_powerdown_prepare,
196 .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
197 .cpu_cache_disable = exynos_cpu_cache_disable,
198 .cluster_cache_disable = exynos_cluster_cache_disable,
Kukjin Kim7c5688e2014-05-28 00:04:34 +0900199 .wait_for_powerdown = exynos_wait_for_powerdown,
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400200 .cpu_is_up = exynos_cpu_is_up,
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900201};
202
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900203/*
204 * Enable cluster-level coherency, in preparation for turning on the MMU.
205 */
206static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
207{
208 asm volatile ("\n"
209 "cmp r0, #1\n"
210 "bxne lr\n"
211 "b cci_enable_port_for_self");
212}
213
Abhilash Kesavanf99acff2014-05-28 01:19:35 +0900214static const struct of_device_id exynos_dt_mcpm_match[] = {
215 { .compatible = "samsung,exynos5420" },
216 { .compatible = "samsung,exynos5800" },
217 {},
218};
219
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900220static void exynos_mcpm_setup_entry_point(void)
221{
222 /*
223 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
224 * as part of secondary_cpu_start(). Let's redirect it to the
225 * mcpm_entry_point(). This is done during both secondary boot-up as
226 * well as system resume.
227 */
228 __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
229 __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
Florian Fainelli64fc2a92017-01-15 03:59:29 +0100230 __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900231}
232
233static struct syscore_ops exynos_mcpm_syscore_ops = {
234 .resume = exynos_mcpm_setup_entry_point,
235};
236
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900237static int __init exynos_mcpm_init(void)
238{
239 struct device_node *node;
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900240 unsigned int value, i;
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900241 int ret;
242
Abhilash Kesavanf99acff2014-05-28 01:19:35 +0900243 node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900244 if (!node)
245 return -ENODEV;
246 of_node_put(node);
247
248 if (!cci_probed())
249 return -ENODEV;
250
251 node = of_find_compatible_node(NULL, NULL,
252 "samsung,exynos4210-sysram-ns");
253 if (!node)
254 return -ENODEV;
255
256 ns_sram_base_addr = of_iomap(node, 0);
257 of_node_put(node);
258 if (!ns_sram_base_addr) {
259 pr_err("failed to map non-secure iRAM base address\n");
260 return -ENOMEM;
261 }
262
Marek Szyprowskiea9dd8f2020-06-29 12:02:18 +0200263 secure_firmware = exynos_secure_firmware_available();
264
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900265 /*
266 * To increase the stability of KFC reset we need to program
267 * the PMU SPARE3 register
268 */
Pankaj Dubey2e94ac42014-07-19 03:43:22 +0900269 pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900270
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900271 ret = mcpm_platform_register(&exynos_power_ops);
272 if (!ret)
273 ret = mcpm_sync_init(exynos_pm_power_up_setup);
Nicolas Pitrefbb04992014-06-24 18:36:32 +0100274 if (!ret)
Nicolas Pitre5f493ac2015-03-16 17:16:07 -0400275 ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900276 if (ret) {
277 iounmap(ns_sram_base_addr);
278 return ret;
279 }
280
281 mcpm_smp_set_ops();
282
283 pr_info("Exynos MCPM support installed\n");
284
285 /*
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900286 * On Exynos5420/5800 for the A15 and A7 clusters:
287 *
288 * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
289 * in a cluster are turned off before turning off the cluster L2.
290 *
291 * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
292 * off before waking it up.
293 *
294 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
295 * turned on before the first man is powered up.
296 */
297 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
Pankaj Dubey2e94ac42014-07-19 03:43:22 +0900298 value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900299 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
300 EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
301 EXYNOS5420_USE_L2_COMMON_UP_STATE;
Pankaj Dubey2e94ac42014-07-19 03:43:22 +0900302 pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
Abhilash Kesavan20fe6f92014-07-05 05:50:58 +0900303 }
304
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900305 exynos_mcpm_setup_entry_point();
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900306
Abhilash Kesavanadc548d2014-11-07 09:20:16 +0900307 register_syscore_ops(&exynos_mcpm_syscore_ops);
Abhilash Kesavanccf55112014-05-16 04:26:30 +0900308
309 return ret;
310}
311
312early_initcall(exynos_mcpm_init);