Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | * |
| 19 | * |
| 20 | * File: mac.h |
| 21 | * |
| 22 | * Purpose: MAC routines |
| 23 | * |
| 24 | * Author: Tevin Chen |
| 25 | * |
| 26 | * Date: May 21, 1996 |
Jim Lieb | 612822f | 2009-08-12 14:54:03 -0700 | [diff] [blame] | 27 | * |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 28 | * Revision History: |
| 29 | * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. |
| 30 | * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. |
| 31 | * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 32 | */ |
| 33 | |
| 34 | #ifndef __MAC_H__ |
| 35 | #define __MAC_H__ |
| 36 | |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 37 | #include "ttype.h" |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 38 | #include "tmacro.h" |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 39 | #include "upc.h" |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 40 | |
| 41 | /*--------------------- Export Definitions -------------------------*/ |
| 42 | // |
| 43 | // Registers in the MAC |
| 44 | // |
| 45 | #define MAC_MAX_CONTEXT_SIZE_PAGE0 256 |
| 46 | #define MAC_MAX_CONTEXT_SIZE_PAGE1 128 |
| 47 | #define MAC_MAX_CONTEXT_SIZE MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1 |
| 48 | |
| 49 | // Registers not related to 802.11b |
| 50 | #define MAC_REG_BCFG0 0x00 |
| 51 | #define MAC_REG_BCFG1 0x01 |
| 52 | #define MAC_REG_FCR0 0x02 |
| 53 | #define MAC_REG_FCR1 0x03 |
| 54 | #define MAC_REG_BISTCMD 0x04 |
| 55 | #define MAC_REG_BISTSR0 0x05 |
| 56 | #define MAC_REG_BISTSR1 0x06 |
| 57 | #define MAC_REG_BISTSR2 0x07 |
| 58 | #define MAC_REG_I2MCSR 0x08 |
| 59 | #define MAC_REG_I2MTGID 0x09 |
| 60 | #define MAC_REG_I2MTGAD 0x0A |
| 61 | #define MAC_REG_I2MCFG 0x0B |
| 62 | #define MAC_REG_I2MDIPT 0x0C |
| 63 | #define MAC_REG_I2MDOPT 0x0E |
| 64 | #define MAC_REG_PMC0 0x10 |
| 65 | #define MAC_REG_PMC1 0x11 |
| 66 | #define MAC_REG_STICKHW 0x12 |
| 67 | #define MAC_REG_LOCALID 0x14 |
| 68 | #define MAC_REG_TESTCFG 0x15 |
| 69 | #define MAC_REG_JUMPER0 0x16 |
| 70 | #define MAC_REG_JUMPER1 0x17 |
| 71 | #define MAC_REG_TMCTL0 0x18 |
| 72 | #define MAC_REG_TMCTL1 0x19 |
| 73 | #define MAC_REG_TMDATA0 0x1C |
| 74 | // MAC Parameter related |
| 75 | #define MAC_REG_LRT 0x20 // |
| 76 | #define MAC_REG_SRT 0x21 // |
| 77 | #define MAC_REG_SIFS 0x22 // |
| 78 | #define MAC_REG_DIFS 0x23 // |
| 79 | #define MAC_REG_EIFS 0x24 // |
| 80 | #define MAC_REG_SLOT 0x25 // |
| 81 | #define MAC_REG_BI 0x26 // |
| 82 | #define MAC_REG_CWMAXMIN0 0x28 // |
| 83 | #define MAC_REG_LINKOFFTOTM 0x2A |
| 84 | #define MAC_REG_SWTMOT 0x2B |
| 85 | #define MAC_REG_MIBCNTR 0x2C |
| 86 | #define MAC_REG_RTSOKCNT 0x2C |
| 87 | #define MAC_REG_RTSFAILCNT 0x2D |
| 88 | #define MAC_REG_ACKFAILCNT 0x2E |
| 89 | #define MAC_REG_FCSERRCNT 0x2F |
| 90 | // TSF Related |
| 91 | #define MAC_REG_TSFCNTR 0x30 // |
| 92 | #define MAC_REG_NEXTTBTT 0x38 // |
| 93 | #define MAC_REG_TSFOFST 0x40 // |
| 94 | #define MAC_REG_TFTCTL 0x48 // |
| 95 | // WMAC Control/Status Related |
| 96 | #define MAC_REG_ENCFG 0x4C // |
| 97 | #define MAC_REG_PAGE1SEL 0x4F // |
| 98 | #define MAC_REG_CFG 0x50 // |
| 99 | #define MAC_REG_TEST 0x52 // |
| 100 | #define MAC_REG_HOSTCR 0x54 // |
| 101 | #define MAC_REG_MACCR 0x55 // |
| 102 | #define MAC_REG_RCR 0x56 // |
| 103 | #define MAC_REG_TCR 0x57 // |
| 104 | #define MAC_REG_IMR 0x58 // |
| 105 | #define MAC_REG_ISR 0x5C |
| 106 | // Power Saving Related |
| 107 | #define MAC_REG_PSCFG 0x60 // |
| 108 | #define MAC_REG_PSCTL 0x61 // |
| 109 | #define MAC_REG_PSPWRSIG 0x62 // |
| 110 | #define MAC_REG_BBCR13 0x63 |
| 111 | #define MAC_REG_AIDATIM 0x64 |
| 112 | #define MAC_REG_PWBT 0x66 |
| 113 | #define MAC_REG_WAKEOKTMR 0x68 |
| 114 | #define MAC_REG_CALTMR 0x69 |
| 115 | #define MAC_REG_SYNSPACCNT 0x6A |
| 116 | #define MAC_REG_WAKSYNOPT 0x6B |
| 117 | // Baseband/IF Control Group |
| 118 | #define MAC_REG_BBREGCTL 0x6C // |
| 119 | #define MAC_REG_CHANNEL 0x6D |
| 120 | #define MAC_REG_BBREGADR 0x6E |
| 121 | #define MAC_REG_BBREGDATA 0x6F |
| 122 | #define MAC_REG_IFREGCTL 0x70 // |
| 123 | #define MAC_REG_IFDATA 0x71 // |
| 124 | #define MAC_REG_ITRTMSET 0x74 // |
Jim Lieb | 612822f | 2009-08-12 14:54:03 -0700 | [diff] [blame] | 125 | #define MAC_REG_PAPEDELAY 0x77 |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 126 | #define MAC_REG_SOFTPWRCTL 0x78 // |
| 127 | #define MAC_REG_GPIOCTL0 0x7A // |
| 128 | #define MAC_REG_GPIOCTL1 0x7B // |
| 129 | |
| 130 | // MAC DMA Related Group |
| 131 | #define MAC_REG_TXDMACTL0 0x7C // |
| 132 | #define MAC_REG_TXDMAPTR0 0x80 // |
| 133 | #define MAC_REG_AC0DMACTL 0x84 // |
| 134 | #define MAC_REG_AC0DMAPTR 0x88 // |
| 135 | #define MAC_REG_BCNDMACTL 0x8C // |
| 136 | #define MAC_REG_BCNDMAPTR 0x90 // |
| 137 | #define MAC_REG_RXDMACTL0 0x94 // |
| 138 | #define MAC_REG_RXDMAPTR0 0x98 // |
| 139 | #define MAC_REG_RXDMACTL1 0x9C // |
| 140 | #define MAC_REG_RXDMAPTR1 0xA0 // |
| 141 | #define MAC_REG_SYNCDMACTL 0xA4 // |
| 142 | #define MAC_REG_SYNCDMAPTR 0xA8 |
| 143 | #define MAC_REG_ATIMDMACTL 0xAC |
| 144 | #define MAC_REG_ATIMDMAPTR 0xB0 |
| 145 | // MiscFF PIO related |
| 146 | #define MAC_REG_MISCFFNDEX 0xB4 |
| 147 | #define MAC_REG_MISCFFCTL 0xB6 |
| 148 | #define MAC_REG_MISCFFDATA 0xB8 |
| 149 | // Extend SW Timer |
| 150 | #define MAC_REG_TMDATA1 0xBC |
| 151 | // WOW Related Group |
| 152 | #define MAC_REG_WAKEUPEN0 0xC0 |
| 153 | #define MAC_REG_WAKEUPEN1 0xC1 |
| 154 | #define MAC_REG_WAKEUPSR0 0xC2 |
| 155 | #define MAC_REG_WAKEUPSR1 0xC3 |
| 156 | #define MAC_REG_WAKE128_0 0xC4 |
| 157 | #define MAC_REG_WAKE128_1 0xD4 |
| 158 | #define MAC_REG_WAKE128_2 0xE4 |
| 159 | #define MAC_REG_WAKE128_3 0xF4 |
| 160 | |
| 161 | /////////////// Page 1 /////////////////// |
| 162 | #define MAC_REG_CRC_128_0 0x04 |
| 163 | #define MAC_REG_CRC_128_1 0x06 |
| 164 | #define MAC_REG_CRC_128_2 0x08 |
| 165 | #define MAC_REG_CRC_128_3 0x0A |
| 166 | // MAC Configuration Group |
| 167 | #define MAC_REG_PAR0 0x0C |
| 168 | #define MAC_REG_PAR4 0x10 |
| 169 | #define MAC_REG_BSSID0 0x14 |
| 170 | #define MAC_REG_BSSID4 0x18 |
| 171 | #define MAC_REG_MAR0 0x1C |
| 172 | #define MAC_REG_MAR4 0x20 |
| 173 | // MAC RSPPKT INFO Group |
| 174 | #define MAC_REG_RSPINF_B_1 0x24 |
| 175 | #define MAC_REG_RSPINF_B_2 0x28 |
| 176 | #define MAC_REG_RSPINF_B_5 0x2C |
| 177 | #define MAC_REG_RSPINF_B_11 0x30 |
| 178 | #define MAC_REG_RSPINF_A_6 0x34 |
| 179 | #define MAC_REG_RSPINF_A_9 0x36 |
| 180 | #define MAC_REG_RSPINF_A_12 0x38 |
| 181 | #define MAC_REG_RSPINF_A_18 0x3A |
| 182 | #define MAC_REG_RSPINF_A_24 0x3C |
| 183 | #define MAC_REG_RSPINF_A_36 0x3E |
| 184 | #define MAC_REG_RSPINF_A_48 0x40 |
| 185 | #define MAC_REG_RSPINF_A_54 0x42 |
| 186 | #define MAC_REG_RSPINF_A_72 0x44 |
| 187 | |
| 188 | // 802.11h relative |
| 189 | #define MAC_REG_QUIETINIT 0x60 |
| 190 | #define MAC_REG_QUIETGAP 0x62 |
| 191 | #define MAC_REG_QUIETDUR 0x64 |
| 192 | #define MAC_REG_MSRCTL 0x66 |
| 193 | #define MAC_REG_MSRBBSTS 0x67 |
| 194 | #define MAC_REG_MSRSTART 0x68 |
| 195 | #define MAC_REG_MSRDURATION 0x70 |
| 196 | #define MAC_REG_CCAFRACTION 0x72 |
| 197 | #define MAC_REG_PWRCCK 0x73 |
| 198 | #define MAC_REG_PWROFDM 0x7C |
| 199 | |
| 200 | |
| 201 | // |
| 202 | // Bits in the BCFG0 register |
| 203 | // |
| 204 | #define BCFG0_PERROFF 0x40 |
| 205 | #define BCFG0_MRDMDIS 0x20 |
| 206 | #define BCFG0_MRDLDIS 0x10 |
| 207 | #define BCFG0_MWMEN 0x08 |
| 208 | #define BCFG0_VSERREN 0x02 |
| 209 | #define BCFG0_LATMEN 0x01 |
| 210 | |
| 211 | // |
| 212 | // Bits in the BCFG1 register |
| 213 | // |
| 214 | #define BCFG1_CFUNOPT 0x80 |
| 215 | #define BCFG1_CREQOPT 0x40 |
| 216 | #define BCFG1_DMA8 0x10 |
| 217 | #define BCFG1_ARBITOPT 0x08 |
| 218 | #define BCFG1_PCIMEN 0x04 |
| 219 | #define BCFG1_MIOEN 0x02 |
| 220 | #define BCFG1_CISDLYEN 0x01 |
| 221 | |
| 222 | // Bits in RAMBIST registers |
| 223 | #define BISTCMD_TSTPAT5 0x00 // |
| 224 | #define BISTCMD_TSTPATA 0x80 // |
| 225 | #define BISTCMD_TSTERR 0x20 // |
| 226 | #define BISTCMD_TSTPATF 0x18 // |
| 227 | #define BISTCMD_TSTPAT0 0x10 // |
| 228 | #define BISTCMD_TSTMODE 0x04 // |
| 229 | #define BISTCMD_TSTITTX 0x03 // |
| 230 | #define BISTCMD_TSTATRX 0x02 // |
| 231 | #define BISTCMD_TSTATTX 0x01 // |
| 232 | #define BISTCMD_TSTRX 0x00 // |
| 233 | #define BISTSR0_BISTGO 0x01 // |
| 234 | #define BISTSR1_TSTSR 0x01 // |
| 235 | #define BISTSR2_CMDPRTEN 0x02 // |
| 236 | #define BISTSR2_RAMTSTEN 0x01 // |
| 237 | |
| 238 | // |
| 239 | // Bits in the I2MCFG EEPROM register |
| 240 | // |
| 241 | #define I2MCFG_BOUNDCTL 0x80 |
| 242 | #define I2MCFG_WAITCTL 0x20 |
| 243 | #define I2MCFG_SCLOECTL 0x10 |
| 244 | #define I2MCFG_WBUSYCTL 0x08 |
| 245 | #define I2MCFG_NORETRY 0x04 |
| 246 | #define I2MCFG_I2MLDSEQ 0x02 |
| 247 | #define I2MCFG_I2CMFAST 0x01 |
| 248 | |
| 249 | // |
| 250 | // Bits in the I2MCSR EEPROM register |
| 251 | // |
| 252 | #define I2MCSR_EEMW 0x80 |
| 253 | #define I2MCSR_EEMR 0x40 |
| 254 | #define I2MCSR_AUTOLD 0x08 |
| 255 | #define I2MCSR_NACK 0x02 |
| 256 | #define I2MCSR_DONE 0x01 |
| 257 | |
| 258 | // |
| 259 | // Bits in the PMC1 register |
| 260 | // |
| 261 | #define SPS_RST 0x80 |
| 262 | #define PCISTIKY 0x40 |
| 263 | #define PME_OVR 0x02 |
| 264 | |
| 265 | // |
| 266 | // Bits in the STICKYHW register |
| 267 | // |
| 268 | #define STICKHW_DS1_SHADOW 0x02 |
| 269 | #define STICKHW_DS0_SHADOW 0x01 |
| 270 | |
| 271 | // |
| 272 | // Bits in the TMCTL register |
| 273 | // |
| 274 | #define TMCTL_TSUSP 0x04 |
| 275 | #define TMCTL_TMD 0x02 |
| 276 | #define TMCTL_TE 0x01 |
| 277 | |
| 278 | // |
| 279 | // Bits in the TFTCTL register |
| 280 | // |
| 281 | #define TFTCTL_HWUTSF 0x80 // |
| 282 | #define TFTCTL_TBTTSYNC 0x40 |
| 283 | #define TFTCTL_HWUTSFEN 0x20 |
| 284 | #define TFTCTL_TSFCNTRRD 0x10 // |
| 285 | #define TFTCTL_TBTTSYNCEN 0x08 // |
| 286 | #define TFTCTL_TSFSYNCEN 0x04 // |
| 287 | #define TFTCTL_TSFCNTRST 0x02 // |
| 288 | #define TFTCTL_TSFCNTREN 0x01 // |
| 289 | |
| 290 | // |
| 291 | // Bits in the EnhanceCFG register |
| 292 | // |
| 293 | #define EnCFG_BarkerPream 0x00020000 |
| 294 | #define EnCFG_NXTBTTCFPSTR 0x00010000 |
| 295 | //#define EnCFG_TXLMT3UPDATE 0x00008000 |
| 296 | //#define EnCFG_TXLMT2UPDATE 0x00004000 |
| 297 | //#define EnCFG_TXLMT1UPDATE 0x00002000 |
| 298 | //#define EnCFG_TXLMT3EN 0x00001000 |
| 299 | //#define EnCFG_TXLMT2EN 0x00000800 |
| 300 | //#define EnCFG_TXLMT1EN 0x00000400 |
| 301 | #define EnCFG_BcnSusClr 0x00000200 |
| 302 | #define EnCFG_BcnSusInd 0x00000100 |
| 303 | //#define EnCFG_CWOFF1 0x00000080 |
| 304 | #define EnCFG_CFP_ProtectEn 0x00000040 |
| 305 | #define EnCFG_ProtectMd 0x00000020 |
| 306 | #define EnCFG_HwParCFP 0x00000010 |
| 307 | //#define EnCFG_QOS 0x00000008 |
| 308 | #define EnCFG_CFNULRSP 0x00000004 |
| 309 | #define EnCFG_BBType_MASK 0x00000003 |
| 310 | #define EnCFG_BBType_g 0x00000002 |
| 311 | #define EnCFG_BBType_b 0x00000001 |
| 312 | #define EnCFG_BBType_a 0x00000000 |
| 313 | |
| 314 | // |
| 315 | // Bits in the Page1Sel register |
| 316 | // |
| 317 | #define PAGE1_SEL 0x01 |
| 318 | |
| 319 | // |
| 320 | // Bits in the CFG register |
| 321 | // |
| 322 | #define CFG_TKIPOPT 0x80 |
| 323 | #define CFG_RXDMAOPT 0x40 |
| 324 | #define CFG_TMOT_SW 0x20 |
| 325 | #define CFG_TMOT_HWLONG 0x10 |
| 326 | #define CFG_TMOT_HW 0x00 |
| 327 | #define CFG_CFPENDOPT 0x08 |
| 328 | #define CFG_BCNSUSEN 0x04 |
| 329 | #define CFG_NOTXTIMEOUT 0x02 |
| 330 | #define CFG_NOBUFOPT 0x01 |
| 331 | |
| 332 | // |
| 333 | // Bits in the TEST register |
| 334 | // |
| 335 | #define TEST_LBEXT 0x80 // |
| 336 | #define TEST_LBINT 0x40 // |
| 337 | #define TEST_LBNONE 0x00 // |
| 338 | #define TEST_SOFTINT 0x20 // |
| 339 | #define TEST_CONTTX 0x10 // |
| 340 | #define TEST_TXPE 0x08 // |
| 341 | #define TEST_NAVDIS 0x04 // |
| 342 | #define TEST_NOCTS 0x02 // |
| 343 | #define TEST_NOACK 0x01 // |
| 344 | |
| 345 | // |
| 346 | // Bits in the HOSTCR register |
| 347 | // |
| 348 | #define HOSTCR_TXONST 0x80 // |
| 349 | #define HOSTCR_RXONST 0x40 // |
| 350 | #define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc |
| 351 | #define HOSTCR_AP 0x10 // Port Type 1 = AP |
| 352 | #define HOSTCR_TXON 0x08 //0000 1000 |
| 353 | #define HOSTCR_RXON 0x04 //0000 0100 |
| 354 | #define HOSTCR_MACEN 0x02 //0000 0010 |
| 355 | #define HOSTCR_SOFTRST 0x01 //0000 0001 |
| 356 | |
| 357 | // |
| 358 | // Bits in the MACCR register |
| 359 | // |
| 360 | #define MACCR_SYNCFLUSHOK 0x04 // |
| 361 | #define MACCR_SYNCFLUSH 0x02 // |
| 362 | #define MACCR_CLRNAV 0x01 // |
| 363 | |
| 364 | // Bits in the MAC_REG_GPIOCTL0 register |
| 365 | // |
| 366 | #define LED_ACTSET 0x01 // |
| 367 | #define LED_RFOFF 0x02 // |
| 368 | #define LED_NOCONNECT 0x04 // |
| 369 | // |
| 370 | // Bits in the RCR register |
| 371 | // |
| 372 | #define RCR_SSID 0x80 |
| 373 | #define RCR_RXALLTYPE 0x40 // |
| 374 | #define RCR_UNICAST 0x20 // |
| 375 | #define RCR_BROADCAST 0x10 // |
| 376 | #define RCR_MULTICAST 0x08 // |
| 377 | #define RCR_WPAERR 0x04 // |
| 378 | #define RCR_ERRCRC 0x02 // |
| 379 | #define RCR_BSSID 0x01 // |
| 380 | |
| 381 | // |
| 382 | // Bits in the TCR register |
| 383 | // |
| 384 | #define TCR_SYNCDCFOPT 0x02 // |
| 385 | #define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable |
| 386 | |
| 387 | // |
| 388 | // Bits in the IMR register |
| 389 | // |
| 390 | #define IMR_MEASURESTART 0x80000000 // |
| 391 | #define IMR_QUIETSTART 0x20000000 // |
| 392 | #define IMR_RADARDETECT 0x10000000 // |
| 393 | #define IMR_MEASUREEND 0x08000000 // |
| 394 | #define IMR_SOFTTIMER1 0x00200000 // |
| 395 | //#define IMR_SYNCFLUSHOK 0x00100000 // |
| 396 | //#define IMR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000 |
| 397 | //#define IMR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000 |
| 398 | //#define IMR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000 |
| 399 | //#define IMR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000 |
| 400 | //#define IMR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000 |
| 401 | //#define IMR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000 |
| 402 | //#define IMR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000 |
| 403 | #define IMR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000 |
| 404 | #define IMR_RXNOBUF 0x00000800 // |
| 405 | #define IMR_MIBNEARFULL 0x00000400 // |
| 406 | #define IMR_SOFTINT 0x00000200 // |
| 407 | #define IMR_FETALERR 0x00000100 // |
| 408 | #define IMR_WATCHDOG 0x00000080 // |
| 409 | #define IMR_SOFTTIMER 0x00000040 // |
| 410 | #define IMR_GPIO 0x00000020 // |
| 411 | #define IMR_TBTT 0x00000010 // |
| 412 | #define IMR_RXDMA0 0x00000008 // |
| 413 | #define IMR_BNTX 0x00000004 // |
| 414 | #define IMR_AC0DMA 0x00000002 // |
| 415 | #define IMR_TXDMA0 0x00000001 // |
| 416 | |
| 417 | |
| 418 | // |
| 419 | // Bits in the ISR register |
| 420 | // |
| 421 | |
| 422 | #define ISR_MEASURESTART 0x80000000 // |
| 423 | #define ISR_QUIETSTART 0x20000000 // |
| 424 | #define ISR_RADARDETECT 0x10000000 // |
| 425 | #define ISR_MEASUREEND 0x08000000 // |
| 426 | #define ISR_SOFTTIMER1 0x00200000 // |
| 427 | //#define ISR_SYNCFLUSHOK 0x00100000 //0001 0000 0000 0000 0000 0000 |
| 428 | //#define ISR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000 |
| 429 | //#define ISR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000 |
| 430 | //#define ISR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000 |
| 431 | //#define ISR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000 |
| 432 | //#define ISR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000 |
| 433 | //#define ISR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000 |
| 434 | //#define ISR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000 |
| 435 | #define ISR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000 |
| 436 | #define ISR_RXNOBUF 0x00000800 //0000 0000 0000 1000 0000 0000 |
| 437 | #define ISR_MIBNEARFULL 0x00000400 //0000 0000 0000 0100 0000 0000 |
| 438 | #define ISR_SOFTINT 0x00000200 // |
| 439 | #define ISR_FETALERR 0x00000100 // |
| 440 | #define ISR_WATCHDOG 0x00000080 // |
| 441 | #define ISR_SOFTTIMER 0x00000040 // |
| 442 | #define ISR_GPIO 0x00000020 // |
| 443 | #define ISR_TBTT 0x00000010 // |
| 444 | #define ISR_RXDMA0 0x00000008 // |
| 445 | #define ISR_BNTX 0x00000004 // |
| 446 | #define ISR_AC0DMA 0x00000002 // |
| 447 | #define ISR_TXDMA0 0x00000001 // |
| 448 | |
| 449 | |
| 450 | // |
| 451 | // Bits in the PSCFG register |
| 452 | // |
| 453 | #define PSCFG_PHILIPMD 0x40 // |
| 454 | #define PSCFG_WAKECALEN 0x20 // |
| 455 | #define PSCFG_WAKETMREN 0x10 // |
| 456 | #define PSCFG_BBPSPROG 0x08 // |
| 457 | #define PSCFG_WAKESYN 0x04 // |
| 458 | #define PSCFG_SLEEPSYN 0x02 // |
| 459 | #define PSCFG_AUTOSLEEP 0x01 // |
| 460 | |
| 461 | // |
| 462 | // Bits in the PSCTL register |
| 463 | // |
| 464 | #define PSCTL_WAKEDONE 0x20 // |
| 465 | #define PSCTL_PS 0x10 // |
| 466 | #define PSCTL_GO2DOZE 0x08 // |
| 467 | #define PSCTL_LNBCN 0x04 // |
| 468 | #define PSCTL_ALBCN 0x02 // |
| 469 | #define PSCTL_PSEN 0x01 // |
| 470 | |
| 471 | // |
| 472 | // Bits in the PSPWSIG register |
| 473 | // |
| 474 | #define PSSIG_WPE3 0x80 // |
| 475 | #define PSSIG_WPE2 0x40 // |
| 476 | #define PSSIG_WPE1 0x20 // |
| 477 | #define PSSIG_WRADIOPE 0x10 // |
| 478 | #define PSSIG_SPE3 0x08 // |
| 479 | #define PSSIG_SPE2 0x04 // |
| 480 | #define PSSIG_SPE1 0x02 // |
| 481 | #define PSSIG_SRADIOPE 0x01 // |
| 482 | |
| 483 | // |
| 484 | // Bits in the BBREGCTL register |
| 485 | // |
| 486 | #define BBREGCTL_DONE 0x04 // |
| 487 | #define BBREGCTL_REGR 0x02 // |
| 488 | #define BBREGCTL_REGW 0x01 // |
| 489 | |
| 490 | // |
| 491 | // Bits in the IFREGCTL register |
| 492 | // |
| 493 | #define IFREGCTL_DONE 0x04 // |
| 494 | #define IFREGCTL_IFRF 0x02 // |
| 495 | #define IFREGCTL_REGW 0x01 // |
| 496 | |
| 497 | // |
| 498 | // Bits in the SOFTPWRCTL register |
| 499 | // |
| 500 | #define SOFTPWRCTL_RFLEOPT 0x0800 // |
| 501 | #define SOFTPWRCTL_TXPEINV 0x0200 // |
| 502 | #define SOFTPWRCTL_SWPECTI 0x0100 // |
| 503 | #define SOFTPWRCTL_SWPAPE 0x0020 // |
| 504 | #define SOFTPWRCTL_SWCALEN 0x0010 // |
| 505 | #define SOFTPWRCTL_SWRADIO_PE 0x0008 // |
| 506 | #define SOFTPWRCTL_SWPE2 0x0004 // |
| 507 | #define SOFTPWRCTL_SWPE1 0x0002 // |
| 508 | #define SOFTPWRCTL_SWPE3 0x0001 // |
| 509 | |
| 510 | // |
| 511 | // Bits in the GPIOCTL1 register |
| 512 | // |
| 513 | #define GPIO1_DATA1 0x20 // |
| 514 | #define GPIO1_MD1 0x10 // |
| 515 | #define GPIO1_DATA0 0x02 // |
| 516 | #define GPIO1_MD0 0x01 // |
| 517 | |
| 518 | // |
| 519 | // Bits in the DMACTL register |
| 520 | // |
| 521 | #define DMACTL_CLRRUN 0x00080000 // |
| 522 | #define DMACTL_RUN 0x00000008 // |
| 523 | #define DMACTL_WAKE 0x00000004 // |
| 524 | #define DMACTL_DEAD 0x00000002 // |
| 525 | #define DMACTL_ACTIVE 0x00000001 // |
| 526 | // |
| 527 | // Bits in the RXDMACTL0 register |
| 528 | // |
| 529 | #define RX_PERPKT 0x00000100 // |
| 530 | #define RX_PERPKTCLR 0x01000000 // |
| 531 | // |
| 532 | // Bits in the BCNDMACTL register |
| 533 | // |
| 534 | #define BEACON_READY 0x01 // |
| 535 | // |
| 536 | // Bits in the MISCFFCTL register |
| 537 | // |
| 538 | #define MISCFFCTL_WRITE 0x0001 // |
| 539 | |
| 540 | |
| 541 | // |
| 542 | // Bits in WAKEUPEN0 |
| 543 | // |
| 544 | #define WAKEUPEN0_DIRPKT 0x10 |
| 545 | #define WAKEUPEN0_LINKOFF 0x08 |
| 546 | #define WAKEUPEN0_ATIMEN 0x04 |
| 547 | #define WAKEUPEN0_TIMEN 0x02 |
| 548 | #define WAKEUPEN0_MAGICEN 0x01 |
| 549 | |
| 550 | // |
| 551 | // Bits in WAKEUPEN1 |
| 552 | // |
| 553 | #define WAKEUPEN1_128_3 0x08 |
| 554 | #define WAKEUPEN1_128_2 0x04 |
| 555 | #define WAKEUPEN1_128_1 0x02 |
| 556 | #define WAKEUPEN1_128_0 0x01 |
| 557 | |
| 558 | // |
| 559 | // Bits in WAKEUPSR0 |
| 560 | // |
| 561 | #define WAKEUPSR0_DIRPKT 0x10 |
| 562 | #define WAKEUPSR0_LINKOFF 0x08 |
| 563 | #define WAKEUPSR0_ATIMEN 0x04 |
| 564 | #define WAKEUPSR0_TIMEN 0x02 |
| 565 | #define WAKEUPSR0_MAGICEN 0x01 |
| 566 | |
| 567 | // |
| 568 | // Bits in WAKEUPSR1 |
| 569 | // |
| 570 | #define WAKEUPSR1_128_3 0x08 |
| 571 | #define WAKEUPSR1_128_2 0x04 |
| 572 | #define WAKEUPSR1_128_1 0x02 |
| 573 | #define WAKEUPSR1_128_0 0x01 |
| 574 | |
| 575 | // |
| 576 | // Bits in the MAC_REG_GPIOCTL register |
| 577 | // |
| 578 | #define GPIO0_MD 0x01 // |
| 579 | #define GPIO0_DATA 0x02 // |
| 580 | #define GPIO0_INTMD 0x04 // |
| 581 | #define GPIO1_MD 0x10 // |
| 582 | #define GPIO1_DATA 0x20 // |
| 583 | |
| 584 | |
| 585 | // |
| 586 | // Bits in the MSRCTL register |
| 587 | // |
| 588 | #define MSRCTL_FINISH 0x80 |
| 589 | #define MSRCTL_READY 0x40 |
| 590 | #define MSRCTL_RADARDETECT 0x20 |
| 591 | #define MSRCTL_EN 0x10 |
| 592 | #define MSRCTL_QUIETTXCHK 0x08 |
| 593 | #define MSRCTL_QUIETRPT 0x04 |
| 594 | #define MSRCTL_QUIETINT 0x02 |
| 595 | #define MSRCTL_QUIETEN 0x01 |
| 596 | // |
| 597 | // Bits in the MSRCTL1 register |
| 598 | // |
| 599 | #define MSRCTL1_TXPWR 0x08 |
| 600 | #define MSRCTL1_CSAPAREN 0x04 |
| 601 | #define MSRCTL1_TXPAUSE 0x01 |
| 602 | |
| 603 | |
| 604 | // Loopback mode |
| 605 | #define MAC_LB_EXT 0x02 // |
| 606 | #define MAC_LB_INTERNAL 0x01 // |
| 607 | #define MAC_LB_NONE 0x00 // |
| 608 | |
| 609 | // Ethernet address filter type |
| 610 | #define PKT_TYPE_NONE 0x00 // turn off receiver |
| 611 | #define PKT_TYPE_ALL_MULTICAST 0x80 |
| 612 | #define PKT_TYPE_PROMISCUOUS 0x40 |
| 613 | #define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted |
| 614 | #define PKT_TYPE_BROADCAST 0x10 |
| 615 | #define PKT_TYPE_MULTICAST 0x08 |
| 616 | #define PKT_TYPE_ERROR_WPA 0x04 |
| 617 | #define PKT_TYPE_ERROR_CRC 0x02 |
| 618 | #define PKT_TYPE_BSSID 0x01 |
| 619 | |
| 620 | #define Default_BI 0x200 |
| 621 | |
| 622 | |
| 623 | // MiscFIFO Offset |
| 624 | #define MISCFIFO_KEYETRY0 32 |
| 625 | #define MISCFIFO_KEYENTRYSIZE 22 |
| 626 | #define MISCFIFO_SYNINFO_IDX 10 |
| 627 | #define MISCFIFO_SYNDATA_IDX 11 |
| 628 | #define MISCFIFO_SYNDATASIZE 21 |
| 629 | |
| 630 | // enabled mask value of irq |
| 631 | #define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \ |
| 632 | IMR_RXDMA1 | \ |
| 633 | IMR_RXNOBUF | \ |
| 634 | IMR_MIBNEARFULL | \ |
| 635 | IMR_SOFTINT | \ |
| 636 | IMR_FETALERR | \ |
| 637 | IMR_WATCHDOG | \ |
| 638 | IMR_SOFTTIMER | \ |
| 639 | IMR_GPIO | \ |
| 640 | IMR_TBTT | \ |
| 641 | IMR_RXDMA0 | \ |
| 642 | IMR_BNTX | \ |
| 643 | IMR_AC0DMA | \ |
| 644 | IMR_TXDMA0) |
| 645 | |
| 646 | // max time out delay time |
| 647 | #define W_MAX_TIMEOUT 0xFFF0U // |
| 648 | |
| 649 | // wait time within loop |
| 650 | #define CB_DELAY_LOOP_WAIT 10 // 10ms |
| 651 | |
| 652 | // |
| 653 | // revision id |
| 654 | // |
| 655 | #define REV_ID_VT3253_A0 0x00 |
| 656 | #define REV_ID_VT3253_A1 0x01 |
| 657 | #define REV_ID_VT3253_B0 0x08 |
| 658 | #define REV_ID_VT3253_B1 0x09 |
| 659 | |
| 660 | /*--------------------- Export Types ------------------------------*/ |
| 661 | |
| 662 | /*--------------------- Export Macros ------------------------------*/ |
| 663 | |
| 664 | #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \ |
| 665 | { \ |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 666 | unsigned char byData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 667 | VNSvInPortB(dwIoBase + byRegOfs, &byData); \ |
| 668 | VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ |
| 669 | } |
| 670 | |
| 671 | #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \ |
| 672 | { \ |
Charles Clément | 2986db5 | 2010-06-24 11:02:26 -0700 | [diff] [blame] | 673 | unsigned short wData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 674 | VNSvInPortW(dwIoBase + byRegOfs, &wData); \ |
| 675 | VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \ |
| 676 | } |
| 677 | |
| 678 | #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \ |
| 679 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 680 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 681 | VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ |
| 682 | VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \ |
| 683 | } |
| 684 | |
| 685 | #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \ |
| 686 | { \ |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 687 | unsigned char byData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 688 | VNSvInPortB(dwIoBase + byRegOfs, &byData); \ |
| 689 | byData &= byMask; \ |
| 690 | VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ |
| 691 | } |
| 692 | |
| 693 | #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \ |
| 694 | { \ |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 695 | unsigned char byData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 696 | VNSvInPortB(dwIoBase + byRegOfs, &byData); \ |
| 697 | VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \ |
| 698 | } |
| 699 | |
| 700 | #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \ |
| 701 | { \ |
Charles Clément | 2986db5 | 2010-06-24 11:02:26 -0700 | [diff] [blame] | 702 | unsigned short wData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 703 | VNSvInPortW(dwIoBase + byRegOfs, &wData); \ |
| 704 | VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \ |
| 705 | } |
| 706 | |
| 707 | #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \ |
| 708 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 709 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 710 | VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ |
| 711 | VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \ |
| 712 | } |
| 713 | |
| 714 | #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \ |
| 715 | { \ |
| 716 | VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \ |
Charles Clément | 9d828c4 | 2010-06-05 15:13:49 -0700 | [diff] [blame] | 717 | (unsigned long *)pdwCurrDescAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 718 | } |
| 719 | |
| 720 | #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \ |
| 721 | { \ |
| 722 | VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \ |
Charles Clément | 9d828c4 | 2010-06-05 15:13:49 -0700 | [diff] [blame] | 723 | (unsigned long *)pdwCurrDescAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 724 | } |
| 725 | |
| 726 | #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \ |
| 727 | { \ |
| 728 | VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \ |
Charles Clément | 9d828c4 | 2010-06-05 15:13:49 -0700 | [diff] [blame] | 729 | (unsigned long *)pdwCurrDescAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 730 | } |
| 731 | |
| 732 | #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \ |
| 733 | { \ |
| 734 | VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \ |
Charles Clément | 9d828c4 | 2010-06-05 15:13:49 -0700 | [diff] [blame] | 735 | (unsigned long *)pdwCurrDescAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 736 | } |
| 737 | |
| 738 | #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \ |
| 739 | { \ |
| 740 | VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \ |
Charles Clément | 9d828c4 | 2010-06-05 15:13:49 -0700 | [diff] [blame] | 741 | (unsigned long *)pdwCurrDescAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 742 | } |
| 743 | |
| 744 | #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \ |
| 745 | { \ |
| 746 | VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \ |
Charles Clément | 9d828c4 | 2010-06-05 15:13:49 -0700 | [diff] [blame] | 747 | (unsigned long *)pdwCurrDescAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 748 | } \ |
| 749 | |
| 750 | // set the chip with current BCN tx descriptor address |
| 751 | #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \ |
| 752 | { \ |
| 753 | VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \ |
| 754 | dwCurrDescAddr); \ |
| 755 | } |
| 756 | |
| 757 | // set the chip with current BCN length |
| 758 | #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \ |
| 759 | { \ |
| 760 | VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \ |
| 761 | wCurrBCNLength); \ |
| 762 | } |
| 763 | |
| 764 | #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \ |
| 765 | { \ |
| 766 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ |
| 767 | VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \ |
Charles Clément | 2989e96 | 2010-06-05 15:13:47 -0700 | [diff] [blame] | 768 | (unsigned char *)pbyEtherAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 769 | VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ |
| 770 | pbyEtherAddr + 1); \ |
| 771 | VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ |
| 772 | pbyEtherAddr + 2); \ |
| 773 | VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ |
| 774 | pbyEtherAddr + 3); \ |
| 775 | VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ |
| 776 | pbyEtherAddr + 4); \ |
| 777 | VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ |
| 778 | pbyEtherAddr + 5); \ |
| 779 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ |
| 780 | } |
| 781 | |
| 782 | #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \ |
| 783 | { \ |
| 784 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ |
| 785 | VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \ |
| 786 | *(pbyEtherAddr)); \ |
| 787 | VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ |
| 788 | *(pbyEtherAddr + 1)); \ |
| 789 | VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ |
| 790 | *(pbyEtherAddr + 2)); \ |
| 791 | VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ |
| 792 | *(pbyEtherAddr + 3)); \ |
| 793 | VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ |
| 794 | *(pbyEtherAddr + 4)); \ |
| 795 | VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ |
| 796 | *(pbyEtherAddr + 5)); \ |
| 797 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ |
| 798 | } |
| 799 | |
| 800 | #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \ |
| 801 | { \ |
| 802 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ |
| 803 | VNSvInPortB(dwIoBase + MAC_REG_PAR0, \ |
Charles Clément | 2989e96 | 2010-06-05 15:13:47 -0700 | [diff] [blame] | 804 | (unsigned char *)pbyEtherAddr); \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 805 | VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \ |
| 806 | pbyEtherAddr + 1); \ |
| 807 | VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \ |
| 808 | pbyEtherAddr + 2); \ |
| 809 | VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \ |
| 810 | pbyEtherAddr + 3); \ |
| 811 | VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \ |
| 812 | pbyEtherAddr + 4); \ |
| 813 | VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \ |
| 814 | pbyEtherAddr + 5); \ |
| 815 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ |
| 816 | } |
| 817 | |
| 818 | |
| 819 | #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \ |
| 820 | { \ |
| 821 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ |
| 822 | VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \ |
| 823 | *pbyEtherAddr); \ |
| 824 | VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \ |
| 825 | *(pbyEtherAddr + 1)); \ |
| 826 | VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \ |
| 827 | *(pbyEtherAddr + 2)); \ |
| 828 | VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \ |
| 829 | *(pbyEtherAddr + 3)); \ |
| 830 | VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \ |
| 831 | *(pbyEtherAddr + 4)); \ |
| 832 | VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \ |
| 833 | *(pbyEtherAddr + 5)); \ |
| 834 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ |
| 835 | } |
| 836 | |
| 837 | |
| 838 | #define MACvClearISR(dwIoBase) \ |
| 839 | { \ |
| 840 | VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE); \ |
| 841 | } |
| 842 | |
| 843 | #define MACvStart(dwIoBase) \ |
| 844 | { \ |
| 845 | VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \ |
| 846 | (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)); \ |
| 847 | } |
| 848 | |
| 849 | #define MACvRx0PerPktMode(dwIoBase) \ |
| 850 | { \ |
| 851 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT); \ |
| 852 | } |
| 853 | |
| 854 | #define MACvRx0BufferFillMode(dwIoBase) \ |
| 855 | { \ |
| 856 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR); \ |
| 857 | } |
| 858 | |
| 859 | #define MACvRx1PerPktMode(dwIoBase) \ |
| 860 | { \ |
| 861 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT); \ |
| 862 | } |
| 863 | |
| 864 | #define MACvRx1BufferFillMode(dwIoBase) \ |
| 865 | { \ |
| 866 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR); \ |
| 867 | } |
| 868 | |
| 869 | #define MACvRxOn(dwIoBase) \ |
| 870 | { \ |
| 871 | MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON); \ |
| 872 | } |
| 873 | |
| 874 | #define MACvReceive0(dwIoBase) \ |
| 875 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 876 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 877 | VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \ |
| 878 | if (dwData & DMACTL_RUN) { \ |
| 879 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE);\ |
| 880 | } \ |
| 881 | else { \ |
| 882 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \ |
| 883 | } \ |
| 884 | } |
| 885 | |
| 886 | #define MACvReceive1(dwIoBase) \ |
| 887 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 888 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 889 | VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \ |
| 890 | if (dwData & DMACTL_RUN) { \ |
| 891 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE);\ |
| 892 | } \ |
| 893 | else { \ |
| 894 | VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \ |
| 895 | } \ |
| 896 | } |
| 897 | |
| 898 | #define MACvTxOn(dwIoBase) \ |
| 899 | { \ |
| 900 | MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON); \ |
| 901 | } |
| 902 | |
| 903 | #define MACvTransmit0(dwIoBase) \ |
| 904 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 905 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 906 | VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \ |
| 907 | if (dwData & DMACTL_RUN) { \ |
| 908 | VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE);\ |
| 909 | } \ |
| 910 | else { \ |
| 911 | VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \ |
| 912 | } \ |
| 913 | } |
| 914 | |
| 915 | #define MACvTransmitAC0(dwIoBase) \ |
| 916 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 917 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 918 | VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \ |
| 919 | if (dwData & DMACTL_RUN) { \ |
| 920 | VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE);\ |
| 921 | } \ |
| 922 | else { \ |
| 923 | VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \ |
| 924 | } \ |
| 925 | } |
| 926 | |
| 927 | #define MACvTransmitSYNC(dwIoBase) \ |
| 928 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 929 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 930 | VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \ |
| 931 | if (dwData & DMACTL_RUN) { \ |
| 932 | VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE);\ |
| 933 | } \ |
| 934 | else { \ |
| 935 | VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \ |
| 936 | } \ |
| 937 | } |
| 938 | |
| 939 | #define MACvTransmitATIM(dwIoBase) \ |
| 940 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 941 | unsigned long dwData; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 942 | VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \ |
| 943 | if (dwData & DMACTL_RUN) { \ |
| 944 | VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE);\ |
| 945 | } \ |
| 946 | else { \ |
| 947 | VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \ |
| 948 | } \ |
| 949 | } |
| 950 | |
| 951 | #define MACvTransmitBCN(dwIoBase) \ |
| 952 | { \ |
| 953 | VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY); \ |
| 954 | } |
| 955 | |
| 956 | #define MACvClearStckDS(dwIoBase) \ |
| 957 | { \ |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 958 | unsigned char byOrgValue; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 959 | VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \ |
| 960 | byOrgValue = byOrgValue & 0xFC; \ |
| 961 | VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \ |
| 962 | } |
| 963 | |
| 964 | #define MACvReadISR(dwIoBase, pdwValue) \ |
| 965 | { \ |
| 966 | VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue); \ |
| 967 | } |
| 968 | |
| 969 | #define MACvWriteISR(dwIoBase, dwValue) \ |
| 970 | { \ |
| 971 | VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue); \ |
| 972 | } |
| 973 | |
| 974 | #define MACvIntEnable(dwIoBase, dwMask) \ |
| 975 | { \ |
| 976 | VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask); \ |
| 977 | } |
| 978 | |
| 979 | #define MACvIntDisable(dwIoBase) \ |
| 980 | { \ |
| 981 | VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0); \ |
| 982 | } |
| 983 | |
| 984 | #define MACvSelectPage0(dwIoBase) \ |
| 985 | { \ |
| 986 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ |
| 987 | } |
| 988 | #define MACvSelectPage1(dwIoBase) \ |
| 989 | { \ |
| 990 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ |
| 991 | } |
| 992 | |
| 993 | #define MACvReadMIBCounter(dwIoBase, pdwCounter) \ |
| 994 | { \ |
| 995 | VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter); \ |
| 996 | } |
| 997 | |
| 998 | #define MACvPwrEvntDisable(dwIoBase) \ |
| 999 | { \ |
| 1000 | VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000); \ |
| 1001 | } |
| 1002 | |
| 1003 | #define MACvEnableProtectMD(dwIoBase) \ |
| 1004 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 1005 | unsigned long dwOrgValue; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1006 | VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \ |
| 1007 | dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \ |
| 1008 | VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ |
| 1009 | } |
| 1010 | |
| 1011 | #define MACvDisableProtectMD(dwIoBase) \ |
| 1012 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 1013 | unsigned long dwOrgValue; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1014 | VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \ |
| 1015 | dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \ |
| 1016 | VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ |
| 1017 | } |
| 1018 | |
| 1019 | #define MACvEnableBarkerPreambleMd(dwIoBase) \ |
| 1020 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 1021 | unsigned long dwOrgValue; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1022 | VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \ |
| 1023 | dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \ |
| 1024 | VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ |
| 1025 | } |
| 1026 | |
| 1027 | #define MACvDisableBarkerPreambleMd(dwIoBase) \ |
| 1028 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 1029 | unsigned long dwOrgValue; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1030 | VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \ |
| 1031 | dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \ |
| 1032 | VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ |
| 1033 | } |
| 1034 | |
| 1035 | #define MACvSetBBType(dwIoBase, byTyp) \ |
| 1036 | { \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 1037 | unsigned long dwOrgValue; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1038 | VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \ |
| 1039 | dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \ |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 1040 | dwOrgValue = dwOrgValue | (unsigned long) byTyp; \ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1041 | VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ |
| 1042 | } |
| 1043 | |
| 1044 | #define MACvReadATIMW(dwIoBase, pwCounter) \ |
| 1045 | { \ |
| 1046 | VNSvInPortW(dwIoBase + MAC_REG_AIDATIM , pwCounter); \ |
| 1047 | } |
| 1048 | |
| 1049 | #define MACvWriteATIMW(dwIoBase, wCounter) \ |
| 1050 | { \ |
| 1051 | VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM , wCounter); \ |
| 1052 | } |
| 1053 | |
| 1054 | #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \ |
| 1055 | { \ |
| 1056 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ |
| 1057 | VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \ |
| 1058 | VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ |
| 1059 | } |
| 1060 | |
| 1061 | #define MACvGPIOIn(dwIoBase, pbyValue) \ |
| 1062 | { \ |
| 1063 | VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue); \ |
| 1064 | } |
| 1065 | |
| 1066 | #define MACvSetRFLE_LatchBase(dwIoBase) \ |
| 1067 | { \ |
| 1068 | MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT); \ |
| 1069 | } |
| 1070 | |
| 1071 | /*--------------------- Export Classes ----------------------------*/ |
| 1072 | |
| 1073 | /*--------------------- Export Variables --------------------------*/ |
| 1074 | |
| 1075 | /*--------------------- Export Functions --------------------------*/ |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1076 | |
Charles Clément | 2986db5 | 2010-06-24 11:02:26 -0700 | [diff] [blame] | 1077 | extern unsigned short TxRate_iwconfig;//2008-5-8 <add> by chester |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1078 | void MACvReadAllRegs(unsigned long dwIoBase, unsigned char *pbyMacRegs); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1079 | |
Charles Clément | 7b6a001 | 2010-08-01 17:15:50 +0200 | [diff] [blame] | 1080 | bool MACbIsRegBitsOn(unsigned long dwIoBase, unsigned char byRegOfs, unsigned char byTestBits); |
| 1081 | bool MACbIsRegBitsOff(unsigned long dwIoBase, unsigned char byRegOfs, unsigned char byTestBits); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1082 | |
Charles Clément | 7b6a001 | 2010-08-01 17:15:50 +0200 | [diff] [blame] | 1083 | bool MACbIsIntDisable(unsigned long dwIoBase); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1084 | |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1085 | unsigned char MACbyReadMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx); |
| 1086 | void MACvWriteMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx, unsigned char byData); |
| 1087 | void MACvSetMultiAddrByHash(unsigned long dwIoBase, unsigned char byHashIdx); |
| 1088 | void MACvResetMultiAddrByHash(unsigned long dwIoBase, unsigned char byHashIdx); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1089 | |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1090 | void MACvSetRxThreshold(unsigned long dwIoBase, unsigned char byThreshold); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1091 | void MACvGetRxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1092 | |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1093 | void MACvSetTxThreshold(unsigned long dwIoBase, unsigned char byThreshold); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1094 | void MACvGetTxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1095 | |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1096 | void MACvSetDmaLength(unsigned long dwIoBase, unsigned char byDmaLength); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1097 | void MACvGetDmaLength(unsigned long dwIoBase, unsigned char *pbyDmaLength); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1098 | |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1099 | void MACvSetShortRetryLimit(unsigned long dwIoBase, unsigned char byRetryLimit); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1100 | void MACvGetShortRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1101 | |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1102 | void MACvSetLongRetryLimit(unsigned long dwIoBase, unsigned char byRetryLimit); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1103 | void MACvGetLongRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1104 | |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1105 | void MACvSetLoopbackMode(unsigned long dwIoBase, unsigned char byLoopbackMode); |
Charles Clément | 7b6a001 | 2010-08-01 17:15:50 +0200 | [diff] [blame] | 1106 | bool MACbIsInLoopbackMode(unsigned long dwIoBase); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1107 | |
Charles Clément | 2986db5 | 2010-06-24 11:02:26 -0700 | [diff] [blame] | 1108 | void MACvSetPacketFilter(unsigned long dwIoBase, unsigned short wFilterType); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1109 | |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1110 | void MACvSaveContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf); |
| 1111 | void MACvRestoreContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf); |
Charles Clément | 7b6a001 | 2010-08-01 17:15:50 +0200 | [diff] [blame] | 1112 | bool MACbCompareContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1113 | |
Charles Clément | 7b6a001 | 2010-08-01 17:15:50 +0200 | [diff] [blame] | 1114 | bool MACbSoftwareReset(unsigned long dwIoBase); |
| 1115 | bool MACbSafeSoftwareReset(unsigned long dwIoBase); |
| 1116 | bool MACbSafeRxOff(unsigned long dwIoBase); |
| 1117 | bool MACbSafeTxOff(unsigned long dwIoBase); |
| 1118 | bool MACbSafeStop(unsigned long dwIoBase); |
| 1119 | bool MACbShutdown(unsigned long dwIoBase); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1120 | void MACvInitialize(unsigned long dwIoBase); |
Charles Clément | 0f4c60d | 2010-06-24 11:02:25 -0700 | [diff] [blame] | 1121 | void MACvSetCurrRx0DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr); |
| 1122 | void MACvSetCurrRx1DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr); |
| 1123 | void MACvSetCurrTXDescAddr(int iTxType, unsigned long dwIoBase, unsigned long dwCurrDescAddr); |
| 1124 | void MACvSetCurrTx0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr); |
| 1125 | void MACvSetCurrAC0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr); |
| 1126 | void MACvSetCurrSyncDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr); |
| 1127 | void MACvSetCurrATIMDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1128 | void MACvTimer0MicroSDelay(unsigned long dwIoBase, unsigned int uDelay); |
| 1129 | void MACvOneShotTimer0MicroSec(unsigned long dwIoBase, unsigned int uDelayTime); |
| 1130 | void MACvOneShotTimer1MicroSec(unsigned long dwIoBase, unsigned int uDelayTime); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1131 | |
Charles Clément | 2986db5 | 2010-06-24 11:02:26 -0700 | [diff] [blame] | 1132 | void MACvSetMISCFifo(unsigned long dwIoBase, unsigned short wOffset, unsigned long dwData); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1133 | |
Charles Clément | 7b6a001 | 2010-08-01 17:15:50 +0200 | [diff] [blame] | 1134 | bool MACbTxDMAOff (unsigned long dwIoBase, unsigned int idx); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1135 | |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1136 | void MACvClearBusSusInd(unsigned long dwIoBase); |
| 1137 | void MACvEnableBusSusEn(unsigned long dwIoBase); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1138 | |
Charles Clément | 7b6a001 | 2010-08-01 17:15:50 +0200 | [diff] [blame] | 1139 | bool MACbFlushSYNCFifo(unsigned long dwIoBase); |
| 1140 | bool MACbPSWakeup(unsigned long dwIoBase); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1141 | |
Charles Clément | 2986db5 | 2010-06-24 11:02:26 -0700 | [diff] [blame] | 1142 | void MACvSetKeyEntry(unsigned long dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx, |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1143 | unsigned int uKeyIdx, unsigned char *pbyAddr, unsigned long *pdwKey, unsigned char byLocalID); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1144 | void MACvDisableKeyEntry(unsigned long dwIoBase, unsigned int uEntryIdx); |
| 1145 | void MACvSetDefaultKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen, |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1146 | unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID); |
| 1147 | //void MACvEnableDefaultKey(unsigned long dwIoBase, unsigned char byLocalID); |
Charles Clément | 412b2d0 | 2010-06-22 08:54:42 -0700 | [diff] [blame] | 1148 | void MACvDisableDefaultKey(unsigned long dwIoBase); |
| 1149 | void MACvSetDefaultTKIPKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen, |
Charles Clément | 3fc9b58 | 2010-06-24 11:02:27 -0700 | [diff] [blame] | 1150 | unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID); |
| 1151 | void MACvSetDefaultKeyCtl(unsigned long dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx, unsigned char byLocalID); |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1152 | |
Forest Bond | 5449c68 | 2009-04-25 10:30:44 -0400 | [diff] [blame] | 1153 | #endif // __MAC_H__ |
| 1154 | |