Google Git
Sign in
android-kvm / linux / 9250e523592a8ced3ecd14abe29fbb1e036bd7eb / . / arch / s390 / kernel / reipl.S
blob: 89ea8c213d8235f3b4dece6746d3b98bd6d2b4c5 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
Heiko Carstensa53c8fa2012-07-20 11:15:04 +0200[diff] [blame]2 * Copyright IBM Corp 2000, 2011
Heiko Carstensc70d0fe2009-03-26 15:24:57 +0100[diff] [blame]3 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
4 * Denis Joseph Barrow,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5 */
6
Jan Glauber144d6342011-07-24 10:48:19 +0200[diff] [blame]7#include <linux/linkage.h>
Heiko Carstenscbb870c2010-02-26 22:37:43 +0100[diff] [blame]8#include <asm/asm-offsets.h>
Heiko Carstenseb546192012-06-04 15:05:43 +0200[diff] [blame]9#include <asm/sigp.h>
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]10
11#
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]12# Issue "store status" for the current CPU to its prefix page
13# and call passed function afterwards
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]14#
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]15# r2 = Function to be called after store status
16# r3 = Parameter for function
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]17#
18ENTRY(store_status)
19 /* Save register one and load save area base */
Martin Schwidefskyc5328902011-12-27 11:27:15 +0100[diff] [blame]20 stg %r1,__LC_SAVE_AREA_RESTART
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]21 /* General purpose registers */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]22 lghi %r1,__LC_GPREGS_SAVE_AREA
23 stmg %r0,%r15,0(%r1)
24 mvc 8(8,%r1),__LC_SAVE_AREA_RESTART
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]25 /* Control registers */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]26 lghi %r1,__LC_CREGS_SAVE_AREA
27 stctg %c0,%c15,0(%r1)
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]28 /* Access registers */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]29 lghi %r1,__LC_AREGS_SAVE_AREA
30 stam %a0,%a15,0(%r1)
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]31 /* Floating point registers */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]32 lghi %r1,__LC_FPREGS_SAVE_AREA
33 std %f0, 0x00(%r1)
34 std %f1, 0x08(%r1)
35 std %f2, 0x10(%r1)
36 std %f3, 0x18(%r1)
37 std %f4, 0x20(%r1)
38 std %f5, 0x28(%r1)
39 std %f6, 0x30(%r1)
40 std %f7, 0x38(%r1)
41 std %f8, 0x40(%r1)
42 std %f9, 0x48(%r1)
43 std %f10,0x50(%r1)
44 std %f11,0x58(%r1)
45 std %f12,0x60(%r1)
46 std %f13,0x68(%r1)
47 std %f14,0x70(%r1)
48 std %f15,0x78(%r1)
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]49 /* Floating point control register */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]50 lghi %r1,__LC_FP_CREG_SAVE_AREA
51 stfpc 0(%r1)
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]52 /* CPU timer */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]53 lghi %r1,__LC_CPU_TIMER_SAVE_AREA
54 stpt 0(%r1)
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]55 /* Store prefix register */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]56 lghi %r1,__LC_PREFIX_SAVE_AREA
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]57 stpx 0(%r1)
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]58 /* Clock comparator - seven bytes */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]59 lghi %r1,__LC_CLOCK_COMP_SAVE_AREA
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]60 larl %r4,.Lclkcmp
61 stckc 0(%r4)
62 mvc 1(7,%r1),1(%r4)
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]63 /* Program status word */
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]64 lghi %r1,__LC_PSW_SAVE_AREA
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]65 epsw %r4,%r5
66 st %r4,0(%r1)
67 st %r5,4(%r1)
Martin Schwidefskyf08b84142015-10-23 09:05:38 +0200[diff] [blame]68 stg %r2,8(%r1)
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]69 lgr %r1,%r2
70 lgr %r2,%r3
71 br %r1
Michael Holzheu60a0c682011-10-30 15:16:40 +0100[diff] [blame]72
73 .section .bss
74 .align 8
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]75.Lclkcmp: .quad 0x0000000000000000
Michael Holzheu60a0c682011-10-30 15:16:40 +0100[diff] [blame]76 .previous
Michael Holzheuef1daec2011-08-03 16:44:21 +0200[diff] [blame]77
78#
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]79# do_reipl_asm
80# Parameter: r2 = schid of reipl device
81#
82
Jan Glauber144d6342011-07-24 10:48:19 +0200[diff] [blame]83ENTRY(do_reipl_asm)
84 basr %r13,0
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]85.Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]86.Lpg1: lgr %r3,%r2
87 larl %r2,.Lstatus
88 brasl %r14,store_status
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]89
Martin Schwidefsky1a36a392015-10-29 10:28:26 +0100[diff] [blame]90.Lstatus: lctlg %c6,%c6,.Lall-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]91 lgr %r1,%r2
92 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
93 stsch .Lschib-.Lpg0(%r13)
94 oi .Lschib+5-.Lpg0(%r13),0x84
Heiko Carstens4bfc86c2015-02-13 13:04:39 +0100[diff] [blame]95.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]96 msch .Lschib-.Lpg0(%r13)
97 lghi %r0,5
98.Lssch: ssch .Liplorb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]99 jz .L001
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]100 brct %r0,.Lssch
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]101 bas %r14,.Ldisab-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]102.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
103.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]104.Lcont: c %r1,__LC_SUBCHANNEL_ID
105 jnz .Ltpi
106 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
107 jnz .Ltpi
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]108 tsch .Liplirb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]109 tm .Liplirb+9-.Lpg0(%r13),0xbf
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]110 jz .L002
111 bas %r14,.Ldisab-.Lpg0(%r13)
112.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
113 jz .L003
114 bas %r14,.Ldisab-.Lpg0(%r13)
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]115.L003: st %r1,__LC_SUBCHANNEL_ID
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]116 lhi %r1,0 # mode 0 = esa
Heiko Carstens4bfc86c2015-02-13 13:04:39 +0100[diff] [blame]117 slr %r0,%r0 # set cpuid to zero
Heiko Carstenseb546192012-06-04 15:05:43 +0200[diff] [blame]118 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]119 lpsw 0
120.Ldisab: sll %r14,1
121 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
122 st %r14,.Ldispsw+12-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]123 lpswe .Ldispsw-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]124 .align 8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]125.Lall: .quad 0x00000000ff000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]126 .align 16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]127/*
128 * These addresses have to be 31 bit otherwise
129 * the sigp will throw a specifcation exception
130 * when switching to ESA mode as bit 31 be set
131 * in the ESA psw.
132 * Bit 31 of the addresses has to be 0 for the
133 * 31bit lpswe instruction a fact they appear to have
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]134 * omitted from the pop.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]135 */
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]136.Lnewpsw: .quad 0x0000000080000000
137 .quad .Lpg1
138.Lpcnew: .quad 0x0000000080000000
139 .quad .Lecs
140.Lionew: .quad 0x0000000080000000
141 .quad .Lcont
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]142.Lwaitpsw: .quad 0x0202000080000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]143 .quad .Ltpi
144.Ldispsw: .quad 0x0002000080000000
145 .quad 0x0000000000000000
146.Liplccws: .long 0x02000000,0x60000018
147 .long 0x08000008,0x20000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]148.Liplorb: .long 0x0049504c,0x0040ff80
149 .long 0x00000000+.Liplccws
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]150.Lschib: .long 0x00000000,0x00000000
151 .long 0x00000000,0x00000000
152 .long 0x00000000,0x00000000
153 .long 0x00000000,0x00000000
154 .long 0x00000000,0x00000000
155 .long 0x00000000,0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]156.Liplirb: .long 0x00000000,0x00000000
157 .long 0x00000000,0x00000000
158 .long 0x00000000,0x00000000
159 .long 0x00000000,0x00000000
160 .long 0x00000000,0x00000000
161 .long 0x00000000,0x00000000
162 .long 0x00000000,0x00000000
163 .long 0x00000000,0x00000000