Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 1 | /* |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 2 | * arch/arm/mach-orion5x/pci.c |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 3 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 4 | * PCI and PCIe functions for Marvell Orion System On Chip |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/pci.h> |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 15 | #include <linux/mbus.h> |
Nicolas Pitre | ff89c46 | 2009-01-07 04:52:58 +0100 | [diff] [blame] | 16 | #include <asm/irq.h> |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 17 | #include <asm/mach/pci.h> |
Lennert Buytenhek | 6f088f1 | 2008-08-09 13:44:58 +0200 | [diff] [blame] | 18 | #include <plat/pcie.h> |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 19 | #include "common.h" |
| 20 | |
| 21 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 22 | * Orion has one PCIe controller and one PCI controller. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 23 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 24 | * Note1: The local PCIe bus number is '0'. The local PCI bus number |
| 25 | * follows the scanned PCIe bridged busses, if any. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 26 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 27 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 28 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on |
| 29 | * device bus, Orion registers, etc. However this code only enable the |
| 30 | * access to DDR banks. |
| 31 | ****************************************************************************/ |
| 32 | |
| 33 | |
| 34 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 35 | * PCIe controller |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 36 | ****************************************************************************/ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 37 | #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 38 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 39 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 40 | { |
| 41 | *dev = orion_pcie_dev_id(PCIE_BASE); |
| 42 | *rev = orion_pcie_rev(PCIE_BASE); |
| 43 | } |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 44 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 45 | static int pcie_valid_config(int bus, int dev) |
| 46 | { |
| 47 | /* |
| 48 | * Don't go out when trying to access -- |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 49 | * 1. nonexisting device on local bus |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 50 | * 2. where there's no device connected (no link) |
| 51 | */ |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 52 | if (bus == 0 && dev == 0) |
| 53 | return 1; |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 54 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 55 | if (!orion_pcie_link_up(PCIE_BASE)) |
| 56 | return 0; |
| 57 | |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 58 | if (bus == 0 && dev != 1) |
| 59 | return 0; |
| 60 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 61 | return 1; |
| 62 | } |
| 63 | |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 64 | |
| 65 | /* |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 66 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 67 | * and then reading the PCIE_CONF_DATA register. Need to make sure these |
| 68 | * transactions are atomic. |
| 69 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 70 | static DEFINE_SPINLOCK(orion5x_pcie_lock); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 71 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 72 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 73 | int size, u32 *val) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 74 | { |
| 75 | unsigned long flags; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 76 | int ret; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 77 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 78 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 79 | *val = 0xffffffff; |
| 80 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 81 | } |
| 82 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 83 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 84 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 85 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 86 | |
| 87 | return ret; |
| 88 | } |
| 89 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 90 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, |
| 91 | int where, int size, u32 *val) |
| 92 | { |
| 93 | int ret; |
| 94 | |
| 95 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
| 96 | *val = 0xffffffff; |
| 97 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * We only support access to the non-extended configuration |
| 102 | * space when using the WA access method (or we would have to |
| 103 | * sacrifice 256M of CPU virtual address space.) |
| 104 | */ |
| 105 | if (where >= 0x100) { |
| 106 | *val = 0xffffffff; |
| 107 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 108 | } |
| 109 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 110 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 111 | bus, devfn, where, size, val); |
| 112 | |
| 113 | return ret; |
| 114 | } |
| 115 | |
| 116 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 117 | int where, int size, u32 val) |
| 118 | { |
| 119 | unsigned long flags; |
| 120 | int ret; |
| 121 | |
| 122 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
| 123 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 124 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 125 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 126 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 127 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 128 | |
| 129 | return ret; |
| 130 | } |
| 131 | |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 132 | static struct pci_ops pcie_ops = { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 133 | .read = pcie_rd_conf, |
| 134 | .write = pcie_wr_conf, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 135 | }; |
| 136 | |
| 137 | |
Lennert Buytenhek | a9984270 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 138 | static int __init pcie_setup(struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 139 | { |
| 140 | struct resource *res; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 141 | int dev; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 142 | |
| 143 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 144 | * Generic PCIe unit setup. |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 145 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 146 | orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 147 | |
| 148 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 149 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
| 150 | * read transaction workaround. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 151 | */ |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 152 | dev = orion_pcie_dev_id(PCIE_BASE); |
| 153 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { |
| 154 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " |
| 155 | "read transaction workaround\n"); |
Lennert Buytenhek | 386a048 | 2008-05-10 17:01:18 +0200 | [diff] [blame] | 156 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 157 | ORION5X_PCIE_WA_SIZE); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 158 | pcie_ops.read = pcie_rd_conf_wa; |
| 159 | } |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 160 | |
| 161 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 162 | * Request resources. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 163 | */ |
| 164 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); |
| 165 | if (!res) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 166 | panic("pcie_setup unable to alloc resources"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 167 | |
| 168 | /* |
| 169 | * IORESOURCE_IO |
| 170 | */ |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 171 | res[0].name = "PCIe I/O Space"; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 172 | res[0].flags = IORESOURCE_IO; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 173 | res[0].start = ORION5X_PCIE_IO_BUS_BASE; |
| 174 | res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 175 | if (request_resource(&ioport_resource, &res[0])) |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 176 | panic("Request PCIe IO resource failed\n"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 177 | sys->resource[0] = &res[0]; |
| 178 | |
| 179 | /* |
| 180 | * IORESOURCE_MEM |
| 181 | */ |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 182 | res[1].name = "PCIe Memory Space"; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 183 | res[1].flags = IORESOURCE_MEM; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 184 | res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; |
| 185 | res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 186 | if (request_resource(&iomem_resource, &res[1])) |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 187 | panic("Request PCIe Memory resource failed\n"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 188 | sys->resource[1] = &res[1]; |
| 189 | |
| 190 | sys->resource[2] = NULL; |
| 191 | sys->io_offset = 0; |
| 192 | |
| 193 | return 1; |
| 194 | } |
| 195 | |
| 196 | /***************************************************************************** |
| 197 | * PCI controller |
| 198 | ****************************************************************************/ |
Nicolas Pitre | fdd8b07 | 2009-04-22 20:08:17 +0100 | [diff] [blame] | 199 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 200 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
| 201 | #define PCI_CMD ORION5X_PCI_REG(0xc00) |
| 202 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) |
| 203 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) |
| 204 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 205 | |
| 206 | /* |
| 207 | * PCI_MODE bits |
| 208 | */ |
| 209 | #define PCI_MODE_64BIT (1 << 2) |
| 210 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) |
| 211 | |
| 212 | /* |
| 213 | * PCI_CMD bits |
| 214 | */ |
| 215 | #define PCI_CMD_HOST_REORDER (1 << 29) |
| 216 | |
| 217 | /* |
| 218 | * PCI_P2P_CONF bits |
| 219 | */ |
| 220 | #define PCI_P2P_BUS_OFFS 16 |
| 221 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) |
| 222 | #define PCI_P2P_DEV_OFFS 24 |
| 223 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) |
| 224 | |
| 225 | /* |
| 226 | * PCI_CONF_ADDR bits |
| 227 | */ |
| 228 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) |
| 229 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) |
| 230 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) |
| 231 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) |
| 232 | #define PCI_CONF_ADDR_EN (1 << 31) |
| 233 | |
| 234 | /* |
| 235 | * Internal configuration space |
| 236 | */ |
| 237 | #define PCI_CONF_FUNC_STAT_CMD 0 |
| 238 | #define PCI_CONF_REG_STAT_CMD 4 |
| 239 | #define PCIX_STAT 0x64 |
| 240 | #define PCIX_STAT_BUS_OFFS 8 |
| 241 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) |
| 242 | |
| 243 | /* |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 244 | * PCI Address Decode Windows registers |
| 245 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 246 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ |
Lennert Buytenhek | e7068ad | 2008-05-10 16:30:01 +0200 | [diff] [blame] | 247 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ |
| 248 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ |
| 249 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) |
| 250 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ |
| 251 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ |
| 252 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ |
| 253 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 254 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) |
| 255 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 256 | |
| 257 | /* |
| 258 | * PCI configuration helpers for BAR settings |
| 259 | */ |
| 260 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) |
| 261 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) |
| 262 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) |
| 263 | |
| 264 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 265 | * PCI config cycles are done by programming the PCI_CONF_ADDR register |
| 266 | * and then reading the PCI_CONF_DATA register. Need to make sure these |
| 267 | * transactions are atomic. |
| 268 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 269 | static DEFINE_SPINLOCK(orion5x_pci_lock); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 270 | |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 271 | static int orion5x_pci_cardbus_mode; |
| 272 | |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 273 | static int orion5x_pci_local_bus_nr(void) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 274 | { |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 275 | u32 conf = readl(PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 276 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); |
| 277 | } |
| 278 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 279 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 280 | u32 where, u32 size, u32 *val) |
| 281 | { |
| 282 | unsigned long flags; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 283 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 284 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 285 | writel(PCI_CONF_BUS(bus) | |
| 286 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
| 287 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 288 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 289 | *val = readl(PCI_CONF_DATA); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 290 | |
| 291 | if (size == 1) |
| 292 | *val = (*val >> (8*(where & 0x3))) & 0xff; |
| 293 | else if (size == 2) |
| 294 | *val = (*val >> (8*(where & 0x3))) & 0xffff; |
| 295 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 296 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 297 | |
| 298 | return PCIBIOS_SUCCESSFUL; |
| 299 | } |
| 300 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 301 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 302 | u32 where, u32 size, u32 val) |
| 303 | { |
| 304 | unsigned long flags; |
| 305 | int ret = PCIBIOS_SUCCESSFUL; |
| 306 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 307 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 308 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 309 | writel(PCI_CONF_BUS(bus) | |
| 310 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
| 311 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 312 | |
| 313 | if (size == 4) { |
| 314 | __raw_writel(val, PCI_CONF_DATA); |
| 315 | } else if (size == 2) { |
| 316 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); |
| 317 | } else if (size == 1) { |
| 318 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); |
| 319 | } else { |
| 320 | ret = PCIBIOS_BAD_REGISTER_NUMBER; |
| 321 | } |
| 322 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 323 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 324 | |
| 325 | return ret; |
| 326 | } |
| 327 | |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 328 | static int orion5x_pci_valid_config(int bus, u32 devfn) |
| 329 | { |
| 330 | if (bus == orion5x_pci_local_bus_nr()) { |
| 331 | /* |
| 332 | * Don't go out for local device |
| 333 | */ |
| 334 | if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) |
| 335 | return 0; |
| 336 | |
| 337 | /* |
| 338 | * When the PCI signals are directly connected to a |
| 339 | * Cardbus slot, ignore all but device IDs 0 and 1. |
| 340 | */ |
| 341 | if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) |
| 342 | return 0; |
| 343 | } |
| 344 | |
| 345 | return 1; |
| 346 | } |
| 347 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 348 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 349 | int where, int size, u32 *val) |
| 350 | { |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 351 | if (!orion5x_pci_valid_config(bus->number, devfn)) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 352 | *val = 0xffffffff; |
| 353 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 354 | } |
| 355 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 356 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 357 | PCI_FUNC(devfn), where, size, val); |
| 358 | } |
| 359 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 360 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 361 | int where, int size, u32 val) |
| 362 | { |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 363 | if (!orion5x_pci_valid_config(bus->number, devfn)) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 364 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 365 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 366 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 367 | PCI_FUNC(devfn), where, size, val); |
| 368 | } |
| 369 | |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 370 | static struct pci_ops pci_ops = { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 371 | .read = orion5x_pci_rd_conf, |
| 372 | .write = orion5x_pci_wr_conf, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 373 | }; |
| 374 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 375 | static void __init orion5x_pci_set_bus_nr(int nr) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 376 | { |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 377 | u32 p2p = readl(PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 378 | |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 379 | if (readl(PCI_MODE) & PCI_MODE_PCIX) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 380 | /* |
| 381 | * PCI-X mode |
| 382 | */ |
| 383 | u32 pcix_status, bus, dev; |
| 384 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; |
| 385 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 386 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 387 | pcix_status &= ~PCIX_STAT_BUS_MASK; |
| 388 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 389 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 390 | } else { |
| 391 | /* |
| 392 | * PCI Conventional mode |
| 393 | */ |
| 394 | p2p &= ~PCI_P2P_BUS_MASK; |
| 395 | p2p |= (nr << PCI_P2P_BUS_OFFS); |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 396 | writel(p2p, PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 397 | } |
| 398 | } |
| 399 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 400 | static void __init orion5x_pci_master_slave_enable(void) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 401 | { |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 402 | int bus_nr, func, reg; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 403 | u32 val; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 404 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 405 | bus_nr = orion5x_pci_local_bus_nr(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 406 | func = PCI_CONF_FUNC_STAT_CMD; |
| 407 | reg = PCI_CONF_REG_STAT_CMD; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 408 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 409 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 410 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 411 | } |
| 412 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 413 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 414 | { |
| 415 | u32 win_enable; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 416 | int bus; |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 417 | int i; |
| 418 | |
| 419 | /* |
| 420 | * First, disable windows. |
| 421 | */ |
| 422 | win_enable = 0xffffffff; |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 423 | writel(win_enable, PCI_BAR_ENABLE); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 424 | |
| 425 | /* |
| 426 | * Setup windows for DDR banks. |
| 427 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 428 | bus = orion5x_pci_local_bus_nr(); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 429 | |
| 430 | for (i = 0; i < dram->num_cs; i++) { |
| 431 | struct mbus_dram_window *cs = dram->cs + i; |
| 432 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); |
| 433 | u32 reg; |
| 434 | u32 val; |
| 435 | |
| 436 | /* |
| 437 | * Write DRAM bank base address register. |
| 438 | */ |
| 439 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 440 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 441 | val = (cs->base & 0xfffff000) | (val & 0xfff); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 442 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 443 | |
| 444 | /* |
| 445 | * Write DRAM bank size register. |
| 446 | */ |
| 447 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 448 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 449 | writel((cs->size - 1) & 0xfffff000, |
| 450 | PCI_BAR_SIZE_DDR_CS(cs->cs_index)); |
| 451 | writel(cs->base & 0xfffff000, |
| 452 | PCI_BAR_REMAP_DDR_CS(cs->cs_index)); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 453 | |
| 454 | /* |
| 455 | * Enable decode window for this chip select. |
| 456 | */ |
| 457 | win_enable &= ~(1 << cs->cs_index); |
| 458 | } |
| 459 | |
| 460 | /* |
| 461 | * Re-enable decode windows. |
| 462 | */ |
Lennert Buytenhek | 79e90dd | 2008-05-28 16:43:48 +0200 | [diff] [blame] | 463 | writel(win_enable, PCI_BAR_ENABLE); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 464 | |
| 465 | /* |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 466 | * Disable automatic update of address remapping when writing to BARs. |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 467 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 468 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 469 | } |
| 470 | |
Lennert Buytenhek | a9984270 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 471 | static int __init pci_setup(struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 472 | { |
| 473 | struct resource *res; |
| 474 | |
| 475 | /* |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 476 | * Point PCI unit MBUS decode windows to DRAM space. |
| 477 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 478 | orion5x_setup_pci_wins(&orion5x_mbus_dram_info); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 479 | |
| 480 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 481 | * Master + Slave enable |
| 482 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 483 | orion5x_pci_master_slave_enable(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 484 | |
| 485 | /* |
| 486 | * Force ordering |
| 487 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 488 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 489 | |
| 490 | /* |
| 491 | * Request resources |
| 492 | */ |
| 493 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); |
| 494 | if (!res) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 495 | panic("pci_setup unable to alloc resources"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 496 | |
| 497 | /* |
| 498 | * IORESOURCE_IO |
| 499 | */ |
| 500 | res[0].name = "PCI I/O Space"; |
| 501 | res[0].flags = IORESOURCE_IO; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 502 | res[0].start = ORION5X_PCI_IO_BUS_BASE; |
| 503 | res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 504 | if (request_resource(&ioport_resource, &res[0])) |
| 505 | panic("Request PCI IO resource failed\n"); |
| 506 | sys->resource[0] = &res[0]; |
| 507 | |
| 508 | /* |
| 509 | * IORESOURCE_MEM |
| 510 | */ |
| 511 | res[1].name = "PCI Memory Space"; |
| 512 | res[1].flags = IORESOURCE_MEM; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 513 | res[1].start = ORION5X_PCI_MEM_PHYS_BASE; |
| 514 | res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 515 | if (request_resource(&iomem_resource, &res[1])) |
| 516 | panic("Request PCI Memory resource failed\n"); |
| 517 | sys->resource[1] = &res[1]; |
| 518 | |
| 519 | sys->resource[2] = NULL; |
| 520 | sys->io_offset = 0; |
| 521 | |
| 522 | return 1; |
| 523 | } |
| 524 | |
| 525 | |
| 526 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 527 | * General PCIe + PCI |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 528 | ****************************************************************************/ |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 529 | static void __devinit rc_pci_fixup(struct pci_dev *dev) |
| 530 | { |
| 531 | /* |
| 532 | * Prevent enumeration of root complex. |
| 533 | */ |
| 534 | if (dev->bus->parent == NULL && dev->devfn == 0) { |
| 535 | int i; |
| 536 | |
| 537 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 538 | dev->resource[i].start = 0; |
| 539 | dev->resource[i].end = 0; |
| 540 | dev->resource[i].flags = 0; |
| 541 | } |
| 542 | } |
| 543 | } |
| 544 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); |
| 545 | |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 546 | static int orion5x_pci_disabled __initdata; |
| 547 | |
| 548 | void __init orion5x_pci_disable(void) |
| 549 | { |
| 550 | orion5x_pci_disabled = 1; |
| 551 | } |
| 552 | |
Lennert Buytenhek | da01bba | 2008-06-26 17:12:50 +0200 | [diff] [blame] | 553 | void __init orion5x_pci_set_cardbus_mode(void) |
| 554 | { |
| 555 | orion5x_pci_cardbus_mode = 1; |
| 556 | } |
| 557 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 558 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 559 | { |
| 560 | int ret = 0; |
| 561 | |
| 562 | if (nr == 0) { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 563 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
| 564 | ret = pcie_setup(sys); |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 565 | } else if (nr == 1 && !orion5x_pci_disabled) { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 566 | orion5x_pci_set_bus_nr(sys->busnr); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 567 | ret = pci_setup(sys); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | return ret; |
| 571 | } |
| 572 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 573 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 574 | { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 575 | struct pci_bus *bus; |
| 576 | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 577 | if (nr == 0) { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 578 | bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 579 | } else if (nr == 1 && !orion5x_pci_disabled) { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 580 | bus = pci_scan_bus(sys->busnr, &pci_ops, sys); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 581 | } else { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 582 | bus = NULL; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 583 | BUG(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 584 | } |
| 585 | |
| 586 | return bus; |
| 587 | } |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 588 | |
| 589 | int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 590 | { |
| 591 | int bus = dev->bus->number; |
| 592 | |
| 593 | /* |
| 594 | * PCIe endpoint? |
| 595 | */ |
Per Andersson | 7a6bb26 | 2008-08-11 12:00:52 +0200 | [diff] [blame] | 596 | if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 597 | return IRQ_ORION5X_PCIE0_INT; |
| 598 | |
| 599 | return -1; |
| 600 | } |