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Tzachi Perelstein038ee082007-10-23 15:14:42 -04001/*
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -04002 * arch/arm/mach-orion5x/pci.c
Tzachi Perelstein038ee082007-10-23 15:14:42 -04003 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -04004 * PCI and PCIe functions for Marvell Orion System On Chip
Tzachi Perelstein038ee082007-10-23 15:14:42 -04005 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -04008 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
Tzachi Perelstein038ee082007-10-23 15:14:42 -040010 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -040015#include <linux/mbus.h>
Nicolas Pitreff89c462009-01-07 04:52:58 +010016#include <asm/irq.h>
Tzachi Perelstein038ee082007-10-23 15:14:42 -040017#include <asm/mach/pci.h>
Lennert Buytenhek6f088f12008-08-09 13:44:58 +020018#include <plat/pcie.h>
Tzachi Perelstein038ee082007-10-23 15:14:42 -040019#include "common.h"
20
21/*****************************************************************************
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040022 * Orion has one PCIe controller and one PCI controller.
Tzachi Perelstein038ee082007-10-23 15:14:42 -040023 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040024 * Note1: The local PCIe bus number is '0'. The local PCI bus number
25 * follows the scanned PCIe bridged busses, if any.
Tzachi Perelstein038ee082007-10-23 15:14:42 -040026 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040027 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
Tzachi Perelstein038ee082007-10-23 15:14:42 -040028 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
29 * device bus, Orion registers, etc. However this code only enable the
30 * access to DDR banks.
31 ****************************************************************************/
32
33
34/*****************************************************************************
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040035 * PCIe controller
Tzachi Perelstein038ee082007-10-23 15:14:42 -040036 ****************************************************************************/
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040037#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
Tzachi Perelstein038ee082007-10-23 15:14:42 -040038
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040039void __init orion5x_pcie_id(u32 *dev, u32 *rev)
Lennert Buytenhekabc01972008-03-27 14:51:40 -040040{
41 *dev = orion_pcie_dev_id(PCIE_BASE);
42 *rev = orion_pcie_rev(PCIE_BASE);
43}
Tzachi Perelstein038ee082007-10-23 15:14:42 -040044
Lennert Buytenhekabc01972008-03-27 14:51:40 -040045static int pcie_valid_config(int bus, int dev)
46{
47 /*
48 * Don't go out when trying to access --
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -040049 * 1. nonexisting device on local bus
Lennert Buytenhekabc01972008-03-27 14:51:40 -040050 * 2. where there's no device connected (no link)
51 */
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -040052 if (bus == 0 && dev == 0)
53 return 1;
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -040054
Lennert Buytenhekabc01972008-03-27 14:51:40 -040055 if (!orion_pcie_link_up(PCIE_BASE))
56 return 0;
57
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -040058 if (bus == 0 && dev != 1)
59 return 0;
60
Lennert Buytenhekabc01972008-03-27 14:51:40 -040061 return 1;
62}
63
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -040064
65/*
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040066 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
Tzachi Perelstein038ee082007-10-23 15:14:42 -040067 * and then reading the PCIE_CONF_DATA register. Need to make sure these
68 * transactions are atomic.
69 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040070static DEFINE_SPINLOCK(orion5x_pcie_lock);
Tzachi Perelstein038ee082007-10-23 15:14:42 -040071
Lennert Buytenhekabc01972008-03-27 14:51:40 -040072static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
73 int size, u32 *val)
Tzachi Perelstein038ee082007-10-23 15:14:42 -040074{
75 unsigned long flags;
Lennert Buytenhekabc01972008-03-27 14:51:40 -040076 int ret;
Tzachi Perelstein038ee082007-10-23 15:14:42 -040077
Lennert Buytenhekabc01972008-03-27 14:51:40 -040078 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
Tzachi Perelstein038ee082007-10-23 15:14:42 -040079 *val = 0xffffffff;
80 return PCIBIOS_DEVICE_NOT_FOUND;
81 }
82
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040083 spin_lock_irqsave(&orion5x_pcie_lock, flags);
Lennert Buytenhekabc01972008-03-27 14:51:40 -040084 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040085 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -040086
87 return ret;
88}
89
Lennert Buytenhekabc01972008-03-27 14:51:40 -040090static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
91 int where, int size, u32 *val)
92{
93 int ret;
94
95 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
96 *val = 0xffffffff;
97 return PCIBIOS_DEVICE_NOT_FOUND;
98 }
99
100 /*
101 * We only support access to the non-extended configuration
102 * space when using the WA access method (or we would have to
103 * sacrifice 256M of CPU virtual address space.)
104 */
105 if (where >= 0x100) {
106 *val = 0xffffffff;
107 return PCIBIOS_DEVICE_NOT_FOUND;
108 }
109
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400110 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400111 bus, devfn, where, size, val);
112
113 return ret;
114}
115
116static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
117 int where, int size, u32 val)
118{
119 unsigned long flags;
120 int ret;
121
122 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
123 return PCIBIOS_DEVICE_NOT_FOUND;
124
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400125 spin_lock_irqsave(&orion5x_pcie_lock, flags);
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400126 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400127 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400128
129 return ret;
130}
131
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400132static struct pci_ops pcie_ops = {
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400133 .read = pcie_rd_conf,
134 .write = pcie_wr_conf,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400135};
136
137
Lennert Buytenheka99842702008-03-27 14:51:41 -0400138static int __init pcie_setup(struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400139{
140 struct resource *res;
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400141 int dev;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400142
143 /*
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400144 * Generic PCIe unit setup.
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400145 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400146 orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400147
148 /*
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400149 * Check whether to apply Orion-1/Orion-NAS PCIe config
150 * read transaction workaround.
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400151 */
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400152 dev = orion_pcie_dev_id(PCIE_BASE);
153 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
154 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
155 "read transaction workaround\n");
Lennert Buytenhek386a0482008-05-10 17:01:18 +0200156 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
157 ORION5X_PCIE_WA_SIZE);
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400158 pcie_ops.read = pcie_rd_conf_wa;
159 }
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400160
161 /*
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400162 * Request resources.
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400163 */
164 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
165 if (!res)
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400166 panic("pcie_setup unable to alloc resources");
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400167
168 /*
169 * IORESOURCE_IO
170 */
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400171 res[0].name = "PCIe I/O Space";
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400172 res[0].flags = IORESOURCE_IO;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400173 res[0].start = ORION5X_PCIE_IO_BUS_BASE;
174 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400175 if (request_resource(&ioport_resource, &res[0]))
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400176 panic("Request PCIe IO resource failed\n");
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400177 sys->resource[0] = &res[0];
178
179 /*
180 * IORESOURCE_MEM
181 */
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400182 res[1].name = "PCIe Memory Space";
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400183 res[1].flags = IORESOURCE_MEM;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400184 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
185 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400186 if (request_resource(&iomem_resource, &res[1]))
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400187 panic("Request PCIe Memory resource failed\n");
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400188 sys->resource[1] = &res[1];
189
190 sys->resource[2] = NULL;
191 sys->io_offset = 0;
192
193 return 1;
194}
195
196/*****************************************************************************
197 * PCI controller
198 ****************************************************************************/
Nicolas Pitrefdd8b072009-04-22 20:08:17 +0100199#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400200#define PCI_MODE ORION5X_PCI_REG(0xd00)
201#define PCI_CMD ORION5X_PCI_REG(0xc00)
202#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
203#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
204#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400205
206/*
207 * PCI_MODE bits
208 */
209#define PCI_MODE_64BIT (1 << 2)
210#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
211
212/*
213 * PCI_CMD bits
214 */
215#define PCI_CMD_HOST_REORDER (1 << 29)
216
217/*
218 * PCI_P2P_CONF bits
219 */
220#define PCI_P2P_BUS_OFFS 16
221#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
222#define PCI_P2P_DEV_OFFS 24
223#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
224
225/*
226 * PCI_CONF_ADDR bits
227 */
228#define PCI_CONF_REG(reg) ((reg) & 0xfc)
229#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
230#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
231#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
232#define PCI_CONF_ADDR_EN (1 << 31)
233
234/*
235 * Internal configuration space
236 */
237#define PCI_CONF_FUNC_STAT_CMD 0
238#define PCI_CONF_REG_STAT_CMD 4
239#define PCIX_STAT 0x64
240#define PCIX_STAT_BUS_OFFS 8
241#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
242
243/*
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400244 * PCI Address Decode Windows registers
245 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400246#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
Lennert Buytenheke7068ad2008-05-10 16:30:01 +0200247 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
248 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
249 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
250#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
251 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
252 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
253 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400254#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
255#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400256
257/*
258 * PCI configuration helpers for BAR settings
259 */
260#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
261#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
262#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
263
264/*
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400265 * PCI config cycles are done by programming the PCI_CONF_ADDR register
266 * and then reading the PCI_CONF_DATA register. Need to make sure these
267 * transactions are atomic.
268 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400269static DEFINE_SPINLOCK(orion5x_pci_lock);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400270
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200271static int orion5x_pci_cardbus_mode;
272
Lennert Buytenhek92b913b2008-04-25 16:28:33 -0400273static int orion5x_pci_local_bus_nr(void)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400274{
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200275 u32 conf = readl(PCI_P2P_CONF);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400276 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
277}
278
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400279static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400280 u32 where, u32 size, u32 *val)
281{
282 unsigned long flags;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400283 spin_lock_irqsave(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400284
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200285 writel(PCI_CONF_BUS(bus) |
286 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
287 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400288
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200289 *val = readl(PCI_CONF_DATA);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400290
291 if (size == 1)
292 *val = (*val >> (8*(where & 0x3))) & 0xff;
293 else if (size == 2)
294 *val = (*val >> (8*(where & 0x3))) & 0xffff;
295
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400296 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400297
298 return PCIBIOS_SUCCESSFUL;
299}
300
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400301static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400302 u32 where, u32 size, u32 val)
303{
304 unsigned long flags;
305 int ret = PCIBIOS_SUCCESSFUL;
306
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400307 spin_lock_irqsave(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400308
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200309 writel(PCI_CONF_BUS(bus) |
310 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
311 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400312
313 if (size == 4) {
314 __raw_writel(val, PCI_CONF_DATA);
315 } else if (size == 2) {
316 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
317 } else if (size == 1) {
318 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
319 } else {
320 ret = PCIBIOS_BAD_REGISTER_NUMBER;
321 }
322
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400323 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400324
325 return ret;
326}
327
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200328static int orion5x_pci_valid_config(int bus, u32 devfn)
329{
330 if (bus == orion5x_pci_local_bus_nr()) {
331 /*
332 * Don't go out for local device
333 */
334 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
335 return 0;
336
337 /*
338 * When the PCI signals are directly connected to a
339 * Cardbus slot, ignore all but device IDs 0 and 1.
340 */
341 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
342 return 0;
343 }
344
345 return 1;
346}
347
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400348static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400349 int where, int size, u32 *val)
350{
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200351 if (!orion5x_pci_valid_config(bus->number, devfn)) {
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400352 *val = 0xffffffff;
353 return PCIBIOS_DEVICE_NOT_FOUND;
354 }
355
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400356 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400357 PCI_FUNC(devfn), where, size, val);
358}
359
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400360static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400361 int where, int size, u32 val)
362{
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200363 if (!orion5x_pci_valid_config(bus->number, devfn))
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400364 return PCIBIOS_DEVICE_NOT_FOUND;
365
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400366 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400367 PCI_FUNC(devfn), where, size, val);
368}
369
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400370static struct pci_ops pci_ops = {
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400371 .read = orion5x_pci_rd_conf,
372 .write = orion5x_pci_wr_conf,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400373};
374
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400375static void __init orion5x_pci_set_bus_nr(int nr)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400376{
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200377 u32 p2p = readl(PCI_P2P_CONF);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400378
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200379 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400380 /*
381 * PCI-X mode
382 */
383 u32 pcix_status, bus, dev;
384 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
385 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400386 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400387 pcix_status &= ~PCIX_STAT_BUS_MASK;
388 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400389 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400390 } else {
391 /*
392 * PCI Conventional mode
393 */
394 p2p &= ~PCI_P2P_BUS_MASK;
395 p2p |= (nr << PCI_P2P_BUS_OFFS);
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200396 writel(p2p, PCI_P2P_CONF);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400397 }
398}
399
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400400static void __init orion5x_pci_master_slave_enable(void)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400401{
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -0400402 int bus_nr, func, reg;
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400403 u32 val;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400404
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400405 bus_nr = orion5x_pci_local_bus_nr();
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400406 func = PCI_CONF_FUNC_STAT_CMD;
407 reg = PCI_CONF_REG_STAT_CMD;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400408 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400409 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400410 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400411}
412
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400413static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400414{
415 u32 win_enable;
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400416 int bus;
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400417 int i;
418
419 /*
420 * First, disable windows.
421 */
422 win_enable = 0xffffffff;
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200423 writel(win_enable, PCI_BAR_ENABLE);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400424
425 /*
426 * Setup windows for DDR banks.
427 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400428 bus = orion5x_pci_local_bus_nr();
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400429
430 for (i = 0; i < dram->num_cs; i++) {
431 struct mbus_dram_window *cs = dram->cs + i;
432 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
433 u32 reg;
434 u32 val;
435
436 /*
437 * Write DRAM bank base address register.
438 */
439 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400440 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400441 val = (cs->base & 0xfffff000) | (val & 0xfff);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400442 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400443
444 /*
445 * Write DRAM bank size register.
446 */
447 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400448 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200449 writel((cs->size - 1) & 0xfffff000,
450 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
451 writel(cs->base & 0xfffff000,
452 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400453
454 /*
455 * Enable decode window for this chip select.
456 */
457 win_enable &= ~(1 << cs->cs_index);
458 }
459
460 /*
461 * Re-enable decode windows.
462 */
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200463 writel(win_enable, PCI_BAR_ENABLE);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400464
465 /*
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200466 * Disable automatic update of address remapping when writing to BARs.
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400467 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400468 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400469}
470
Lennert Buytenheka99842702008-03-27 14:51:41 -0400471static int __init pci_setup(struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400472{
473 struct resource *res;
474
475 /*
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400476 * Point PCI unit MBUS decode windows to DRAM space.
477 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400478 orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400479
480 /*
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400481 * Master + Slave enable
482 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400483 orion5x_pci_master_slave_enable();
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400484
485 /*
486 * Force ordering
487 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400488 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400489
490 /*
491 * Request resources
492 */
493 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
494 if (!res)
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400495 panic("pci_setup unable to alloc resources");
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400496
497 /*
498 * IORESOURCE_IO
499 */
500 res[0].name = "PCI I/O Space";
501 res[0].flags = IORESOURCE_IO;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400502 res[0].start = ORION5X_PCI_IO_BUS_BASE;
503 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400504 if (request_resource(&ioport_resource, &res[0]))
505 panic("Request PCI IO resource failed\n");
506 sys->resource[0] = &res[0];
507
508 /*
509 * IORESOURCE_MEM
510 */
511 res[1].name = "PCI Memory Space";
512 res[1].flags = IORESOURCE_MEM;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400513 res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
514 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400515 if (request_resource(&iomem_resource, &res[1]))
516 panic("Request PCI Memory resource failed\n");
517 sys->resource[1] = &res[1];
518
519 sys->resource[2] = NULL;
520 sys->io_offset = 0;
521
522 return 1;
523}
524
525
526/*****************************************************************************
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400527 * General PCIe + PCI
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400528 ****************************************************************************/
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -0400529static void __devinit rc_pci_fixup(struct pci_dev *dev)
530{
531 /*
532 * Prevent enumeration of root complex.
533 */
534 if (dev->bus->parent == NULL && dev->devfn == 0) {
535 int i;
536
537 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
538 dev->resource[i].start = 0;
539 dev->resource[i].end = 0;
540 dev->resource[i].flags = 0;
541 }
542 }
543}
544DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
545
Per Andersson7a6bb262008-08-11 12:00:52 +0200546static int orion5x_pci_disabled __initdata;
547
548void __init orion5x_pci_disable(void)
549{
550 orion5x_pci_disabled = 1;
551}
552
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200553void __init orion5x_pci_set_cardbus_mode(void)
554{
555 orion5x_pci_cardbus_mode = 1;
556}
557
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400558int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400559{
560 int ret = 0;
561
562 if (nr == 0) {
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400563 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
564 ret = pcie_setup(sys);
Per Andersson7a6bb262008-08-11 12:00:52 +0200565 } else if (nr == 1 && !orion5x_pci_disabled) {
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400566 orion5x_pci_set_bus_nr(sys->busnr);
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400567 ret = pci_setup(sys);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400568 }
569
570 return ret;
571}
572
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400573struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400574{
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400575 struct pci_bus *bus;
576
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400577 if (nr == 0) {
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400578 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
Per Andersson7a6bb262008-08-11 12:00:52 +0200579 } else if (nr == 1 && !orion5x_pci_disabled) {
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400580 bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400581 } else {
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400582 bus = NULL;
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400583 BUG();
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400584 }
585
586 return bus;
587}
Lennert Buytenhek92b913b2008-04-25 16:28:33 -0400588
589int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
590{
591 int bus = dev->bus->number;
592
593 /*
594 * PCIe endpoint?
595 */
Per Andersson7a6bb262008-08-11 12:00:52 +0200596 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
Lennert Buytenhek92b913b2008-04-25 16:28:33 -0400597 return IRQ_ORION5X_PCIE0_INT;
598
599 return -1;
600}