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Dinh Nguyen4b36daf2019-04-03 16:43:51 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019, Intel Corporation
4 */
5
6/dts-v1/;
7#include <dt-bindings/reset/altr,rst-mgr-s10.h>
8#include <dt-bindings/gpio/gpio.h>
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +01009#include <dt-bindings/interrupt-controller/arm-gic.h>
Dinh Nguyen48f36de2019-08-09 12:28:06 -070010#include <dt-bindings/clock/agilex-clock.h>
Dinh Nguyen4b36daf2019-04-03 16:43:51 -050011
12/ {
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
Richard Gongaa743372019-10-17 14:34:40 -050017 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
20 ranges;
21
22 service_reserved: svcbuffer@0 {
23 compatible = "shared-dma-pool";
Richard Gong2232aeb2020-08-04 17:01:32 -050024 reg = <0x0 0x0 0x0 0x2000000>;
Richard Gongaa743372019-10-17 14:34:40 -050025 alignment = <0x1000>;
26 no-map;
27 };
28 };
29
Dinh Nguyen4b36daf2019-04-03 16:43:51 -050030 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu0: cpu@0 {
35 compatible = "arm,cortex-a53";
36 device_type = "cpu";
37 enable-method = "psci";
38 reg = <0x0>;
39 };
40
41 cpu1: cpu@1 {
42 compatible = "arm,cortex-a53";
43 device_type = "cpu";
44 enable-method = "psci";
45 reg = <0x1>;
46 };
47
48 cpu2: cpu@2 {
49 compatible = "arm,cortex-a53";
50 device_type = "cpu";
51 enable-method = "psci";
52 reg = <0x2>;
53 };
54
55 cpu3: cpu@3 {
56 compatible = "arm,cortex-a53";
57 device_type = "cpu";
58 enable-method = "psci";
59 reg = <0x3>;
60 };
61 };
62
63 pmu {
64 compatible = "arm,armv8-pmuv3";
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +010065 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -050069 interrupt-affinity = <&cpu0>,
70 <&cpu1>,
71 <&cpu2>,
72 <&cpu3>;
73 interrupt-parent = <&intc>;
74 };
75
76 psci {
77 compatible = "arm,psci-0.2";
78 method = "smc";
79 };
80
Krzysztof Kozlowskiae68efe2021-03-08 18:09:43 +010081 intc: interrupt-controller@fffc1000 {
Dinh Nguyen4b36daf2019-04-03 16:43:51 -050082 compatible = "arm,gic-400", "arm,cortex-a15-gic";
83 #interrupt-cells = <3>;
84 interrupt-controller;
85 reg = <0x0 0xfffc1000 0x0 0x1000>,
86 <0x0 0xfffc2000 0x0 0x2000>,
87 <0x0 0xfffc4000 0x0 0x2000>,
88 <0x0 0xfffc6000 0x0 0x2000>;
89 };
90
Krzysztof Kozlowskid2e59302021-03-08 18:09:38 +010091 clocks {
92 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 };
96
97 cb_intosc_ls_clk: cb-intosc-ls-clk {
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
100 };
101
102 f2s_free_clk: f2s-free-clk {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 };
106
107 osc1: osc1 {
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
110 };
111
112 qspi_clk: qspi-clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 clock-frequency = <200000000>;
116 };
117 };
118
Krzysztof Kozlowski9f1f6272021-03-08 18:09:39 +0100119 timer {
120 compatible = "arm,armv8-timer";
121 interrupt-parent = <&intc>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100122 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
123 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
124 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
125 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
Krzysztof Kozlowski9f1f6272021-03-08 18:09:39 +0100126 };
127
Krzysztof Kozlowski9e474422021-03-08 18:09:41 +0100128 usbphy0: usbphy {
129 #phy-cells = <0>;
130 compatible = "usb-nop-xceiv";
131 };
132
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500133 soc {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "simple-bus";
137 device_type = "soc";
138 interrupt-parent = <&intc>;
139 ranges = <0 0 0 0xffffffff>;
140
Richard Gongaa743372019-10-17 14:34:40 -0500141 base_fpga_region {
Dinh Nguyen2f8ba0372023-01-25 14:07:00 -0600142 #address-cells = <0x2>;
143 #size-cells = <0x2>;
Richard Gongaa743372019-10-17 14:34:40 -0500144 compatible = "fpga-region";
145 fpga-mgr = <&fpga_mgr>;
146 };
147
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700148 clkmgr: clock-controller@ffd10000 {
149 compatible = "intel,agilex-clkmgr";
150 reg = <0xffd10000 0x1000>;
151 #clock-cells = <1>;
152 };
153
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500154 gmac0: ethernet@ff800000 {
Ley Foon Tan8c867382020-02-27 04:20:14 +0800155 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500156 reg = <0xff800000 0x2000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100157 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500158 interrupt-names = "macirq";
159 mac-address = [00 00 00 00 00 00];
160 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
Dinh Nguyen331085a2023-06-27 16:59:42 -0500161 reset-names = "stmmaceth", "ahb";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500162 tx-fifo-depth = <16384>;
163 rx-fifo-depth = <16384>;
164 snps,multicast-filter-bins = <256>;
165 iommus = <&smmu 1>;
Thor Thayer2f804ba2019-11-12 08:56:00 -0600166 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
Dinh Nguyen6e043c62020-08-31 12:56:55 -0500167 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
168 clock-names = "stmmaceth", "ptp_ref";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500169 status = "disabled";
170 };
171
172 gmac1: ethernet@ff802000 {
Ley Foon Tan8c867382020-02-27 04:20:14 +0800173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500174 reg = <0xff802000 0x2000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100175 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500176 interrupt-names = "macirq";
177 mac-address = [00 00 00 00 00 00];
178 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
Dinh Nguyen331085a2023-06-27 16:59:42 -0500179 reset-names = "stmmaceth", "ahb";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500180 tx-fifo-depth = <16384>;
181 rx-fifo-depth = <16384>;
182 snps,multicast-filter-bins = <256>;
183 iommus = <&smmu 2>;
Dinh Nguyenb7ff3a42021-02-04 14:24:33 -0600184 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
Dinh Nguyen6e043c62020-08-31 12:56:55 -0500185 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
186 clock-names = "stmmaceth", "ptp_ref";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500187 status = "disabled";
188 };
189
190 gmac2: ethernet@ff804000 {
Ley Foon Tan8c867382020-02-27 04:20:14 +0800191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500192 reg = <0xff804000 0x2000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100193 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500194 interrupt-names = "macirq";
195 mac-address = [00 00 00 00 00 00];
196 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
Dinh Nguyen331085a2023-06-27 16:59:42 -0500197 reset-names = "stmmaceth", "ahb";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500198 tx-fifo-depth = <16384>;
199 rx-fifo-depth = <16384>;
200 snps,multicast-filter-bins = <256>;
201 iommus = <&smmu 3>;
Dinh Nguyenb7ff3a42021-02-04 14:24:33 -0600202 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
Dinh Nguyen6e043c62020-08-31 12:56:55 -0500203 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
204 clock-names = "stmmaceth", "ptp_ref";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500205 status = "disabled";
206 };
207
208 gpio0: gpio@ffc03200 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "snps,dw-apb-gpio";
212 reg = <0xffc03200 0x100>;
213 resets = <&rst GPIO0_RESET>;
214 status = "disabled";
215
216 porta: gpio-controller@0 {
217 compatible = "snps,dw-apb-gpio-port";
218 gpio-controller;
219 #gpio-cells = <2>;
220 snps,nr-gpios = <24>;
221 reg = <0>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100224 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500225 };
226 };
227
228 gpio1: gpio@ffc03300 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "snps,dw-apb-gpio";
232 reg = <0xffc03300 0x100>;
233 resets = <&rst GPIO1_RESET>;
234 status = "disabled";
235
236 portb: gpio-controller@0 {
237 compatible = "snps,dw-apb-gpio-port";
238 gpio-controller;
239 #gpio-cells = <2>;
240 snps,nr-gpios = <24>;
241 reg = <0>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100244 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500245 };
246 };
247
248 i2c0: i2c@ffc02800 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "snps,designware-i2c";
252 reg = <0xffc02800 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100253 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500254 resets = <&rst I2C0_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700255 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500256 status = "disabled";
257 };
258
259 i2c1: i2c@ffc02900 {
260 #address-cells = <1>;
261 #size-cells = <0>;
262 compatible = "snps,designware-i2c";
263 reg = <0xffc02900 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500265 resets = <&rst I2C1_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700266 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500267 status = "disabled";
268 };
269
270 i2c2: i2c@ffc02a00 {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "snps,designware-i2c";
274 reg = <0xffc02a00 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100275 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500276 resets = <&rst I2C2_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700277 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500278 status = "disabled";
279 };
280
281 i2c3: i2c@ffc02b00 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "snps,designware-i2c";
285 reg = <0xffc02b00 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100286 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500287 resets = <&rst I2C3_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700288 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500289 status = "disabled";
290 };
291
292 i2c4: i2c@ffc02c00 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "snps,designware-i2c";
296 reg = <0xffc02c00 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500298 resets = <&rst I2C4_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700299 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500300 status = "disabled";
301 };
302
Krzysztof Kozlowski9ffc4e02021-12-27 14:35:58 +0100303 mmc: mmc@ff808000 {
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500304 #address-cells = <1>;
305 #size-cells = <0>;
306 compatible = "altr,socfpga-dw-mshc";
307 reg = <0xff808000 0x1000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100308 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500309 fifo-depth = <0x400>;
310 resets = <&rst SDMMC_RESET>;
311 reset-names = "reset";
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700312 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
313 <&clkmgr AGILEX_SDMMC_CLK>;
314 clock-names = "biu", "ciu";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500315 iommus = <&smmu 5>;
Dinh Nguyen31354122022-09-15 20:45:37 -0500316 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500317 status = "disabled";
318 };
319
Krzysztof Kozlowskiae68efe2021-03-08 18:09:43 +0100320 nand: nand-controller@ffb90000 {
Dinh Nguyen68441352019-11-08 09:39:30 -0600321 #address-cells = <1>;
322 #size-cells = <0>;
323 compatible = "altr,socfpga-denali-nand";
324 reg = <0xffb90000 0x10000>,
325 <0xffb80000 0x1000>;
326 reg-names = "nand_data", "denali_reg";
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100327 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyend4ae4dd2020-06-30 13:44:37 -0500328 clocks = <&clkmgr AGILEX_NAND_CLK>,
329 <&clkmgr AGILEX_NAND_X_CLK>,
330 <&clkmgr AGILEX_NAND_ECC_CLK>;
331 clock-names = "nand", "nand_x", "ecc";
Dinh Nguyen68441352019-11-08 09:39:30 -0600332 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
333 status = "disabled";
334 };
335
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500336 ocram: sram@ffe00000 {
337 compatible = "mmio-sram";
338 reg = <0xffe00000 0x40000>;
Dinh Nguyen6de298f2023-06-23 02:27:48 -0500339 #address-cells = <1>;
340 #size-cells = <1>;
341 ranges = <0 0xffe00000 0x40000>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500342 };
343
Krzysztof Kozlowskie3e4ffe2022-01-29 18:55:35 +0100344 pdma: dma-controller@ffda0000 {
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0xffda0000 0x1000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100347 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500356 #dma-cells = <1>;
Dinh Nguyene10c1842019-06-20 10:25:07 -0500357 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
358 reset-names = "dma", "dma-ocp";
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700359 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
360 clock-names = "apb_pclk";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500361 };
362
Dinh Nguyen21ab7032023-01-23 12:12:38 -0600363 pinctrl0: pinctrl@ffd13000 {
364 compatible = "pinctrl-single";
365 #pinctrl-cells = <1>;
366 reg = <0xffd13000 0xa0>;
367 pinctrl-single,register-width = <32>;
368 pinctrl-single,function-mask = <0x0000000f>;
369 };
370
371 pinctrl1: pinconf@ffd13100 {
372 compatible = "pinctrl-single";
373 #pinctrl-cells = <1>;
374 reg = <0xffd13100 0x20>;
375 pinctrl-single,register-width = <32>;
376 };
377
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500378 rst: rstmgr@ffd11000 {
Dinh Nguyenc91e8f32023-06-25 15:12:40 -0500379 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500380 reg = <0xffd11000 0x100>;
Dinh Nguyenc91e8f32023-06-25 15:12:40 -0500381 #reset-cells = <1>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500382 };
383
384 smmu: iommu@fa000000 {
385 compatible = "arm,mmu-500", "arm,smmu-v2";
386 reg = <0xfa000000 0x40000>;
387 #global-interrupts = <2>;
388 #iommu-cells = <1>;
389 interrupt-parent = <&intc>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100390 /* Global Secure Fault */
391 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
392 /* Global Non-secure Fault */
393 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500394 /* Non-secure Context Interrupts (32) */
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100395 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500427 stream-match-mask = <0x7ff0>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700428 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
429 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
430 <&clkmgr AGILEX_L4_MAIN_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500431 status = "disabled";
432 };
433
434 spi0: spi@ffda4000 {
435 compatible = "snps,dw-apb-ssi";
436 #address-cells = <1>;
437 #size-cells = <0>;
438 reg = <0xffda4000 0x1000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100439 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500440 resets = <&rst SPIM0_RESET>;
Dinh Nguyen0ef91cc2020-06-30 15:18:16 -0500441 reset-names = "spi";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500442 reg-io-width = <4>;
443 num-cs = <4>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700444 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500445 status = "disabled";
446 };
447
448 spi1: spi@ffda5000 {
449 compatible = "snps,dw-apb-ssi";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 reg = <0xffda5000 0x1000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100453 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500454 resets = <&rst SPIM1_RESET>;
Dinh Nguyen0ef91cc2020-06-30 15:18:16 -0500455 reset-names = "spi";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500456 reg-io-width = <4>;
457 num-cs = <4>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700458 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500459 status = "disabled";
460 };
461
462 sysmgr: sysmgr@ffd12000 {
Thor Thayera6706bd2019-11-08 16:40:53 -0600463 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500464 reg = <0xffd12000 0x500>;
465 };
466
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500467 timer0: timer0@ffc03000 {
468 compatible = "snps,dw-apb-timer";
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100469 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500470 reg = <0xffc03000 0x100>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700471 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
472 clock-names = "timer";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500473 };
474
475 timer1: timer1@ffc03100 {
476 compatible = "snps,dw-apb-timer";
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100477 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500478 reg = <0xffc03100 0x100>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700479 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
480 clock-names = "timer";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500481 };
482
483 timer2: timer2@ffd00000 {
484 compatible = "snps,dw-apb-timer";
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100485 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500486 reg = <0xffd00000 0x100>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700487 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
488 clock-names = "timer";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500489 };
490
491 timer3: timer3@ffd00100 {
492 compatible = "snps,dw-apb-timer";
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100493 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500494 reg = <0xffd00100 0x100>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700495 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
496 clock-names = "timer";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500497 };
498
Krzysztof Kozlowskiae68efe2021-03-08 18:09:43 +0100499 uart0: serial@ffc02000 {
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500500 compatible = "snps,dw-apb-uart";
501 reg = <0xffc02000 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100502 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500503 reg-shift = <2>;
504 reg-io-width = <4>;
505 resets = <&rst UART0_RESET>;
506 status = "disabled";
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700507 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500508 };
509
Krzysztof Kozlowskiae68efe2021-03-08 18:09:43 +0100510 uart1: serial@ffc02100 {
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500511 compatible = "snps,dw-apb-uart";
512 reg = <0xffc02100 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100513 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500514 reg-shift = <2>;
515 reg-io-width = <4>;
516 resets = <&rst UART1_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700517 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500518 status = "disabled";
519 };
520
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500521 usb0: usb@ffb00000 {
Dinh Nguyen268a4912022-01-06 17:53:31 -0600522 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500523 reg = <0xffb00000 0x40000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100524 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500525 phys = <&usbphy0>;
526 phy-names = "usb2-phy";
527 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
528 reset-names = "dwc2", "dwc2-ecc";
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700529 clocks = <&clkmgr AGILEX_USB_CLK>;
Krzysztof Kozlowski4b557e12022-02-18 17:15:22 +0100530 clock-names = "otg";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500531 iommus = <&smmu 6>;
532 status = "disabled";
533 };
534
535 usb1: usb@ffb40000 {
Dinh Nguyen268a4912022-01-06 17:53:31 -0600536 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500537 reg = <0xffb40000 0x40000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100538 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500539 phys = <&usbphy0>;
540 phy-names = "usb2-phy";
541 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
542 reset-names = "dwc2", "dwc2-ecc";
543 iommus = <&smmu 7>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700544 clocks = <&clkmgr AGILEX_USB_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500545 status = "disabled";
546 };
547
548 watchdog0: watchdog@ffd00200 {
549 compatible = "snps,dw-wdt";
550 reg = <0xffd00200 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100551 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500552 resets = <&rst WATCHDOG0_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700553 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500554 status = "disabled";
555 };
556
557 watchdog1: watchdog@ffd00300 {
558 compatible = "snps,dw-wdt";
559 reg = <0xffd00300 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100560 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500561 resets = <&rst WATCHDOG1_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700562 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500563 status = "disabled";
564 };
565
566 watchdog2: watchdog@ffd00400 {
567 compatible = "snps,dw-wdt";
568 reg = <0xffd00400 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100569 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500570 resets = <&rst WATCHDOG2_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700571 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500572 status = "disabled";
573 };
574
575 watchdog3: watchdog@ffd00500 {
576 compatible = "snps,dw-wdt";
577 reg = <0xffd00500 0x100>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100578 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500579 resets = <&rst WATCHDOG3_RESET>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700580 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500581 status = "disabled";
582 };
583
584 sdr: sdr@f8011100 {
585 compatible = "altr,sdr-ctl", "syscon";
586 reg = <0xf8011100 0xc0>;
587 };
588
Thor Thayer310704e2019-11-08 15:50:25 -0600589 eccmgr {
590 compatible = "altr,socfpga-s10-ecc-manager",
591 "altr,socfpga-a10-ecc-manager";
592 altr,sysmgr-syscon = <&sysmgr>;
593 #address-cells = <1>;
594 #size-cells = <1>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100595 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
Thor Thayer310704e2019-11-08 15:50:25 -0600596 interrupt-controller;
597 #interrupt-cells = <2>;
598 ranges;
599
600 sdramedac {
601 compatible = "altr,sdram-edac-s10";
602 altr,sdr-syscon = <&sdr>;
Niravkumar L Rabaraa2a4ee52022-05-30 15:25:30 +0800603 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
Thor Thayer310704e2019-11-08 15:50:25 -0600604 };
605
606 ocram-ecc@ff8cc000 {
607 compatible = "altr,socfpga-s10-ocram-ecc",
608 "altr,socfpga-a10-ocram-ecc";
609 reg = <0xff8cc000 0x100>;
610 altr,ecc-parent = <&ocram>;
Niravkumar L Rabaraa2a4ee52022-05-30 15:25:30 +0800611 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
Thor Thayer310704e2019-11-08 15:50:25 -0600612 };
613
614 usb0-ecc@ff8c4000 {
615 compatible = "altr,socfpga-s10-usb-ecc",
616 "altr,socfpga-usb-ecc";
617 reg = <0xff8c4000 0x100>;
618 altr,ecc-parent = <&usb0>;
Niravkumar L Rabaraa2a4ee52022-05-30 15:25:30 +0800619 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
Thor Thayer310704e2019-11-08 15:50:25 -0600620 };
621
622 emac0-rx-ecc@ff8c0000 {
623 compatible = "altr,socfpga-s10-eth-mac-ecc",
624 "altr,socfpga-eth-mac-ecc";
625 reg = <0xff8c0000 0x100>;
626 altr,ecc-parent = <&gmac0>;
Niravkumar L Rabaraa2a4ee52022-05-30 15:25:30 +0800627 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
Thor Thayer310704e2019-11-08 15:50:25 -0600628 };
629
630 emac0-tx-ecc@ff8c0400 {
631 compatible = "altr,socfpga-s10-eth-mac-ecc",
632 "altr,socfpga-eth-mac-ecc";
633 reg = <0xff8c0400 0x100>;
634 altr,ecc-parent = <&gmac0>;
Niravkumar L Rabaraa2a4ee52022-05-30 15:25:30 +0800635 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
Thor Thayer310704e2019-11-08 15:50:25 -0600636 };
637
638 sdmmca-ecc@ff8c8c00 {
639 compatible = "altr,socfpga-s10-sdmmc-ecc",
640 "altr,socfpga-sdmmc-ecc";
641 reg = <0xff8c8c00 0x100>;
642 altr,ecc-parent = <&mmc>;
Niravkumar L Rabaraa2a4ee52022-05-30 15:25:30 +0800643 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
644 <15 IRQ_TYPE_LEVEL_HIGH>;
Thor Thayer310704e2019-11-08 15:50:25 -0600645 };
646 };
647
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500648 qspi: spi@ff8d2000 {
Dinh Nguyen36de9912021-11-22 09:10:03 -0600649 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500650 #address-cells = <1>;
651 #size-cells = <0>;
652 reg = <0xff8d2000 0x100>,
653 <0xff900000 0x100000>;
Krzysztof Kozlowskif10ffbf2021-03-08 18:09:42 +0100654 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500655 cdns,fifo-depth = <128>;
656 cdns,fifo-width = <4>;
657 cdns,trigger-address = <0x00000000>;
Dinh Nguyen48f36de2019-08-09 12:28:06 -0700658 clocks = <&qspi_clk>;
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500659
660 status = "disabled";
661 };
Richard Gongaa743372019-10-17 14:34:40 -0500662
663 firmware {
664 svc {
Richard Gongfd0d0942020-02-14 10:00:50 -0600665 compatible = "intel,agilex-svc";
Richard Gongaa743372019-10-17 14:34:40 -0500666 method = "smc";
667 memory-region = <&service_reserved>;
668
669 fpga_mgr: fpga-mgr {
Richard Gong8d6b6bb2020-02-14 10:00:47 -0600670 compatible = "intel,agilex-soc-fpga-mgr";
Richard Gongaa743372019-10-17 14:34:40 -0500671 };
672 };
673 };
Dinh Nguyen4b36daf2019-04-03 16:43:51 -0500674 };
675};