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Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +00001#ifndef __POWERNV_PCI_H
2#define __POWERNV_PCI_H
3
4struct pci_dn;
5
6enum pnv_phb_type {
Gavin Shanaa0c0332013-04-25 19:20:57 +00007 PNV_PHB_P5IOC2 = 0,
8 PNV_PHB_IODA1 = 1,
9 PNV_PHB_IODA2 = 2,
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000010};
11
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000012/* Precise PHB model for error management */
13enum pnv_phb_model {
14 PNV_PHB_MODEL_UNKNOWN,
15 PNV_PHB_MODEL_P5IOC2,
16 PNV_PHB_MODEL_P7IOC,
Gavin Shanaa0c0332013-04-25 19:20:57 +000017 PNV_PHB_MODEL_PHB3,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000018};
19
Gavin Shan5c9d6d72013-09-06 09:00:03 +080020#define PNV_PCI_DIAG_BUF_SIZE 8192
Gavin Shan7ebdf952012-08-20 03:49:15 +000021#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
Guo Chao262af552014-07-21 14:42:30 +100024#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
Wei Yang781a8682015-03-25 16:23:57 +080026#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000027
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000028/* Data associated with a PE, including IOMMU tracking etc.. */
Gavin Shan4cce9552013-04-25 19:21:00 +000029struct pnv_phb;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000030struct pnv_ioda_pe {
Gavin Shan7ebdf952012-08-20 03:49:15 +000031 unsigned long flags;
Gavin Shan4cce9552013-04-25 19:21:00 +000032 struct pnv_phb *phb;
Gavin Shan7ebdf952012-08-20 03:49:15 +000033
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000034 /* A PE can be associated with a single device or an
35 * entire bus (& children). In the former case, pdev
36 * is populated, in the later case, pbus is.
37 */
Wei Yang781a8682015-03-25 16:23:57 +080038#ifdef CONFIG_PCI_IOV
39 struct pci_dev *parent_dev;
40#endif
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000041 struct pci_dev *pdev;
42 struct pci_bus *pbus;
43
44 /* Effective RID (device RID for a device PE and base bus
45 * RID with devfn 0 for a bus PE)
46 */
47 unsigned int rid;
48
49 /* PE number */
50 unsigned int pe_number;
51
52 /* "Weight" assigned to the PE for the sake of DMA resource
53 * allocations
54 */
55 unsigned int dma_weight;
56
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000057 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
58 int tce32_seg;
59 int tce32_segcount;
Alexey Kardashevskiyb348aa62015-06-05 16:35:08 +100060 struct iommu_table_group table_group;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000061
Benjamin Herrenschmidtcd15b042014-02-11 11:32:38 +110062 /* 64-bit TCE bypass region */
63 bool tce_bypass_enabled;
64 uint64_t tce_bypass_base;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000065
66 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
67 * and -1 if not supported. (It's actually identical to the
68 * PE number)
69 */
70 int mve_number;
71
Guo Chao262af552014-07-21 14:42:30 +100072 /* PEs in compound case */
73 struct pnv_ioda_pe *master;
74 struct list_head slaves;
75
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000076 /* Link in list of PE#s */
Gavin Shan7ebdf952012-08-20 03:49:15 +000077 struct list_head dma_link;
78 struct list_head list;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +000079};
80
Gavin Shanf5bc6b72014-04-24 18:00:09 +100081#define PNV_PHB_FLAG_EEH (1 << 0)
82
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000083struct pnv_phb {
84 struct pci_controller *hose;
85 enum pnv_phb_type type;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +000086 enum pnv_phb_model model;
Gavin Shan8747f362013-06-20 13:21:06 +080087 u64 hub_id;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000088 u64 opal_id;
Gavin Shanf5bc6b72014-04-24 18:00:09 +100089 int flags;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000090 void __iomem *regs;
Gavin Shandb1266c2012-08-20 03:49:18 +000091 int initialized;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +000092 spinlock_t lock;
93
Gavin Shan37c367f2013-06-20 18:13:25 +080094#ifdef CONFIG_DEBUG_FS
Gavin Shan7f52a5262014-04-24 18:00:18 +100095 int has_dbgfs;
Gavin Shan37c367f2013-06-20 18:13:25 +080096 struct dentry *dbgfs;
97#endif
98
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +000099#ifdef CONFIG_PCI_MSI
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000100 unsigned int msi_base;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000101 unsigned int msi32_support;
Gavin Shanfb1b55d2013-03-05 21:12:37 +0000102 struct msi_bitmap msi_bmp;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000103#endif
104 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
Gavin Shan137436c2013-04-25 19:20:59 +0000105 unsigned int hwirq, unsigned int virq,
106 unsigned int is_64, struct msi_msg *msg);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000107 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
Gavin Shanfe7e85c2014-09-30 12:39:10 +1000108 u64 (*dma_get_required_mask)(struct pnv_phb *phb,
109 struct pci_dev *pdev);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000110 void (*fixup_phb)(struct pci_controller *hose);
111 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
Guo Chao262af552014-07-21 14:42:30 +1000112 int (*init_m64)(struct pnv_phb *phb);
Gavin Shan96a2f922015-06-19 12:26:17 +1000113 void (*reserve_m64_pe)(struct pci_bus *bus,
114 unsigned long *pe_bitmap, bool all);
Guo Chao262af552014-07-21 14:42:30 +1000115 int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
Gavin Shan49dec922014-07-21 14:42:33 +1000116 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
117 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
118 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000119
120 union {
121 struct {
122 struct iommu_table iommu_table;
Alexey Kardashevskiyb348aa62015-06-05 16:35:08 +1000123 struct iommu_table_group table_group;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000124 } p5ioc2;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000125
126 struct {
127 /* Global bridge info */
128 unsigned int total_pe;
Gavin Shan36954dc2013-11-04 16:32:47 +0800129 unsigned int reserved_pe;
Guo Chao262af552014-07-21 14:42:30 +1000130
131 /* 32-bit MMIO window */
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000132 unsigned int m32_size;
133 unsigned int m32_segsize;
134 unsigned int m32_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000135
136 /* 64-bit MMIO window */
137 unsigned int m64_bar_idx;
138 unsigned long m64_size;
139 unsigned long m64_segsize;
140 unsigned long m64_base;
141 unsigned long m64_bar_alloc;
142
143 /* IO ports */
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000144 unsigned int io_size;
145 unsigned int io_segsize;
146 unsigned int io_pci_base;
147
148 /* PE allocation bitmap */
149 unsigned long *pe_alloc;
Wei Yang781a8682015-03-25 16:23:57 +0800150 /* PE allocation mutex */
151 struct mutex pe_alloc_mutex;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000152
153 /* M32 & IO segment maps */
154 unsigned int *m32_segmap;
155 unsigned int *io_segmap;
156 struct pnv_ioda_pe *pe_array;
157
Gavin Shan137436c2013-04-25 19:20:59 +0000158 /* IRQ chip */
159 int irq_chip_init;
160 struct irq_chip irq_chip;
161
Gavin Shan7ebdf952012-08-20 03:49:15 +0000162 /* Sorted list of used PE's based
163 * on the sequence of creation
164 */
165 struct list_head pe_list;
Wei Yang781a8682015-03-25 16:23:57 +0800166 struct mutex pe_list_mutex;
Gavin Shan7ebdf952012-08-20 03:49:15 +0000167
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000168 /* Reverse map of PEs, will have to extend if
169 * we are to support more than 256 PEs, indexed
170 * bus { bus, devfn }
171 */
172 unsigned char pe_rmap[0x10000];
173
174 /* 32-bit TCE tables allocation */
175 unsigned long tce32_count;
176
177 /* Total "weight" for the sake of DMA resources
178 * allocation
179 */
180 unsigned int dma_weight;
181 unsigned int dma_pe_count;
182
183 /* Sorted list of used PE's, sorted at
184 * boot for resource allocation purposes
185 */
Gavin Shan7ebdf952012-08-20 03:49:15 +0000186 struct list_head pe_dma_list;
Alexey Kardashevskiy5780fb02015-06-05 16:35:12 +1000187
188 /* TCE cache invalidate registers (physical and
189 * remapped)
190 */
191 phys_addr_t tce_inval_reg_phys;
192 __be64 __iomem *tce_inval_reg;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000193 } ioda;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000194 };
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000195
Brian W Hartca1de5d2013-12-20 13:06:01 -0600196 /* PHB and hub status structure */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000197 union {
198 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
199 struct OpalIoP7IOCPhbErrorData p7ioc;
Gavin Shan93aef2a2013-11-22 16:28:45 +0800200 struct OpalIoPhb3ErrorData phb3;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600201 struct OpalIoP7IOCErrorData hub_diag;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000202 } diag;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600203
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000204};
205
206extern struct pci_ops pnv_pci_ops;
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000207extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
208 unsigned long uaddr, enum dma_data_direction direction,
209 struct dma_attrs *attrs);
210extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
Alexey Kardashevskiy05c6cfb2015-06-05 16:35:15 +1000211extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
212 unsigned long *hpa, enum dma_data_direction *direction);
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000213extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000214
Gavin Shan93aef2a2013-11-22 16:28:45 +0800215void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
216 unsigned char *log_buff);
Gavin Shan3532a7412015-03-17 16:15:03 +1100217int pnv_pci_cfg_read(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800218 int where, int size, u32 *val);
Gavin Shan3532a7412015-03-17 16:15:03 +1100219int pnv_pci_cfg_write(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800220 int where, int size, u32 val);
Alexey Kardashevskiy0eaf4de2015-06-05 16:35:09 +1000221extern struct iommu_table *pnv_pci_table_alloc(int nid);
222
223extern long pnv_pci_link_table_and_group(int node, int num,
224 struct iommu_table *tbl,
225 struct iommu_table_group *table_group);
226extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
227 struct iommu_table_group *table_group);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000228extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
229 void *tce_mem, u64 tce_size,
Alexey Kardashevskiy8fa5d452014-06-06 18:44:03 +1000230 u64 dma_offset, unsigned page_shift);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000231extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000232extern void pnv_pci_init_ioda_hub(struct device_node *np);
Gavin Shanaa0c0332013-04-25 19:20:57 +0000233extern void pnv_pci_init_ioda2_phb(struct device_node *np);
Gavin Shan4cce9552013-04-25 19:21:00 +0000234extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
Benjamin Herrenschmidt3ad26e52013-10-11 18:23:53 +1100235 __be64 *startp, __be64 *endp, bool rm);
Gavin Shand92a2082014-04-24 18:00:24 +1000236extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
Gavin Shancadf3642015-02-16 14:45:47 +1100237extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
Benjamin Herrenschmidt73ed1482013-05-10 16:59:18 +1000238
Daniel Axtens92ae0352015-04-28 15:12:05 +1000239extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
240extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
241extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
242
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000243#endif /* __POWERNV_PCI_H */