Thomas Gleixner | 1621633 | 2019-05-19 15:51:31 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 2 | /* |
Juergen Beisert | 259bcaa | 2008-07-05 10:02:54 +0200 | [diff] [blame] | 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 4 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 7 | #include <linux/module.h> |
Juergen Beisert | 259bcaa | 2008-07-05 10:02:54 +0200 | [diff] [blame] | 8 | #include <linux/irq.h> |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 9 | #include <linux/irqdomain.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 10 | #include <linux/io.h> |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 11 | #include <linux/of.h> |
Martin Kaiser | 9b454d1 | 2018-02-27 22:29:15 +0100 | [diff] [blame] | 12 | #include <linux/of_address.h> |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 13 | #include <asm/mach/irq.h> |
Jason Liu | 98de0cb | 2011-11-03 17:31:26 +0800 | [diff] [blame] | 14 | #include <asm/exception.h> |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 15 | |
Shawn Guo | e337247 | 2012-09-13 21:01:00 +0800 | [diff] [blame] | 16 | #include "common.h" |
Shawn Guo | 50f2de6 | 2012-09-14 14:14:45 +0800 | [diff] [blame] | 17 | #include "hardware.h" |
Peter Horton | cdc3f10 | 2010-12-06 11:37:38 +0000 | [diff] [blame] | 18 | #include "irq-common.h" |
| 19 | |
Sascha Hauer | 84c9fa4 | 2009-02-18 20:59:04 +0100 | [diff] [blame] | 20 | #define AVIC_INTCNTL 0x00 /* int control reg */ |
| 21 | #define AVIC_NIMASK 0x04 /* int mask reg */ |
| 22 | #define AVIC_INTENNUM 0x08 /* int enable number reg */ |
| 23 | #define AVIC_INTDISNUM 0x0C /* int disable number reg */ |
| 24 | #define AVIC_INTENABLEH 0x10 /* int enable reg high */ |
| 25 | #define AVIC_INTENABLEL 0x14 /* int enable reg low */ |
| 26 | #define AVIC_INTTYPEH 0x18 /* int type reg high */ |
| 27 | #define AVIC_INTTYPEL 0x1C /* int type reg low */ |
| 28 | #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ |
| 29 | #define AVIC_NIVECSR 0x40 /* norm int vector/status */ |
| 30 | #define AVIC_FIVECSR 0x44 /* fast int vector/status */ |
| 31 | #define AVIC_INTSRCH 0x48 /* int source reg high */ |
| 32 | #define AVIC_INTSRCL 0x4C /* int source reg low */ |
| 33 | #define AVIC_INTFRCH 0x50 /* int force reg high */ |
| 34 | #define AVIC_INTFRCL 0x54 /* int force reg low */ |
| 35 | #define AVIC_NIPNDH 0x58 /* norm int pending high */ |
| 36 | #define AVIC_NIPNDL 0x5C /* norm int pending low */ |
| 37 | #define AVIC_FIPNDH 0x60 /* fast int pending high */ |
| 38 | #define AVIC_FIPNDL 0x64 /* fast int pending low */ |
| 39 | |
Sascha Hauer | 5a24d69 | 2011-05-10 18:16:10 +0200 | [diff] [blame] | 40 | #define AVIC_NUM_IRQS 64 |
| 41 | |
Martin Kaiser | 9b454d1 | 2018-02-27 22:29:15 +0100 | [diff] [blame] | 42 | /* low power interrupt mask registers */ |
| 43 | #define MX25_CCM_LPIMR0 0x68 |
| 44 | #define MX25_CCM_LPIMR1 0x6C |
| 45 | |
Fabio Estevam | ae00ac7 | 2013-03-25 09:20:40 -0300 | [diff] [blame] | 46 | static void __iomem *avic_base; |
Martin Kaiser | 9b454d1 | 2018-02-27 22:29:15 +0100 | [diff] [blame] | 47 | static void __iomem *mx25_ccm_base; |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 48 | static struct irq_domain *domain; |
Juergen Beisert | 259bcaa | 2008-07-05 10:02:54 +0200 | [diff] [blame] | 49 | |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 50 | #ifdef CONFIG_FIQ |
Alexander Shiyan | d1e1c31 | 2016-06-19 09:55:53 +0300 | [diff] [blame] | 51 | static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 52 | { |
| 53 | unsigned int irqt; |
| 54 | |
Alexander Shiyan | d1e1c31 | 2016-06-19 09:55:53 +0300 | [diff] [blame] | 55 | if (hwirq >= AVIC_NUM_IRQS) |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 56 | return -EINVAL; |
| 57 | |
Alexander Shiyan | d1e1c31 | 2016-06-19 09:55:53 +0300 | [diff] [blame] | 58 | if (hwirq < AVIC_NUM_IRQS / 2) { |
| 59 | irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); |
| 60 | imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 61 | } else { |
Alexander Shiyan | d1e1c31 | 2016-06-19 09:55:53 +0300 | [diff] [blame] | 62 | hwirq -= AVIC_NUM_IRQS / 2; |
| 63 | irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); |
| 64 | imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 69 | #endif /* CONFIG_FIQ */ |
| 70 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 71 | |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 72 | static struct mxc_extra_irq avic_extra_irq = { |
Peter Horton | cdc3f10 | 2010-12-06 11:37:38 +0000 | [diff] [blame] | 73 | #ifdef CONFIG_FIQ |
| 74 | .set_irq_fiq = avic_set_irq_fiq, |
| 75 | #endif |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 76 | }; |
| 77 | |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 78 | #ifdef CONFIG_PM |
Fabio Estevam | 5fe839d | 2013-02-05 15:36:16 -0200 | [diff] [blame] | 79 | static u32 avic_saved_mask_reg[2]; |
| 80 | |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 81 | static void avic_irq_suspend(struct irq_data *d) |
| 82 | { |
| 83 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 84 | struct irq_chip_type *ct = gc->chip_types; |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 85 | int idx = d->hwirq >> 5; |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 86 | |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame] | 87 | avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); |
| 88 | imx_writel(gc->wake_active, avic_base + ct->regs.mask); |
Martin Kaiser | 9b454d1 | 2018-02-27 22:29:15 +0100 | [diff] [blame] | 89 | |
| 90 | if (mx25_ccm_base) { |
| 91 | u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? |
| 92 | MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; |
| 93 | /* |
| 94 | * The interrupts which are still enabled will be used as wakeup |
| 95 | * sources. Allow those interrupts in low-power mode. |
| 96 | * The LPIMR registers use 0 to allow an interrupt, the AVIC |
| 97 | * registers use 1. |
| 98 | */ |
| 99 | imx_writel(~gc->wake_active, mx25_ccm_base + offs); |
| 100 | } |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | static void avic_irq_resume(struct irq_data *d) |
| 104 | { |
| 105 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 106 | struct irq_chip_type *ct = gc->chip_types; |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 107 | int idx = d->hwirq >> 5; |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 108 | |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame] | 109 | imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); |
Martin Kaiser | 9b454d1 | 2018-02-27 22:29:15 +0100 | [diff] [blame] | 110 | |
| 111 | if (mx25_ccm_base) { |
| 112 | u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? |
| 113 | MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; |
| 114 | |
| 115 | imx_writel(0xffffffff, mx25_ccm_base + offs); |
| 116 | } |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | #else |
| 120 | #define avic_irq_suspend NULL |
| 121 | #define avic_irq_resume NULL |
| 122 | #endif |
| 123 | |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 124 | static __init void avic_init_gc(int idx, unsigned int irq_start) |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 125 | { |
| 126 | struct irq_chip_generic *gc; |
| 127 | struct irq_chip_type *ct; |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 128 | |
| 129 | gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, |
| 130 | handle_level_irq); |
| 131 | gc->private = &avic_extra_irq; |
| 132 | gc->wake_enabled = IRQ_MSK(32); |
| 133 | |
| 134 | ct = gc->chip_types; |
| 135 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
| 136 | ct->chip.irq_unmask = irq_gc_mask_set_bit; |
| 137 | ct->chip.irq_ack = irq_gc_mask_clr_bit; |
| 138 | ct->chip.irq_set_wake = irq_gc_set_wake; |
| 139 | ct->chip.irq_suspend = avic_irq_suspend; |
| 140 | ct->chip.irq_resume = avic_irq_resume; |
| 141 | ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; |
| 142 | ct->regs.ack = ct->regs.mask; |
| 143 | |
| 144 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); |
| 145 | } |
| 146 | |
Alexander Shiyan | 000bf9e | 2014-05-11 11:35:57 +0400 | [diff] [blame] | 147 | static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) |
Sascha Hauer | b6de943 | 2011-09-20 14:28:17 +0200 | [diff] [blame] | 148 | { |
| 149 | u32 nivector; |
| 150 | |
| 151 | do { |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame] | 152 | nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; |
Sascha Hauer | b6de943 | 2011-09-20 14:28:17 +0200 | [diff] [blame] | 153 | if (nivector == 0xffff) |
| 154 | break; |
| 155 | |
Marc Zyngier | 9705ca3 | 2014-08-26 11:03:37 +0100 | [diff] [blame] | 156 | handle_domain_irq(domain, nivector, regs); |
Sascha Hauer | b6de943 | 2011-09-20 14:28:17 +0200 | [diff] [blame] | 157 | } while (1); |
| 158 | } |
| 159 | |
Robert Schwebel | 2c130fd | 2008-03-28 11:02:13 +0100 | [diff] [blame] | 160 | /* |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 161 | * This function initializes the AVIC hardware and disables all the |
| 162 | * interrupts. It registers the interrupt enable and disable functions |
| 163 | * to the kernel for each interrupt source. |
| 164 | */ |
Sascha Hauer | c5aa0ad | 2009-05-25 17:36:19 +0200 | [diff] [blame] | 165 | void __init mxc_init_irq(void __iomem *irqbase) |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 166 | { |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 167 | struct device_node *np; |
| 168 | int irq_base; |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 169 | int i; |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 170 | |
Sascha Hauer | c5aa0ad | 2009-05-25 17:36:19 +0200 | [diff] [blame] | 171 | avic_base = irqbase; |
Sascha Hauer | 84c9fa4 | 2009-02-18 20:59:04 +0100 | [diff] [blame] | 172 | |
Martin Kaiser | 9b454d1 | 2018-02-27 22:29:15 +0100 | [diff] [blame] | 173 | np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm"); |
| 174 | mx25_ccm_base = of_iomap(np, 0); |
| 175 | |
| 176 | if (mx25_ccm_base) { |
| 177 | /* |
| 178 | * By default, we mask all interrupts. We set the actual mask |
| 179 | * before we go into low-power mode. |
| 180 | */ |
| 181 | imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0); |
| 182 | imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1); |
| 183 | } |
| 184 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 185 | /* put the AVIC into the reset value with |
| 186 | * all interrupts disabled |
| 187 | */ |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame] | 188 | imx_writel(0, avic_base + AVIC_INTCNTL); |
| 189 | imx_writel(0x1f, avic_base + AVIC_NIMASK); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 190 | |
| 191 | /* disable all interrupts */ |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame] | 192 | imx_writel(0, avic_base + AVIC_INTENABLEH); |
| 193 | imx_writel(0, avic_base + AVIC_INTENABLEL); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 194 | |
| 195 | /* all IRQ no FIQ */ |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame] | 196 | imx_writel(0, avic_base + AVIC_INTTYPEH); |
| 197 | imx_writel(0, avic_base + AVIC_INTTYPEL); |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 198 | |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 199 | irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); |
| 200 | WARN_ON(irq_base < 0); |
| 201 | |
| 202 | np = of_find_compatible_node(NULL, NULL, "fsl,avic"); |
| 203 | domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, |
| 204 | &irq_domain_simple_ops, NULL); |
| 205 | WARN_ON(!domain); |
| 206 | |
| 207 | for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) |
| 208 | avic_init_gc(i, irq_base); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 209 | |
Darius Augulis | 479c901 | 2008-09-09 11:29:41 +0200 | [diff] [blame] | 210 | /* Set default priority value (0) for all IRQ's */ |
| 211 | for (i = 0; i < 8; i++) |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame] | 212 | imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 213 | |
Alexander Shiyan | 000bf9e | 2014-05-11 11:35:57 +0400 | [diff] [blame] | 214 | set_handle_irq(avic_handle_irq); |
| 215 | |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 216 | #ifdef CONFIG_FIQ |
| 217 | /* Initialize FIQ */ |
Shawn Guo | bc89663 | 2012-06-28 14:42:08 +0800 | [diff] [blame] | 218 | init_FIQ(FIQ_START); |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 219 | #endif |
| 220 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 221 | printk(KERN_INFO "MXC IRQ initialized\n"); |
| 222 | } |