Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 1 | config IRQCHIP |
| 2 | def_bool y |
| 3 | depends on OF_IRQ |
| 4 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 5 | config ARM_GIC |
| 6 | bool |
| 7 | select IRQ_DOMAIN |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 8 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 9 | select MULTI_IRQ_HANDLER |
| 10 | |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 11 | config ARM_GIC_V2M |
| 12 | bool |
| 13 | depends on ARM_GIC |
| 14 | depends on PCI && PCI_MSI |
| 15 | select PCI_MSI_IRQ_DOMAIN |
| 16 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 17 | config GIC_NON_BANKED |
| 18 | bool |
| 19 | |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 20 | config ARM_GIC_V3 |
| 21 | bool |
| 22 | select IRQ_DOMAIN |
| 23 | select MULTI_IRQ_HANDLER |
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 24 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 25 | |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 26 | config ARM_GIC_V3_ITS |
| 27 | bool |
| 28 | select PCI_MSI_IRQ_DOMAIN |
Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 29 | |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 30 | config ARM_NVIC |
| 31 | bool |
| 32 | select IRQ_DOMAIN |
Stefan Agner | 2d9f59f | 2015-05-16 11:44:16 +0200 | [diff] [blame] | 33 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 34 | select GENERIC_IRQ_CHIP |
| 35 | |
| 36 | config ARM_VIC |
| 37 | bool |
| 38 | select IRQ_DOMAIN |
| 39 | select MULTI_IRQ_HANDLER |
| 40 | |
| 41 | config ARM_VIC_NR |
| 42 | int |
| 43 | default 4 if ARCH_S5PV210 |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 44 | default 2 |
| 45 | depends on ARM_VIC |
| 46 | help |
| 47 | The maximum number of VICs available in the system, for |
| 48 | power management. |
| 49 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 50 | config ATMEL_AIC_IRQ |
| 51 | bool |
| 52 | select GENERIC_IRQ_CHIP |
| 53 | select IRQ_DOMAIN |
| 54 | select MULTI_IRQ_HANDLER |
| 55 | select SPARSE_IRQ |
| 56 | |
| 57 | config ATMEL_AIC5_IRQ |
| 58 | bool |
| 59 | select GENERIC_IRQ_CHIP |
| 60 | select IRQ_DOMAIN |
| 61 | select MULTI_IRQ_HANDLER |
| 62 | select SPARSE_IRQ |
| 63 | |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 64 | config BCM7038_L1_IRQ |
| 65 | bool |
| 66 | select GENERIC_IRQ_CHIP |
| 67 | select IRQ_DOMAIN |
| 68 | |
Kevin Cernekee | a4fcbb8 | 2014-11-06 22:44:27 -0800 | [diff] [blame] | 69 | config BCM7120_L2_IRQ |
| 70 | bool |
| 71 | select GENERIC_IRQ_CHIP |
| 72 | select IRQ_DOMAIN |
| 73 | |
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 74 | config BRCMSTB_L2_IRQ |
| 75 | bool |
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 76 | select GENERIC_IRQ_CHIP |
| 77 | select IRQ_DOMAIN |
| 78 | |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 79 | config DW_APB_ICTL |
| 80 | bool |
Jisheng Zhang | e158849 | 2014-10-22 20:59:10 +0800 | [diff] [blame] | 81 | select GENERIC_IRQ_CHIP |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 82 | select IRQ_DOMAIN |
| 83 | |
James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 84 | config IMGPDC_IRQ |
| 85 | bool |
| 86 | select GENERIC_IRQ_CHIP |
| 87 | select IRQ_DOMAIN |
| 88 | |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 89 | config IRQ_MIPS_CPU |
| 90 | bool |
| 91 | select GENERIC_IRQ_CHIP |
| 92 | select IRQ_DOMAIN |
| 93 | |
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 94 | config CLPS711X_IRQCHIP |
| 95 | bool |
| 96 | depends on ARCH_CLPS711X |
| 97 | select IRQ_DOMAIN |
| 98 | select MULTI_IRQ_HANDLER |
| 99 | select SPARSE_IRQ |
| 100 | default y |
| 101 | |
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 102 | config OR1K_PIC |
| 103 | bool |
| 104 | select IRQ_DOMAIN |
| 105 | |
Felipe Balbi | 8598066c | 2014-09-15 16:15:02 -0500 | [diff] [blame] | 106 | config OMAP_IRQCHIP |
| 107 | bool |
| 108 | select GENERIC_IRQ_CHIP |
| 109 | select IRQ_DOMAIN |
| 110 | |
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 111 | config ORION_IRQCHIP |
| 112 | bool |
| 113 | select IRQ_DOMAIN |
| 114 | select MULTI_IRQ_HANDLER |
| 115 | |
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 116 | config RENESAS_INTC_IRQPIN |
| 117 | bool |
| 118 | select IRQ_DOMAIN |
| 119 | |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 120 | config RENESAS_IRQC |
| 121 | bool |
| 122 | select IRQ_DOMAIN |
| 123 | |
Lee Jones | 0708848 | 2015-02-18 15:13:58 +0000 | [diff] [blame] | 124 | config ST_IRQCHIP |
| 125 | bool |
| 126 | select REGMAP |
| 127 | select MFD_SYSCON |
| 128 | help |
| 129 | Enables SysCfg Controlled IRQs on STi based platforms. |
| 130 | |
Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 131 | config TB10X_IRQC |
| 132 | bool |
| 133 | select IRQ_DOMAIN |
| 134 | select GENERIC_IRQ_CHIP |
| 135 | |
Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 136 | config VERSATILE_FPGA_IRQ |
| 137 | bool |
| 138 | select IRQ_DOMAIN |
| 139 | |
| 140 | config VERSATILE_FPGA_IRQ_NR |
| 141 | int |
| 142 | default 4 |
| 143 | depends on VERSATILE_FPGA_IRQ |
Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 144 | |
| 145 | config XTENSA_MX |
| 146 | bool |
| 147 | select IRQ_DOMAIN |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 148 | |
| 149 | config IRQ_CROSSBAR |
| 150 | bool |
| 151 | help |
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 152 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 153 | The primary irqchip invokes the crossbar's callback which inturn allocates |
| 154 | a free irq and configures the IP. Thus the peripheral interrupts are |
| 155 | routed to one of the free irqchip interrupt lines. |
Grygorii Strashko | 89323f8 | 2014-07-23 17:40:30 +0300 | [diff] [blame] | 156 | |
| 157 | config KEYSTONE_IRQ |
| 158 | tristate "Keystone 2 IRQ controller IP" |
| 159 | depends on ARCH_KEYSTONE |
| 160 | help |
| 161 | Support for Texas Instruments Keystone 2 IRQ controller IP which |
| 162 | is part of the Keystone 2 IPC mechanism |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 163 | |
| 164 | config MIPS_GIC |
| 165 | bool |
| 166 | select MIPS_CM |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 167 | |
Paul Burton | 44e08e7 | 2015-05-24 16:11:31 +0100 | [diff] [blame] | 168 | config INGENIC_IRQ |
| 169 | bool |
| 170 | depends on MACH_INGENIC |
| 171 | default y |
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 172 | |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 173 | config RENESAS_H8300H_INTC |
| 174 | bool |
| 175 | select IRQ_DOMAIN |
| 176 | |
| 177 | config RENESAS_H8S_INTC |
| 178 | bool |
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 179 | select IRQ_DOMAIN |