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Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000011config ARM_GIC_V2M
12 bool
13 depends on ARM_GIC
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
16
Rob Herring81243e42012-11-20 21:21:40 -060017config GIC_NON_BANKED
18 bool
19
Marc Zyngier021f6532014-06-30 16:01:31 +010020config ARM_GIC_V3
21 bool
22 select IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000024 select IRQ_DOMAIN_HIERARCHY
Marc Zyngier021f6532014-06-30 16:01:31 +010025
Marc Zyngier19812722014-11-24 14:35:19 +000026config ARM_GIC_V3_ITS
27 bool
28 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +020029
Rob Herring44430ec2012-10-27 17:25:26 -050030config ARM_NVIC
31 bool
32 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020033 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050034 select GENERIC_IRQ_CHIP
35
36config ARM_VIC
37 bool
38 select IRQ_DOMAIN
39 select MULTI_IRQ_HANDLER
40
41config ARM_VIC_NR
42 int
43 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050044 default 2
45 depends on ARM_VIC
46 help
47 The maximum number of VICs available in the system, for
48 power management.
49
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020050config ATMEL_AIC_IRQ
51 bool
52 select GENERIC_IRQ_CHIP
53 select IRQ_DOMAIN
54 select MULTI_IRQ_HANDLER
55 select SPARSE_IRQ
56
57config ATMEL_AIC5_IRQ
58 bool
59 select GENERIC_IRQ_CHIP
60 select IRQ_DOMAIN
61 select MULTI_IRQ_HANDLER
62 select SPARSE_IRQ
63
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080064config BCM7038_L1_IRQ
65 bool
66 select GENERIC_IRQ_CHIP
67 select IRQ_DOMAIN
68
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -080069config BCM7120_L2_IRQ
70 bool
71 select GENERIC_IRQ_CHIP
72 select IRQ_DOMAIN
73
Florian Fainelli7f646e92014-05-23 17:40:53 -070074config BRCMSTB_L2_IRQ
75 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -070076 select GENERIC_IRQ_CHIP
77 select IRQ_DOMAIN
78
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +020079config DW_APB_ICTL
80 bool
Jisheng Zhange1588492014-10-22 20:59:10 +080081 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +020082 select IRQ_DOMAIN
83
James Hoganb6ef9162013-04-22 15:43:50 +010084config IMGPDC_IRQ
85 bool
86 select GENERIC_IRQ_CHIP
87 select IRQ_DOMAIN
88
Ralf Baechle67e38cf2015-05-26 18:20:06 +020089config IRQ_MIPS_CPU
90 bool
91 select GENERIC_IRQ_CHIP
92 select IRQ_DOMAIN
93
Alexander Shiyanafc98d92014-02-02 12:07:46 +040094config CLPS711X_IRQCHIP
95 bool
96 depends on ARCH_CLPS711X
97 select IRQ_DOMAIN
98 select MULTI_IRQ_HANDLER
99 select SPARSE_IRQ
100 default y
101
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300102config OR1K_PIC
103 bool
104 select IRQ_DOMAIN
105
Felipe Balbi8598066c2014-09-15 16:15:02 -0500106config OMAP_IRQCHIP
107 bool
108 select GENERIC_IRQ_CHIP
109 select IRQ_DOMAIN
110
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200111config ORION_IRQCHIP
112 bool
113 select IRQ_DOMAIN
114 select MULTI_IRQ_HANDLER
115
Magnus Damm44358042013-02-18 23:28:34 +0900116config RENESAS_INTC_IRQPIN
117 bool
118 select IRQ_DOMAIN
119
Magnus Dammfbc83b72013-02-27 17:15:01 +0900120config RENESAS_IRQC
121 bool
122 select IRQ_DOMAIN
123
Lee Jones07088482015-02-18 15:13:58 +0000124config ST_IRQCHIP
125 bool
126 select REGMAP
127 select MFD_SYSCON
128 help
129 Enables SysCfg Controlled IRQs on STi based platforms.
130
Christian Ruppertb06eb012013-06-25 18:29:57 +0200131config TB10X_IRQC
132 bool
133 select IRQ_DOMAIN
134 select GENERIC_IRQ_CHIP
135
Linus Walleij2389d502012-10-31 22:04:31 +0100136config VERSATILE_FPGA_IRQ
137 bool
138 select IRQ_DOMAIN
139
140config VERSATILE_FPGA_IRQ_NR
141 int
142 default 4
143 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400144
145config XTENSA_MX
146 bool
147 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530148
149config IRQ_CROSSBAR
150 bool
151 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900152 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530153 The primary irqchip invokes the crossbar's callback which inturn allocates
154 a free irq and configures the IP. Thus the peripheral interrupts are
155 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300156
157config KEYSTONE_IRQ
158 tristate "Keystone 2 IRQ controller IP"
159 depends on ARCH_KEYSTONE
160 help
161 Support for Texas Instruments Keystone 2 IRQ controller IP which
162 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700163
164config MIPS_GIC
165 bool
166 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900167
Paul Burton44e08e72015-05-24 16:11:31 +0100168config INGENIC_IRQ
169 bool
170 depends on MACH_INGENIC
171 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700172
Yoshinori Sato8a764482015-05-10 02:30:47 +0900173config RENESAS_H8300H_INTC
174 bool
175 select IRQ_DOMAIN
176
177config RENESAS_H8S_INTC
178 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700179 select IRQ_DOMAIN