Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Tegra20 External Memory Controller driver |
| 4 | * |
| 5 | * Author: Dmitry Osipenko <digetx@gmail.com> |
| 6 | */ |
| 7 | |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 8 | #include <linux/bitfield.h> |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 9 | #include <linux/clk.h> |
Dmitry Osipenko | 77ab499 | 2019-08-12 00:00:31 +0300 | [diff] [blame] | 10 | #include <linux/clk/tegra.h> |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 11 | #include <linux/debugfs.h> |
Dmitry Osipenko | dedf62d | 2020-11-11 04:14:34 +0300 | [diff] [blame] | 12 | #include <linux/devfreq.h> |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 13 | #include <linux/err.h> |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 14 | #include <linux/interconnect-provider.h> |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 15 | #include <linux/interrupt.h> |
Dmitry Osipenko | d039cf2 | 2019-08-12 00:00:32 +0300 | [diff] [blame] | 16 | #include <linux/io.h> |
Dmitry Osipenko | adbcec8 | 2020-03-19 22:36:47 +0300 | [diff] [blame] | 17 | #include <linux/iopoll.h> |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 20 | #include <linux/mutex.h> |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 21 | #include <linux/of.h> |
| 22 | #include <linux/platform_device.h> |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 23 | #include <linux/pm_opp.h> |
| 24 | #include <linux/slab.h> |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 25 | #include <linux/sort.h> |
| 26 | #include <linux/types.h> |
| 27 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 28 | #include <soc/tegra/common.h> |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 29 | #include <soc/tegra/fuse.h> |
| 30 | |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 31 | #include "../jedec_ddr.h" |
| 32 | #include "../of_memory.h" |
| 33 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 34 | #include "mc.h" |
| 35 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 36 | #define EMC_INTSTATUS 0x000 |
| 37 | #define EMC_INTMASK 0x004 |
Dmitry Osipenko | c72396f | 2019-08-12 00:00:33 +0300 | [diff] [blame] | 38 | #define EMC_DBG 0x008 |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 39 | #define EMC_ADR_CFG_0 0x010 |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 40 | #define EMC_TIMING_CONTROL 0x028 |
| 41 | #define EMC_RC 0x02c |
| 42 | #define EMC_RFC 0x030 |
| 43 | #define EMC_RAS 0x034 |
| 44 | #define EMC_RP 0x038 |
| 45 | #define EMC_R2W 0x03c |
| 46 | #define EMC_W2R 0x040 |
| 47 | #define EMC_R2P 0x044 |
| 48 | #define EMC_W2P 0x048 |
| 49 | #define EMC_RD_RCD 0x04c |
| 50 | #define EMC_WR_RCD 0x050 |
| 51 | #define EMC_RRD 0x054 |
| 52 | #define EMC_REXT 0x058 |
| 53 | #define EMC_WDV 0x05c |
| 54 | #define EMC_QUSE 0x060 |
| 55 | #define EMC_QRST 0x064 |
| 56 | #define EMC_QSAFE 0x068 |
| 57 | #define EMC_RDV 0x06c |
| 58 | #define EMC_REFRESH 0x070 |
| 59 | #define EMC_BURST_REFRESH_NUM 0x074 |
| 60 | #define EMC_PDEX2WR 0x078 |
| 61 | #define EMC_PDEX2RD 0x07c |
| 62 | #define EMC_PCHG2PDEN 0x080 |
| 63 | #define EMC_ACT2PDEN 0x084 |
| 64 | #define EMC_AR2PDEN 0x088 |
| 65 | #define EMC_RW2PDEN 0x08c |
| 66 | #define EMC_TXSR 0x090 |
| 67 | #define EMC_TCKE 0x094 |
| 68 | #define EMC_TFAW 0x098 |
| 69 | #define EMC_TRPAB 0x09c |
| 70 | #define EMC_TCLKSTABLE 0x0a0 |
| 71 | #define EMC_TCLKSTOP 0x0a4 |
| 72 | #define EMC_TREFBW 0x0a8 |
| 73 | #define EMC_QUSE_EXTRA 0x0ac |
| 74 | #define EMC_ODT_WRITE 0x0b0 |
| 75 | #define EMC_ODT_READ 0x0b4 |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 76 | #define EMC_MRR 0x0ec |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 77 | #define EMC_FBIO_CFG5 0x104 |
| 78 | #define EMC_FBIO_CFG6 0x114 |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 79 | #define EMC_STAT_CONTROL 0x160 |
| 80 | #define EMC_STAT_LLMC_CONTROL 0x178 |
| 81 | #define EMC_STAT_PWR_CLOCK_LIMIT 0x198 |
| 82 | #define EMC_STAT_PWR_CLOCKS 0x19c |
| 83 | #define EMC_STAT_PWR_COUNT 0x1a0 |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 84 | #define EMC_AUTO_CAL_INTERVAL 0x2a8 |
| 85 | #define EMC_CFG_2 0x2b8 |
| 86 | #define EMC_CFG_DIG_DLL 0x2bc |
| 87 | #define EMC_DLL_XFORM_DQS 0x2c0 |
| 88 | #define EMC_DLL_XFORM_QUSE 0x2c4 |
| 89 | #define EMC_ZCAL_REF_CNT 0x2e0 |
| 90 | #define EMC_ZCAL_WAIT_CNT 0x2e4 |
| 91 | #define EMC_CFG_CLKTRIM_0 0x2d0 |
| 92 | #define EMC_CFG_CLKTRIM_1 0x2d4 |
| 93 | #define EMC_CFG_CLKTRIM_2 0x2d8 |
| 94 | |
| 95 | #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) |
| 96 | #define EMC_CLKCHANGE_PD_ENABLE BIT(1) |
| 97 | #define EMC_CLKCHANGE_SR_ENABLE BIT(2) |
| 98 | |
| 99 | #define EMC_TIMING_UPDATE BIT(0) |
| 100 | |
| 101 | #define EMC_REFRESH_OVERFLOW_INT BIT(3) |
| 102 | #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 103 | #define EMC_MRR_DIVLD_INT BIT(5) |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 104 | |
Dmitry Osipenko | c72396f | 2019-08-12 00:00:33 +0300 | [diff] [blame] | 105 | #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) |
| 106 | #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) |
| 107 | #define EMC_DBG_FORCE_UPDATE BIT(2) |
| 108 | #define EMC_DBG_READ_DQM_CTRL BIT(9) |
| 109 | #define EMC_DBG_CFG_PRIORITY BIT(24) |
| 110 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 111 | #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 112 | #define EMC_FBIO_CFG5_DRAM_TYPE GENMASK(1, 0) |
| 113 | |
| 114 | #define EMC_MRR_DEV_SELECTN GENMASK(31, 30) |
| 115 | #define EMC_MRR_MRR_MA GENMASK(23, 16) |
| 116 | #define EMC_MRR_MRR_DATA GENMASK(15, 0) |
| 117 | |
| 118 | #define EMC_ADR_CFG_0_EMEM_NUMDEV GENMASK(25, 24) |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 119 | |
Dmitry Osipenko | dedf62d | 2020-11-11 04:14:34 +0300 | [diff] [blame] | 120 | #define EMC_PWR_GATHER_CLEAR (1 << 8) |
| 121 | #define EMC_PWR_GATHER_DISABLE (2 << 8) |
| 122 | #define EMC_PWR_GATHER_ENABLE (3 << 8) |
| 123 | |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 124 | enum emc_dram_type { |
| 125 | DRAM_TYPE_RESERVED, |
| 126 | DRAM_TYPE_DDR1, |
| 127 | DRAM_TYPE_LPDDR2, |
| 128 | DRAM_TYPE_DDR2, |
| 129 | }; |
| 130 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 131 | static const u16 emc_timing_registers[] = { |
| 132 | EMC_RC, |
| 133 | EMC_RFC, |
| 134 | EMC_RAS, |
| 135 | EMC_RP, |
| 136 | EMC_R2W, |
| 137 | EMC_W2R, |
| 138 | EMC_R2P, |
| 139 | EMC_W2P, |
| 140 | EMC_RD_RCD, |
| 141 | EMC_WR_RCD, |
| 142 | EMC_RRD, |
| 143 | EMC_REXT, |
| 144 | EMC_WDV, |
| 145 | EMC_QUSE, |
| 146 | EMC_QRST, |
| 147 | EMC_QSAFE, |
| 148 | EMC_RDV, |
| 149 | EMC_REFRESH, |
| 150 | EMC_BURST_REFRESH_NUM, |
| 151 | EMC_PDEX2WR, |
| 152 | EMC_PDEX2RD, |
| 153 | EMC_PCHG2PDEN, |
| 154 | EMC_ACT2PDEN, |
| 155 | EMC_AR2PDEN, |
| 156 | EMC_RW2PDEN, |
| 157 | EMC_TXSR, |
| 158 | EMC_TCKE, |
| 159 | EMC_TFAW, |
| 160 | EMC_TRPAB, |
| 161 | EMC_TCLKSTABLE, |
| 162 | EMC_TCLKSTOP, |
| 163 | EMC_TREFBW, |
| 164 | EMC_QUSE_EXTRA, |
| 165 | EMC_FBIO_CFG6, |
| 166 | EMC_ODT_WRITE, |
| 167 | EMC_ODT_READ, |
| 168 | EMC_FBIO_CFG5, |
| 169 | EMC_CFG_DIG_DLL, |
| 170 | EMC_DLL_XFORM_DQS, |
| 171 | EMC_DLL_XFORM_QUSE, |
| 172 | EMC_ZCAL_REF_CNT, |
| 173 | EMC_ZCAL_WAIT_CNT, |
| 174 | EMC_AUTO_CAL_INTERVAL, |
| 175 | EMC_CFG_CLKTRIM_0, |
| 176 | EMC_CFG_CLKTRIM_1, |
| 177 | EMC_CFG_CLKTRIM_2, |
| 178 | }; |
| 179 | |
| 180 | struct emc_timing { |
| 181 | unsigned long rate; |
| 182 | u32 data[ARRAY_SIZE(emc_timing_registers)]; |
| 183 | }; |
| 184 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 185 | enum emc_rate_request_type { |
Dmitry Osipenko | dedf62d | 2020-11-11 04:14:34 +0300 | [diff] [blame] | 186 | EMC_RATE_DEVFREQ, |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 187 | EMC_RATE_DEBUG, |
| 188 | EMC_RATE_ICC, |
| 189 | EMC_RATE_TYPE_MAX, |
| 190 | }; |
| 191 | |
| 192 | struct emc_rate_request { |
| 193 | unsigned long min_rate; |
| 194 | unsigned long max_rate; |
| 195 | }; |
| 196 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 197 | struct tegra_emc { |
| 198 | struct device *dev; |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 199 | struct tegra_mc *mc; |
| 200 | struct icc_provider provider; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 201 | struct notifier_block clk_nb; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 202 | struct clk *clk; |
| 203 | void __iomem *regs; |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 204 | unsigned int dram_bus_width; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 205 | |
| 206 | struct emc_timing *timings; |
| 207 | unsigned int num_timings; |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 208 | |
| 209 | struct { |
| 210 | struct dentry *root; |
| 211 | unsigned long min_rate; |
| 212 | unsigned long max_rate; |
| 213 | } debugfs; |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 214 | |
| 215 | /* |
| 216 | * There are multiple sources in the EMC driver which could request |
| 217 | * a min/max clock rate, these rates are contained in this array. |
| 218 | */ |
| 219 | struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; |
| 220 | |
| 221 | /* protect shared rate-change code path */ |
| 222 | struct mutex rate_lock; |
Dmitry Osipenko | dedf62d | 2020-11-11 04:14:34 +0300 | [diff] [blame] | 223 | |
| 224 | struct devfreq_simple_ondemand_data ondemand_data; |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 225 | |
| 226 | /* memory chip identity information */ |
| 227 | union lpddr2_basic_config4 basic_conf4; |
| 228 | unsigned int manufacturer_id; |
| 229 | unsigned int revision_id1; |
| 230 | unsigned int revision_id2; |
| 231 | |
| 232 | bool mrr_error; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 233 | }; |
| 234 | |
| 235 | static irqreturn_t tegra_emc_isr(int irq, void *data) |
| 236 | { |
| 237 | struct tegra_emc *emc = data; |
Dmitry Osipenko | adbcec8 | 2020-03-19 22:36:47 +0300 | [diff] [blame] | 238 | u32 intmask = EMC_REFRESH_OVERFLOW_INT; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 239 | u32 status; |
| 240 | |
| 241 | status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; |
| 242 | if (!status) |
| 243 | return IRQ_NONE; |
| 244 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 245 | /* notify about HW problem */ |
| 246 | if (status & EMC_REFRESH_OVERFLOW_INT) |
| 247 | dev_err_ratelimited(emc->dev, |
| 248 | "refresh request overflow timeout\n"); |
| 249 | |
| 250 | /* clear interrupts */ |
| 251 | writel_relaxed(status, emc->regs + EMC_INTSTATUS); |
| 252 | |
| 253 | return IRQ_HANDLED; |
| 254 | } |
| 255 | |
| 256 | static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, |
| 257 | unsigned long rate) |
| 258 | { |
| 259 | struct emc_timing *timing = NULL; |
| 260 | unsigned int i; |
| 261 | |
| 262 | for (i = 0; i < emc->num_timings; i++) { |
| 263 | if (emc->timings[i].rate >= rate) { |
| 264 | timing = &emc->timings[i]; |
| 265 | break; |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | if (!timing) { |
| 270 | dev_err(emc->dev, "no timing for rate %lu\n", rate); |
| 271 | return NULL; |
| 272 | } |
| 273 | |
| 274 | return timing; |
| 275 | } |
| 276 | |
| 277 | static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) |
| 278 | { |
| 279 | struct emc_timing *timing = tegra_emc_find_timing(emc, rate); |
| 280 | unsigned int i; |
| 281 | |
| 282 | if (!timing) |
| 283 | return -EINVAL; |
| 284 | |
| 285 | dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", |
| 286 | __func__, timing->rate, rate); |
| 287 | |
| 288 | /* program shadow registers */ |
| 289 | for (i = 0; i < ARRAY_SIZE(timing->data); i++) |
| 290 | writel_relaxed(timing->data[i], |
| 291 | emc->regs + emc_timing_registers[i]); |
| 292 | |
| 293 | /* wait until programming has settled */ |
| 294 | readl_relaxed(emc->regs + emc_timing_registers[i - 1]); |
| 295 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) |
| 300 | { |
Dmitry Osipenko | adbcec8 | 2020-03-19 22:36:47 +0300 | [diff] [blame] | 301 | int err; |
| 302 | u32 v; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 303 | |
| 304 | dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); |
| 305 | |
| 306 | if (flush) { |
| 307 | /* manually initiate memory timing update */ |
| 308 | writel_relaxed(EMC_TIMING_UPDATE, |
| 309 | emc->regs + EMC_TIMING_CONTROL); |
| 310 | return 0; |
| 311 | } |
| 312 | |
Dmitry Osipenko | adbcec8 | 2020-03-19 22:36:47 +0300 | [diff] [blame] | 313 | err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, |
| 314 | v & EMC_CLKCHANGE_COMPLETE_INT, |
| 315 | 1, 100); |
| 316 | if (err) { |
| 317 | dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); |
| 318 | return err; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | static int tegra_emc_clk_change_notify(struct notifier_block *nb, |
| 325 | unsigned long msg, void *data) |
| 326 | { |
| 327 | struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); |
| 328 | struct clk_notifier_data *cnd = data; |
| 329 | int err; |
| 330 | |
| 331 | switch (msg) { |
| 332 | case PRE_RATE_CHANGE: |
| 333 | err = emc_prepare_timing_change(emc, cnd->new_rate); |
| 334 | break; |
| 335 | |
| 336 | case ABORT_RATE_CHANGE: |
| 337 | err = emc_prepare_timing_change(emc, cnd->old_rate); |
| 338 | if (err) |
| 339 | break; |
| 340 | |
| 341 | err = emc_complete_timing_change(emc, true); |
| 342 | break; |
| 343 | |
| 344 | case POST_RATE_CHANGE: |
| 345 | err = emc_complete_timing_change(emc, false); |
| 346 | break; |
| 347 | |
| 348 | default: |
| 349 | return NOTIFY_DONE; |
| 350 | } |
| 351 | |
| 352 | return notifier_from_errno(err); |
| 353 | } |
| 354 | |
| 355 | static int load_one_timing_from_dt(struct tegra_emc *emc, |
| 356 | struct emc_timing *timing, |
| 357 | struct device_node *node) |
| 358 | { |
| 359 | u32 rate; |
| 360 | int err; |
| 361 | |
| 362 | if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { |
| 363 | dev_err(emc->dev, "incompatible DT node: %pOF\n", node); |
| 364 | return -EINVAL; |
| 365 | } |
| 366 | |
| 367 | err = of_property_read_u32(node, "clock-frequency", &rate); |
| 368 | if (err) { |
| 369 | dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", |
| 370 | node, err); |
| 371 | return err; |
| 372 | } |
| 373 | |
| 374 | err = of_property_read_u32_array(node, "nvidia,emc-registers", |
| 375 | timing->data, |
| 376 | ARRAY_SIZE(emc_timing_registers)); |
| 377 | if (err) { |
| 378 | dev_err(emc->dev, |
| 379 | "timing %pOF: failed to read emc timing data: %d\n", |
| 380 | node, err); |
| 381 | return err; |
| 382 | } |
| 383 | |
| 384 | /* |
| 385 | * The EMC clock rate is twice the bus rate, and the bus rate is |
| 386 | * measured in kHz. |
| 387 | */ |
| 388 | timing->rate = rate * 2 * 1000; |
| 389 | |
| 390 | dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", |
| 391 | __func__, node, timing->rate); |
| 392 | |
| 393 | return 0; |
| 394 | } |
| 395 | |
| 396 | static int cmp_timings(const void *_a, const void *_b) |
| 397 | { |
| 398 | const struct emc_timing *a = _a; |
| 399 | const struct emc_timing *b = _b; |
| 400 | |
| 401 | if (a->rate < b->rate) |
| 402 | return -1; |
| 403 | |
| 404 | if (a->rate > b->rate) |
| 405 | return 1; |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, |
| 411 | struct device_node *node) |
| 412 | { |
| 413 | struct device_node *child; |
| 414 | struct emc_timing *timing; |
| 415 | int child_count; |
| 416 | int err; |
| 417 | |
| 418 | child_count = of_get_child_count(node); |
| 419 | if (!child_count) { |
| 420 | dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); |
| 421 | return -EINVAL; |
| 422 | } |
| 423 | |
| 424 | emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), |
| 425 | GFP_KERNEL); |
| 426 | if (!emc->timings) |
| 427 | return -ENOMEM; |
| 428 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 429 | timing = emc->timings; |
| 430 | |
| 431 | for_each_child_of_node(node, child) { |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 432 | if (of_node_name_eq(child, "lpddr2")) |
| 433 | continue; |
| 434 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 435 | err = load_one_timing_from_dt(emc, timing++, child); |
| 436 | if (err) { |
| 437 | of_node_put(child); |
| 438 | return err; |
| 439 | } |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 440 | |
| 441 | emc->num_timings++; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 442 | } |
| 443 | |
| 444 | sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, |
| 445 | NULL); |
| 446 | |
Dmitry Osipenko | f012ade8 | 2021-03-31 02:04:45 +0300 | [diff] [blame] | 447 | dev_info_once(emc->dev, |
| 448 | "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", |
| 449 | emc->num_timings, |
| 450 | tegra_read_ram_code(), |
| 451 | emc->timings[0].rate / 1000000, |
| 452 | emc->timings[emc->num_timings - 1].rate / 1000000); |
Dmitry Osipenko | f541efa | 2019-08-12 00:00:34 +0300 | [diff] [blame] | 453 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 454 | return 0; |
| 455 | } |
| 456 | |
| 457 | static struct device_node * |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 458 | tegra_emc_find_node_by_ram_code(struct tegra_emc *emc) |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 459 | { |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 460 | struct device *dev = emc->dev; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 461 | struct device_node *np; |
| 462 | u32 value, ram_code; |
| 463 | int err; |
| 464 | |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 465 | if (emc->mrr_error) { |
| 466 | dev_warn(dev, "memory timings skipped due to MRR error\n"); |
| 467 | return NULL; |
| 468 | } |
| 469 | |
Dmitry Osipenko | fa4794f | 2020-11-04 19:49:10 +0300 | [diff] [blame] | 470 | if (of_get_child_count(dev->of_node) == 0) { |
Dmitry Osipenko | f012ade8 | 2021-03-31 02:04:45 +0300 | [diff] [blame] | 471 | dev_info_once(dev, "device-tree doesn't have memory timings\n"); |
Dmitry Osipenko | fa4794f | 2020-11-04 19:49:10 +0300 | [diff] [blame] | 472 | return NULL; |
| 473 | } |
| 474 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 475 | if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) |
| 476 | return of_node_get(dev->of_node); |
| 477 | |
| 478 | ram_code = tegra_read_ram_code(); |
| 479 | |
| 480 | for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; |
| 481 | np = of_find_node_by_name(np, "emc-tables")) { |
| 482 | err = of_property_read_u32(np, "nvidia,ram-code", &value); |
| 483 | if (err || value != ram_code) { |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 484 | struct device_node *lpddr2_np; |
| 485 | bool cfg_mismatches = false; |
| 486 | |
| 487 | lpddr2_np = of_find_node_by_name(np, "lpddr2"); |
| 488 | if (lpddr2_np) { |
| 489 | const struct lpddr2_info *info; |
| 490 | |
| 491 | info = of_lpddr2_get_info(lpddr2_np, dev); |
| 492 | if (info) { |
| 493 | if (info->manufacturer_id >= 0 && |
| 494 | info->manufacturer_id != emc->manufacturer_id) |
| 495 | cfg_mismatches = true; |
| 496 | |
| 497 | if (info->revision_id1 >= 0 && |
| 498 | info->revision_id1 != emc->revision_id1) |
| 499 | cfg_mismatches = true; |
| 500 | |
| 501 | if (info->revision_id2 >= 0 && |
| 502 | info->revision_id2 != emc->revision_id2) |
| 503 | cfg_mismatches = true; |
| 504 | |
| 505 | if (info->density != emc->basic_conf4.density) |
| 506 | cfg_mismatches = true; |
| 507 | |
| 508 | if (info->io_width != emc->basic_conf4.io_width) |
| 509 | cfg_mismatches = true; |
| 510 | |
| 511 | if (info->arch_type != emc->basic_conf4.arch_type) |
| 512 | cfg_mismatches = true; |
| 513 | } else { |
| 514 | dev_err(dev, "failed to parse %pOF\n", lpddr2_np); |
| 515 | cfg_mismatches = true; |
| 516 | } |
| 517 | |
| 518 | of_node_put(lpddr2_np); |
| 519 | } else { |
| 520 | cfg_mismatches = true; |
| 521 | } |
| 522 | |
| 523 | if (cfg_mismatches) { |
| 524 | of_node_put(np); |
| 525 | continue; |
| 526 | } |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | return np; |
| 530 | } |
| 531 | |
| 532 | dev_err(dev, "no memory timings for RAM code %u found in device tree\n", |
| 533 | ram_code); |
| 534 | |
| 535 | return NULL; |
| 536 | } |
| 537 | |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 538 | static int emc_read_lpddr_mode_register(struct tegra_emc *emc, |
| 539 | unsigned int emem_dev, |
| 540 | unsigned int register_addr, |
| 541 | unsigned int *register_data) |
| 542 | { |
Dmitry Osipenko | 9ff6843 | 2021-12-22 07:32:15 +0300 | [diff] [blame] | 543 | u32 memory_dev = emem_dev ? 1 : 2; |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 544 | u32 val, mr_mask = 0xff; |
| 545 | int err; |
| 546 | |
| 547 | /* clear data-valid interrupt status */ |
| 548 | writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS); |
| 549 | |
| 550 | /* issue mode register read request */ |
| 551 | val = FIELD_PREP(EMC_MRR_DEV_SELECTN, memory_dev); |
| 552 | val |= FIELD_PREP(EMC_MRR_MRR_MA, register_addr); |
| 553 | |
| 554 | writel_relaxed(val, emc->regs + EMC_MRR); |
| 555 | |
| 556 | /* wait for the LPDDR2 data-valid interrupt */ |
| 557 | err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val, |
| 558 | val & EMC_MRR_DIVLD_INT, |
| 559 | 1, 100); |
| 560 | if (err) { |
| 561 | dev_err(emc->dev, "mode register %u read failed: %d\n", |
| 562 | register_addr, err); |
| 563 | emc->mrr_error = true; |
| 564 | return err; |
| 565 | } |
| 566 | |
| 567 | /* read out mode register data */ |
| 568 | val = readl_relaxed(emc->regs + EMC_MRR); |
| 569 | *register_data = FIELD_GET(EMC_MRR_MRR_DATA, val) & mr_mask; |
| 570 | |
| 571 | return 0; |
| 572 | } |
| 573 | |
| 574 | static void emc_read_lpddr_sdram_info(struct tegra_emc *emc, |
| 575 | unsigned int emem_dev, |
| 576 | bool print_out) |
| 577 | { |
| 578 | /* these registers are standard for all LPDDR JEDEC memory chips */ |
| 579 | emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id); |
| 580 | emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1); |
| 581 | emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2); |
| 582 | emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value); |
| 583 | |
| 584 | if (!print_out) |
| 585 | return; |
| 586 | |
| 587 | dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n", |
| 588 | emem_dev, emc->manufacturer_id, |
| 589 | lpddr2_jedec_manufacturer(emc->manufacturer_id), |
| 590 | emc->revision_id1, emc->revision_id2, |
| 591 | 4 >> emc->basic_conf4.arch_type, |
| 592 | 64 << emc->basic_conf4.density, |
| 593 | 32 >> emc->basic_conf4.io_width); |
| 594 | } |
| 595 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 596 | static int emc_setup_hw(struct tegra_emc *emc) |
| 597 | { |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 598 | u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; |
Dmitry Osipenko | adbcec8 | 2020-03-19 22:36:47 +0300 | [diff] [blame] | 599 | u32 intmask = EMC_REFRESH_OVERFLOW_INT; |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 600 | static bool print_sdram_info_once; |
| 601 | enum emc_dram_type dram_type; |
| 602 | const char *dram_type_str; |
| 603 | unsigned int emem_numdev; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 604 | |
| 605 | emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); |
| 606 | |
| 607 | /* |
| 608 | * Depending on a memory type, DRAM should enter either self-refresh |
| 609 | * or power-down state on EMC clock change. |
| 610 | */ |
| 611 | if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && |
| 612 | !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { |
| 613 | dev_err(emc->dev, |
| 614 | "bootloader didn't specify DRAM auto-suspend mode\n"); |
| 615 | return -EINVAL; |
| 616 | } |
| 617 | |
| 618 | /* enable EMC and CAR to handshake on PLL divider/source changes */ |
| 619 | emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; |
| 620 | writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); |
| 621 | |
| 622 | /* initialize interrupt */ |
| 623 | writel_relaxed(intmask, emc->regs + EMC_INTMASK); |
| 624 | writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); |
| 625 | |
Dmitry Osipenko | c72396f | 2019-08-12 00:00:33 +0300 | [diff] [blame] | 626 | /* ensure that unwanted debug features are disabled */ |
| 627 | emc_dbg = readl_relaxed(emc->regs + EMC_DBG); |
| 628 | emc_dbg |= EMC_DBG_CFG_PRIORITY; |
| 629 | emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; |
| 630 | emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; |
| 631 | emc_dbg &= ~EMC_DBG_FORCE_UPDATE; |
| 632 | writel_relaxed(emc_dbg, emc->regs + EMC_DBG); |
| 633 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 634 | emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); |
| 635 | |
| 636 | if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16) |
| 637 | emc->dram_bus_width = 16; |
| 638 | else |
| 639 | emc->dram_bus_width = 32; |
| 640 | |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 641 | dram_type = FIELD_GET(EMC_FBIO_CFG5_DRAM_TYPE, emc_fbio); |
| 642 | |
| 643 | switch (dram_type) { |
| 644 | case DRAM_TYPE_RESERVED: |
| 645 | dram_type_str = "INVALID"; |
| 646 | break; |
| 647 | case DRAM_TYPE_DDR1: |
| 648 | dram_type_str = "DDR1"; |
| 649 | break; |
| 650 | case DRAM_TYPE_LPDDR2: |
| 651 | dram_type_str = "LPDDR2"; |
| 652 | break; |
| 653 | case DRAM_TYPE_DDR2: |
| 654 | dram_type_str = "DDR2"; |
| 655 | break; |
| 656 | } |
| 657 | |
| 658 | emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG_0); |
| 659 | emem_numdev = FIELD_GET(EMC_ADR_CFG_0_EMEM_NUMDEV, emc_adr_cfg) + 1; |
| 660 | |
| 661 | dev_info_once(emc->dev, "%ubit DRAM bus, %u %s %s attached\n", |
| 662 | emc->dram_bus_width, emem_numdev, dram_type_str, |
| 663 | emem_numdev == 2 ? "devices" : "device"); |
| 664 | |
| 665 | if (dram_type == DRAM_TYPE_LPDDR2) { |
| 666 | while (emem_numdev--) |
| 667 | emc_read_lpddr_sdram_info(emc, emem_numdev, |
| 668 | !print_sdram_info_once); |
| 669 | print_sdram_info_once = true; |
| 670 | } |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 671 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 672 | return 0; |
| 673 | } |
| 674 | |
Dmitry Osipenko | 77ab499 | 2019-08-12 00:00:31 +0300 | [diff] [blame] | 675 | static long emc_round_rate(unsigned long rate, |
| 676 | unsigned long min_rate, |
| 677 | unsigned long max_rate, |
| 678 | void *arg) |
| 679 | { |
| 680 | struct emc_timing *timing = NULL; |
| 681 | struct tegra_emc *emc = arg; |
| 682 | unsigned int i; |
| 683 | |
Dmitry Osipenko | fa4794f | 2020-11-04 19:49:10 +0300 | [diff] [blame] | 684 | if (!emc->num_timings) |
| 685 | return clk_get_rate(emc->clk); |
| 686 | |
Dmitry Osipenko | 77ab499 | 2019-08-12 00:00:31 +0300 | [diff] [blame] | 687 | min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); |
| 688 | |
| 689 | for (i = 0; i < emc->num_timings; i++) { |
| 690 | if (emc->timings[i].rate < rate && i != emc->num_timings - 1) |
| 691 | continue; |
| 692 | |
| 693 | if (emc->timings[i].rate > max_rate) { |
| 694 | i = max(i, 1u) - 1; |
| 695 | |
| 696 | if (emc->timings[i].rate < min_rate) |
| 697 | break; |
| 698 | } |
| 699 | |
| 700 | if (emc->timings[i].rate < min_rate) |
| 701 | continue; |
| 702 | |
| 703 | timing = &emc->timings[i]; |
| 704 | break; |
| 705 | } |
| 706 | |
| 707 | if (!timing) { |
| 708 | dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", |
| 709 | rate, min_rate, max_rate); |
| 710 | return -EINVAL; |
| 711 | } |
| 712 | |
| 713 | return timing->rate; |
| 714 | } |
| 715 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 716 | static void tegra_emc_rate_requests_init(struct tegra_emc *emc) |
| 717 | { |
| 718 | unsigned int i; |
| 719 | |
| 720 | for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { |
| 721 | emc->requested_rate[i].min_rate = 0; |
| 722 | emc->requested_rate[i].max_rate = ULONG_MAX; |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | static int emc_request_rate(struct tegra_emc *emc, |
| 727 | unsigned long new_min_rate, |
| 728 | unsigned long new_max_rate, |
| 729 | enum emc_rate_request_type type) |
| 730 | { |
| 731 | struct emc_rate_request *req = emc->requested_rate; |
| 732 | unsigned long min_rate = 0, max_rate = ULONG_MAX; |
| 733 | unsigned int i; |
| 734 | int err; |
| 735 | |
| 736 | /* select minimum and maximum rates among the requested rates */ |
| 737 | for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { |
| 738 | if (i == type) { |
| 739 | min_rate = max(new_min_rate, min_rate); |
| 740 | max_rate = min(new_max_rate, max_rate); |
| 741 | } else { |
| 742 | min_rate = max(req->min_rate, min_rate); |
| 743 | max_rate = min(req->max_rate, max_rate); |
| 744 | } |
| 745 | } |
| 746 | |
| 747 | if (min_rate > max_rate) { |
| 748 | dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", |
| 749 | __func__, type, min_rate, max_rate); |
| 750 | return -ERANGE; |
| 751 | } |
| 752 | |
| 753 | /* |
| 754 | * EMC rate-changes should go via OPP API because it manages voltage |
| 755 | * changes. |
| 756 | */ |
| 757 | err = dev_pm_opp_set_rate(emc->dev, min_rate); |
| 758 | if (err) |
| 759 | return err; |
| 760 | |
| 761 | emc->requested_rate[type].min_rate = new_min_rate; |
| 762 | emc->requested_rate[type].max_rate = new_max_rate; |
| 763 | |
| 764 | return 0; |
| 765 | } |
| 766 | |
| 767 | static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, |
| 768 | enum emc_rate_request_type type) |
| 769 | { |
| 770 | struct emc_rate_request *req = &emc->requested_rate[type]; |
| 771 | int ret; |
| 772 | |
| 773 | mutex_lock(&emc->rate_lock); |
| 774 | ret = emc_request_rate(emc, rate, req->max_rate, type); |
| 775 | mutex_unlock(&emc->rate_lock); |
| 776 | |
| 777 | return ret; |
| 778 | } |
| 779 | |
| 780 | static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, |
| 781 | enum emc_rate_request_type type) |
| 782 | { |
| 783 | struct emc_rate_request *req = &emc->requested_rate[type]; |
| 784 | int ret; |
| 785 | |
| 786 | mutex_lock(&emc->rate_lock); |
| 787 | ret = emc_request_rate(emc, req->min_rate, rate, type); |
| 788 | mutex_unlock(&emc->rate_lock); |
| 789 | |
| 790 | return ret; |
| 791 | } |
| 792 | |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 793 | /* |
| 794 | * debugfs interface |
| 795 | * |
| 796 | * The memory controller driver exposes some files in debugfs that can be used |
| 797 | * to control the EMC frequency. The top-level directory can be found here: |
| 798 | * |
| 799 | * /sys/kernel/debug/emc |
| 800 | * |
| 801 | * It contains the following files: |
| 802 | * |
| 803 | * - available_rates: This file contains a list of valid, space-separated |
| 804 | * EMC frequencies. |
| 805 | * |
| 806 | * - min_rate: Writing a value to this file sets the given frequency as the |
| 807 | * floor of the permitted range. If this is higher than the currently |
| 808 | * configured EMC frequency, this will cause the frequency to be |
| 809 | * increased so that it stays within the valid range. |
| 810 | * |
| 811 | * - max_rate: Similarily to the min_rate file, writing a value to this file |
| 812 | * sets the given frequency as the ceiling of the permitted range. If |
| 813 | * the value is lower than the currently configured EMC frequency, this |
| 814 | * will cause the frequency to be decreased so that it stays within the |
| 815 | * valid range. |
| 816 | */ |
| 817 | |
| 818 | static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) |
| 819 | { |
| 820 | unsigned int i; |
| 821 | |
| 822 | for (i = 0; i < emc->num_timings; i++) |
| 823 | if (rate == emc->timings[i].rate) |
| 824 | return true; |
| 825 | |
| 826 | return false; |
| 827 | } |
| 828 | |
| 829 | static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) |
| 830 | { |
| 831 | struct tegra_emc *emc = s->private; |
| 832 | const char *prefix = ""; |
| 833 | unsigned int i; |
| 834 | |
| 835 | for (i = 0; i < emc->num_timings; i++) { |
| 836 | seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); |
| 837 | prefix = " "; |
| 838 | } |
| 839 | |
| 840 | seq_puts(s, "\n"); |
| 841 | |
| 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | static int tegra_emc_debug_available_rates_open(struct inode *inode, |
| 846 | struct file *file) |
| 847 | { |
| 848 | return single_open(file, tegra_emc_debug_available_rates_show, |
| 849 | inode->i_private); |
| 850 | } |
| 851 | |
| 852 | static const struct file_operations tegra_emc_debug_available_rates_fops = { |
| 853 | .open = tegra_emc_debug_available_rates_open, |
| 854 | .read = seq_read, |
| 855 | .llseek = seq_lseek, |
| 856 | .release = single_release, |
| 857 | }; |
| 858 | |
| 859 | static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) |
| 860 | { |
| 861 | struct tegra_emc *emc = data; |
| 862 | |
| 863 | *rate = emc->debugfs.min_rate; |
| 864 | |
| 865 | return 0; |
| 866 | } |
| 867 | |
| 868 | static int tegra_emc_debug_min_rate_set(void *data, u64 rate) |
| 869 | { |
| 870 | struct tegra_emc *emc = data; |
| 871 | int err; |
| 872 | |
| 873 | if (!tegra_emc_validate_rate(emc, rate)) |
| 874 | return -EINVAL; |
| 875 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 876 | err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 877 | if (err < 0) |
| 878 | return err; |
| 879 | |
| 880 | emc->debugfs.min_rate = rate; |
| 881 | |
| 882 | return 0; |
| 883 | } |
| 884 | |
| 885 | DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops, |
| 886 | tegra_emc_debug_min_rate_get, |
| 887 | tegra_emc_debug_min_rate_set, "%llu\n"); |
| 888 | |
| 889 | static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) |
| 890 | { |
| 891 | struct tegra_emc *emc = data; |
| 892 | |
| 893 | *rate = emc->debugfs.max_rate; |
| 894 | |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | static int tegra_emc_debug_max_rate_set(void *data, u64 rate) |
| 899 | { |
| 900 | struct tegra_emc *emc = data; |
| 901 | int err; |
| 902 | |
| 903 | if (!tegra_emc_validate_rate(emc, rate)) |
| 904 | return -EINVAL; |
| 905 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 906 | err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 907 | if (err < 0) |
| 908 | return err; |
| 909 | |
| 910 | emc->debugfs.max_rate = rate; |
| 911 | |
| 912 | return 0; |
| 913 | } |
| 914 | |
| 915 | DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops, |
| 916 | tegra_emc_debug_max_rate_get, |
| 917 | tegra_emc_debug_max_rate_set, "%llu\n"); |
| 918 | |
| 919 | static void tegra_emc_debugfs_init(struct tegra_emc *emc) |
| 920 | { |
| 921 | struct device *dev = emc->dev; |
| 922 | unsigned int i; |
| 923 | int err; |
| 924 | |
| 925 | emc->debugfs.min_rate = ULONG_MAX; |
| 926 | emc->debugfs.max_rate = 0; |
| 927 | |
| 928 | for (i = 0; i < emc->num_timings; i++) { |
| 929 | if (emc->timings[i].rate < emc->debugfs.min_rate) |
| 930 | emc->debugfs.min_rate = emc->timings[i].rate; |
| 931 | |
| 932 | if (emc->timings[i].rate > emc->debugfs.max_rate) |
| 933 | emc->debugfs.max_rate = emc->timings[i].rate; |
| 934 | } |
| 935 | |
Dmitry Osipenko | 2243af4 | 2020-02-25 02:58:34 +0300 | [diff] [blame] | 936 | if (!emc->num_timings) { |
| 937 | emc->debugfs.min_rate = clk_get_rate(emc->clk); |
| 938 | emc->debugfs.max_rate = emc->debugfs.min_rate; |
| 939 | } |
| 940 | |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 941 | err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, |
| 942 | emc->debugfs.max_rate); |
| 943 | if (err < 0) { |
| 944 | dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", |
| 945 | emc->debugfs.min_rate, emc->debugfs.max_rate, |
| 946 | emc->clk); |
| 947 | } |
| 948 | |
| 949 | emc->debugfs.root = debugfs_create_dir("emc", NULL); |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 950 | |
Dmitry Osipenko | 6cc8823 | 2020-03-13 11:57:39 +0300 | [diff] [blame] | 951 | debugfs_create_file("available_rates", 0444, emc->debugfs.root, |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 952 | emc, &tegra_emc_debug_available_rates_fops); |
Dmitry Osipenko | 6cc8823 | 2020-03-13 11:57:39 +0300 | [diff] [blame] | 953 | debugfs_create_file("min_rate", 0644, emc->debugfs.root, |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 954 | emc, &tegra_emc_debug_min_rate_fops); |
Dmitry Osipenko | 6cc8823 | 2020-03-13 11:57:39 +0300 | [diff] [blame] | 955 | debugfs_create_file("max_rate", 0644, emc->debugfs.root, |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 956 | emc, &tegra_emc_debug_max_rate_fops); |
| 957 | } |
| 958 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 959 | static inline struct tegra_emc * |
| 960 | to_tegra_emc_provider(struct icc_provider *provider) |
| 961 | { |
| 962 | return container_of(provider, struct tegra_emc, provider); |
| 963 | } |
| 964 | |
| 965 | static struct icc_node_data * |
| 966 | emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) |
| 967 | { |
| 968 | struct icc_provider *provider = data; |
| 969 | struct icc_node_data *ndata; |
| 970 | struct icc_node *node; |
| 971 | |
| 972 | /* External Memory is the only possible ICC route */ |
| 973 | list_for_each_entry(node, &provider->nodes, node_list) { |
| 974 | if (node->id != TEGRA_ICC_EMEM) |
| 975 | continue; |
| 976 | |
| 977 | ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); |
| 978 | if (!ndata) |
| 979 | return ERR_PTR(-ENOMEM); |
| 980 | |
| 981 | /* |
| 982 | * SRC and DST nodes should have matching TAG in order to have |
| 983 | * it set by default for a requested path. |
| 984 | */ |
| 985 | ndata->tag = TEGRA_MC_ICC_TAG_ISO; |
| 986 | ndata->node = node; |
| 987 | |
| 988 | return ndata; |
| 989 | } |
| 990 | |
| 991 | return ERR_PTR(-EPROBE_DEFER); |
| 992 | } |
| 993 | |
| 994 | static int emc_icc_set(struct icc_node *src, struct icc_node *dst) |
| 995 | { |
| 996 | struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); |
| 997 | unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); |
| 998 | unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); |
| 999 | unsigned long long rate = max(avg_bw, peak_bw); |
| 1000 | unsigned int dram_data_bus_width_bytes; |
| 1001 | int err; |
| 1002 | |
| 1003 | /* |
| 1004 | * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data |
| 1005 | * is sampled on both clock edges. This means that EMC clock rate |
| 1006 | * equals to the peak data-rate. |
| 1007 | */ |
| 1008 | dram_data_bus_width_bytes = emc->dram_bus_width / 8; |
| 1009 | do_div(rate, dram_data_bus_width_bytes); |
| 1010 | rate = min_t(u64, rate, U32_MAX); |
| 1011 | |
| 1012 | err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); |
| 1013 | if (err) |
| 1014 | return err; |
| 1015 | |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
| 1019 | static int tegra_emc_interconnect_init(struct tegra_emc *emc) |
| 1020 | { |
| 1021 | const struct tegra_mc_soc *soc; |
| 1022 | struct icc_node *node; |
| 1023 | int err; |
| 1024 | |
| 1025 | emc->mc = devm_tegra_memory_controller_get(emc->dev); |
| 1026 | if (IS_ERR(emc->mc)) |
| 1027 | return PTR_ERR(emc->mc); |
| 1028 | |
| 1029 | soc = emc->mc->soc; |
| 1030 | |
| 1031 | emc->provider.dev = emc->dev; |
| 1032 | emc->provider.set = emc_icc_set; |
| 1033 | emc->provider.data = &emc->provider; |
| 1034 | emc->provider.aggregate = soc->icc_ops->aggregate; |
| 1035 | emc->provider.xlate_extended = emc_of_icc_xlate_extended; |
| 1036 | |
| 1037 | err = icc_provider_add(&emc->provider); |
| 1038 | if (err) |
| 1039 | goto err_msg; |
| 1040 | |
| 1041 | /* create External Memory Controller node */ |
| 1042 | node = icc_node_create(TEGRA_ICC_EMC); |
| 1043 | if (IS_ERR(node)) { |
| 1044 | err = PTR_ERR(node); |
| 1045 | goto del_provider; |
| 1046 | } |
| 1047 | |
| 1048 | node->name = "External Memory Controller"; |
| 1049 | icc_node_add(node, &emc->provider); |
| 1050 | |
| 1051 | /* link External Memory Controller to External Memory (DRAM) */ |
| 1052 | err = icc_link_create(node, TEGRA_ICC_EMEM); |
| 1053 | if (err) |
| 1054 | goto remove_nodes; |
| 1055 | |
| 1056 | /* create External Memory node */ |
| 1057 | node = icc_node_create(TEGRA_ICC_EMEM); |
| 1058 | if (IS_ERR(node)) { |
| 1059 | err = PTR_ERR(node); |
| 1060 | goto remove_nodes; |
| 1061 | } |
| 1062 | |
| 1063 | node->name = "External Memory (DRAM)"; |
| 1064 | icc_node_add(node, &emc->provider); |
| 1065 | |
| 1066 | return 0; |
| 1067 | |
| 1068 | remove_nodes: |
| 1069 | icc_nodes_remove(&emc->provider); |
| 1070 | del_provider: |
| 1071 | icc_provider_del(&emc->provider); |
| 1072 | err_msg: |
| 1073 | dev_err(emc->dev, "failed to initialize ICC: %d\n", err); |
| 1074 | |
| 1075 | return err; |
| 1076 | } |
| 1077 | |
Dmitry Osipenko | cba3902 | 2020-11-11 04:14:33 +0300 | [diff] [blame] | 1078 | static void devm_tegra_emc_unset_callback(void *data) |
| 1079 | { |
| 1080 | tegra20_clk_set_emc_round_callback(NULL, NULL); |
| 1081 | } |
| 1082 | |
| 1083 | static void devm_tegra_emc_unreg_clk_notifier(void *data) |
| 1084 | { |
| 1085 | struct tegra_emc *emc = data; |
| 1086 | |
| 1087 | clk_notifier_unregister(emc->clk, &emc->clk_nb); |
| 1088 | } |
| 1089 | |
| 1090 | static int tegra_emc_init_clk(struct tegra_emc *emc) |
| 1091 | { |
| 1092 | int err; |
| 1093 | |
| 1094 | tegra20_clk_set_emc_round_callback(emc_round_rate, emc); |
| 1095 | |
| 1096 | err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, |
| 1097 | NULL); |
| 1098 | if (err) |
| 1099 | return err; |
| 1100 | |
| 1101 | emc->clk = devm_clk_get(emc->dev, NULL); |
| 1102 | if (IS_ERR(emc->clk)) { |
| 1103 | dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); |
| 1104 | return PTR_ERR(emc->clk); |
| 1105 | } |
| 1106 | |
| 1107 | err = clk_notifier_register(emc->clk, &emc->clk_nb); |
| 1108 | if (err) { |
| 1109 | dev_err(emc->dev, "failed to register clk notifier: %d\n", err); |
| 1110 | return err; |
| 1111 | } |
| 1112 | |
| 1113 | err = devm_add_action_or_reset(emc->dev, |
| 1114 | devm_tegra_emc_unreg_clk_notifier, emc); |
| 1115 | if (err) |
| 1116 | return err; |
| 1117 | |
| 1118 | return 0; |
| 1119 | } |
| 1120 | |
Dmitry Osipenko | dedf62d | 2020-11-11 04:14:34 +0300 | [diff] [blame] | 1121 | static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq, |
| 1122 | u32 flags) |
| 1123 | { |
| 1124 | struct tegra_emc *emc = dev_get_drvdata(dev); |
| 1125 | struct dev_pm_opp *opp; |
| 1126 | unsigned long rate; |
| 1127 | |
| 1128 | opp = devfreq_recommended_opp(dev, freq, flags); |
| 1129 | if (IS_ERR(opp)) { |
| 1130 | dev_err(dev, "failed to find opp for %lu Hz\n", *freq); |
| 1131 | return PTR_ERR(opp); |
| 1132 | } |
| 1133 | |
| 1134 | rate = dev_pm_opp_get_freq(opp); |
| 1135 | dev_pm_opp_put(opp); |
| 1136 | |
| 1137 | return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ); |
| 1138 | } |
| 1139 | |
| 1140 | static int tegra_emc_devfreq_get_dev_status(struct device *dev, |
| 1141 | struct devfreq_dev_status *stat) |
| 1142 | { |
| 1143 | struct tegra_emc *emc = dev_get_drvdata(dev); |
| 1144 | |
| 1145 | /* freeze counters */ |
| 1146 | writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); |
| 1147 | |
| 1148 | /* |
| 1149 | * busy_time: number of clocks EMC request was accepted |
| 1150 | * total_time: number of clocks PWR_GATHER control was set to ENABLE |
| 1151 | */ |
| 1152 | stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); |
| 1153 | stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); |
| 1154 | stat->current_frequency = clk_get_rate(emc->clk); |
| 1155 | |
| 1156 | /* clear counters and restart */ |
| 1157 | writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); |
| 1158 | writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); |
| 1159 | |
| 1160 | return 0; |
| 1161 | } |
| 1162 | |
| 1163 | static struct devfreq_dev_profile tegra_emc_devfreq_profile = { |
| 1164 | .polling_ms = 30, |
| 1165 | .target = tegra_emc_devfreq_target, |
| 1166 | .get_dev_status = tegra_emc_devfreq_get_dev_status, |
| 1167 | }; |
| 1168 | |
| 1169 | static int tegra_emc_devfreq_init(struct tegra_emc *emc) |
| 1170 | { |
| 1171 | struct devfreq *devfreq; |
| 1172 | |
| 1173 | /* |
| 1174 | * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold |
| 1175 | * should be less than 50. Secondly, multiple active memory clients |
| 1176 | * may cause over 20% of lost clock cycles due to stalls caused by |
| 1177 | * competing memory accesses. This means that threshold should be |
| 1178 | * set to a less than 30 in order to have a properly working governor. |
| 1179 | */ |
| 1180 | emc->ondemand_data.upthreshold = 20; |
| 1181 | |
| 1182 | /* |
| 1183 | * Reset statistic gathers state, select global bandwidth for the |
| 1184 | * statistics collection mode and set clocks counter saturation |
| 1185 | * limit to maximum. |
| 1186 | */ |
| 1187 | writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); |
| 1188 | writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); |
| 1189 | writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); |
| 1190 | |
| 1191 | devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, |
| 1192 | DEVFREQ_GOV_SIMPLE_ONDEMAND, |
| 1193 | &emc->ondemand_data); |
| 1194 | if (IS_ERR(devfreq)) { |
| 1195 | dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq); |
| 1196 | return PTR_ERR(devfreq); |
| 1197 | } |
| 1198 | |
| 1199 | return 0; |
| 1200 | } |
| 1201 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1202 | static int tegra_emc_probe(struct platform_device *pdev) |
| 1203 | { |
Dmitry Osipenko | f8c9670 | 2021-06-01 05:31:14 +0300 | [diff] [blame] | 1204 | struct tegra_core_opp_params opp_params = {}; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1205 | struct device_node *np; |
| 1206 | struct tegra_emc *emc; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1207 | int irq, err; |
| 1208 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1209 | irq = platform_get_irq(pdev, 0); |
| 1210 | if (irq < 0) { |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1211 | dev_err(&pdev->dev, "please update your device tree\n"); |
| 1212 | return irq; |
| 1213 | } |
| 1214 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1215 | emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); |
Dmitry Osipenko | fa4794f | 2020-11-04 19:49:10 +0300 | [diff] [blame] | 1216 | if (!emc) |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1217 | return -ENOMEM; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1218 | |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 1219 | mutex_init(&emc->rate_lock); |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1220 | emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; |
| 1221 | emc->dev = &pdev->dev; |
| 1222 | |
Dmitry Osipenko | 4e84d0a | 2020-11-04 19:49:05 +0300 | [diff] [blame] | 1223 | emc->regs = devm_platform_ioremap_resource(pdev, 0); |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1224 | if (IS_ERR(emc->regs)) |
| 1225 | return PTR_ERR(emc->regs); |
| 1226 | |
| 1227 | err = emc_setup_hw(emc); |
| 1228 | if (err) |
| 1229 | return err; |
| 1230 | |
Dmitry Osipenko | 131dd9a | 2021-10-07 01:46:59 +0300 | [diff] [blame] | 1231 | np = tegra_emc_find_node_by_ram_code(emc); |
| 1232 | if (np) { |
| 1233 | err = tegra_emc_load_timings_from_dt(emc, np); |
| 1234 | of_node_put(np); |
| 1235 | if (err) |
| 1236 | return err; |
| 1237 | } |
| 1238 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1239 | err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, |
| 1240 | dev_name(&pdev->dev), emc); |
| 1241 | if (err) { |
Dmitry Osipenko | e09312f | 2020-11-11 04:14:35 +0300 | [diff] [blame] | 1242 | dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1243 | return err; |
| 1244 | } |
| 1245 | |
Dmitry Osipenko | cba3902 | 2020-11-11 04:14:33 +0300 | [diff] [blame] | 1246 | err = tegra_emc_init_clk(emc); |
| 1247 | if (err) |
| 1248 | return err; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1249 | |
Dmitry Osipenko | f8c9670 | 2021-06-01 05:31:14 +0300 | [diff] [blame] | 1250 | opp_params.init_state = true; |
| 1251 | |
| 1252 | err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 1253 | if (err) |
Dmitry Osipenko | cba3902 | 2020-11-11 04:14:33 +0300 | [diff] [blame] | 1254 | return err; |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 1255 | |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 1256 | platform_set_drvdata(pdev, emc); |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 1257 | tegra_emc_rate_requests_init(emc); |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 1258 | tegra_emc_debugfs_init(emc); |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 1259 | tegra_emc_interconnect_init(emc); |
Dmitry Osipenko | dedf62d | 2020-11-11 04:14:34 +0300 | [diff] [blame] | 1260 | tegra_emc_devfreq_init(emc); |
Thierry Reding | 8209eef | 2019-12-22 12:40:32 +0100 | [diff] [blame] | 1261 | |
Dmitry Osipenko | 0260979 | 2020-11-04 19:49:09 +0300 | [diff] [blame] | 1262 | /* |
| 1263 | * Don't allow the kernel module to be unloaded. Unloading adds some |
| 1264 | * extra complexity which doesn't really worth the effort in a case of |
| 1265 | * this driver. |
| 1266 | */ |
| 1267 | try_module_get(THIS_MODULE); |
| 1268 | |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1269 | return 0; |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1270 | } |
| 1271 | |
| 1272 | static const struct of_device_id tegra_emc_of_match[] = { |
| 1273 | { .compatible = "nvidia,tegra20-emc", }, |
| 1274 | {}, |
| 1275 | }; |
Dmitry Osipenko | 0260979 | 2020-11-04 19:49:09 +0300 | [diff] [blame] | 1276 | MODULE_DEVICE_TABLE(of, tegra_emc_of_match); |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1277 | |
| 1278 | static struct platform_driver tegra_emc_driver = { |
| 1279 | .probe = tegra_emc_probe, |
| 1280 | .driver = { |
| 1281 | .name = "tegra20-emc", |
| 1282 | .of_match_table = tegra_emc_of_match, |
| 1283 | .suppress_bind_attrs = true, |
Dmitry Osipenko | d5ef16b | 2020-11-04 19:49:11 +0300 | [diff] [blame] | 1284 | .sync_state = icc_sync_state, |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1285 | }, |
| 1286 | }; |
Dmitry Osipenko | 0260979 | 2020-11-04 19:49:09 +0300 | [diff] [blame] | 1287 | module_platform_driver(tegra_emc_driver); |
Dmitry Osipenko | 96e5da7 | 2018-10-21 21:30:52 +0300 | [diff] [blame] | 1288 | |
Dmitry Osipenko | 0260979 | 2020-11-04 19:49:09 +0300 | [diff] [blame] | 1289 | MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); |
| 1290 | MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver"); |
Dmitry Osipenko | 14b43c2 | 2021-10-20 02:15:24 +0300 | [diff] [blame] | 1291 | MODULE_SOFTDEP("pre: governor_simpleondemand"); |
Dmitry Osipenko | 0260979 | 2020-11-04 19:49:09 +0300 | [diff] [blame] | 1292 | MODULE_LICENSE("GPL v2"); |