Greg Kroah-Hartman | 5fd54ac | 2017-11-03 11:28:30 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 2 | /* |
| 3 | * ci.h - common structures, functions, and macros of the ChipIdea driver |
| 4 | * |
| 5 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. |
| 6 | * |
| 7 | * Author: David Lopo |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __DRIVERS_USB_CHIPIDEA_CI_H |
| 11 | #define __DRIVERS_USB_CHIPIDEA_CI_H |
| 12 | |
| 13 | #include <linux/list.h> |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 14 | #include <linux/irqreturn.h> |
Alexander Shishkin | eb70e5a | 2012-05-11 17:25:54 +0300 | [diff] [blame] | 15 | #include <linux/usb.h> |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 16 | #include <linux/usb/gadget.h> |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 17 | #include <linux/usb/otg-fsm.h> |
Stephen Boyd | 7bb7e9b | 2016-12-28 14:56:55 -0800 | [diff] [blame] | 18 | #include <linux/usb/otg.h> |
| 19 | #include <linux/ulpi/interface.h> |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 20 | |
| 21 | /****************************************************************************** |
| 22 | * DEFINE |
| 23 | *****************************************************************************/ |
Michael Grzeschik | b983e51 | 2013-03-30 12:54:10 +0200 | [diff] [blame] | 24 | #define TD_PAGE_COUNT 5 |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 25 | #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 26 | #define ENDPT_MAX 32 |
| 27 | |
| 28 | /****************************************************************************** |
Marc Kleine-Budde | 21395a1 | 2014-01-06 10:10:38 +0800 | [diff] [blame] | 29 | * REGISTERS |
| 30 | *****************************************************************************/ |
Peter Chen | 655d32e | 2015-02-11 12:44:54 +0800 | [diff] [blame] | 31 | /* Identification Registers */ |
| 32 | #define ID_ID 0x0 |
| 33 | #define ID_HWGENERAL 0x4 |
| 34 | #define ID_HWHOST 0x8 |
| 35 | #define ID_HWDEVICE 0xc |
| 36 | #define ID_HWTXBUF 0x10 |
| 37 | #define ID_HWRXBUF 0x14 |
| 38 | #define ID_SBUSCFG 0x90 |
| 39 | |
Marc Kleine-Budde | 21395a1 | 2014-01-06 10:10:38 +0800 | [diff] [blame] | 40 | /* register indices */ |
| 41 | enum ci_hw_regs { |
| 42 | CAP_CAPLENGTH, |
| 43 | CAP_HCCPARAMS, |
| 44 | CAP_DCCPARAMS, |
| 45 | CAP_TESTMODE, |
| 46 | CAP_LAST = CAP_TESTMODE, |
| 47 | OP_USBCMD, |
| 48 | OP_USBSTS, |
| 49 | OP_USBINTR, |
| 50 | OP_DEVICEADDR, |
| 51 | OP_ENDPTLISTADDR, |
Peter Chen | 2836267 | 2015-06-18 11:51:53 +0800 | [diff] [blame] | 52 | OP_TTCTRL, |
Peter Chen | 96625ea | 2015-03-17 17:32:45 +0800 | [diff] [blame] | 53 | OP_BURSTSIZE, |
Stephen Boyd | 7bb7e9b | 2016-12-28 14:56:55 -0800 | [diff] [blame] | 54 | OP_ULPI_VIEWPORT, |
Marc Kleine-Budde | 21395a1 | 2014-01-06 10:10:38 +0800 | [diff] [blame] | 55 | OP_PORTSC, |
| 56 | OP_DEVLC, |
| 57 | OP_OTGSC, |
| 58 | OP_USBMODE, |
| 59 | OP_ENDPTSETUPSTAT, |
| 60 | OP_ENDPTPRIME, |
| 61 | OP_ENDPTFLUSH, |
| 62 | OP_ENDPTSTAT, |
| 63 | OP_ENDPTCOMPLETE, |
| 64 | OP_ENDPTCTRL, |
| 65 | /* endptctrl1..15 follow */ |
| 66 | OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, |
| 67 | }; |
| 68 | |
| 69 | /****************************************************************************** |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 70 | * STRUCTURES |
| 71 | *****************************************************************************/ |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 72 | /** |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 73 | * struct ci_hw_ep - endpoint representation |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 74 | * @ep: endpoint structure for gadget drivers |
| 75 | * @dir: endpoint direction (TX/RX) |
| 76 | * @num: endpoint number |
| 77 | * @type: endpoint type |
| 78 | * @name: string description of the endpoint |
| 79 | * @qh: queue head for this endpoint |
| 80 | * @wedge: is the endpoint wedged |
Richard Zhao | 26c696c | 2012-07-07 22:56:40 +0800 | [diff] [blame] | 81 | * @ci: pointer to the controller |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 82 | * @lock: pointer to controller's spinlock |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 83 | * @td_pool: pointer to controller's TD pool |
| 84 | */ |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 85 | struct ci_hw_ep { |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 86 | struct usb_ep ep; |
| 87 | u8 dir; |
| 88 | u8 num; |
| 89 | u8 type; |
| 90 | char name[16]; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 91 | struct { |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 92 | struct list_head queue; |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 93 | struct ci_hw_qh *ptr; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 94 | dma_addr_t dma; |
| 95 | } qh; |
| 96 | int wedge; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 97 | |
| 98 | /* global resources */ |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 99 | struct ci_hdrc *ci; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 100 | spinlock_t *lock; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 101 | struct dma_pool *td_pool; |
Michael Grzeschik | 2e27041 | 2013-06-13 17:59:54 +0300 | [diff] [blame] | 102 | struct td_node *pending_td; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 103 | }; |
| 104 | |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 105 | enum ci_role { |
| 106 | CI_ROLE_HOST = 0, |
| 107 | CI_ROLE_GADGET, |
| 108 | CI_ROLE_END, |
| 109 | }; |
| 110 | |
Peter Chen | cb271f3 | 2015-02-11 12:44:55 +0800 | [diff] [blame] | 111 | enum ci_revision { |
| 112 | CI_REVISION_1X = 10, /* Revision 1.x */ |
| 113 | CI_REVISION_20 = 20, /* Revision 2.0 */ |
| 114 | CI_REVISION_21, /* Revision 2.1 */ |
| 115 | CI_REVISION_22, /* Revision 2.2 */ |
| 116 | CI_REVISION_23, /* Revision 2.3 */ |
| 117 | CI_REVISION_24, /* Revision 2.4 */ |
| 118 | CI_REVISION_25, /* Revision 2.5 */ |
| 119 | CI_REVISION_25_PLUS, /* Revision above than 2.5 */ |
| 120 | CI_REVISION_UNKNOWN = 99, /* Unknown Revision */ |
| 121 | }; |
| 122 | |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 123 | /** |
| 124 | * struct ci_role_driver - host/gadget role driver |
Peter Chen | 1935388 | 2014-09-22 08:14:17 +0800 | [diff] [blame] | 125 | * @start: start this role |
| 126 | * @stop: stop this role |
| 127 | * @irq: irq handler for this role |
| 128 | * @name: role name string (host/gadget) |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 129 | */ |
| 130 | struct ci_role_driver { |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 131 | int (*start)(struct ci_hdrc *); |
| 132 | void (*stop)(struct ci_hdrc *); |
| 133 | irqreturn_t (*irq)(struct ci_hdrc *); |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 134 | const char *name; |
| 135 | }; |
| 136 | |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 137 | /** |
| 138 | * struct hw_bank - hardware register mapping representation |
| 139 | * @lpm: set if the device is LPM capable |
Alexander Shishkin | eb70e5a | 2012-05-11 17:25:54 +0300 | [diff] [blame] | 140 | * @phys: physical address of the controller's registers |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 141 | * @abs: absolute address of the beginning of register window |
| 142 | * @cap: capability registers |
| 143 | * @op: operational registers |
| 144 | * @size: size of the register window |
| 145 | * @regmap: register lookup table |
| 146 | */ |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 147 | struct hw_bank { |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 148 | unsigned lpm; |
Alexander Shishkin | eb70e5a | 2012-05-11 17:25:54 +0300 | [diff] [blame] | 149 | resource_size_t phys; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 150 | void __iomem *abs; |
| 151 | void __iomem *cap; |
| 152 | void __iomem *op; |
| 153 | size_t size; |
Marc Kleine-Budde | 21395a1 | 2014-01-06 10:10:38 +0800 | [diff] [blame] | 154 | void __iomem *regmap[OP_LAST + 1]; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 155 | }; |
| 156 | |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 157 | /** |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 158 | * struct ci_hdrc - chipidea device representation |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 159 | * @dev: pointer to parent device |
| 160 | * @lock: access synchronization |
| 161 | * @hw_bank: hardware register mapping |
| 162 | * @irq: IRQ number |
| 163 | * @roles: array of supported roles for this controller |
| 164 | * @role: current role |
| 165 | * @is_otg: if the device is otg-capable |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 166 | * @fsm: otg finite state machine |
Li Jun | 3a316ec | 2015-03-20 16:28:06 +0800 | [diff] [blame] | 167 | * @otg_fsm_hrtimer: hrtimer for otg fsm timers |
| 168 | * @hr_timeouts: time out list for active otg fsm timers |
| 169 | * @enabled_otg_timer_bits: bits of enabled otg timers |
| 170 | * @next_otg_timer: next nearest enabled timer to be expired |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 171 | * @work: work for role changing |
| 172 | * @wq: workqueue thread |
| 173 | * @qh_pool: allocation pool for queue heads |
| 174 | * @td_pool: allocation pool for transfer descriptors |
| 175 | * @gadget: device side representation for peripheral controller |
| 176 | * @driver: gadget driver |
Li Jun | 4f4555c | 2017-03-07 10:35:01 +0800 | [diff] [blame] | 177 | * @resume_state: save the state of gadget suspend from |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 178 | * @hw_ep_max: total number of endpoints supported by hardware |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 179 | * @ci_hw_ep: array of endpoints |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 180 | * @ep0_dir: ep0 direction |
| 181 | * @ep0out: pointer to ep0 OUT endpoint |
| 182 | * @ep0in: pointer to ep0 IN endpoint |
| 183 | * @status: ep0 status request |
| 184 | * @setaddr: if we should set the address on status completion |
| 185 | * @address: usb address received from the host |
| 186 | * @remote_wakeup: host-enabled remote wakeup |
| 187 | * @suspended: suspended by host |
| 188 | * @test_mode: the selected test mode |
Richard Zhao | 77c4400 | 2012-06-29 17:48:53 +0800 | [diff] [blame] | 189 | * @platdata: platform specific information supplied by parent device |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 190 | * @vbus_active: is VBUS active |
Stephen Boyd | 7bb7e9b | 2016-12-28 14:56:55 -0800 | [diff] [blame] | 191 | * @ulpi: pointer to ULPI device, if any |
| 192 | * @ulpi_ops: ULPI read/write ops for this device |
Antoine Tenart | 1e5e2d3 | 2014-10-30 18:41:19 +0100 | [diff] [blame] | 193 | * @phy: pointer to PHY, if any |
| 194 | * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework |
Alexander Shishkin | eb70e5a | 2012-05-11 17:25:54 +0300 | [diff] [blame] | 195 | * @hcd: pointer to usb_hcd for ehci host driver |
Alexander Shishkin | 2d65128 | 2013-03-30 12:53:51 +0200 | [diff] [blame] | 196 | * @debugfs: root dentry for this controller in debugfs |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 197 | * @id_event: indicates there is an id event, and handled at ci_otg_work |
| 198 | * @b_sess_valid_event: indicates there is a vbus event, and handled |
| 199 | * at ci_otg_work |
Peter Chen | ed8f831 | 2014-01-10 13:51:27 +0800 | [diff] [blame] | 200 | * @imx28_write_fix: Freescale imx28 needs swp instruction for writing |
Peter Chen | 1f874ed | 2015-02-11 12:44:45 +0800 | [diff] [blame] | 201 | * @supports_runtime_pm: if runtime pm is supported |
| 202 | * @in_lpm: if the core in low power mode |
| 203 | * @wakeup_int: if wakeup interrupt occur |
Peter Chen | cb271f3 | 2015-02-11 12:44:55 +0800 | [diff] [blame] | 204 | * @rev: The revision number for controller |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 205 | */ |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 206 | struct ci_hdrc { |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 207 | struct device *dev; |
| 208 | spinlock_t lock; |
| 209 | struct hw_bank hw_bank; |
| 210 | int irq; |
| 211 | struct ci_role_driver *roles[CI_ROLE_END]; |
| 212 | enum ci_role role; |
| 213 | bool is_otg; |
Antoine Tenart | ef44cb4 | 2014-10-30 18:41:16 +0100 | [diff] [blame] | 214 | struct usb_otg otg; |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 215 | struct otg_fsm fsm; |
Li Jun | 3a316ec | 2015-03-20 16:28:06 +0800 | [diff] [blame] | 216 | struct hrtimer otg_fsm_hrtimer; |
| 217 | ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS]; |
| 218 | unsigned enabled_otg_timer_bits; |
| 219 | enum otg_fsm_timer next_otg_timer; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 220 | struct work_struct work; |
| 221 | struct workqueue_struct *wq; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 222 | |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 223 | struct dma_pool *qh_pool; |
| 224 | struct dma_pool *td_pool; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 225 | |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 226 | struct usb_gadget gadget; |
| 227 | struct usb_gadget_driver *driver; |
Li Jun | 4f4555c | 2017-03-07 10:35:01 +0800 | [diff] [blame] | 228 | enum usb_device_state resume_state; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 229 | unsigned hw_ep_max; |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 230 | struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 231 | u32 ep0_dir; |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 232 | struct ci_hw_ep *ep0out, *ep0in; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 233 | |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 234 | struct usb_request *status; |
| 235 | bool setaddr; |
| 236 | u8 address; |
| 237 | u8 remote_wakeup; |
| 238 | u8 suspended; |
| 239 | u8 test_mode; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 240 | |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 241 | struct ci_hdrc_platform_data *platdata; |
Alexander Shishkin | 551a8ac | 2012-05-11 17:25:49 +0300 | [diff] [blame] | 242 | int vbus_active; |
Stephen Boyd | 7bb7e9b | 2016-12-28 14:56:55 -0800 | [diff] [blame] | 243 | #ifdef CONFIG_USB_CHIPIDEA_ULPI |
| 244 | struct ulpi *ulpi; |
| 245 | struct ulpi_ops ulpi_ops; |
| 246 | #endif |
Antoine Tenart | 1e5e2d3 | 2014-10-30 18:41:19 +0100 | [diff] [blame] | 247 | struct phy *phy; |
| 248 | /* old usb_phy interface */ |
Antoine Tenart | ef44cb4 | 2014-10-30 18:41:16 +0100 | [diff] [blame] | 249 | struct usb_phy *usb_phy; |
Alexander Shishkin | eb70e5a | 2012-05-11 17:25:54 +0300 | [diff] [blame] | 250 | struct usb_hcd *hcd; |
Alexander Shishkin | 2d65128 | 2013-03-30 12:53:51 +0200 | [diff] [blame] | 251 | struct dentry *debugfs; |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 252 | bool id_event; |
| 253 | bool b_sess_valid_event; |
Peter Chen | ed8f831 | 2014-01-10 13:51:27 +0800 | [diff] [blame] | 254 | bool imx28_write_fix; |
Peter Chen | 1f874ed | 2015-02-11 12:44:45 +0800 | [diff] [blame] | 255 | bool supports_runtime_pm; |
| 256 | bool in_lpm; |
| 257 | bool wakeup_int; |
Peter Chen | cb271f3 | 2015-02-11 12:44:55 +0800 | [diff] [blame] | 258 | enum ci_revision rev; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 259 | }; |
| 260 | |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 261 | static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 262 | { |
| 263 | BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); |
| 264 | return ci->roles[ci->role]; |
| 265 | } |
| 266 | |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 267 | static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 268 | { |
| 269 | int ret; |
| 270 | |
| 271 | if (role >= CI_ROLE_END) |
| 272 | return -EINVAL; |
| 273 | |
| 274 | if (!ci->roles[role]) |
| 275 | return -ENXIO; |
| 276 | |
| 277 | ret = ci->roles[role]->start(ci); |
| 278 | if (!ret) |
| 279 | ci->role = role; |
| 280 | return ret; |
| 281 | } |
| 282 | |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 283 | static inline void ci_role_stop(struct ci_hdrc *ci) |
Alexander Shishkin | 5f36e23 | 2012-05-11 17:25:47 +0300 | [diff] [blame] | 284 | { |
| 285 | enum ci_role role = ci->role; |
| 286 | |
| 287 | if (role == CI_ROLE_END) |
| 288 | return; |
| 289 | |
| 290 | ci->role = CI_ROLE_END; |
| 291 | |
| 292 | ci->roles[role]->stop(ci); |
| 293 | } |
| 294 | |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 295 | /** |
Peter Chen | 655d32e | 2015-02-11 12:44:54 +0800 | [diff] [blame] | 296 | * hw_read_id_reg: reads from a identification register |
| 297 | * @ci: the controller |
| 298 | * @offset: offset from the beginning of identification registers region |
| 299 | * @mask: bitfield mask |
| 300 | * |
| 301 | * This function returns register contents |
| 302 | */ |
| 303 | static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) |
| 304 | { |
| 305 | return ioread32(ci->hw_bank.abs + offset) & mask; |
| 306 | } |
| 307 | |
| 308 | /** |
| 309 | * hw_write_id_reg: writes to a identification register |
| 310 | * @ci: the controller |
| 311 | * @offset: offset from the beginning of identification registers region |
| 312 | * @mask: bitfield mask |
| 313 | * @data: new value |
| 314 | */ |
| 315 | static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset, |
| 316 | u32 mask, u32 data) |
| 317 | { |
| 318 | if (~mask) |
| 319 | data = (ioread32(ci->hw_bank.abs + offset) & ~mask) |
| 320 | | (data & mask); |
| 321 | |
| 322 | iowrite32(data, ci->hw_bank.abs + offset); |
| 323 | } |
| 324 | |
| 325 | /** |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 326 | * hw_read: reads from a hw register |
Peter Chen | 1935388 | 2014-09-22 08:14:17 +0800 | [diff] [blame] | 327 | * @ci: the controller |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 328 | * @reg: register index |
| 329 | * @mask: bitfield mask |
| 330 | * |
| 331 | * This function returns register contents |
| 332 | */ |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 333 | static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 334 | { |
Richard Zhao | 26c696c | 2012-07-07 22:56:40 +0800 | [diff] [blame] | 335 | return ioread32(ci->hw_bank.regmap[reg]) & mask; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 336 | } |
| 337 | |
Peter Chen | ed8f831 | 2014-01-10 13:51:27 +0800 | [diff] [blame] | 338 | #ifdef CONFIG_SOC_IMX28 |
| 339 | static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
| 340 | { |
| 341 | __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); |
| 342 | } |
| 343 | #else |
| 344 | static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
| 345 | { |
| 346 | } |
| 347 | #endif |
| 348 | |
| 349 | static inline void __hw_write(struct ci_hdrc *ci, u32 val, |
| 350 | void __iomem *addr) |
| 351 | { |
| 352 | if (ci->imx28_write_fix) |
| 353 | imx28_ci_writel(val, addr); |
| 354 | else |
| 355 | iowrite32(val, addr); |
| 356 | } |
| 357 | |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 358 | /** |
| 359 | * hw_write: writes to a hw register |
Peter Chen | 1935388 | 2014-09-22 08:14:17 +0800 | [diff] [blame] | 360 | * @ci: the controller |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 361 | * @reg: register index |
| 362 | * @mask: bitfield mask |
| 363 | * @data: new value |
| 364 | */ |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 365 | static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 366 | u32 mask, u32 data) |
| 367 | { |
| 368 | if (~mask) |
Richard Zhao | 26c696c | 2012-07-07 22:56:40 +0800 | [diff] [blame] | 369 | data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 370 | | (data & mask); |
| 371 | |
Peter Chen | ed8f831 | 2014-01-10 13:51:27 +0800 | [diff] [blame] | 372 | __hw_write(ci, data, ci->hw_bank.regmap[reg]); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | /** |
| 376 | * hw_test_and_clear: tests & clears a hw register |
Peter Chen | 1935388 | 2014-09-22 08:14:17 +0800 | [diff] [blame] | 377 | * @ci: the controller |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 378 | * @reg: register index |
| 379 | * @mask: bitfield mask |
| 380 | * |
| 381 | * This function returns register contents |
| 382 | */ |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 383 | static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 384 | u32 mask) |
| 385 | { |
Richard Zhao | 26c696c | 2012-07-07 22:56:40 +0800 | [diff] [blame] | 386 | u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 387 | |
Peter Chen | ed8f831 | 2014-01-10 13:51:27 +0800 | [diff] [blame] | 388 | __hw_write(ci, val, ci->hw_bank.regmap[reg]); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 389 | return val; |
| 390 | } |
| 391 | |
| 392 | /** |
| 393 | * hw_test_and_write: tests & writes a hw register |
Peter Chen | 1935388 | 2014-09-22 08:14:17 +0800 | [diff] [blame] | 394 | * @ci: the controller |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 395 | * @reg: register index |
| 396 | * @mask: bitfield mask |
| 397 | * @data: new value |
| 398 | * |
| 399 | * This function returns register contents |
| 400 | */ |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 401 | static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 402 | u32 mask, u32 data) |
| 403 | { |
Richard Zhao | 26c696c | 2012-07-07 22:56:40 +0800 | [diff] [blame] | 404 | u32 val = hw_read(ci, reg, ~0); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 405 | |
Richard Zhao | 26c696c | 2012-07-07 22:56:40 +0800 | [diff] [blame] | 406 | hw_write(ci, reg, mask, data); |
Felipe Balbi | 727b4dd | 2013-03-30 12:53:55 +0200 | [diff] [blame] | 407 | return (val & mask) >> __ffs(mask); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 408 | } |
| 409 | |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 410 | /** |
| 411 | * ci_otg_is_fsm_mode: runtime check if otg controller |
| 412 | * is in otg fsm mode. |
Peter Chen | 1935388 | 2014-09-22 08:14:17 +0800 | [diff] [blame] | 413 | * |
| 414 | * @ci: chipidea device |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 415 | */ |
| 416 | static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) |
| 417 | { |
| 418 | #ifdef CONFIG_USB_OTG_FSM |
Li Jun | b0930d4c | 2015-07-09 15:18:46 +0800 | [diff] [blame] | 419 | struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps; |
| 420 | |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 421 | return ci->is_otg && ci->roles[CI_ROLE_HOST] && |
Li Jun | b0930d4c | 2015-07-09 15:18:46 +0800 | [diff] [blame] | 422 | ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support || |
| 423 | otg_caps->hnp_support || otg_caps->adp_support); |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 424 | #else |
| 425 | return false; |
| 426 | #endif |
| 427 | } |
| 428 | |
Stephen Boyd | 7bb7e9b | 2016-12-28 14:56:55 -0800 | [diff] [blame] | 429 | #if IS_ENABLED(CONFIG_USB_CHIPIDEA_ULPI) |
| 430 | int ci_ulpi_init(struct ci_hdrc *ci); |
| 431 | void ci_ulpi_exit(struct ci_hdrc *ci); |
| 432 | int ci_ulpi_resume(struct ci_hdrc *ci); |
| 433 | #else |
| 434 | static inline int ci_ulpi_init(struct ci_hdrc *ci) { return 0; } |
| 435 | static inline void ci_ulpi_exit(struct ci_hdrc *ci) { } |
| 436 | static inline int ci_ulpi_resume(struct ci_hdrc *ci) { return 0; } |
| 437 | #endif |
| 438 | |
Li Jun | 36304b0 | 2014-04-23 15:56:39 +0800 | [diff] [blame] | 439 | u32 hw_read_intr_enable(struct ci_hdrc *ci); |
| 440 | |
| 441 | u32 hw_read_intr_status(struct ci_hdrc *ci); |
| 442 | |
Peter Chen | 5b15730 | 2014-11-26 13:44:33 +0800 | [diff] [blame] | 443 | int hw_device_reset(struct ci_hdrc *ci); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 444 | |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 445 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 446 | |
Alexander Shishkin | 8e22978 | 2013-06-24 14:46:36 +0300 | [diff] [blame] | 447 | u8 hw_port_test_get(struct ci_hdrc *ci); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 448 | |
Stephen Boyd | 7bb7e9b | 2016-12-28 14:56:55 -0800 | [diff] [blame] | 449 | void hw_phymode_configure(struct ci_hdrc *ci); |
| 450 | |
Peter Chen | bf9c85e | 2015-03-17 10:40:50 +0800 | [diff] [blame] | 451 | void ci_platform_configure(struct ci_hdrc *ci); |
| 452 | |
Peter Chen | 9d8c850 | 2015-10-23 10:33:58 +0800 | [diff] [blame] | 453 | int dbg_create_files(struct ci_hdrc *ci); |
| 454 | |
| 455 | void dbg_remove_files(struct ci_hdrc *ci); |
Alexander Shishkin | e443b33 | 2012-05-11 17:25:46 +0300 | [diff] [blame] | 456 | #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ |