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Dan Williams4cdadfd2021-02-16 20:09:50 -08001# SPDX-License-Identifier: GPL-2.0-only
2menuconfig CXL_BUS
3 tristate "CXL (Compute Express Link) Devices Support"
4 depends on PCI
Arnd Bergmann9171dfc2023-07-03 13:29:13 +02005 select FW_LOADER
6 select FW_UPLOAD
Ira Weiny3eddcc92022-07-19 13:52:47 -07007 select PCI_DOE
Dave Jiangad6f04c2023-12-21 15:03:13 -07008 select FIRMWARE_TABLE
Robert Richter4cce9c62024-04-24 17:47:56 +02009 select NUMA_KEEP_MEMINFO if (NUMA && X86)
Dan Williams4cdadfd2021-02-16 20:09:50 -080010 help
11 CXL is a bus that is electrically compatible with PCI Express, but
12 layers three protocols on that signalling (CXL.io, CXL.cache, and
13 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
14 locally, the CXL.mem protocol allows devices to be fully coherent
15 memory targets, the CXL.io protocol is equivalent to PCI Express.
16 Say 'y' to enable support for the configuration and management of
17 devices supporting these protocols.
18
19if CXL_BUS
20
Ben Widawsky68cdd3d2022-01-23 16:28:44 -080021config CXL_PCI
22 tristate "PCI manageability"
Dan Williams3feaa2d2021-06-09 09:01:41 -070023 default CXL_BUS
Dan Williams4cdadfd2021-02-16 20:09:50 -080024 help
Ben Widawsky68cdd3d2022-01-23 16:28:44 -080025 The CXL specification defines a "CXL memory device" sub-class in the
26 PCI "memory controller" base class of devices. Device's identified by
27 this class code provide support for volatile and / or persistent
28 memory to be mapped into the system address map (Host-managed Device
29 Memory (HDM)).
Dan Williams4cdadfd2021-02-16 20:09:50 -080030
Ben Widawsky68cdd3d2022-01-23 16:28:44 -080031 Say 'y/m' to enable a driver that will attach to CXL memory expander
32 devices enumerated by the memory device class code for configuration
33 and management primarily via the mailbox interface. See Chapter 2.3
34 Type 3 CXL Device in the CXL 2.0 specification for more details.
Dan Williams4cdadfd2021-02-16 20:09:50 -080035
36 If unsure say 'm'.
Ben Widawsky13237182021-02-16 20:09:54 -080037
38config CXL_MEM_RAW_COMMANDS
39 bool "RAW Command Interface for Memory Devices"
Ben Widawsky68cdd3d2022-01-23 16:28:44 -080040 depends on CXL_PCI
Ben Widawsky13237182021-02-16 20:09:54 -080041 help
42 Enable CXL RAW command interface.
43
44 The CXL driver ioctl interface may assign a kernel ioctl command
45 number for each specification defined opcode. At any given point in
46 time the number of opcodes that the specification defines and a device
47 may implement may exceed the kernel's set of associated ioctl function
48 numbers. The mismatch is either by omission, specification is too new,
49 or by design. When prototyping new hardware, or developing / debugging
50 the driver it is useful to be able to submit any possible command to
51 the hardware, even commands that may crash the kernel due to their
52 potential impact to memory currently in use by the kernel.
53
54 If developing CXL hardware or the driver say Y, otherwise say N.
Dan Williams4812be92021-06-09 09:01:35 -070055
56config CXL_ACPI
57 tristate "CXL ACPI: Platform Support"
58 depends on ACPI
Dave Jiangad6f04c2023-12-21 15:03:13 -070059 depends on ACPI_NUMA
Dan Williams3feaa2d2021-06-09 09:01:41 -070060 default CXL_BUS
Dan Williamsf4ce1f72021-10-29 12:51:48 -070061 select ACPI_TABLE_LIB
Dave Jiangad6f04c2023-12-21 15:03:13 -070062 select ACPI_HMAT
Dan Williams4812be92021-06-09 09:01:35 -070063 help
64 Enable support for host managed device memory (HDM) resources
65 published by a platform's ACPI CXL memory layout description. See
66 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
67 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
68 (https://www.computeexpresslink.org/spec-landing). The CXL core
69 consumes these resource to publish the root of a cxl_port decode
70 hierarchy to map regions that represent System RAM, or Persistent
71 Memory regions to be managed by LIBNVDIMM.
72
73 If unsure say 'm'.
Dan Williams8fdcb172021-06-15 16:18:17 -070074
75config CXL_PMEM
76 tristate "CXL PMEM: Persistent Memory Support"
77 depends on LIBNVDIMM
78 default CXL_BUS
79 help
80 In addition to typical memory resources a platform may also advertise
81 support for persistent memory attached via CXL. This support is
82 managed via a bridge driver from CXL to the LIBNVDIMM system
83 subsystem. Say 'y/m' to enable support for enumerating and
84 provisioning the persistent memory capacity of CXL memory expanders.
85
86 If unsure say 'm'.
Ben Widawsky54cdbf82022-02-01 13:07:51 -080087
Ben Widawsky8dd2bc02022-02-04 07:18:31 -080088config CXL_MEM
89 tristate "CXL: Memory Expansion"
90 depends on CXL_PCI
91 default CXL_BUS
92 help
93 The CXL.mem protocol allows a device to act as a provider of "System
94 RAM" and/or "Persistent Memory" that is fully coherent as if the
95 memory were attached to the typical CPU memory controller. This is
96 known as HDM "Host-managed Device Memory".
97
98 Say 'y/m' to enable a driver that will attach to CXL.mem devices for
99 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
100 specification for a detailed description of HDM.
101
102 If unsure say 'm'.
103
Ben Widawsky54cdbf82022-02-01 13:07:51 -0800104config CXL_PORT
105 default CXL_BUS
106 tristate
107
Dan Williams9ea4dcf2022-04-22 15:58:11 -0700108config CXL_SUSPEND
109 def_bool y
110 depends on SUSPEND && CXL_MEM
111
Ben Widawsky779dd202021-06-08 10:28:34 -0700112config CXL_REGION
Dan Williams45d235c2023-02-10 01:06:27 -0800113 bool "CXL: Region Support"
Ben Widawsky779dd202021-06-08 10:28:34 -0700114 default CXL_BUS
Dan Williams23a22cd2022-04-25 11:43:44 -0700115 # For MAX_PHYSMEM_BITS
116 depends on SPARSEMEM
Ben Widawsky779dd202021-06-08 10:28:34 -0700117 select MEMREGION
Dan Williams23a22cd2022-04-25 11:43:44 -0700118 select GET_FREE_REGION
Dan Williams45d235c2023-02-10 01:06:27 -0800119 help
120 Enable the CXL core to enumerate and provision CXL regions. A CXL
121 region is defined by one or more CXL expanders that decode a given
122 system-physical address range. For CXL regions established by
123 platform-firmware this option enables memory error handling to
124 identify the devices participating in a given interleaved memory
125 range. Otherwise, platform-firmware managed CXL is enabled by being
126 placed in the system address map and does not need a driver.
127
128 If unsure say 'y'
Ben Widawsky779dd202021-06-08 10:28:34 -0700129
Dan Williamsd18bc742022-12-01 14:03:41 -0800130config CXL_REGION_INVALIDATION_TEST
131 bool "CXL: Region Cache Management Bypass (TEST)"
132 depends on CXL_REGION
133 help
134 CXL Region management and security operations potentially invalidate
Randy Dunlapcbbd05d2023-01-24 19:22:21 -0800135 the content of CPU caches without notifying those caches to
Dan Williamsd18bc742022-12-01 14:03:41 -0800136 invalidate the affected cachelines. The CXL Region driver attempts
137 to invalidate caches when those events occur. If that invalidation
138 fails the region will fail to enable. Reasons for cache
139 invalidation failure are due to the CPU not providing a cache
140 invalidation mechanism. For example usage of wbinvd is restricted to
141 bare metal x86. However, for testing purposes toggling this option
142 can disable that data integrity safety and proceed with enabling
143 regions when there might be conflicting contents in the CPU cache.
144
145 If unsure, or if this kernel is meant for production environments,
146 say N.
147
Dan Williams4cdadfd2021-02-16 20:09:50 -0800148endif