Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | menuconfig CXL_BUS |
| 3 | tristate "CXL (Compute Express Link) Devices Support" |
| 4 | depends on PCI |
Arnd Bergmann | 9171dfc | 2023-07-03 13:29:13 +0200 | [diff] [blame] | 5 | select FW_LOADER |
| 6 | select FW_UPLOAD |
Ira Weiny | 3eddcc9 | 2022-07-19 13:52:47 -0700 | [diff] [blame] | 7 | select PCI_DOE |
Dave Jiang | ad6f04c | 2023-12-21 15:03:13 -0700 | [diff] [blame] | 8 | select FIRMWARE_TABLE |
Robert Richter | 4cce9c6 | 2024-04-24 17:47:56 +0200 | [diff] [blame] | 9 | select NUMA_KEEP_MEMINFO if (NUMA && X86) |
Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 10 | help |
| 11 | CXL is a bus that is electrically compatible with PCI Express, but |
| 12 | layers three protocols on that signalling (CXL.io, CXL.cache, and |
| 13 | CXL.mem). The CXL.cache protocol allows devices to hold cachelines |
| 14 | locally, the CXL.mem protocol allows devices to be fully coherent |
| 15 | memory targets, the CXL.io protocol is equivalent to PCI Express. |
| 16 | Say 'y' to enable support for the configuration and management of |
| 17 | devices supporting these protocols. |
| 18 | |
| 19 | if CXL_BUS |
| 20 | |
Ben Widawsky | 68cdd3d | 2022-01-23 16:28:44 -0800 | [diff] [blame] | 21 | config CXL_PCI |
| 22 | tristate "PCI manageability" |
Dan Williams | 3feaa2d | 2021-06-09 09:01:41 -0700 | [diff] [blame] | 23 | default CXL_BUS |
Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 24 | help |
Ben Widawsky | 68cdd3d | 2022-01-23 16:28:44 -0800 | [diff] [blame] | 25 | The CXL specification defines a "CXL memory device" sub-class in the |
| 26 | PCI "memory controller" base class of devices. Device's identified by |
| 27 | this class code provide support for volatile and / or persistent |
| 28 | memory to be mapped into the system address map (Host-managed Device |
| 29 | Memory (HDM)). |
Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 30 | |
Ben Widawsky | 68cdd3d | 2022-01-23 16:28:44 -0800 | [diff] [blame] | 31 | Say 'y/m' to enable a driver that will attach to CXL memory expander |
| 32 | devices enumerated by the memory device class code for configuration |
| 33 | and management primarily via the mailbox interface. See Chapter 2.3 |
| 34 | Type 3 CXL Device in the CXL 2.0 specification for more details. |
Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 35 | |
| 36 | If unsure say 'm'. |
Ben Widawsky | 1323718 | 2021-02-16 20:09:54 -0800 | [diff] [blame] | 37 | |
| 38 | config CXL_MEM_RAW_COMMANDS |
| 39 | bool "RAW Command Interface for Memory Devices" |
Ben Widawsky | 68cdd3d | 2022-01-23 16:28:44 -0800 | [diff] [blame] | 40 | depends on CXL_PCI |
Ben Widawsky | 1323718 | 2021-02-16 20:09:54 -0800 | [diff] [blame] | 41 | help |
| 42 | Enable CXL RAW command interface. |
| 43 | |
| 44 | The CXL driver ioctl interface may assign a kernel ioctl command |
| 45 | number for each specification defined opcode. At any given point in |
| 46 | time the number of opcodes that the specification defines and a device |
| 47 | may implement may exceed the kernel's set of associated ioctl function |
| 48 | numbers. The mismatch is either by omission, specification is too new, |
| 49 | or by design. When prototyping new hardware, or developing / debugging |
| 50 | the driver it is useful to be able to submit any possible command to |
| 51 | the hardware, even commands that may crash the kernel due to their |
| 52 | potential impact to memory currently in use by the kernel. |
| 53 | |
| 54 | If developing CXL hardware or the driver say Y, otherwise say N. |
Dan Williams | 4812be9 | 2021-06-09 09:01:35 -0700 | [diff] [blame] | 55 | |
| 56 | config CXL_ACPI |
| 57 | tristate "CXL ACPI: Platform Support" |
| 58 | depends on ACPI |
Dave Jiang | ad6f04c | 2023-12-21 15:03:13 -0700 | [diff] [blame] | 59 | depends on ACPI_NUMA |
Dan Williams | 3feaa2d | 2021-06-09 09:01:41 -0700 | [diff] [blame] | 60 | default CXL_BUS |
Dan Williams | f4ce1f7 | 2021-10-29 12:51:48 -0700 | [diff] [blame] | 61 | select ACPI_TABLE_LIB |
Dave Jiang | ad6f04c | 2023-12-21 15:03:13 -0700 | [diff] [blame] | 62 | select ACPI_HMAT |
Dan Williams | 4812be9 | 2021-06-09 09:01:35 -0700 | [diff] [blame] | 63 | help |
| 64 | Enable support for host managed device memory (HDM) resources |
| 65 | published by a platform's ACPI CXL memory layout description. See |
| 66 | Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 |
| 67 | specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) |
| 68 | (https://www.computeexpresslink.org/spec-landing). The CXL core |
| 69 | consumes these resource to publish the root of a cxl_port decode |
| 70 | hierarchy to map regions that represent System RAM, or Persistent |
| 71 | Memory regions to be managed by LIBNVDIMM. |
| 72 | |
| 73 | If unsure say 'm'. |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 74 | |
| 75 | config CXL_PMEM |
| 76 | tristate "CXL PMEM: Persistent Memory Support" |
| 77 | depends on LIBNVDIMM |
| 78 | default CXL_BUS |
| 79 | help |
| 80 | In addition to typical memory resources a platform may also advertise |
| 81 | support for persistent memory attached via CXL. This support is |
| 82 | managed via a bridge driver from CXL to the LIBNVDIMM system |
| 83 | subsystem. Say 'y/m' to enable support for enumerating and |
| 84 | provisioning the persistent memory capacity of CXL memory expanders. |
| 85 | |
| 86 | If unsure say 'm'. |
Ben Widawsky | 54cdbf8 | 2022-02-01 13:07:51 -0800 | [diff] [blame] | 87 | |
Ben Widawsky | 8dd2bc0 | 2022-02-04 07:18:31 -0800 | [diff] [blame] | 88 | config CXL_MEM |
| 89 | tristate "CXL: Memory Expansion" |
| 90 | depends on CXL_PCI |
| 91 | default CXL_BUS |
| 92 | help |
| 93 | The CXL.mem protocol allows a device to act as a provider of "System |
| 94 | RAM" and/or "Persistent Memory" that is fully coherent as if the |
| 95 | memory were attached to the typical CPU memory controller. This is |
| 96 | known as HDM "Host-managed Device Memory". |
| 97 | |
| 98 | Say 'y/m' to enable a driver that will attach to CXL.mem devices for |
| 99 | memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0 |
| 100 | specification for a detailed description of HDM. |
| 101 | |
| 102 | If unsure say 'm'. |
| 103 | |
Ben Widawsky | 54cdbf8 | 2022-02-01 13:07:51 -0800 | [diff] [blame] | 104 | config CXL_PORT |
| 105 | default CXL_BUS |
| 106 | tristate |
| 107 | |
Dan Williams | 9ea4dcf | 2022-04-22 15:58:11 -0700 | [diff] [blame] | 108 | config CXL_SUSPEND |
| 109 | def_bool y |
| 110 | depends on SUSPEND && CXL_MEM |
| 111 | |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 112 | config CXL_REGION |
Dan Williams | 45d235c | 2023-02-10 01:06:27 -0800 | [diff] [blame] | 113 | bool "CXL: Region Support" |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 114 | default CXL_BUS |
Dan Williams | 23a22cd | 2022-04-25 11:43:44 -0700 | [diff] [blame] | 115 | # For MAX_PHYSMEM_BITS |
| 116 | depends on SPARSEMEM |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 117 | select MEMREGION |
Dan Williams | 23a22cd | 2022-04-25 11:43:44 -0700 | [diff] [blame] | 118 | select GET_FREE_REGION |
Dan Williams | 45d235c | 2023-02-10 01:06:27 -0800 | [diff] [blame] | 119 | help |
| 120 | Enable the CXL core to enumerate and provision CXL regions. A CXL |
| 121 | region is defined by one or more CXL expanders that decode a given |
| 122 | system-physical address range. For CXL regions established by |
| 123 | platform-firmware this option enables memory error handling to |
| 124 | identify the devices participating in a given interleaved memory |
| 125 | range. Otherwise, platform-firmware managed CXL is enabled by being |
| 126 | placed in the system address map and does not need a driver. |
| 127 | |
| 128 | If unsure say 'y' |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 129 | |
Dan Williams | d18bc74 | 2022-12-01 14:03:41 -0800 | [diff] [blame] | 130 | config CXL_REGION_INVALIDATION_TEST |
| 131 | bool "CXL: Region Cache Management Bypass (TEST)" |
| 132 | depends on CXL_REGION |
| 133 | help |
| 134 | CXL Region management and security operations potentially invalidate |
Randy Dunlap | cbbd05d | 2023-01-24 19:22:21 -0800 | [diff] [blame] | 135 | the content of CPU caches without notifying those caches to |
Dan Williams | d18bc74 | 2022-12-01 14:03:41 -0800 | [diff] [blame] | 136 | invalidate the affected cachelines. The CXL Region driver attempts |
| 137 | to invalidate caches when those events occur. If that invalidation |
| 138 | fails the region will fail to enable. Reasons for cache |
| 139 | invalidation failure are due to the CPU not providing a cache |
| 140 | invalidation mechanism. For example usage of wbinvd is restricted to |
| 141 | bare metal x86. However, for testing purposes toggling this option |
| 142 | can disable that data integrity safety and proceed with enabling |
| 143 | regions when there might be conflicting contents in the CPU cache. |
| 144 | |
| 145 | If unsure, or if this kernel is meant for production environments, |
| 146 | say N. |
| 147 | |
Dan Williams | 4cdadfd | 2021-02-16 20:09:50 -0800 | [diff] [blame] | 148 | endif |