Arnd Bergmann | f3f66f5 | 2005-10-31 20:08:37 -0500 | [diff] [blame] | 1 | #ifndef CELL_IOMMU_H |
| 2 | #define CELL_IOMMU_H |
Arnd Bergmann | ae209cf | 2005-06-23 09:43:54 +1000 | [diff] [blame] | 3 | |
| 4 | /* some constants */ |
| 5 | enum { |
| 6 | /* segment table entries */ |
| 7 | IOST_VALID_MASK = 0x8000000000000000ul, |
| 8 | IOST_TAG_MASK = 0x3000000000000000ul, |
| 9 | IOST_PT_BASE_MASK = 0x000003fffffff000ul, |
| 10 | IOST_NNPT_MASK = 0x0000000000000fe0ul, |
| 11 | IOST_PS_MASK = 0x000000000000000ful, |
| 12 | |
| 13 | IOST_PS_4K = 0x1, |
| 14 | IOST_PS_64K = 0x3, |
| 15 | IOST_PS_1M = 0x5, |
| 16 | IOST_PS_16M = 0x7, |
| 17 | |
| 18 | /* iopt tag register */ |
| 19 | IOPT_VALID_MASK = 0x0000000200000000ul, |
| 20 | IOPT_TAG_MASK = 0x00000001fffffffful, |
| 21 | |
| 22 | /* iopt cache register */ |
| 23 | IOPT_PROT_MASK = 0xc000000000000000ul, |
| 24 | IOPT_PROT_NONE = 0x0000000000000000ul, |
| 25 | IOPT_PROT_READ = 0x4000000000000000ul, |
| 26 | IOPT_PROT_WRITE = 0x8000000000000000ul, |
| 27 | IOPT_PROT_RW = 0xc000000000000000ul, |
| 28 | IOPT_COHERENT = 0x2000000000000000ul, |
| 29 | |
| 30 | IOPT_ORDER_MASK = 0x1800000000000000ul, |
| 31 | /* order access to same IOID/VC on same address */ |
| 32 | IOPT_ORDER_ADDR = 0x0800000000000000ul, |
| 33 | /* similar, but only after a write access */ |
| 34 | IOPT_ORDER_WRITES = 0x1000000000000000ul, |
| 35 | /* Order all accesses to same IOID/VC */ |
| 36 | IOPT_ORDER_VC = 0x1800000000000000ul, |
| 37 | |
| 38 | IOPT_RPN_MASK = 0x000003fffffff000ul, |
| 39 | IOPT_HINT_MASK = 0x0000000000000800ul, |
| 40 | IOPT_IOID_MASK = 0x00000000000007fful, |
| 41 | |
| 42 | IOSTO_ENABLE = 0x8000000000000000ul, |
| 43 | IOSTO_ORIGIN = 0x000003fffffff000ul, |
| 44 | IOSTO_HW = 0x0000000000000800ul, |
| 45 | IOSTO_SW = 0x0000000000000400ul, |
| 46 | |
| 47 | IOCMD_CONF_TE = 0x0000800000000000ul, |
| 48 | |
| 49 | /* memory mapped registers */ |
| 50 | IOC_PT_CACHE_DIR = 0x000, |
| 51 | IOC_ST_CACHE_DIR = 0x800, |
| 52 | IOC_PT_CACHE_REG = 0x910, |
| 53 | IOC_ST_ORIGIN = 0x918, |
| 54 | IOC_CONF = 0x930, |
| 55 | |
| 56 | /* The high bit needs to be set on every DMA address, |
| 57 | only 2GB are addressable */ |
Arnd Bergmann | f3f66f5 | 2005-10-31 20:08:37 -0500 | [diff] [blame] | 58 | CELL_DMA_VALID = 0x80000000, |
| 59 | CELL_DMA_MASK = 0x7fffffff, |
Arnd Bergmann | ae209cf | 2005-06-23 09:43:54 +1000 | [diff] [blame] | 60 | }; |
| 61 | |
| 62 | |
Arnd Bergmann | f3f66f5 | 2005-10-31 20:08:37 -0500 | [diff] [blame] | 63 | void cell_init_iommu(void); |
Arnd Bergmann | ae209cf | 2005-06-23 09:43:54 +1000 | [diff] [blame] | 64 | |
| 65 | #endif |