Sudeep Dutt | aa27bad | 2013-09-05 16:42:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel MIC Platform Software Stack (MPSS) |
| 3 | * |
| 4 | * Copyright(c) 2013 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License, version 2, as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * General Public License for more details. |
| 14 | * |
| 15 | * The full GNU General Public License is included in this distribution in |
| 16 | * the file called "COPYING". |
| 17 | * |
| 18 | * Disclaimer: The codes contained in these modules may be specific to |
| 19 | * the Intel Software Development Platform codenamed: Knights Ferry, and |
| 20 | * the Intel product codenamed: Knights Corner, and are not backward |
| 21 | * compatible with other Intel products. Additionally, Intel will NOT |
| 22 | * support the codes or instruction set in future products. |
| 23 | * |
| 24 | * Intel MIC Card driver. |
| 25 | * |
| 26 | */ |
| 27 | #ifndef _MIC_X100_CARD_H_ |
| 28 | #define _MIC_X100_CARD_H_ |
| 29 | |
| 30 | #define MIC_X100_MMIO_BASE 0x08007C0000ULL |
| 31 | #define MIC_X100_MMIO_LEN 0x00020000ULL |
| 32 | #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000ULL |
| 33 | |
| 34 | #define MIC_X100_SBOX_SPAD0 0x0000AB20 |
| 35 | #define MIC_X100_SBOX_SDBIC0 0x0000CC90 |
| 36 | #define MIC_X100_SBOX_SDBIC0_DBREQ_BIT 0x80000000 |
| 37 | #define MIC_X100_SBOX_RDMASR0 0x0000B180 |
Sudeep Dutt | dd8d8d4 | 2015-04-29 05:32:39 -0700 | [diff] [blame] | 38 | #define MIC_X100_SBOX_APICICR0 0x0000A9D0 |
Sudeep Dutt | aa27bad | 2013-09-05 16:42:06 -0700 | [diff] [blame] | 39 | |
| 40 | #define MIC_X100_MAX_DOORBELL_IDX 8 |
| 41 | |
| 42 | #define MIC_X100_NUM_SBOX_IRQ 8 |
| 43 | #define MIC_X100_NUM_RDMASR_IRQ 8 |
| 44 | #define MIC_X100_SBOX_IRQ_BASE 0 |
| 45 | #define MIC_X100_RDMASR_IRQ_BASE 17 |
| 46 | |
| 47 | #define MIC_X100_IRQ_BASE 26 |
| 48 | |
| 49 | #endif |