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Krzysztof Kozlowski84b21702017-12-25 20:54:32 +01001/* SPDX-License-Identifier: GPL-2.0 */
2/*
Russell Kinga09e64f2008-08-05 16:14:15 +01003 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
Russell Kinga09e64f2008-08-05 16:14:15 +01007 * S3C2443 clock register definitions
Krzysztof Kozlowski84b21702017-12-25 20:54:32 +01008 */
Russell Kinga09e64f2008-08-05 16:14:15 +01009
10#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
11#define __ASM_ARM_REGS_S3C2443_CLOCK
12
13#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
14
15#define S3C2443_PLLCON_MDIVSHIFT 16
16#define S3C2443_PLLCON_PDIVSHIFT 8
17#define S3C2443_PLLCON_SDIVSHIFT 0
18#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
19#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
20#define S3C2443_PLLCON_SDIVMASK (3)
21
22#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
23#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
24#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
25#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
26#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
27#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
28#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
29#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
30#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
31#define S3C2443_SWRST S3C2443_CLKREG(0x44)
32#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
33#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
34#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
35#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
Thomas Abraham0a94c6b2011-05-07 22:24:49 +020036#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
37#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
38#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
39#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
Russell Kinga09e64f2008-08-05 16:14:15 +010040
Russell Kinga09e64f2008-08-05 16:14:15 +010041#define S3C2443_PLLCON_OFF (1<<24)
42
Wei Shuai78af4732008-08-26 22:54:08 +010043#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
44#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
45#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
46#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
47#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
Russell Kinga09e64f2008-08-05 16:14:15 +010048
Russell Kinga09e64f2008-08-05 16:14:15 +010049#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
50
Russell Kinga09e64f2008-08-05 16:14:15 +010051#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
52#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
53
54#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
55
56#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
57#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
58
59#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
60#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
61
Heiko Stuebner0d23d052011-10-14 15:08:56 +090062#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
Russell Kinga09e64f2008-08-05 16:14:15 +010063#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
64#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
65#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
66#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
67#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
68#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
69#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
70#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
71#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
72#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
73
Ben Dooks9aa753c2010-01-30 09:19:59 +020074/* S3C2443_CLKDIV1 removed, only used in clock.c code */
Russell Kinga09e64f2008-08-05 16:14:15 +010075
76#define S3C2443_CLKCON_NAND
77
78#define S3C2443_HCLKCON_DMA0 (1<<0)
79#define S3C2443_HCLKCON_DMA1 (1<<1)
80#define S3C2443_HCLKCON_DMA2 (1<<2)
81#define S3C2443_HCLKCON_DMA3 (1<<3)
82#define S3C2443_HCLKCON_DMA4 (1<<4)
83#define S3C2443_HCLKCON_DMA5 (1<<5)
84#define S3C2443_HCLKCON_CAMIF (1<<8)
Ben Dooksdc5d2e82010-04-30 19:34:25 +090085#define S3C2443_HCLKCON_LCDC (1<<9)
Russell Kinga09e64f2008-08-05 16:14:15 +010086#define S3C2443_HCLKCON_USBH (1<<11)
87#define S3C2443_HCLKCON_USBD (1<<12)
Yauhen Kharuzhy95d67912011-01-06 13:04:33 +090088#define S3C2416_HCLKCON_HSMMC0 (1<<15)
Russell Kinga09e64f2008-08-05 16:14:15 +010089#define S3C2443_HCLKCON_HSMMC (1<<16)
90#define S3C2443_HCLKCON_CFC (1<<17)
91#define S3C2443_HCLKCON_SSMC (1<<18)
92#define S3C2443_HCLKCON_DRAMC (1<<19)
93
94#define S3C2443_PCLKCON_UART0 (1<<0)
95#define S3C2443_PCLKCON_UART1 (1<<1)
96#define S3C2443_PCLKCON_UART2 (1<<2)
97#define S3C2443_PCLKCON_UART3 (1<<3)
98#define S3C2443_PCLKCON_IIC (1<<4)
99#define S3C2443_PCLKCON_SDI (1<<5)
Heiko Stuebnerbd95be62011-09-27 08:44:57 +0900100#define S3C2443_PCLKCON_HSSPI (1<<6)
Russell Kinga09e64f2008-08-05 16:14:15 +0100101#define S3C2443_PCLKCON_ADC (1<<7)
102#define S3C2443_PCLKCON_AC97 (1<<8)
103#define S3C2443_PCLKCON_IIS (1<<9)
104#define S3C2443_PCLKCON_PWMT (1<<10)
105#define S3C2443_PCLKCON_WDT (1<<11)
106#define S3C2443_PCLKCON_RTC (1<<12)
107#define S3C2443_PCLKCON_GPIO (1<<13)
108#define S3C2443_PCLKCON_SPI0 (1<<14)
109#define S3C2443_PCLKCON_SPI1 (1<<15)
110
111#define S3C2443_SCLKCON_DDRCLK (1<<16)
112#define S3C2443_SCLKCON_SSMCCLK (1<<15)
113#define S3C2443_SCLKCON_HSSPICLK (1<<14)
114#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
115#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
116#define S3C2443_SCLKCON_CAMCLK (1<<11)
117#define S3C2443_SCLKCON_DISPCLK (1<<10)
118#define S3C2443_SCLKCON_I2SCLK (1<<9)
119#define S3C2443_SCLKCON_UARTCLK (1<<8)
120#define S3C2443_SCLKCON_USBHOST (1<<1)
121
Abhilash Kesavan6436b6a2010-10-20 19:43:35 +0900122#define S3C2443_PWRCFG_SLEEP (1<<15)
123
Thomas Abraham0a94c6b2011-05-07 22:24:49 +0200124#define S3C2443_PWRCFG_USBPHY (1 << 4)
125
126#define S3C2443_URSTCON_FUNCRST (1 << 2)
127#define S3C2443_URSTCON_PHYRST (1 << 0)
128
129#define S3C2443_PHYCTRL_CLKSEL (1 << 3)
130#define S3C2443_PHYCTRL_EXTCLK (1 << 2)
131#define S3C2443_PHYCTRL_PLLSEL (1 << 1)
132#define S3C2443_PHYCTRL_DSPORT (1 << 0)
133
134#define S3C2443_PHYPWR_COMMON_ON (1 << 31)
135#define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
136#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
137#define S3C2443_PHYPWR_XO_ON (1 << 2)
138#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
139#define S3C2443_PHYPWR_FSUSPEND (1 << 0)
140
141#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
142#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
143#define S3C2443_UCLKCON_TCLKEN (1 << 0)
144
Russell Kinga09e64f2008-08-05 16:14:15 +0100145#include <asm/div64.h>
146
147static inline unsigned int
148s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
149{
150 unsigned int mdiv, pdiv, sdiv;
151 uint64_t fvco;
152
153 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
154 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
155 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
156
157 mdiv &= S3C2443_PLLCON_MDIVMASK;
158 pdiv &= S3C2443_PLLCON_PDIVMASK;
159 sdiv &= S3C2443_PLLCON_SDIVMASK;
160
161 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
162 do_div(fvco, pdiv << sdiv);
163
164 return (unsigned int)fvco;
165}
166
167static inline unsigned int
168s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
169{
170 unsigned int mdiv, pdiv, sdiv;
171 uint64_t fvco;
172
173 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
174 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
175 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
176
177 mdiv &= S3C2443_PLLCON_MDIVMASK;
178 pdiv &= S3C2443_PLLCON_PDIVMASK;
179 sdiv &= S3C2443_PLLCON_SDIVMASK;
180
181 fvco = (uint64_t)baseclk * (mdiv + 8);
182 do_div(fvco, (pdiv + 2) << sdiv);
183
184 return (unsigned int)fvco;
185}
186
187#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
188