blob: c9faa85408593b58d1022c01e4162af33b8ffab8 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Florian Fainelli80105be2014-04-24 18:08:57 -07002/*
3 * Broadcom BCM7xxx System Port Ethernet MAC driver
4 *
5 * Copyright (C) 2014 Broadcom Corporation
Florian Fainelli80105be2014-04-24 18:08:57 -07006 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/netdevice.h>
Vladimir Olteanf46b9b8e2021-01-07 03:24:00 +020015#include <linux/dsa/brcm.h>
Florian Fainelli80105be2014-04-24 18:08:57 -070016#include <linux/etherdevice.h>
17#include <linux/platform_device.h>
18#include <linux/of.h>
19#include <linux/of_net.h>
20#include <linux/of_mdio.h>
21#include <linux/phy.h>
22#include <linux/phy_fixed.h>
Andrew Lunnc6e970a2017-03-28 23:45:06 +020023#include <net/dsa.h>
Florian Fainelli31bc72d2020-09-01 14:43:47 -070024#include <linux/clk.h>
Florian Fainelli80105be2014-04-24 18:08:57 -070025#include <net/ip.h>
26#include <net/ipv6.h>
27
28#include "bcmsysport.h"
29
30/* I/O accessors register helpers */
31#define BCM_SYSPORT_IO_MACRO(name, offset) \
32static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
33{ \
Florian Fainellif1dd1992017-08-29 13:35:15 -070034 u32 reg = readl_relaxed(priv->base + offset + off); \
Florian Fainelli80105be2014-04-24 18:08:57 -070035 return reg; \
36} \
37static inline void name##_writel(struct bcm_sysport_priv *priv, \
38 u32 val, u32 off) \
39{ \
Florian Fainellif1dd1992017-08-29 13:35:15 -070040 writel_relaxed(val, priv->base + offset + off); \
Florian Fainelli80105be2014-04-24 18:08:57 -070041} \
42
43BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
44BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
45BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
Florian Fainelli44a45242017-01-20 11:08:27 -080046BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET);
Florian Fainelli80105be2014-04-24 18:08:57 -070047BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
Florian Fainelli80105be2014-04-24 18:08:57 -070048BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
49BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
50BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
51BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
52BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
53
Florian Fainelli44a45242017-01-20 11:08:27 -080054/* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact
55 * same layout, except it has been moved by 4 bytes up, *sigh*
56 */
57static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off)
58{
59 if (priv->is_lite && off >= RDMA_STATUS)
60 off += 4;
Florian Fainellif1dd1992017-08-29 13:35:15 -070061 return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off);
Florian Fainelli44a45242017-01-20 11:08:27 -080062}
63
64static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off)
65{
66 if (priv->is_lite && off >= RDMA_STATUS)
67 off += 4;
Florian Fainellif1dd1992017-08-29 13:35:15 -070068 writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off);
Florian Fainelli44a45242017-01-20 11:08:27 -080069}
70
71static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit)
72{
73 if (!priv->is_lite) {
74 return BIT(bit);
75 } else {
76 if (bit >= ACB_ALGO)
77 return BIT(bit + 1);
78 else
79 return BIT(bit);
80 }
81}
82
Florian Fainelli80105be2014-04-24 18:08:57 -070083/* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
84 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
85 */
86#define BCM_SYSPORT_INTR_L2(which) \
87static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
88 u32 mask) \
89{ \
Florian Fainelli80105be2014-04-24 18:08:57 -070090 priv->irq##which##_mask &= ~(mask); \
Florian Fainelli9a0a5c42016-08-24 14:21:41 -070091 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
Florian Fainelli80105be2014-04-24 18:08:57 -070092} \
93static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
94 u32 mask) \
95{ \
96 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
97 priv->irq##which##_mask |= (mask); \
98} \
99
100BCM_SYSPORT_INTR_L2(0)
101BCM_SYSPORT_INTR_L2(1)
102
103/* Register accesses to GISB/RBUS registers are expensive (few hundred
104 * nanoseconds), so keep the check for 64-bits explicit here to save
105 * one register write per-packet on 32-bits platforms.
106 */
107static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
108 void __iomem *d,
109 dma_addr_t addr)
110{
111#ifdef CONFIG_PHYS_ADDR_T_64BIT
Florian Fainellif1dd1992017-08-29 13:35:15 -0700112 writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700113 d + DESC_ADDR_HI_STATUS_LEN);
Florian Fainelli80105be2014-04-24 18:08:57 -0700114#endif
Florian Fainellif1dd1992017-08-29 13:35:15 -0700115 writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);
Florian Fainelli80105be2014-04-24 18:08:57 -0700116}
117
Florian Fainelli80105be2014-04-24 18:08:57 -0700118/* Ethtool operations */
Florian Fainelli10b476c2018-09-27 15:36:10 -0700119static void bcm_sysport_set_rx_csum(struct net_device *dev,
120 netdev_features_t wanted)
Florian Fainelli80105be2014-04-24 18:08:57 -0700121{
122 struct bcm_sysport_priv *priv = netdev_priv(dev);
123 u32 reg;
124
Florian Fainelli9d34c1cb2014-07-01 21:08:39 -0700125 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
Florian Fainelli80105be2014-04-24 18:08:57 -0700126 reg = rxchk_readl(priv, RXCHK_CONTROL);
Florian Fainellia40061e2019-02-15 12:16:51 -0800127 /* Clear L2 header checks, which would prevent BPDUs
128 * from being received.
129 */
130 reg &= ~RXCHK_L2_HDR_DIS;
Florian Fainelli9d34c1cb2014-07-01 21:08:39 -0700131 if (priv->rx_chk_en)
Florian Fainelli80105be2014-04-24 18:08:57 -0700132 reg |= RXCHK_EN;
133 else
134 reg &= ~RXCHK_EN;
135
136 /* If UniMAC forwards CRC, we need to skip over it to get
137 * a valid CHK bit to be set in the per-packet status word
138 */
Florian Fainelli9d34c1cb2014-07-01 21:08:39 -0700139 if (priv->rx_chk_en && priv->crc_fwd)
Florian Fainelli80105be2014-04-24 18:08:57 -0700140 reg |= RXCHK_SKIP_FCS;
141 else
142 reg &= ~RXCHK_SKIP_FCS;
143
Florian Fainellid09d3032014-08-28 15:11:03 -0700144 /* If Broadcom tags are enabled (e.g: using a switch), make
145 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
146 * tag after the Ethernet MAC Source Address.
147 */
148 if (netdev_uses_dsa(dev))
149 reg |= RXCHK_BRCM_TAG_EN;
150 else
151 reg &= ~RXCHK_BRCM_TAG_EN;
152
Florian Fainelli80105be2014-04-24 18:08:57 -0700153 rxchk_writel(priv, reg, RXCHK_CONTROL);
Florian Fainelli80105be2014-04-24 18:08:57 -0700154}
155
Florian Fainelli10b476c2018-09-27 15:36:10 -0700156static void bcm_sysport_set_tx_csum(struct net_device *dev,
157 netdev_features_t wanted)
Florian Fainelli80105be2014-04-24 18:08:57 -0700158{
159 struct bcm_sysport_priv *priv = netdev_priv(dev);
160 u32 reg;
161
162 /* Hardware transmit checksum requires us to enable the Transmit status
163 * block prepended to the packet contents
164 */
Florian Fainelli6e9fdb62020-07-06 14:29:39 -0700165 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
166 NETIF_F_HW_VLAN_CTAG_TX));
Florian Fainelli80105be2014-04-24 18:08:57 -0700167 reg = tdma_readl(priv, TDMA_CONTROL);
168 if (priv->tsb_en)
Florian Fainelli44a45242017-01-20 11:08:27 -0800169 reg |= tdma_control_bit(priv, TSB_EN);
Florian Fainelli80105be2014-04-24 18:08:57 -0700170 else
Florian Fainelli44a45242017-01-20 11:08:27 -0800171 reg &= ~tdma_control_bit(priv, TSB_EN);
Florian Fainelli6e9fdb62020-07-06 14:29:39 -0700172 /* Indicating that software inserts Broadcom tags is needed for the TX
173 * checksum to be computed correctly when using VLAN HW acceleration,
174 * else it has no effect, so it can always be turned on.
175 */
176 if (netdev_uses_dsa(dev))
177 reg |= tdma_control_bit(priv, SW_BRCM_TAG);
178 else
179 reg &= ~tdma_control_bit(priv, SW_BRCM_TAG);
Florian Fainelli80105be2014-04-24 18:08:57 -0700180 tdma_writel(priv, reg, TDMA_CONTROL);
Florian Fainelli6e9fdb62020-07-06 14:29:39 -0700181
182 /* Default TPID is ETH_P_8021AD, change to ETH_P_8021Q */
183 if (wanted & NETIF_F_HW_VLAN_CTAG_TX)
184 tdma_writel(priv, ETH_P_8021Q, TDMA_TPID);
Florian Fainelli80105be2014-04-24 18:08:57 -0700185}
186
187static int bcm_sysport_set_features(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700188 netdev_features_t features)
Florian Fainelli80105be2014-04-24 18:08:57 -0700189{
Florian Fainelli10b476c2018-09-27 15:36:10 -0700190 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainelli31bc72d2020-09-01 14:43:47 -0700191 int ret;
192
193 ret = clk_prepare_enable(priv->clk);
194 if (ret)
195 return ret;
Florian Fainelli80105be2014-04-24 18:08:57 -0700196
Florian Fainelli10b476c2018-09-27 15:36:10 -0700197 /* Read CRC forward */
198 if (!priv->is_lite)
199 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
200 else
201 priv->crc_fwd = !((gib_readl(priv, GIB_CONTROL) &
202 GIB_FCS_STRIP) >> GIB_FCS_STRIP_SHIFT);
Florian Fainelli80105be2014-04-24 18:08:57 -0700203
Florian Fainelli10b476c2018-09-27 15:36:10 -0700204 bcm_sysport_set_rx_csum(dev, features);
205 bcm_sysport_set_tx_csum(dev, features);
206
Florian Fainelli31bc72d2020-09-01 14:43:47 -0700207 clk_disable_unprepare(priv->clk);
208
Florian Fainelli10b476c2018-09-27 15:36:10 -0700209 return 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700210}
211
212/* Hardware counters must be kept in sync because the order/offset
213 * is important here (order in structure declaration = order in hardware)
214 */
215static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
216 /* general stats */
kiki good10377ba2017-08-04 00:07:45 +0100217 STAT_NETDEV64(rx_packets),
218 STAT_NETDEV64(tx_packets),
219 STAT_NETDEV64(rx_bytes),
220 STAT_NETDEV64(tx_bytes),
Florian Fainelli80105be2014-04-24 18:08:57 -0700221 STAT_NETDEV(rx_errors),
222 STAT_NETDEV(tx_errors),
223 STAT_NETDEV(rx_dropped),
224 STAT_NETDEV(tx_dropped),
225 STAT_NETDEV(multicast),
226 /* UniMAC RSV counters */
227 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
228 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
229 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
230 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
231 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
232 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
233 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
234 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
235 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
236 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
237 STAT_MIB_RX("rx_pkts", mib.rx.pkt),
238 STAT_MIB_RX("rx_bytes", mib.rx.bytes),
239 STAT_MIB_RX("rx_multicast", mib.rx.mca),
240 STAT_MIB_RX("rx_broadcast", mib.rx.bca),
241 STAT_MIB_RX("rx_fcs", mib.rx.fcs),
242 STAT_MIB_RX("rx_control", mib.rx.cf),
243 STAT_MIB_RX("rx_pause", mib.rx.pf),
244 STAT_MIB_RX("rx_unknown", mib.rx.uo),
245 STAT_MIB_RX("rx_align", mib.rx.aln),
246 STAT_MIB_RX("rx_outrange", mib.rx.flr),
247 STAT_MIB_RX("rx_code", mib.rx.cde),
248 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
249 STAT_MIB_RX("rx_oversize", mib.rx.ovr),
250 STAT_MIB_RX("rx_jabber", mib.rx.jbr),
251 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
252 STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
253 STAT_MIB_RX("rx_unicast", mib.rx.uc),
254 STAT_MIB_RX("rx_ppp", mib.rx.ppp),
255 STAT_MIB_RX("rx_crc", mib.rx.rcrc),
256 /* UniMAC TSV counters */
257 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
258 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
259 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
260 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
261 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
262 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
263 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
264 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
265 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
266 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
267 STAT_MIB_TX("tx_pkts", mib.tx.pkts),
268 STAT_MIB_TX("tx_multicast", mib.tx.mca),
269 STAT_MIB_TX("tx_broadcast", mib.tx.bca),
270 STAT_MIB_TX("tx_pause", mib.tx.pf),
271 STAT_MIB_TX("tx_control", mib.tx.cf),
272 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
273 STAT_MIB_TX("tx_oversize", mib.tx.ovr),
274 STAT_MIB_TX("tx_defer", mib.tx.drf),
275 STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
276 STAT_MIB_TX("tx_single_col", mib.tx.scl),
277 STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
278 STAT_MIB_TX("tx_late_col", mib.tx.lcl),
279 STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
280 STAT_MIB_TX("tx_frags", mib.tx.frg),
281 STAT_MIB_TX("tx_total_col", mib.tx.ncl),
282 STAT_MIB_TX("tx_jabber", mib.tx.jbr),
283 STAT_MIB_TX("tx_bytes", mib.tx.bytes),
284 STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
285 STAT_MIB_TX("tx_unicast", mib.tx.uc),
286 /* UniMAC RUNT counters */
287 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
288 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
289 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
290 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
291 /* RXCHK misc statistics */
292 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
293 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700294 RXCHK_OTHER_DISC_CNTR),
Florian Fainelli80105be2014-04-24 18:08:57 -0700295 /* RBUF misc statistics */
296 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
297 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
Florian Fainellib98deb22022-10-28 15:21:40 -0700298 /* RDMA misc statistics */
299 STAT_RDMA("rdma_ovflow_cnt", mib.rdma_ovflow_cnt, RDMA_OVFL_DISC_CNTR),
Florian Fainelli55ff4ea2015-02-28 18:09:17 -0800300 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
301 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
302 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
Florian Fainellia5d78ce2018-09-27 15:36:14 -0700303 STAT_MIB_SOFT("tx_realloc_tsb", mib.tx_realloc_tsb),
304 STAT_MIB_SOFT("tx_realloc_tsb_failed", mib.tx_realloc_tsb_failed),
Florian Fainelli30defeb2017-03-23 10:36:46 -0700305 /* Per TX-queue statistics are dynamically appended */
Florian Fainelli80105be2014-04-24 18:08:57 -0700306};
307
308#define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
309
310static void bcm_sysport_get_drvinfo(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700311 struct ethtool_drvinfo *info)
Florian Fainelli80105be2014-04-24 18:08:57 -0700312{
Wolfram Sangf029c782022-08-30 22:14:54 +0200313 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
314 strscpy(info->bus_info, "platform", sizeof(info->bus_info));
Florian Fainelli80105be2014-04-24 18:08:57 -0700315}
316
317static u32 bcm_sysport_get_msglvl(struct net_device *dev)
318{
319 struct bcm_sysport_priv *priv = netdev_priv(dev);
320
321 return priv->msg_enable;
322}
323
324static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
325{
326 struct bcm_sysport_priv *priv = netdev_priv(dev);
327
328 priv->msg_enable = enable;
329}
330
Florian Fainelli44a45242017-01-20 11:08:27 -0800331static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type)
332{
333 switch (type) {
334 case BCM_SYSPORT_STAT_NETDEV:
kiki good10377ba2017-08-04 00:07:45 +0100335 case BCM_SYSPORT_STAT_NETDEV64:
Florian Fainelli44a45242017-01-20 11:08:27 -0800336 case BCM_SYSPORT_STAT_RXCHK:
337 case BCM_SYSPORT_STAT_RBUF:
Florian Fainellib98deb22022-10-28 15:21:40 -0700338 case BCM_SYSPORT_STAT_RDMA:
Florian Fainelli44a45242017-01-20 11:08:27 -0800339 case BCM_SYSPORT_STAT_SOFT:
340 return true;
341 default:
342 return false;
343 }
344}
345
Florian Fainelli80105be2014-04-24 18:08:57 -0700346static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
347{
Florian Fainelli44a45242017-01-20 11:08:27 -0800348 struct bcm_sysport_priv *priv = netdev_priv(dev);
349 const struct bcm_sysport_stats *s;
350 unsigned int i, j;
351
Florian Fainelli80105be2014-04-24 18:08:57 -0700352 switch (string_set) {
353 case ETH_SS_STATS:
Florian Fainelli44a45242017-01-20 11:08:27 -0800354 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
355 s = &bcm_sysport_gstrings_stats[i];
356 if (priv->is_lite &&
357 !bcm_sysport_lite_stat_valid(s->type))
358 continue;
359 j++;
360 }
Florian Fainelli30defeb2017-03-23 10:36:46 -0700361 /* Include per-queue statistics */
362 return j + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
Florian Fainelli80105be2014-04-24 18:08:57 -0700363 default:
364 return -EOPNOTSUPP;
365 }
366}
367
368static void bcm_sysport_get_strings(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700369 u32 stringset, u8 *data)
Florian Fainelli80105be2014-04-24 18:08:57 -0700370{
Florian Fainelli44a45242017-01-20 11:08:27 -0800371 struct bcm_sysport_priv *priv = netdev_priv(dev);
372 const struct bcm_sysport_stats *s;
Florian Fainelli30defeb2017-03-23 10:36:46 -0700373 char buf[128];
Florian Fainelli44a45242017-01-20 11:08:27 -0800374 int i, j;
Florian Fainelli80105be2014-04-24 18:08:57 -0700375
376 switch (stringset) {
377 case ETH_SS_STATS:
Florian Fainelli44a45242017-01-20 11:08:27 -0800378 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
379 s = &bcm_sysport_gstrings_stats[i];
380 if (priv->is_lite &&
381 !bcm_sysport_lite_stat_valid(s->type))
382 continue;
383
384 memcpy(data + j * ETH_GSTRING_LEN, s->stat_string,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700385 ETH_GSTRING_LEN);
Florian Fainelli44a45242017-01-20 11:08:27 -0800386 j++;
Florian Fainelli80105be2014-04-24 18:08:57 -0700387 }
Florian Fainelli30defeb2017-03-23 10:36:46 -0700388
389 for (i = 0; i < dev->num_tx_queues; i++) {
390 snprintf(buf, sizeof(buf), "txq%d_packets", i);
391 memcpy(data + j * ETH_GSTRING_LEN, buf,
392 ETH_GSTRING_LEN);
393 j++;
394
395 snprintf(buf, sizeof(buf), "txq%d_bytes", i);
396 memcpy(data + j * ETH_GSTRING_LEN, buf,
397 ETH_GSTRING_LEN);
398 j++;
399 }
Florian Fainelli80105be2014-04-24 18:08:57 -0700400 break;
401 default:
402 break;
403 }
404}
405
406static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
407{
408 int i, j = 0;
409
410 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
411 const struct bcm_sysport_stats *s;
412 u8 offset = 0;
413 u32 val = 0;
414 char *p;
415
416 s = &bcm_sysport_gstrings_stats[i];
417 switch (s->type) {
418 case BCM_SYSPORT_STAT_NETDEV:
kiki good10377ba2017-08-04 00:07:45 +0100419 case BCM_SYSPORT_STAT_NETDEV64:
Florian Fainelli55ff4ea2015-02-28 18:09:17 -0800420 case BCM_SYSPORT_STAT_SOFT:
Florian Fainelli80105be2014-04-24 18:08:57 -0700421 continue;
422 case BCM_SYSPORT_STAT_MIB_RX:
423 case BCM_SYSPORT_STAT_MIB_TX:
424 case BCM_SYSPORT_STAT_RUNT:
Florian Fainelli44a45242017-01-20 11:08:27 -0800425 if (priv->is_lite)
426 continue;
427
Florian Fainelli80105be2014-04-24 18:08:57 -0700428 if (s->type != BCM_SYSPORT_STAT_MIB_RX)
429 offset = UMAC_MIB_STAT_OFFSET;
430 val = umac_readl(priv, UMAC_MIB_START + j + offset);
431 break;
432 case BCM_SYSPORT_STAT_RXCHK:
433 val = rxchk_readl(priv, s->reg_offset);
434 if (val == ~0)
435 rxchk_writel(priv, 0, s->reg_offset);
436 break;
437 case BCM_SYSPORT_STAT_RBUF:
438 val = rbuf_readl(priv, s->reg_offset);
439 if (val == ~0)
440 rbuf_writel(priv, 0, s->reg_offset);
441 break;
Florian Fainellib98deb22022-10-28 15:21:40 -0700442 case BCM_SYSPORT_STAT_RDMA:
443 if (!priv->is_lite)
444 continue;
445
446 val = rdma_readl(priv, s->reg_offset);
447 if (val == ~0)
448 rdma_writel(priv, 0, s->reg_offset);
449 break;
Florian Fainelli80105be2014-04-24 18:08:57 -0700450 }
451
452 j += s->stat_sizeof;
453 p = (char *)priv + s->stat_offset;
454 *(u32 *)p = val;
455 }
456
457 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
458}
459
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700460static void bcm_sysport_update_tx_stats(struct bcm_sysport_priv *priv,
461 u64 *tx_bytes, u64 *tx_packets)
462{
463 struct bcm_sysport_tx_ring *ring;
464 u64 bytes = 0, packets = 0;
465 unsigned int start;
466 unsigned int q;
467
468 for (q = 0; q < priv->netdev->num_tx_queues; q++) {
469 ring = &priv->tx_rings[q];
470 do {
Thomas Gleixner068c38a2022-10-26 15:22:14 +0200471 start = u64_stats_fetch_begin(&priv->syncp);
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700472 bytes = ring->bytes;
473 packets = ring->packets;
Thomas Gleixner068c38a2022-10-26 15:22:14 +0200474 } while (u64_stats_fetch_retry(&priv->syncp, start));
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700475
476 *tx_bytes += bytes;
477 *tx_packets += packets;
478 }
479}
480
Florian Fainelli80105be2014-04-24 18:08:57 -0700481static void bcm_sysport_get_stats(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700482 struct ethtool_stats *stats, u64 *data)
Florian Fainelli80105be2014-04-24 18:08:57 -0700483{
484 struct bcm_sysport_priv *priv = netdev_priv(dev);
kiki good10377ba2017-08-04 00:07:45 +0100485 struct bcm_sysport_stats64 *stats64 = &priv->stats64;
486 struct u64_stats_sync *syncp = &priv->syncp;
Florian Fainelli30defeb2017-03-23 10:36:46 -0700487 struct bcm_sysport_tx_ring *ring;
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700488 u64 tx_bytes = 0, tx_packets = 0;
kiki good10377ba2017-08-04 00:07:45 +0100489 unsigned int start;
Florian Fainelli44a45242017-01-20 11:08:27 -0800490 int i, j;
Florian Fainelli80105be2014-04-24 18:08:57 -0700491
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700492 if (netif_running(dev)) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700493 bcm_sysport_update_mib_counters(priv);
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700494 bcm_sysport_update_tx_stats(priv, &tx_bytes, &tx_packets);
495 stats64->tx_bytes = tx_bytes;
496 stats64->tx_packets = tx_packets;
497 }
Florian Fainelli80105be2014-04-24 18:08:57 -0700498
Florian Fainelli44a45242017-01-20 11:08:27 -0800499 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700500 const struct bcm_sysport_stats *s;
501 char *p;
502
503 s = &bcm_sysport_gstrings_stats[i];
504 if (s->type == BCM_SYSPORT_STAT_NETDEV)
505 p = (char *)&dev->stats;
kiki good10377ba2017-08-04 00:07:45 +0100506 else if (s->type == BCM_SYSPORT_STAT_NETDEV64)
507 p = (char *)stats64;
Florian Fainelli80105be2014-04-24 18:08:57 -0700508 else
509 p = (char *)priv;
kiki good10377ba2017-08-04 00:07:45 +0100510
Florian Fainelli50ddfba2017-08-08 14:45:09 -0700511 if (priv->is_lite && !bcm_sysport_lite_stat_valid(s->type))
512 continue;
Florian Fainelli80105be2014-04-24 18:08:57 -0700513 p += s->stat_offset;
kiki good10377ba2017-08-04 00:07:45 +0100514
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700515 if (s->stat_sizeof == sizeof(u64) &&
516 s->type == BCM_SYSPORT_STAT_NETDEV64) {
kiki good10377ba2017-08-04 00:07:45 +0100517 do {
Thomas Gleixner068c38a2022-10-26 15:22:14 +0200518 start = u64_stats_fetch_begin(syncp);
kiki good10377ba2017-08-04 00:07:45 +0100519 data[i] = *(u64 *)p;
Thomas Gleixner068c38a2022-10-26 15:22:14 +0200520 } while (u64_stats_fetch_retry(syncp, start));
Florian Fainelli8ecb1a22017-09-18 16:31:30 -0700521 } else
kiki good10377ba2017-08-04 00:07:45 +0100522 data[i] = *(u32 *)p;
Florian Fainelli44a45242017-01-20 11:08:27 -0800523 j++;
Florian Fainelli80105be2014-04-24 18:08:57 -0700524 }
Florian Fainelli30defeb2017-03-23 10:36:46 -0700525
526 /* For SYSTEMPORT Lite since we have holes in our statistics, j would
527 * be equal to BCM_SYSPORT_STATS_LEN at the end of the loop, but it
528 * needs to point to how many total statistics we have minus the
529 * number of per TX queue statistics
530 */
531 j = bcm_sysport_get_sset_count(dev, ETH_SS_STATS) -
532 dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
533
534 for (i = 0; i < dev->num_tx_queues; i++) {
535 ring = &priv->tx_rings[i];
536 data[j] = ring->packets;
537 j++;
538 data[j] = ring->bytes;
539 j++;
540 }
Florian Fainelli80105be2014-04-24 18:08:57 -0700541}
542
Florian Fainelli83e82f42014-07-01 21:08:40 -0700543static void bcm_sysport_get_wol(struct net_device *dev,
544 struct ethtool_wolinfo *wol)
545{
546 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainelli83e82f42014-07-01 21:08:40 -0700547
Florian Fainellibb9051a22018-08-07 10:50:23 -0700548 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
Florian Fainelli83e82f42014-07-01 21:08:40 -0700549 wol->wolopts = priv->wolopts;
550
551 if (!(priv->wolopts & WAKE_MAGICSECURE))
552 return;
553
Florian Fainelli8dfb8d22019-02-01 13:23:38 -0800554 memcpy(wol->sopass, priv->sopass, sizeof(priv->sopass));
Florian Fainelli83e82f42014-07-01 21:08:40 -0700555}
556
557static int bcm_sysport_set_wol(struct net_device *dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700558 struct ethtool_wolinfo *wol)
Florian Fainelli83e82f42014-07-01 21:08:40 -0700559{
560 struct bcm_sysport_priv *priv = netdev_priv(dev);
561 struct device *kdev = &priv->pdev->dev;
Florian Fainellibb9051a22018-08-07 10:50:23 -0700562 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
Florian Fainelli83e82f42014-07-01 21:08:40 -0700563
564 if (!device_can_wakeup(kdev))
565 return -ENOTSUPP;
566
567 if (wol->wolopts & ~supported)
568 return -EINVAL;
569
Florian Fainelli8dfb8d22019-02-01 13:23:38 -0800570 if (wol->wolopts & WAKE_MAGICSECURE)
571 memcpy(priv->sopass, wol->sopass, sizeof(priv->sopass));
Florian Fainelli83e82f42014-07-01 21:08:40 -0700572
573 /* Flag the device and relevant IRQ as wakeup capable */
574 if (wol->wolopts) {
575 device_set_wakeup_enable(kdev, 1);
Florian Fainelli61b423a2014-10-10 10:51:54 -0700576 if (priv->wol_irq_disabled)
577 enable_irq_wake(priv->wol_irq);
Florian Fainelli83e82f42014-07-01 21:08:40 -0700578 priv->wol_irq_disabled = 0;
579 } else {
580 device_set_wakeup_enable(kdev, 0);
581 /* Avoid unbalanced disable_irq_wake calls */
582 if (!priv->wol_irq_disabled)
583 disable_irq_wake(priv->wol_irq);
584 priv->wol_irq_disabled = 1;
585 }
586
587 priv->wolopts = wol->wolopts;
588
589 return 0;
590}
591
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700592static void bcm_sysport_set_rx_coalesce(struct bcm_sysport_priv *priv,
593 u32 usecs, u32 pkts)
Florian Fainellib6e0e872018-03-22 18:19:32 -0700594{
595 u32 reg;
596
597 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
598 reg &= ~(RDMA_INTR_THRESH_MASK |
599 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700600 reg |= pkts;
601 reg |= DIV_ROUND_UP(usecs * 1000, 8192) << RDMA_TIMEOUT_SHIFT;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700602 rdma_writel(priv, reg, RDMA_MBDONE_INTR);
603}
604
Florian Fainellifd41f2b2018-03-28 15:15:36 -0700605static void bcm_sysport_set_tx_coalesce(struct bcm_sysport_tx_ring *ring,
606 struct ethtool_coalesce *ec)
Florian Fainellib6e0e872018-03-22 18:19:32 -0700607{
608 struct bcm_sysport_priv *priv = ring->priv;
609 u32 reg;
610
611 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(ring->index));
612 reg &= ~(RING_INTR_THRESH_MASK |
613 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
Florian Fainellifd41f2b2018-03-28 15:15:36 -0700614 reg |= ec->tx_max_coalesced_frames;
615 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
Florian Fainellib6e0e872018-03-22 18:19:32 -0700616 RING_TIMEOUT_SHIFT;
617 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(ring->index));
618}
619
Florian Fainellib1a15e82015-05-11 15:12:41 -0700620static int bcm_sysport_get_coalesce(struct net_device *dev,
Yufeng Mof3ccfda12021-08-20 15:35:18 +0800621 struct ethtool_coalesce *ec,
622 struct kernel_ethtool_coalesce *kernel_coal,
623 struct netlink_ext_ack *extack)
Florian Fainellib1a15e82015-05-11 15:12:41 -0700624{
625 struct bcm_sysport_priv *priv = netdev_priv(dev);
626 u32 reg;
627
628 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
629
630 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
631 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
632
Florian Fainellid0634862015-05-11 15:12:42 -0700633 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
634
635 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
636 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700637 ec->use_adaptive_rx_coalesce = priv->dim.use_dim;
Florian Fainellid0634862015-05-11 15:12:42 -0700638
Florian Fainellib1a15e82015-05-11 15:12:41 -0700639 return 0;
640}
641
642static int bcm_sysport_set_coalesce(struct net_device *dev,
Yufeng Mof3ccfda12021-08-20 15:35:18 +0800643 struct ethtool_coalesce *ec,
644 struct kernel_ethtool_coalesce *kernel_coal,
645 struct netlink_ext_ack *extack)
Florian Fainellib1a15e82015-05-11 15:12:41 -0700646{
647 struct bcm_sysport_priv *priv = netdev_priv(dev);
Tal Gilboa8960b382019-01-31 16:44:48 +0200648 struct dim_cq_moder moder;
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700649 u32 usecs, pkts;
Florian Fainellib1a15e82015-05-11 15:12:41 -0700650 unsigned int i;
Florian Fainellib1a15e82015-05-11 15:12:41 -0700651
Florian Fainellid0634862015-05-11 15:12:42 -0700652 /* Base system clock is 125Mhz, DMA timeout is this reference clock
653 * divided by 1024, which yield roughly 8.192 us, our maximum value has
654 * to fit in the RING_TIMEOUT_MASK (16 bits).
Florian Fainellib1a15e82015-05-11 15:12:41 -0700655 */
656 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
Florian Fainellid0634862015-05-11 15:12:42 -0700657 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
658 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
659 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
Florian Fainellib1a15e82015-05-11 15:12:41 -0700660 return -EINVAL;
661
Florian Fainellid0634862015-05-11 15:12:42 -0700662 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
Jakub Kicinskif4a76615f2020-03-09 19:15:00 -0700663 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0))
Florian Fainellib1a15e82015-05-11 15:12:41 -0700664 return -EINVAL;
665
Florian Fainellifd41f2b2018-03-28 15:15:36 -0700666 for (i = 0; i < dev->num_tx_queues; i++)
667 bcm_sysport_set_tx_coalesce(&priv->tx_rings[i], ec);
Florian Fainellib1a15e82015-05-11 15:12:41 -0700668
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700669 priv->rx_coalesce_usecs = ec->rx_coalesce_usecs;
670 priv->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
671 usecs = priv->rx_coalesce_usecs;
672 pkts = priv->rx_max_coalesced_frames;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700673
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700674 if (ec->use_adaptive_rx_coalesce && !priv->dim.use_dim) {
Tal Gilboa026a8072018-04-24 13:36:01 +0300675 moder = net_dim_get_def_rx_moderation(priv->dim.dim.mode);
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700676 usecs = moder.usec;
677 pkts = moder.pkts;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700678 }
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700679
Florian Fainellib6e0e872018-03-22 18:19:32 -0700680 priv->dim.use_dim = ec->use_adaptive_rx_coalesce;
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -0700681
682 /* Apply desired coalescing parameters */
683 bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
Florian Fainellid0634862015-05-11 15:12:42 -0700684
Florian Fainellib1a15e82015-05-11 15:12:41 -0700685 return 0;
686}
687
Florian Fainelli80105be2014-04-24 18:08:57 -0700688static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
689{
Florian Fainellic45182e2017-08-24 15:20:41 -0700690 dev_consume_skb_any(cb->skb);
Florian Fainelli80105be2014-04-24 18:08:57 -0700691 cb->skb = NULL;
692 dma_unmap_addr_set(cb, dma_addr, 0);
693}
694
Florian Fainellic73b0182015-05-28 15:24:43 -0700695static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
696 struct bcm_sysport_cb *cb)
Florian Fainelli80105be2014-04-24 18:08:57 -0700697{
698 struct device *kdev = &priv->pdev->dev;
699 struct net_device *ndev = priv->netdev;
Florian Fainellic73b0182015-05-28 15:24:43 -0700700 struct sk_buff *skb, *rx_skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700701 dma_addr_t mapping;
Florian Fainelli80105be2014-04-24 18:08:57 -0700702
Florian Fainellic73b0182015-05-28 15:24:43 -0700703 /* Allocate a new SKB for a new packet */
Doug Berger3554e542020-04-23 16:13:30 -0700704 skb = __netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH,
705 GFP_ATOMIC | __GFP_NOWARN);
Florian Fainellic73b0182015-05-28 15:24:43 -0700706 if (!skb) {
707 priv->mib.alloc_rx_buff_failed++;
Florian Fainelli80105be2014-04-24 18:08:57 -0700708 netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
Florian Fainellic73b0182015-05-28 15:24:43 -0700709 return NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -0700710 }
711
Florian Fainellic73b0182015-05-28 15:24:43 -0700712 mapping = dma_map_single(kdev, skb->data,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700713 RX_BUF_LENGTH, DMA_FROM_DEVICE);
Florian Fainellic73b0182015-05-28 15:24:43 -0700714 if (dma_mapping_error(kdev, mapping)) {
Florian Fainelli60b4ea12014-11-19 10:29:55 -0800715 priv->mib.rx_dma_failed++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700716 dev_kfree_skb_any(skb);
Florian Fainelli80105be2014-04-24 18:08:57 -0700717 netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
Florian Fainellic73b0182015-05-28 15:24:43 -0700718 return NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -0700719 }
720
Florian Fainellic73b0182015-05-28 15:24:43 -0700721 /* Grab the current SKB on the ring */
722 rx_skb = cb->skb;
723 if (likely(rx_skb))
724 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
725 RX_BUF_LENGTH, DMA_FROM_DEVICE);
726
727 /* Put the new SKB on the ring */
728 cb->skb = skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700729 dma_unmap_addr_set(cb, dma_addr, mapping);
Florian Fainellibaf387a2015-05-28 15:24:42 -0700730 dma_desc_set_addr(priv, cb->bd_addr, mapping);
Florian Fainelli80105be2014-04-24 18:08:57 -0700731
732 netif_dbg(priv, rx_status, ndev, "RX refill\n");
733
Florian Fainellic73b0182015-05-28 15:24:43 -0700734 /* Return the current SKB to the caller */
735 return rx_skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700736}
737
738static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
739{
740 struct bcm_sysport_cb *cb;
Florian Fainellic73b0182015-05-28 15:24:43 -0700741 struct sk_buff *skb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700742 unsigned int i;
743
744 for (i = 0; i < priv->num_rx_bds; i++) {
Florian Fainellibaf387a2015-05-28 15:24:42 -0700745 cb = &priv->rx_cbs[i];
Florian Fainellic73b0182015-05-28 15:24:43 -0700746 skb = bcm_sysport_rx_refill(priv, cb);
Markus Elfring399e06a2019-08-22 20:02:56 +0200747 dev_kfree_skb(skb);
Florian Fainellic73b0182015-05-28 15:24:43 -0700748 if (!cb->skb)
749 return -ENOMEM;
Florian Fainelli80105be2014-04-24 18:08:57 -0700750 }
751
Florian Fainellic73b0182015-05-28 15:24:43 -0700752 return 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700753}
754
755/* Poll the hardware for up to budget packets to process */
756static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
757 unsigned int budget)
758{
kiki good10377ba2017-08-04 00:07:45 +0100759 struct bcm_sysport_stats64 *stats64 = &priv->stats64;
Florian Fainelli80105be2014-04-24 18:08:57 -0700760 struct net_device *ndev = priv->netdev;
761 unsigned int processed = 0, to_process;
Florian Fainellib6e0e872018-03-22 18:19:32 -0700762 unsigned int processed_bytes = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700763 struct bcm_sysport_cb *cb;
764 struct sk_buff *skb;
765 unsigned int p_index;
766 u16 len, status;
Paul Gortmaker3afc5572014-05-30 15:39:30 -0400767 struct bcm_rsb *rsb;
Florian Fainelli80105be2014-04-24 18:08:57 -0700768
Florian Fainelli6baa785a2017-03-23 10:36:47 -0700769 /* Clear status before servicing to reduce spurious interrupts */
770 intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR);
771
Florian Fainelli44a45242017-01-20 11:08:27 -0800772 /* Determine how much we should process since last call, SYSTEMPORT Lite
773 * groups the producer and consumer indexes into the same 32-bit
774 * which we access using RDMA_CONS_INDEX
775 */
776 if (!priv->is_lite)
777 p_index = rdma_readl(priv, RDMA_PROD_INDEX);
778 else
779 p_index = rdma_readl(priv, RDMA_CONS_INDEX);
Florian Fainelli80105be2014-04-24 18:08:57 -0700780 p_index &= RDMA_PROD_INDEX_MASK;
781
Florian Fainellie9d7af72017-03-23 10:36:48 -0700782 to_process = (p_index - priv->rx_c_index) & RDMA_CONS_INDEX_MASK;
Florian Fainelli80105be2014-04-24 18:08:57 -0700783
784 netif_dbg(priv, rx_status, ndev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700785 "p_index=%d rx_c_index=%d to_process=%d\n",
786 p_index, priv->rx_c_index, to_process);
Florian Fainelli80105be2014-04-24 18:08:57 -0700787
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700788 while ((processed < to_process) && (processed < budget)) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700789 cb = &priv->rx_cbs[priv->rx_read_ptr];
Florian Fainellic73b0182015-05-28 15:24:43 -0700790 skb = bcm_sysport_rx_refill(priv, cb);
Florian Fainellife24ba02014-09-08 11:37:51 -0700791
Florian Fainellife24ba02014-09-08 11:37:51 -0700792
793 /* We do not have a backing SKB, so we do not a corresponding
794 * DMA mapping for this incoming packet since
795 * bcm_sysport_rx_refill always either has both skb and mapping
796 * or none.
797 */
798 if (unlikely(!skb)) {
799 netif_err(priv, rx_err, ndev, "out of memory!\n");
800 ndev->stats.rx_dropped++;
801 ndev->stats.rx_errors++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700802 goto next;
Florian Fainellife24ba02014-09-08 11:37:51 -0700803 }
804
Florian Fainelli80105be2014-04-24 18:08:57 -0700805 /* Extract the Receive Status Block prepended */
Paul Gortmaker3afc5572014-05-30 15:39:30 -0400806 rsb = (struct bcm_rsb *)skb->data;
Florian Fainelli80105be2014-04-24 18:08:57 -0700807 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
808 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700809 DESC_STATUS_MASK;
Florian Fainelli80105be2014-04-24 18:08:57 -0700810
Florian Fainelli80105be2014-04-24 18:08:57 -0700811 netif_dbg(priv, rx_status, ndev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700812 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
813 p_index, priv->rx_c_index, priv->rx_read_ptr,
814 len, status);
Florian Fainelli80105be2014-04-24 18:08:57 -0700815
Florian Fainelli25977ac2015-05-28 15:24:44 -0700816 if (unlikely(len > RX_BUF_LENGTH)) {
817 netif_err(priv, rx_status, ndev, "oversized packet\n");
818 ndev->stats.rx_length_errors++;
819 ndev->stats.rx_errors++;
820 dev_kfree_skb_any(skb);
821 goto next;
822 }
823
Florian Fainelli80105be2014-04-24 18:08:57 -0700824 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
825 netif_err(priv, rx_status, ndev, "fragmented packet!\n");
826 ndev->stats.rx_dropped++;
827 ndev->stats.rx_errors++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700828 dev_kfree_skb_any(skb);
829 goto next;
Florian Fainelli80105be2014-04-24 18:08:57 -0700830 }
831
832 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
833 netif_err(priv, rx_err, ndev, "error packet\n");
Florian Fainelliad51c612014-06-05 10:22:16 -0700834 if (status & RX_STATUS_OVFLOW)
Florian Fainelli80105be2014-04-24 18:08:57 -0700835 ndev->stats.rx_over_errors++;
836 ndev->stats.rx_dropped++;
837 ndev->stats.rx_errors++;
Florian Fainellic73b0182015-05-28 15:24:43 -0700838 dev_kfree_skb_any(skb);
839 goto next;
Florian Fainelli80105be2014-04-24 18:08:57 -0700840 }
841
842 skb_put(skb, len);
843
844 /* Hardware validated our checksum */
845 if (likely(status & DESC_L4_CSUM))
846 skb->ip_summed = CHECKSUM_UNNECESSARY;
847
Florian Fainellie0ea05d2014-06-05 10:22:17 -0700848 /* Hardware pre-pends packets with 2bytes before Ethernet
849 * header plus we have the Receive Status Block, strip off all
850 * of this from the SKB.
Florian Fainelli80105be2014-04-24 18:08:57 -0700851 */
852 skb_pull(skb, sizeof(*rsb) + 2);
853 len -= (sizeof(*rsb) + 2);
Florian Fainellib6e0e872018-03-22 18:19:32 -0700854 processed_bytes += len;
Florian Fainelli80105be2014-04-24 18:08:57 -0700855
856 /* UniMAC may forward CRC */
857 if (priv->crc_fwd) {
858 skb_trim(skb, len - ETH_FCS_LEN);
859 len -= ETH_FCS_LEN;
860 }
861
862 skb->protocol = eth_type_trans(skb, ndev);
863 ndev->stats.rx_packets++;
864 ndev->stats.rx_bytes += len;
kiki good10377ba2017-08-04 00:07:45 +0100865 u64_stats_update_begin(&priv->syncp);
866 stats64->rx_packets++;
867 stats64->rx_bytes += len;
868 u64_stats_update_end(&priv->syncp);
Florian Fainelli80105be2014-04-24 18:08:57 -0700869
870 napi_gro_receive(&priv->napi, skb);
Florian Fainellic73b0182015-05-28 15:24:43 -0700871next:
872 processed++;
873 priv->rx_read_ptr++;
874
875 if (priv->rx_read_ptr == priv->num_rx_bds)
876 priv->rx_read_ptr = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700877 }
878
Florian Fainellib6e0e872018-03-22 18:19:32 -0700879 priv->dim.packets = processed;
880 priv->dim.bytes = processed_bytes;
881
Florian Fainelli80105be2014-04-24 18:08:57 -0700882 return processed;
883}
884
Florian Fainelli30defeb2017-03-23 10:36:46 -0700885static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring *ring,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700886 struct bcm_sysport_cb *cb,
887 unsigned int *bytes_compl,
888 unsigned int *pkts_compl)
Florian Fainelli80105be2014-04-24 18:08:57 -0700889{
Florian Fainelli30defeb2017-03-23 10:36:46 -0700890 struct bcm_sysport_priv *priv = ring->priv;
Florian Fainelli80105be2014-04-24 18:08:57 -0700891 struct device *kdev = &priv->pdev->dev;
Florian Fainelli80105be2014-04-24 18:08:57 -0700892
893 if (cb->skb) {
Florian Fainelli80105be2014-04-24 18:08:57 -0700894 *bytes_compl += cb->skb->len;
895 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700896 dma_unmap_len(cb, dma_len),
897 DMA_TO_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -0700898 (*pkts_compl)++;
899 bcm_sysport_free_cb(cb);
900 /* SKB fragment */
901 } else if (dma_unmap_addr(cb, dma_addr)) {
kiki good10377ba2017-08-04 00:07:45 +0100902 *bytes_compl += dma_unmap_len(cb, dma_len);
Florian Fainelli80105be2014-04-24 18:08:57 -0700903 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700904 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -0700905 dma_unmap_addr_set(cb, dma_addr, 0);
906 }
907}
908
909/* Reclaim queued SKBs for transmission completion, lockless version */
910static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
911 struct bcm_sysport_tx_ring *ring)
912{
Florian Fainelli80105be2014-04-24 18:08:57 -0700913 unsigned int pkts_compl = 0, bytes_compl = 0;
kiki good10377ba2017-08-04 00:07:45 +0100914 struct net_device *ndev = priv->netdev;
Florian Fainelli484d8022018-03-13 14:45:07 -0700915 unsigned int txbds_processed = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700916 struct bcm_sysport_cb *cb;
Florian Fainelli484d8022018-03-13 14:45:07 -0700917 unsigned int txbds_ready;
918 unsigned int c_index;
Florian Fainelli80105be2014-04-24 18:08:57 -0700919 u32 hw_ind;
920
Florian Fainelli6baa785a2017-03-23 10:36:47 -0700921 /* Clear status before servicing to reduce spurious interrupts */
922 if (!ring->priv->is_lite)
923 intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR);
924 else
925 intrl2_0_writel(ring->priv, BIT(ring->index +
926 INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR);
927
Florian Fainelli80105be2014-04-24 18:08:57 -0700928 /* Compute how many descriptors have been processed since last call */
929 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
930 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
Florian Fainelli484d8022018-03-13 14:45:07 -0700931 txbds_ready = (c_index - ring->c_index) & RING_CONS_INDEX_MASK;
Florian Fainelli80105be2014-04-24 18:08:57 -0700932
933 netif_dbg(priv, tx_done, ndev,
Florian Fainelli484d8022018-03-13 14:45:07 -0700934 "ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
935 ring->index, ring->c_index, c_index, txbds_ready);
Florian Fainelli80105be2014-04-24 18:08:57 -0700936
Florian Fainelli484d8022018-03-13 14:45:07 -0700937 while (txbds_processed < txbds_ready) {
938 cb = &ring->cbs[ring->clean_index];
Florian Fainelli30defeb2017-03-23 10:36:46 -0700939 bcm_sysport_tx_reclaim_one(ring, cb, &bytes_compl, &pkts_compl);
Florian Fainelli80105be2014-04-24 18:08:57 -0700940
941 ring->desc_count++;
Florian Fainelli484d8022018-03-13 14:45:07 -0700942 txbds_processed++;
943
944 if (likely(ring->clean_index < ring->size - 1))
945 ring->clean_index++;
946 else
947 ring->clean_index = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -0700948 }
949
kiki good10377ba2017-08-04 00:07:45 +0100950 u64_stats_update_begin(&priv->syncp);
951 ring->packets += pkts_compl;
952 ring->bytes += bytes_compl;
953 u64_stats_update_end(&priv->syncp);
954
Florian Fainelli80105be2014-04-24 18:08:57 -0700955 ring->c_index = c_index;
956
Florian Fainelli80105be2014-04-24 18:08:57 -0700957 netif_dbg(priv, tx_done, ndev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -0700958 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
959 ring->index, ring->c_index, pkts_compl, bytes_compl);
Florian Fainelli80105be2014-04-24 18:08:57 -0700960
961 return pkts_compl;
962}
963
964/* Locked version of the per-ring TX reclaim routine */
965static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
966 struct bcm_sysport_tx_ring *ring)
967{
Florian Fainelli148d3d02017-01-12 12:09:09 -0800968 struct netdev_queue *txq;
Florian Fainelli80105be2014-04-24 18:08:57 -0700969 unsigned int released;
Florian Fainellid8498082014-06-05 10:22:15 -0700970 unsigned long flags;
Florian Fainelli80105be2014-04-24 18:08:57 -0700971
Florian Fainelli148d3d02017-01-12 12:09:09 -0800972 txq = netdev_get_tx_queue(priv->netdev, ring->index);
973
Florian Fainellid8498082014-06-05 10:22:15 -0700974 spin_lock_irqsave(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -0700975 released = __bcm_sysport_tx_reclaim(priv, ring);
Florian Fainelli148d3d02017-01-12 12:09:09 -0800976 if (released)
977 netif_tx_wake_queue(txq);
978
Florian Fainellid8498082014-06-05 10:22:15 -0700979 spin_unlock_irqrestore(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -0700980
981 return released;
982}
983
Florian Fainelli148d3d02017-01-12 12:09:09 -0800984/* Locked version of the per-ring TX reclaim, but does not wake the queue */
985static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv,
986 struct bcm_sysport_tx_ring *ring)
987{
988 unsigned long flags;
989
990 spin_lock_irqsave(&ring->lock, flags);
991 __bcm_sysport_tx_reclaim(priv, ring);
992 spin_unlock_irqrestore(&ring->lock, flags);
993}
994
Florian Fainelli80105be2014-04-24 18:08:57 -0700995static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
996{
997 struct bcm_sysport_tx_ring *ring =
998 container_of(napi, struct bcm_sysport_tx_ring, napi);
999 unsigned int work_done = 0;
1000
1001 work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
1002
Florian Fainelli16f62d92014-06-26 10:06:46 -07001003 if (work_done == 0) {
Florian Fainelli80105be2014-04-24 18:08:57 -07001004 napi_complete(napi);
1005 /* re-enable TX interrupt */
Florian Fainelli44a45242017-01-20 11:08:27 -08001006 if (!ring->priv->is_lite)
1007 intrl2_1_mask_clear(ring->priv, BIT(ring->index));
1008 else
1009 intrl2_0_mask_clear(ring->priv, BIT(ring->index +
1010 INTRL2_0_TDMA_MBDONE_SHIFT));
Florian Fainelli9dfa9a22014-11-12 15:40:43 -08001011
1012 return 0;
Florian Fainelli80105be2014-04-24 18:08:57 -07001013 }
1014
Florian Fainelli9dfa9a22014-11-12 15:40:43 -08001015 return budget;
Florian Fainelli80105be2014-04-24 18:08:57 -07001016}
1017
1018static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
1019{
1020 unsigned int q;
1021
1022 for (q = 0; q < priv->netdev->num_tx_queues; q++)
1023 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
1024}
1025
1026static int bcm_sysport_poll(struct napi_struct *napi, int budget)
1027{
1028 struct bcm_sysport_priv *priv =
1029 container_of(napi, struct bcm_sysport_priv, napi);
Yamin Friedmanf06d0ca2019-07-23 10:22:47 +03001030 struct dim_sample dim_sample = {};
Florian Fainelli80105be2014-04-24 18:08:57 -07001031 unsigned int work_done = 0;
1032
1033 work_done = bcm_sysport_desc_rx(priv, budget);
1034
1035 priv->rx_c_index += work_done;
1036 priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
Florian Fainelli44a45242017-01-20 11:08:27 -08001037
1038 /* SYSTEMPORT Lite groups the producer/consumer index, producer is
1039 * maintained by HW, but writes to it will be ignore while RDMA
1040 * is active
1041 */
1042 if (!priv->is_lite)
1043 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
1044 else
1045 rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX);
Florian Fainelli80105be2014-04-24 18:08:57 -07001046
1047 if (work_done < budget) {
Florian Fainellic82f47e2016-04-20 11:37:09 -07001048 napi_complete_done(napi, work_done);
Florian Fainelli80105be2014-04-24 18:08:57 -07001049 /* re-enable RX interrupts */
1050 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
1051 }
1052
Florian Fainellib6e0e872018-03-22 18:19:32 -07001053 if (priv->dim.use_dim) {
Tal Gilboa8960b382019-01-31 16:44:48 +02001054 dim_update_sample(priv->dim.event_ctr, priv->dim.packets,
1055 priv->dim.bytes, &dim_sample);
Florian Fainellib6e0e872018-03-22 18:19:32 -07001056 net_dim(&priv->dim.dim, dim_sample);
1057 }
1058
Florian Fainelli80105be2014-04-24 18:08:57 -07001059 return work_done;
1060}
1061
Florian Fainelli542261162018-08-03 11:08:44 -07001062static void mpd_enable_set(struct bcm_sysport_priv *priv, bool enable)
Florian Fainelli83e82f42014-07-01 21:08:40 -07001063{
Florian Fainellibb9051a22018-08-07 10:50:23 -07001064 u32 reg, bit;
Florian Fainelli83e82f42014-07-01 21:08:40 -07001065
Florian Fainelli542261162018-08-03 11:08:44 -07001066 reg = umac_readl(priv, UMAC_MPD_CTRL);
1067 if (enable)
1068 reg |= MPD_EN;
1069 else
1070 reg &= ~MPD_EN;
1071 umac_writel(priv, reg, UMAC_MPD_CTRL);
Florian Fainellibb9051a22018-08-07 10:50:23 -07001072
1073 if (priv->is_lite)
1074 bit = RBUF_ACPI_EN_LITE;
1075 else
1076 bit = RBUF_ACPI_EN;
1077
1078 reg = rbuf_readl(priv, RBUF_CONTROL);
1079 if (enable)
1080 reg |= bit;
1081 else
1082 reg &= ~bit;
1083 rbuf_writel(priv, reg, RBUF_CONTROL);
Florian Fainelli542261162018-08-03 11:08:44 -07001084}
1085
1086static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
1087{
Florian Fainelli80f8dea2018-11-06 12:58:41 -08001088 unsigned int index;
Florian Fainellibb9051a22018-08-07 10:50:23 -07001089 u32 reg;
1090
Florian Fainellibb9051a22018-08-07 10:50:23 -07001091 /* Disable RXCHK, active filters and Broadcom tag matching */
1092 reg = rxchk_readl(priv, RXCHK_CONTROL);
1093 reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK <<
1094 RXCHK_BRCM_TAG_MATCH_SHIFT | RXCHK_EN | RXCHK_BRCM_TAG_EN);
1095 rxchk_writel(priv, reg, RXCHK_CONTROL);
Florian Fainelli83e82f42014-07-01 21:08:40 -07001096
Florian Fainelli80f8dea2018-11-06 12:58:41 -08001097 /* Make sure we restore correct CID index in case HW lost
1098 * its context during deep idle state
1099 */
1100 for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
1101 rxchk_writel(priv, priv->filters_loc[index] <<
1102 RXCHK_BRCM_TAG_CID_SHIFT, RXCHK_BRCM_TAG(index));
1103 rxchk_writel(priv, 0xff00ffff, RXCHK_BRCM_TAG_MASK(index));
1104 }
1105
Florian Fainelli83e82f42014-07-01 21:08:40 -07001106 /* Clear the MagicPacket detection logic */
Florian Fainelli542261162018-08-03 11:08:44 -07001107 mpd_enable_set(priv, false);
Florian Fainelli83e82f42014-07-01 21:08:40 -07001108
Florian Fainelli45ec3182018-10-02 16:52:03 -07001109 reg = intrl2_0_readl(priv, INTRL2_CPU_STATUS);
1110 if (reg & INTRL2_0_MPD)
1111 netdev_info(priv->netdev, "Wake-on-LAN (MPD) interrupt!\n");
1112
1113 if (reg & INTRL2_0_BRCM_MATCH_TAG) {
1114 reg = rxchk_readl(priv, RXCHK_BRCM_TAG_MATCH_STATUS) &
1115 RXCHK_BRCM_TAG_MATCH_MASK;
1116 netdev_info(priv->netdev,
1117 "Wake-on-LAN (filters 0x%02x) interrupt!\n", reg);
1118 }
1119
Florian Fainelli83e82f42014-07-01 21:08:40 -07001120 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
1121}
Florian Fainelli80105be2014-04-24 18:08:57 -07001122
Florian Fainellib6e0e872018-03-22 18:19:32 -07001123static void bcm_sysport_dim_work(struct work_struct *work)
1124{
Tal Gilboa8960b382019-01-31 16:44:48 +02001125 struct dim *dim = container_of(work, struct dim, work);
Florian Fainellib6e0e872018-03-22 18:19:32 -07001126 struct bcm_sysport_net_dim *ndim =
1127 container_of(dim, struct bcm_sysport_net_dim, dim);
1128 struct bcm_sysport_priv *priv =
1129 container_of(ndim, struct bcm_sysport_priv, dim);
Tal Gilboa8960b382019-01-31 16:44:48 +02001130 struct dim_cq_moder cur_profile = net_dim_get_rx_moderation(dim->mode,
1131 dim->profile_ix);
Florian Fainellib6e0e872018-03-22 18:19:32 -07001132
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07001133 bcm_sysport_set_rx_coalesce(priv, cur_profile.usec, cur_profile.pkts);
Tal Gilboac002bd52018-11-05 12:07:52 +02001134 dim->state = DIM_START_MEASURE;
Florian Fainellib6e0e872018-03-22 18:19:32 -07001135}
1136
Florian Fainelli80105be2014-04-24 18:08:57 -07001137/* RX and misc interrupt routine */
1138static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
1139{
1140 struct net_device *dev = dev_id;
1141 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainelli44a45242017-01-20 11:08:27 -08001142 struct bcm_sysport_tx_ring *txr;
1143 unsigned int ring, ring_bit;
Florian Fainelli80105be2014-04-24 18:08:57 -07001144
1145 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
1146 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1147 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1148
1149 if (unlikely(priv->irq0_stat == 0)) {
1150 netdev_warn(priv->netdev, "spurious RX interrupt\n");
1151 return IRQ_NONE;
1152 }
1153
1154 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
Florian Fainellib6e0e872018-03-22 18:19:32 -07001155 priv->dim.event_ctr++;
Florian Fainelli80105be2014-04-24 18:08:57 -07001156 if (likely(napi_schedule_prep(&priv->napi))) {
1157 /* disable RX interrupts */
1158 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
Florian Fainelliba909502016-04-20 11:37:08 -07001159 __napi_schedule_irqoff(&priv->napi);
Florian Fainelli80105be2014-04-24 18:08:57 -07001160 }
1161 }
1162
1163 /* TX ring is full, perform a full reclaim since we do not know
1164 * which one would trigger this interrupt
1165 */
1166 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
1167 bcm_sysport_tx_reclaim_all(priv);
1168
Florian Fainelli44a45242017-01-20 11:08:27 -08001169 if (!priv->is_lite)
1170 goto out;
1171
1172 for (ring = 0; ring < dev->num_tx_queues; ring++) {
1173 ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT);
1174 if (!(priv->irq0_stat & ring_bit))
1175 continue;
1176
1177 txr = &priv->tx_rings[ring];
1178
1179 if (likely(napi_schedule_prep(&txr->napi))) {
1180 intrl2_0_mask_set(priv, ring_bit);
1181 __napi_schedule(&txr->napi);
1182 }
1183 }
1184out:
Florian Fainelli80105be2014-04-24 18:08:57 -07001185 return IRQ_HANDLED;
1186}
1187
1188/* TX interrupt service routine */
1189static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
1190{
1191 struct net_device *dev = dev_id;
1192 struct bcm_sysport_priv *priv = netdev_priv(dev);
1193 struct bcm_sysport_tx_ring *txr;
1194 unsigned int ring;
1195
1196 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
1197 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
1198 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1199
1200 if (unlikely(priv->irq1_stat == 0)) {
1201 netdev_warn(priv->netdev, "spurious TX interrupt\n");
1202 return IRQ_NONE;
1203 }
1204
1205 for (ring = 0; ring < dev->num_tx_queues; ring++) {
1206 if (!(priv->irq1_stat & BIT(ring)))
1207 continue;
1208
1209 txr = &priv->tx_rings[ring];
1210
1211 if (likely(napi_schedule_prep(&txr->napi))) {
1212 intrl2_1_mask_set(priv, BIT(ring));
Florian Fainelliba909502016-04-20 11:37:08 -07001213 __napi_schedule_irqoff(&txr->napi);
Florian Fainelli80105be2014-04-24 18:08:57 -07001214 }
1215 }
1216
1217 return IRQ_HANDLED;
1218}
1219
Florian Fainelli83e82f42014-07-01 21:08:40 -07001220static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
1221{
1222 struct bcm_sysport_priv *priv = dev_id;
1223
1224 pm_wakeup_event(&priv->pdev->dev, 0);
1225
1226 return IRQ_HANDLED;
1227}
1228
Florian Fainelli6cec4f52015-07-31 11:42:55 -07001229#ifdef CONFIG_NET_POLL_CONTROLLER
1230static void bcm_sysport_poll_controller(struct net_device *dev)
1231{
1232 struct bcm_sysport_priv *priv = netdev_priv(dev);
1233
1234 disable_irq(priv->irq0);
1235 bcm_sysport_rx_isr(priv->irq0, priv);
1236 enable_irq(priv->irq0);
1237
Florian Fainelli44a45242017-01-20 11:08:27 -08001238 if (!priv->is_lite) {
1239 disable_irq(priv->irq1);
1240 bcm_sysport_tx_isr(priv->irq1, priv);
1241 enable_irq(priv->irq1);
1242 }
Florian Fainelli6cec4f52015-07-31 11:42:55 -07001243}
1244#endif
1245
Florian Fainellie87474a2014-10-02 09:43:16 -07001246static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
1247 struct net_device *dev)
Florian Fainelli80105be2014-04-24 18:08:57 -07001248{
Florian Fainellia5d78ce2018-09-27 15:36:14 -07001249 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07001250 struct sk_buff *nskb;
Paul Gortmaker3afc5572014-05-30 15:39:30 -04001251 struct bcm_tsb *tsb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001252 u32 csum_info;
1253 u8 ip_proto;
1254 u16 csum_start;
Florian Fainellic0eb0552018-04-02 15:58:56 -07001255 __be16 ip_ver;
Florian Fainelli80105be2014-04-24 18:08:57 -07001256
1257 /* Re-allocate SKB if needed */
1258 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
1259 nskb = skb_realloc_headroom(skb, sizeof(*tsb));
Florian Fainelli80105be2014-04-24 18:08:57 -07001260 if (!nskb) {
Florian Fainelliaa6ca0e2018-09-27 15:36:13 -07001261 dev_kfree_skb_any(skb);
Florian Fainellia5d78ce2018-09-27 15:36:14 -07001262 priv->mib.tx_realloc_tsb_failed++;
Florian Fainelli80105be2014-04-24 18:08:57 -07001263 dev->stats.tx_errors++;
1264 dev->stats.tx_dropped++;
Florian Fainellie87474a2014-10-02 09:43:16 -07001265 return NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -07001266 }
Florian Fainelliaa6ca0e2018-09-27 15:36:13 -07001267 dev_consume_skb_any(skb);
Florian Fainelli80105be2014-04-24 18:08:57 -07001268 skb = nskb;
Florian Fainellia5d78ce2018-09-27 15:36:14 -07001269 priv->mib.tx_realloc_tsb++;
Florian Fainelli80105be2014-04-24 18:08:57 -07001270 }
1271
Johannes Bergd58ff352017-06-16 14:29:23 +02001272 tsb = skb_push(skb, sizeof(*tsb));
Florian Fainelli80105be2014-04-24 18:08:57 -07001273 /* Zero-out TSB by default */
1274 memset(tsb, 0, sizeof(*tsb));
1275
Florian Fainelli6e9fdb62020-07-06 14:29:39 -07001276 if (skb_vlan_tag_present(skb)) {
Colin Ian Kinge3cbdaf2020-07-08 19:37:23 +01001277 tsb->pcp_dei_vid = skb_vlan_tag_get_prio(skb) & PCP_DEI_MASK;
Florian Fainelli6e9fdb62020-07-06 14:29:39 -07001278 tsb->pcp_dei_vid |= (u32)skb_vlan_tag_get_id(skb) << VID_SHIFT;
1279 }
1280
Florian Fainelli80105be2014-04-24 18:08:57 -07001281 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Florian Fainellic0eb0552018-04-02 15:58:56 -07001282 ip_ver = skb->protocol;
Florian Fainelli80105be2014-04-24 18:08:57 -07001283 switch (ip_ver) {
Florian Fainellic0eb0552018-04-02 15:58:56 -07001284 case htons(ETH_P_IP):
Florian Fainelli80105be2014-04-24 18:08:57 -07001285 ip_proto = ip_hdr(skb)->protocol;
1286 break;
Florian Fainellic0eb0552018-04-02 15:58:56 -07001287 case htons(ETH_P_IPV6):
Florian Fainelli80105be2014-04-24 18:08:57 -07001288 ip_proto = ipv6_hdr(skb)->nexthdr;
1289 break;
1290 default:
Florian Fainellie87474a2014-10-02 09:43:16 -07001291 return skb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001292 }
1293
1294 /* Get the checksum offset and the L4 (transport) offset */
1295 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
Florian Fainelli6e9fdb62020-07-06 14:29:39 -07001296 /* Account for the HW inserted VLAN tag */
1297 if (skb_vlan_tag_present(skb))
1298 csum_start += VLAN_HLEN;
Florian Fainelli80105be2014-04-24 18:08:57 -07001299 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
1300 csum_info |= (csum_start << L4_PTR_SHIFT);
1301
1302 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1303 csum_info |= L4_LENGTH_VALID;
Florian Fainellic0eb0552018-04-02 15:58:56 -07001304 if (ip_proto == IPPROTO_UDP &&
1305 ip_ver == htons(ETH_P_IP))
Florian Fainelli80105be2014-04-24 18:08:57 -07001306 csum_info |= L4_UDP;
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001307 } else {
Florian Fainelli80105be2014-04-24 18:08:57 -07001308 csum_info = 0;
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001309 }
Florian Fainelli80105be2014-04-24 18:08:57 -07001310
1311 tsb->l4_ptr_dest_map = csum_info;
1312 }
1313
Florian Fainellie87474a2014-10-02 09:43:16 -07001314 return skb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001315}
1316
1317static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
1318 struct net_device *dev)
1319{
1320 struct bcm_sysport_priv *priv = netdev_priv(dev);
1321 struct device *kdev = &priv->pdev->dev;
1322 struct bcm_sysport_tx_ring *ring;
Florian Fainelli8b8e6e72021-12-15 12:24:49 -08001323 unsigned long flags, desc_flags;
Florian Fainelli80105be2014-04-24 18:08:57 -07001324 struct bcm_sysport_cb *cb;
1325 struct netdev_queue *txq;
Florian Fainelli7e6e1852019-04-22 09:46:44 -07001326 u32 len_status, addr_lo;
Florian Fainellidab531b2014-05-14 19:32:14 -07001327 unsigned int skb_len;
Florian Fainelli80105be2014-04-24 18:08:57 -07001328 dma_addr_t mapping;
Florian Fainelli80105be2014-04-24 18:08:57 -07001329 u16 queue;
1330 int ret;
1331
1332 queue = skb_get_queue_mapping(skb);
1333 txq = netdev_get_tx_queue(dev, queue);
1334 ring = &priv->tx_rings[queue];
1335
Florian Fainellid8498082014-06-05 10:22:15 -07001336 /* lock against tx reclaim in BH context and TX ring full interrupt */
1337 spin_lock_irqsave(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -07001338 if (unlikely(ring->desc_count == 0)) {
1339 netif_tx_stop_queue(txq);
1340 netdev_err(dev, "queue %d awake and ring full!\n", queue);
1341 ret = NETDEV_TX_BUSY;
1342 goto out;
1343 }
1344
Florian Fainelli38e5a852017-01-03 16:34:49 -08001345 /* Insert TSB and checksum infos */
1346 if (priv->tsb_en) {
1347 skb = bcm_sysport_insert_tsb(skb, dev);
1348 if (!skb) {
1349 ret = NETDEV_TX_OK;
1350 goto out;
1351 }
1352 }
1353
Florian Fainellibb7da332017-01-03 16:34:48 -08001354 skb_len = skb->len;
Florian Fainellidab531b2014-05-14 19:32:14 -07001355
1356 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -07001357 if (dma_mapping_error(kdev, mapping)) {
Florian Fainelli60b4ea12014-11-19 10:29:55 -08001358 priv->mib.tx_dma_failed++;
Florian Fainelli80105be2014-04-24 18:08:57 -07001359 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001360 skb->data, skb_len);
Florian Fainelli80105be2014-04-24 18:08:57 -07001361 ret = NETDEV_TX_OK;
1362 goto out;
1363 }
1364
1365 /* Remember the SKB for future freeing */
1366 cb = &ring->cbs[ring->curr_desc];
1367 cb->skb = skb;
1368 dma_unmap_addr_set(cb, dma_addr, mapping);
Florian Fainellidab531b2014-05-14 19:32:14 -07001369 dma_unmap_len_set(cb, dma_len, skb_len);
Florian Fainelli80105be2014-04-24 18:08:57 -07001370
Florian Fainelli7e6e1852019-04-22 09:46:44 -07001371 addr_lo = lower_32_bits(mapping);
Florian Fainelli80105be2014-04-24 18:08:57 -07001372 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
Florian Fainellidab531b2014-05-14 19:32:14 -07001373 len_status |= (skb_len << DESC_LEN_SHIFT);
Florian Fainelli80105be2014-04-24 18:08:57 -07001374 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001375 DESC_STATUS_SHIFT;
Florian Fainelli80105be2014-04-24 18:08:57 -07001376 if (skb->ip_summed == CHECKSUM_PARTIAL)
1377 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
Florian Fainelli6e9fdb62020-07-06 14:29:39 -07001378 if (skb_vlan_tag_present(skb))
1379 len_status |= (TX_STATUS_VLAN_VID_TSB << DESC_STATUS_SHIFT);
Florian Fainelli80105be2014-04-24 18:08:57 -07001380
1381 ring->curr_desc++;
1382 if (ring->curr_desc == ring->size)
1383 ring->curr_desc = 0;
1384 ring->desc_count--;
1385
Florian Fainelli7e6e1852019-04-22 09:46:44 -07001386 /* Ports are latched, so write upper address first */
Florian Fainelli8b8e6e72021-12-15 12:24:49 -08001387 spin_lock_irqsave(&priv->desc_lock, desc_flags);
Florian Fainelli7e6e1852019-04-22 09:46:44 -07001388 tdma_writel(priv, len_status, TDMA_WRITE_PORT_HI(ring->index));
1389 tdma_writel(priv, addr_lo, TDMA_WRITE_PORT_LO(ring->index));
Florian Fainelli8b8e6e72021-12-15 12:24:49 -08001390 spin_unlock_irqrestore(&priv->desc_lock, desc_flags);
Florian Fainelli80105be2014-04-24 18:08:57 -07001391
1392 /* Check ring space and update SW control flow */
1393 if (ring->desc_count == 0)
1394 netif_tx_stop_queue(txq);
1395
1396 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001397 ring->index, ring->desc_count, ring->curr_desc);
Florian Fainelli80105be2014-04-24 18:08:57 -07001398
1399 ret = NETDEV_TX_OK;
1400out:
Florian Fainellid8498082014-06-05 10:22:15 -07001401 spin_unlock_irqrestore(&ring->lock, flags);
Florian Fainelli80105be2014-04-24 18:08:57 -07001402 return ret;
1403}
1404
Michael S. Tsirkin0290bd22019-12-10 09:23:51 -05001405static void bcm_sysport_tx_timeout(struct net_device *dev, unsigned int txqueue)
Florian Fainelli80105be2014-04-24 18:08:57 -07001406{
1407 netdev_warn(dev, "transmit timeout!\n");
1408
Florian Westphal860e9532016-05-03 16:33:13 +02001409 netif_trans_update(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07001410 dev->stats.tx_errors++;
1411
1412 netif_tx_wake_all_queues(dev);
1413}
1414
1415/* phylib adjust link callback */
1416static void bcm_sysport_adj_link(struct net_device *dev)
1417{
1418 struct bcm_sysport_priv *priv = netdev_priv(dev);
Philippe Reynes715a0222016-06-19 20:39:08 +02001419 struct phy_device *phydev = dev->phydev;
Florian Fainelli80105be2014-04-24 18:08:57 -07001420 unsigned int changed = 0;
1421 u32 cmd_bits = 0, reg;
1422
1423 if (priv->old_link != phydev->link) {
1424 changed = 1;
1425 priv->old_link = phydev->link;
1426 }
1427
1428 if (priv->old_duplex != phydev->duplex) {
1429 changed = 1;
1430 priv->old_duplex = phydev->duplex;
1431 }
1432
Florian Fainelli44a45242017-01-20 11:08:27 -08001433 if (priv->is_lite)
1434 goto out;
1435
Florian Fainelli80105be2014-04-24 18:08:57 -07001436 switch (phydev->speed) {
1437 case SPEED_2500:
1438 cmd_bits = CMD_SPEED_2500;
1439 break;
1440 case SPEED_1000:
1441 cmd_bits = CMD_SPEED_1000;
1442 break;
1443 case SPEED_100:
1444 cmd_bits = CMD_SPEED_100;
1445 break;
1446 case SPEED_10:
1447 cmd_bits = CMD_SPEED_10;
1448 break;
1449 default:
1450 break;
1451 }
1452 cmd_bits <<= CMD_SPEED_SHIFT;
1453
1454 if (phydev->duplex == DUPLEX_HALF)
1455 cmd_bits |= CMD_HD_EN;
1456
1457 if (priv->old_pause != phydev->pause) {
1458 changed = 1;
1459 priv->old_pause = phydev->pause;
1460 }
1461
1462 if (!phydev->pause)
1463 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
1464
Florian Fainelli4a804c02014-09-02 11:17:07 -07001465 if (!changed)
1466 return;
1467
1468 if (phydev->link) {
Florian Fainellid5e32cc2014-05-14 19:32:13 -07001469 reg = umac_readl(priv, UMAC_CMD);
1470 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
Florian Fainelli80105be2014-04-24 18:08:57 -07001471 CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
1472 CMD_TX_PAUSE_IGNORE);
Florian Fainellid5e32cc2014-05-14 19:32:13 -07001473 reg |= cmd_bits;
1474 umac_writel(priv, reg, UMAC_CMD);
Florian Fainellid5e32cc2014-05-14 19:32:13 -07001475 }
Florian Fainelli44a45242017-01-20 11:08:27 -08001476out:
1477 if (changed)
1478 phy_print_status(phydev);
Florian Fainelli80105be2014-04-24 18:08:57 -07001479}
1480
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07001481static void bcm_sysport_init_dim(struct bcm_sysport_priv *priv,
Florian Fainellib6e0e872018-03-22 18:19:32 -07001482 void (*cb)(struct work_struct *work))
1483{
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07001484 struct bcm_sysport_net_dim *dim = &priv->dim;
1485
Florian Fainellib6e0e872018-03-22 18:19:32 -07001486 INIT_WORK(&dim->dim.work, cb);
Tal Gilboac002bd52018-11-05 12:07:52 +02001487 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
Florian Fainellib6e0e872018-03-22 18:19:32 -07001488 dim->event_ctr = 0;
1489 dim->packets = 0;
1490 dim->bytes = 0;
1491}
1492
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07001493static void bcm_sysport_init_rx_coalesce(struct bcm_sysport_priv *priv)
1494{
1495 struct bcm_sysport_net_dim *dim = &priv->dim;
Tal Gilboa8960b382019-01-31 16:44:48 +02001496 struct dim_cq_moder moder;
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07001497 u32 usecs, pkts;
1498
1499 usecs = priv->rx_coalesce_usecs;
1500 pkts = priv->rx_max_coalesced_frames;
1501
1502 /* If DIM was enabled, re-apply default parameters */
1503 if (dim->use_dim) {
Tal Gilboa026a8072018-04-24 13:36:01 +03001504 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07001505 usecs = moder.usec;
1506 pkts = moder.pkts;
1507 }
1508
1509 bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
1510}
1511
Florian Fainelli80105be2014-04-24 18:08:57 -07001512static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
1513 unsigned int index)
1514{
1515 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
Florian Fainelli80105be2014-04-24 18:08:57 -07001516 size_t size;
Florian Fainelli80105be2014-04-24 18:08:57 -07001517 u32 reg;
1518
1519 /* Simple descriptors partitioning for now */
1520 size = 256;
1521
Florian Fainelli40a8a312014-07-09 17:36:47 -07001522 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
Florian Fainelli80105be2014-04-24 18:08:57 -07001523 if (!ring->cbs) {
1524 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1525 return -ENOMEM;
1526 }
1527
1528 /* Initialize SW view of the ring */
1529 spin_lock_init(&ring->lock);
1530 ring->priv = priv;
Jakub Kicinski16d083e22022-05-04 09:37:24 -07001531 netif_napi_add_tx(priv->netdev, &ring->napi, bcm_sysport_tx_poll);
Florian Fainelli80105be2014-04-24 18:08:57 -07001532 ring->index = index;
1533 ring->size = size;
Florian Fainelli484d8022018-03-13 14:45:07 -07001534 ring->clean_index = 0;
Florian Fainelli80105be2014-04-24 18:08:57 -07001535 ring->alloc_size = ring->size;
Florian Fainelli80105be2014-04-24 18:08:57 -07001536 ring->desc_count = ring->size;
1537 ring->curr_desc = 0;
1538
1539 /* Initialize HW ring */
1540 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
1541 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
1542 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
1543 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
Florian Fainellid1565762017-10-11 10:57:50 -07001544
1545 /* Configure QID and port mapping */
1546 reg = tdma_readl(priv, TDMA_DESC_RING_MAPPING(index));
1547 reg &= ~(RING_QID_MASK | RING_PORT_ID_MASK << RING_PORT_ID_SHIFT);
Florian Fainelli3ded76a2017-11-01 11:29:47 -07001548 if (ring->inspect) {
1549 reg |= ring->switch_queue & RING_QID_MASK;
1550 reg |= ring->switch_port << RING_PORT_ID_SHIFT;
1551 } else {
1552 reg |= RING_IGNORE_STATUS;
1553 }
Florian Fainellid1565762017-10-11 10:57:50 -07001554 tdma_writel(priv, reg, TDMA_DESC_RING_MAPPING(index));
Florian Fainelli6e9fdb62020-07-06 14:29:39 -07001555 reg = 0;
1556 /* Adjust the packet size calculations if SYSTEMPORT is responsible
1557 * for HW insertion of VLAN tags
1558 */
1559 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)
1560 reg = VLAN_HLEN << RING_PKT_SIZE_ADJ_SHIFT;
1561 tdma_writel(priv, reg, TDMA_DESC_RING_PCP_DEI_VID(index));
Florian Fainelli80105be2014-04-24 18:08:57 -07001562
Florian Fainelli723934f2017-10-11 10:57:52 -07001563 /* Enable ACB algorithm 2 */
1564 reg = tdma_readl(priv, TDMA_CONTROL);
1565 reg |= tdma_control_bit(priv, ACB_ALGO);
1566 tdma_writel(priv, reg, TDMA_CONTROL);
1567
Florian Fainelli487234c2017-09-01 17:32:34 -07001568 /* Do not use tdma_control_bit() here because TSB_SWAP1 collides
1569 * with the original definition of ACB_ALGO
1570 */
1571 reg = tdma_readl(priv, TDMA_CONTROL);
1572 if (priv->is_lite)
1573 reg &= ~BIT(TSB_SWAP1);
1574 /* Set a correct TSB format based on host endian */
1575 if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
1576 reg |= tdma_control_bit(priv, TSB_SWAP0);
1577 else
1578 reg &= ~tdma_control_bit(priv, TSB_SWAP0);
1579 tdma_writel(priv, reg, TDMA_CONTROL);
1580
Florian Fainelli80105be2014-04-24 18:08:57 -07001581 /* Program the number of descriptors as MAX_THRESHOLD and half of
1582 * its size for the hysteresis trigger
1583 */
1584 tdma_writel(priv, ring->size |
1585 1 << RING_HYST_THRESH_SHIFT,
1586 TDMA_DESC_RING_MAX_HYST(index));
1587
1588 /* Enable the ring queue in the arbiter */
1589 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
1590 reg |= (1 << index);
1591 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
1592
1593 napi_enable(&ring->napi);
1594
1595 netif_dbg(priv, hw, priv->netdev,
Florian Fainelli7e6e1852019-04-22 09:46:44 -07001596 "TDMA cfg, size=%d, switch q=%d,port=%d\n",
1597 ring->size, ring->switch_queue,
Florian Fainellid1565762017-10-11 10:57:50 -07001598 ring->switch_port);
Florian Fainelli80105be2014-04-24 18:08:57 -07001599
1600 return 0;
1601}
1602
1603static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001604 unsigned int index)
Florian Fainelli80105be2014-04-24 18:08:57 -07001605{
1606 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
Florian Fainelli80105be2014-04-24 18:08:57 -07001607 u32 reg;
1608
1609 /* Caller should stop the TDMA engine */
1610 reg = tdma_readl(priv, TDMA_STATUS);
1611 if (!(reg & TDMA_DISABLED))
1612 netdev_warn(priv->netdev, "TDMA not stopped!\n");
1613
Florian Fainelli914adb52014-10-31 15:51:35 -07001614 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
1615 * fail, so by checking this pointer we know whether the TX ring was
1616 * fully initialized or not.
1617 */
1618 if (!ring->cbs)
1619 return;
1620
Florian Fainelli80105be2014-04-24 18:08:57 -07001621 napi_disable(&ring->napi);
1622 netif_napi_del(&ring->napi);
1623
Florian Fainelli148d3d02017-01-12 12:09:09 -08001624 bcm_sysport_tx_clean(priv, ring);
Florian Fainelli80105be2014-04-24 18:08:57 -07001625
1626 kfree(ring->cbs);
1627 ring->cbs = NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -07001628 ring->size = 0;
1629 ring->alloc_size = 0;
1630
1631 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
1632}
1633
1634/* RDMA helper */
1635static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001636 unsigned int enable)
Florian Fainelli80105be2014-04-24 18:08:57 -07001637{
1638 unsigned int timeout = 1000;
1639 u32 reg;
1640
1641 reg = rdma_readl(priv, RDMA_CONTROL);
1642 if (enable)
1643 reg |= RDMA_EN;
1644 else
1645 reg &= ~RDMA_EN;
1646 rdma_writel(priv, reg, RDMA_CONTROL);
1647
1648 /* Poll for RMDA disabling completion */
1649 do {
1650 reg = rdma_readl(priv, RDMA_STATUS);
1651 if (!!(reg & RDMA_DISABLED) == !enable)
1652 return 0;
1653 usleep_range(1000, 2000);
1654 } while (timeout-- > 0);
1655
1656 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
1657
1658 return -ETIMEDOUT;
1659}
1660
1661/* TDMA helper */
1662static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001663 unsigned int enable)
Florian Fainelli80105be2014-04-24 18:08:57 -07001664{
1665 unsigned int timeout = 1000;
1666 u32 reg;
1667
1668 reg = tdma_readl(priv, TDMA_CONTROL);
1669 if (enable)
Florian Fainelli44a45242017-01-20 11:08:27 -08001670 reg |= tdma_control_bit(priv, TDMA_EN);
Florian Fainelli80105be2014-04-24 18:08:57 -07001671 else
Florian Fainelli44a45242017-01-20 11:08:27 -08001672 reg &= ~tdma_control_bit(priv, TDMA_EN);
Florian Fainelli80105be2014-04-24 18:08:57 -07001673 tdma_writel(priv, reg, TDMA_CONTROL);
1674
1675 /* Poll for TMDA disabling completion */
1676 do {
1677 reg = tdma_readl(priv, TDMA_STATUS);
1678 if (!!(reg & TDMA_DISABLED) == !enable)
1679 return 0;
1680
1681 usleep_range(1000, 2000);
1682 } while (timeout-- > 0);
1683
1684 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
1685
1686 return -ETIMEDOUT;
1687}
1688
1689static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
1690{
Florian Fainellibaf387a2015-05-28 15:24:42 -07001691 struct bcm_sysport_cb *cb;
Florian Fainelli80105be2014-04-24 18:08:57 -07001692 u32 reg;
1693 int ret;
Florian Fainellibaf387a2015-05-28 15:24:42 -07001694 int i;
Florian Fainelli80105be2014-04-24 18:08:57 -07001695
1696 /* Initialize SW view of the RX ring */
Florian Fainelli44a45242017-01-20 11:08:27 -08001697 priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC;
Florian Fainelli80105be2014-04-24 18:08:57 -07001698 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
Florian Fainelli80105be2014-04-24 18:08:57 -07001699 priv->rx_c_index = 0;
1700 priv->rx_read_ptr = 0;
Florian Fainelli40a8a312014-07-09 17:36:47 -07001701 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
1702 GFP_KERNEL);
Florian Fainelli80105be2014-04-24 18:08:57 -07001703 if (!priv->rx_cbs) {
1704 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1705 return -ENOMEM;
1706 }
1707
Florian Fainellibaf387a2015-05-28 15:24:42 -07001708 for (i = 0; i < priv->num_rx_bds; i++) {
1709 cb = priv->rx_cbs + i;
1710 cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
1711 }
1712
Florian Fainelli80105be2014-04-24 18:08:57 -07001713 ret = bcm_sysport_alloc_rx_bufs(priv);
1714 if (ret) {
1715 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
1716 return ret;
1717 }
1718
1719 /* Initialize HW, ensure RDMA is disabled */
1720 reg = rdma_readl(priv, RDMA_STATUS);
1721 if (!(reg & RDMA_DISABLED))
1722 rdma_enable_set(priv, 0);
1723
1724 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
1725 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
1726 rdma_writel(priv, 0, RDMA_PROD_INDEX);
1727 rdma_writel(priv, 0, RDMA_CONS_INDEX);
1728 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
1729 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
1730 /* Operate the queue in ring mode */
1731 rdma_writel(priv, 0, RDMA_START_ADDR_HI);
1732 rdma_writel(priv, 0, RDMA_START_ADDR_LO);
1733 rdma_writel(priv, 0, RDMA_END_ADDR_HI);
Florian Fainelli44a45242017-01-20 11:08:27 -08001734 rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO);
Florian Fainelli80105be2014-04-24 18:08:57 -07001735
Florian Fainelli80105be2014-04-24 18:08:57 -07001736 netif_dbg(priv, hw, priv->netdev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001737 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1738 priv->num_rx_bds, priv->rx_bds);
Florian Fainelli80105be2014-04-24 18:08:57 -07001739
1740 return 0;
1741}
1742
1743static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
1744{
1745 struct bcm_sysport_cb *cb;
1746 unsigned int i;
1747 u32 reg;
1748
1749 /* Caller should ensure RDMA is disabled */
1750 reg = rdma_readl(priv, RDMA_STATUS);
1751 if (!(reg & RDMA_DISABLED))
1752 netdev_warn(priv->netdev, "RDMA not stopped!\n");
1753
1754 for (i = 0; i < priv->num_rx_bds; i++) {
1755 cb = &priv->rx_cbs[i];
1756 if (dma_unmap_addr(cb, dma_addr))
1757 dma_unmap_single(&priv->pdev->dev,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001758 dma_unmap_addr(cb, dma_addr),
1759 RX_BUF_LENGTH, DMA_FROM_DEVICE);
Florian Fainelli80105be2014-04-24 18:08:57 -07001760 bcm_sysport_free_cb(cb);
1761 }
1762
1763 kfree(priv->rx_cbs);
1764 priv->rx_cbs = NULL;
1765
1766 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
1767}
1768
1769static void bcm_sysport_set_rx_mode(struct net_device *dev)
1770{
1771 struct bcm_sysport_priv *priv = netdev_priv(dev);
1772 u32 reg;
1773
Florian Fainelli44a45242017-01-20 11:08:27 -08001774 if (priv->is_lite)
1775 return;
1776
Florian Fainelli80105be2014-04-24 18:08:57 -07001777 reg = umac_readl(priv, UMAC_CMD);
1778 if (dev->flags & IFF_PROMISC)
1779 reg |= CMD_PROMISC;
1780 else
1781 reg &= ~CMD_PROMISC;
1782 umac_writel(priv, reg, UMAC_CMD);
1783
1784 /* No support for ALLMULTI */
1785 if (dev->flags & IFF_ALLMULTI)
1786 return;
1787}
1788
1789static inline void umac_enable_set(struct bcm_sysport_priv *priv,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07001790 u32 mask, unsigned int enable)
Florian Fainelli80105be2014-04-24 18:08:57 -07001791{
1792 u32 reg;
1793
Florian Fainelli44a45242017-01-20 11:08:27 -08001794 if (!priv->is_lite) {
1795 reg = umac_readl(priv, UMAC_CMD);
1796 if (enable)
1797 reg |= mask;
1798 else
1799 reg &= ~mask;
1800 umac_writel(priv, reg, UMAC_CMD);
1801 } else {
1802 reg = gib_readl(priv, GIB_CONTROL);
1803 if (enable)
1804 reg |= mask;
1805 else
1806 reg &= ~mask;
1807 gib_writel(priv, reg, GIB_CONTROL);
1808 }
Florian Fainelli00b91c62014-05-15 14:33:53 -07001809
1810 /* UniMAC stops on a packet boundary, wait for a full-sized packet
1811 * to be processed (1 msec).
1812 */
1813 if (enable == 0)
1814 usleep_range(1000, 2000);
Florian Fainelli80105be2014-04-24 18:08:57 -07001815}
1816
Florian Fainelli412bce82014-06-26 10:06:45 -07001817static inline void umac_reset(struct bcm_sysport_priv *priv)
Florian Fainelli80105be2014-04-24 18:08:57 -07001818{
Florian Fainelli80105be2014-04-24 18:08:57 -07001819 u32 reg;
Florian Fainelli80105be2014-04-24 18:08:57 -07001820
Florian Fainelli44a45242017-01-20 11:08:27 -08001821 if (priv->is_lite)
1822 return;
1823
Florian Fainelli412bce82014-06-26 10:06:45 -07001824 reg = umac_readl(priv, UMAC_CMD);
1825 reg |= CMD_SW_RESET;
1826 umac_writel(priv, reg, UMAC_CMD);
1827 udelay(10);
1828 reg = umac_readl(priv, UMAC_CMD);
1829 reg &= ~CMD_SW_RESET;
1830 umac_writel(priv, reg, UMAC_CMD);
Florian Fainelli80105be2014-04-24 18:08:57 -07001831}
1832
1833static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
Jakub Kicinski76660752021-10-14 07:24:31 -07001834 const unsigned char *addr)
Florian Fainelli80105be2014-04-24 18:08:57 -07001835{
Florian Fainelli44a45242017-01-20 11:08:27 -08001836 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1837 addr[3];
1838 u32 mac1 = (addr[4] << 8) | addr[5];
1839
1840 if (!priv->is_lite) {
1841 umac_writel(priv, mac0, UMAC_MAC0);
1842 umac_writel(priv, mac1, UMAC_MAC1);
1843 } else {
1844 gib_writel(priv, mac0, GIB_MAC0);
1845 gib_writel(priv, mac1, GIB_MAC1);
1846 }
Florian Fainelli80105be2014-04-24 18:08:57 -07001847}
1848
1849static void topctrl_flush(struct bcm_sysport_priv *priv)
1850{
1851 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1852 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1853 mdelay(1);
1854 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1855 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
1856}
1857
Florian Fainellifb3b5962014-12-08 15:59:18 -08001858static int bcm_sysport_change_mac(struct net_device *dev, void *p)
1859{
1860 struct bcm_sysport_priv *priv = netdev_priv(dev);
1861 struct sockaddr *addr = p;
1862
1863 if (!is_valid_ether_addr(addr->sa_data))
1864 return -EINVAL;
1865
Jakub Kicinskia05e4c02021-10-04 09:05:21 -07001866 eth_hw_addr_set(dev, addr->sa_data);
Florian Fainellifb3b5962014-12-08 15:59:18 -08001867
1868 /* interface is disabled, changes to MAC will be reflected on next
1869 * open call
1870 */
1871 if (!netif_running(dev))
1872 return 0;
1873
1874 umac_set_hw_addr(priv, dev->dev_addr);
1875
1876 return 0;
1877}
1878
kiki good10377ba2017-08-04 00:07:45 +01001879static void bcm_sysport_get_stats64(struct net_device *dev,
1880 struct rtnl_link_stats64 *stats)
Florian Fainelli30defeb2017-03-23 10:36:46 -07001881{
1882 struct bcm_sysport_priv *priv = netdev_priv(dev);
kiki good10377ba2017-08-04 00:07:45 +01001883 struct bcm_sysport_stats64 *stats64 = &priv->stats64;
kiki good10377ba2017-08-04 00:07:45 +01001884 unsigned int start;
Florian Fainelli30defeb2017-03-23 10:36:46 -07001885
kiki good10377ba2017-08-04 00:07:45 +01001886 netdev_stats_to_stats64(stats, &dev->stats);
1887
Florian Fainelli8ecb1a22017-09-18 16:31:30 -07001888 bcm_sysport_update_tx_stats(priv, &stats->tx_bytes,
1889 &stats->tx_packets);
kiki good10377ba2017-08-04 00:07:45 +01001890
1891 do {
Thomas Gleixner068c38a2022-10-26 15:22:14 +02001892 start = u64_stats_fetch_begin(&priv->syncp);
kiki good10377ba2017-08-04 00:07:45 +01001893 stats->rx_packets = stats64->rx_packets;
1894 stats->rx_bytes = stats64->rx_bytes;
Thomas Gleixner068c38a2022-10-26 15:22:14 +02001895 } while (u64_stats_fetch_retry(&priv->syncp, start));
Florian Fainelli30defeb2017-03-23 10:36:46 -07001896}
1897
Florian Fainellib02e6d92014-07-01 21:08:37 -07001898static void bcm_sysport_netif_start(struct net_device *dev)
1899{
1900 struct bcm_sysport_priv *priv = netdev_priv(dev);
1901
1902 /* Enable NAPI */
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07001903 bcm_sysport_init_dim(priv, bcm_sysport_dim_work);
1904 bcm_sysport_init_rx_coalesce(priv);
Florian Fainellib02e6d92014-07-01 21:08:37 -07001905 napi_enable(&priv->napi);
1906
Florian Fainelli8edf0042014-10-28 11:12:00 -07001907 /* Enable RX interrupt and TX ring full interrupt */
1908 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1909
Philippe Reynes715a0222016-06-19 20:39:08 +02001910 phy_start(dev->phydev);
Florian Fainellib02e6d92014-07-01 21:08:37 -07001911
Florian Fainelli44a45242017-01-20 11:08:27 -08001912 /* Enable TX interrupts for the TXQs */
1913 if (!priv->is_lite)
1914 intrl2_1_mask_clear(priv, 0xffffffff);
1915 else
1916 intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK);
Florian Fainellib02e6d92014-07-01 21:08:37 -07001917}
1918
Florian Fainelli40755a02014-07-01 21:08:38 -07001919static void rbuf_init(struct bcm_sysport_priv *priv)
1920{
1921 u32 reg;
1922
1923 reg = rbuf_readl(priv, RBUF_CONTROL);
1924 reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
Florian Fainelli44a45242017-01-20 11:08:27 -08001925 /* Set a correct RSB format on SYSTEMPORT Lite */
Florian Fainelli389a06b2017-08-29 13:35:17 -07001926 if (priv->is_lite)
Florian Fainelli44a45242017-01-20 11:08:27 -08001927 reg &= ~RBUF_RSB_SWAP1;
Florian Fainelli389a06b2017-08-29 13:35:17 -07001928
1929 /* Set a correct RSB format based on host endian */
1930 if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
Florian Fainelli44a45242017-01-20 11:08:27 -08001931 reg |= RBUF_RSB_SWAP0;
Florian Fainelli389a06b2017-08-29 13:35:17 -07001932 else
1933 reg &= ~RBUF_RSB_SWAP0;
Florian Fainelli40755a02014-07-01 21:08:38 -07001934 rbuf_writel(priv, reg, RBUF_CONTROL);
1935}
1936
Florian Fainelli44a45242017-01-20 11:08:27 -08001937static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv)
1938{
1939 intrl2_0_mask_set(priv, 0xffffffff);
1940 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1941 if (!priv->is_lite) {
1942 intrl2_1_mask_set(priv, 0xffffffff);
1943 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1944 }
1945}
1946
1947static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv)
1948{
Florian Fainelli93824c82017-11-02 16:08:40 -07001949 u32 reg;
Florian Fainelli44a45242017-01-20 11:08:27 -08001950
Florian Fainelli93824c82017-11-02 16:08:40 -07001951 reg = gib_readl(priv, GIB_CONTROL);
1952 /* Include Broadcom tag in pad extension and fix up IPG_LENGTH */
Florian Fainelli44a45242017-01-20 11:08:27 -08001953 if (netdev_uses_dsa(priv->netdev)) {
Florian Fainelli44a45242017-01-20 11:08:27 -08001954 reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT);
1955 reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT;
Florian Fainelli44a45242017-01-20 11:08:27 -08001956 }
Florian Fainelli93824c82017-11-02 16:08:40 -07001957 reg &= ~(GIB_IPG_LEN_MASK << GIB_IPG_LEN_SHIFT);
1958 reg |= 12 << GIB_IPG_LEN_SHIFT;
1959 gib_writel(priv, reg, GIB_CONTROL);
Florian Fainelli44a45242017-01-20 11:08:27 -08001960}
1961
Florian Fainelli80105be2014-04-24 18:08:57 -07001962static int bcm_sysport_open(struct net_device *dev)
1963{
1964 struct bcm_sysport_priv *priv = netdev_priv(dev);
Philippe Reynes715a0222016-06-19 20:39:08 +02001965 struct phy_device *phydev;
Florian Fainelli80105be2014-04-24 18:08:57 -07001966 unsigned int i;
Florian Fainelli80105be2014-04-24 18:08:57 -07001967 int ret;
1968
Florian Fainelli31bc72d2020-09-01 14:43:47 -07001969 clk_prepare_enable(priv->clk);
1970
Florian Fainelli80105be2014-04-24 18:08:57 -07001971 /* Reset UniMAC */
Florian Fainelli412bce82014-06-26 10:06:45 -07001972 umac_reset(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07001973
1974 /* Flush TX and RX FIFOs at TOPCTRL level */
1975 topctrl_flush(priv);
1976
1977 /* Disable the UniMAC RX/TX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07001978 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
Florian Fainelli80105be2014-04-24 18:08:57 -07001979
1980 /* Enable RBUF 2bytes alignment and Receive Status Block */
Florian Fainelli40755a02014-07-01 21:08:38 -07001981 rbuf_init(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07001982
1983 /* Set maximum frame length */
Florian Fainelli44a45242017-01-20 11:08:27 -08001984 if (!priv->is_lite)
1985 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1986 else
1987 gib_set_pad_extension(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07001988
Florian Fainelli297357d2018-09-27 15:36:11 -07001989 /* Apply features again in case we changed them while interface was
1990 * down
1991 */
1992 bcm_sysport_set_features(dev, dev->features);
1993
Florian Fainelli80105be2014-04-24 18:08:57 -07001994 /* Set MAC address */
1995 umac_set_hw_addr(priv, dev->dev_addr);
1996
Philippe Reynes715a0222016-06-19 20:39:08 +02001997 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
1998 0, priv->phy_interface);
1999 if (!phydev) {
Florian Fainelli80105be2014-04-24 18:08:57 -07002000 netdev_err(dev, "could not attach to PHY\n");
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002001 ret = -ENODEV;
2002 goto out_clk_disable;
Florian Fainelli80105be2014-04-24 18:08:57 -07002003 }
2004
Florian Fainelli9f172132022-10-25 16:42:01 -07002005 /* Indicate that the MAC is responsible for PHY PM */
2006 phydev->mac_managed_pm = true;
2007
Florian Fainelli80105be2014-04-24 18:08:57 -07002008 /* Reset house keeping link status */
2009 priv->old_duplex = -1;
2010 priv->old_link = -1;
2011 priv->old_pause = -1;
2012
2013 /* mask all interrupts and request them */
Florian Fainelli44a45242017-01-20 11:08:27 -08002014 bcm_sysport_mask_all_intrs(priv);
Florian Fainelli80105be2014-04-24 18:08:57 -07002015
2016 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
2017 if (ret) {
2018 netdev_err(dev, "failed to request RX interrupt\n");
2019 goto out_phy_disconnect;
2020 }
2021
Florian Fainelli44a45242017-01-20 11:08:27 -08002022 if (!priv->is_lite) {
2023 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0,
2024 dev->name, dev);
2025 if (ret) {
2026 netdev_err(dev, "failed to request TX interrupt\n");
2027 goto out_free_irq0;
2028 }
Florian Fainelli80105be2014-04-24 18:08:57 -07002029 }
2030
2031 /* Initialize both hardware and software ring */
Florian Fainelli8b8e6e72021-12-15 12:24:49 -08002032 spin_lock_init(&priv->desc_lock);
Florian Fainelli80105be2014-04-24 18:08:57 -07002033 for (i = 0; i < dev->num_tx_queues; i++) {
2034 ret = bcm_sysport_init_tx_ring(priv, i);
2035 if (ret) {
2036 netdev_err(dev, "failed to initialize TX ring %d\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002037 i);
Florian Fainelli80105be2014-04-24 18:08:57 -07002038 goto out_free_tx_ring;
2039 }
2040 }
2041
2042 /* Initialize linked-list */
2043 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
2044
2045 /* Initialize RX ring */
2046 ret = bcm_sysport_init_rx_ring(priv);
2047 if (ret) {
2048 netdev_err(dev, "failed to initialize RX ring\n");
2049 goto out_free_rx_ring;
2050 }
2051
2052 /* Turn on RDMA */
2053 ret = rdma_enable_set(priv, 1);
2054 if (ret)
2055 goto out_free_rx_ring;
2056
Florian Fainelli80105be2014-04-24 18:08:57 -07002057 /* Turn on TDMA */
2058 ret = tdma_enable_set(priv, 1);
2059 if (ret)
2060 goto out_clear_rx_int;
2061
Florian Fainelli80105be2014-04-24 18:08:57 -07002062 /* Turn on UniMAC TX/RX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07002063 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
Florian Fainelli80105be2014-04-24 18:08:57 -07002064
Florian Fainellib02e6d92014-07-01 21:08:37 -07002065 bcm_sysport_netif_start(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002066
Florian Fainelli7cb6a2a2018-11-01 15:55:38 -07002067 netif_tx_start_all_queues(dev);
2068
Florian Fainelli80105be2014-04-24 18:08:57 -07002069 return 0;
2070
2071out_clear_rx_int:
2072 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
2073out_free_rx_ring:
2074 bcm_sysport_fini_rx_ring(priv);
2075out_free_tx_ring:
2076 for (i = 0; i < dev->num_tx_queues; i++)
2077 bcm_sysport_fini_tx_ring(priv, i);
Florian Fainelli44a45242017-01-20 11:08:27 -08002078 if (!priv->is_lite)
2079 free_irq(priv->irq1, dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002080out_free_irq0:
2081 free_irq(priv->irq0, dev);
2082out_phy_disconnect:
Philippe Reynes715a0222016-06-19 20:39:08 +02002083 phy_disconnect(phydev);
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002084out_clk_disable:
2085 clk_disable_unprepare(priv->clk);
Florian Fainelli80105be2014-04-24 18:08:57 -07002086 return ret;
2087}
2088
Florian Fainellib02e6d92014-07-01 21:08:37 -07002089static void bcm_sysport_netif_stop(struct net_device *dev)
Florian Fainelli80105be2014-04-24 18:08:57 -07002090{
2091 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002092
2093 /* stop all software from updating hardware */
Florian Fainelli7cb6a2a2018-11-01 15:55:38 -07002094 netif_tx_disable(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002095 napi_disable(&priv->napi);
Florian Fainellib6e0e872018-03-22 18:19:32 -07002096 cancel_work_sync(&priv->dim.dim.work);
Philippe Reynes715a0222016-06-19 20:39:08 +02002097 phy_stop(dev->phydev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002098
2099 /* mask all interrupts */
Florian Fainelli44a45242017-01-20 11:08:27 -08002100 bcm_sysport_mask_all_intrs(priv);
Florian Fainellib02e6d92014-07-01 21:08:37 -07002101}
2102
2103static int bcm_sysport_stop(struct net_device *dev)
2104{
2105 struct bcm_sysport_priv *priv = netdev_priv(dev);
2106 unsigned int i;
2107 int ret;
2108
2109 bcm_sysport_netif_stop(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002110
2111 /* Disable UniMAC RX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07002112 umac_enable_set(priv, CMD_RX_EN, 0);
Florian Fainelli80105be2014-04-24 18:08:57 -07002113
2114 ret = tdma_enable_set(priv, 0);
2115 if (ret) {
2116 netdev_err(dev, "timeout disabling RDMA\n");
2117 return ret;
2118 }
2119
2120 /* Wait for a maximum packet size to be drained */
2121 usleep_range(2000, 3000);
2122
2123 ret = rdma_enable_set(priv, 0);
2124 if (ret) {
2125 netdev_err(dev, "timeout disabling TDMA\n");
2126 return ret;
2127 }
2128
2129 /* Disable UniMAC TX */
Florian Fainelli18e21b02014-07-01 21:08:36 -07002130 umac_enable_set(priv, CMD_TX_EN, 0);
Florian Fainelli80105be2014-04-24 18:08:57 -07002131
2132 /* Free RX/TX rings SW structures */
2133 for (i = 0; i < dev->num_tx_queues; i++)
2134 bcm_sysport_fini_tx_ring(priv, i);
2135 bcm_sysport_fini_rx_ring(priv);
2136
2137 free_irq(priv->irq0, dev);
Florian Fainelli44a45242017-01-20 11:08:27 -08002138 if (!priv->is_lite)
2139 free_irq(priv->irq1, dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002140
2141 /* Disconnect from PHY */
Philippe Reynes715a0222016-06-19 20:39:08 +02002142 phy_disconnect(dev->phydev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002143
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002144 clk_disable_unprepare(priv->clk);
2145
Florian Fainelli80105be2014-04-24 18:08:57 -07002146 return 0;
2147}
2148
Florian Fainellibb9051a22018-08-07 10:50:23 -07002149static int bcm_sysport_rule_find(struct bcm_sysport_priv *priv,
2150 u64 location)
2151{
2152 unsigned int index;
2153 u32 reg;
2154
2155 for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
2156 reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index));
2157 reg >>= RXCHK_BRCM_TAG_CID_SHIFT;
2158 reg &= RXCHK_BRCM_TAG_CID_MASK;
2159 if (reg == location)
2160 return index;
2161 }
2162
2163 return -EINVAL;
2164}
2165
2166static int bcm_sysport_rule_get(struct bcm_sysport_priv *priv,
2167 struct ethtool_rxnfc *nfc)
2168{
2169 int index;
2170
2171 /* This is not a rule that we know about */
2172 index = bcm_sysport_rule_find(priv, nfc->fs.location);
2173 if (index < 0)
2174 return -EOPNOTSUPP;
2175
2176 nfc->fs.ring_cookie = RX_CLS_FLOW_WAKE;
2177
2178 return 0;
2179}
2180
2181static int bcm_sysport_rule_set(struct bcm_sysport_priv *priv,
2182 struct ethtool_rxnfc *nfc)
2183{
2184 unsigned int index;
2185 u32 reg;
2186
2187 /* We cannot match locations greater than what the classification ID
2188 * permits (256 entries)
2189 */
2190 if (nfc->fs.location > RXCHK_BRCM_TAG_CID_MASK)
2191 return -E2BIG;
2192
2193 /* We cannot support flows that are not destined for a wake-up */
2194 if (nfc->fs.ring_cookie != RX_CLS_FLOW_WAKE)
2195 return -EOPNOTSUPP;
2196
Florian Fainellibb9051a22018-08-07 10:50:23 -07002197 index = find_first_zero_bit(priv->filters, RXCHK_BRCM_TAG_MAX);
Colin Ian Kingc0368592020-03-12 15:04:30 +00002198 if (index >= RXCHK_BRCM_TAG_MAX)
Yury Norov1ef1b692022-01-23 10:38:33 -08002199 /* All filters are already in use, we cannot match more rules */
Florian Fainellibb9051a22018-08-07 10:50:23 -07002200 return -ENOSPC;
2201
2202 /* Location is the classification ID, and index is the position
2203 * within one of our 8 possible filters to be programmed
2204 */
2205 reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index));
2206 reg &= ~(RXCHK_BRCM_TAG_CID_MASK << RXCHK_BRCM_TAG_CID_SHIFT);
2207 reg |= nfc->fs.location << RXCHK_BRCM_TAG_CID_SHIFT;
2208 rxchk_writel(priv, reg, RXCHK_BRCM_TAG(index));
2209 rxchk_writel(priv, 0xff00ffff, RXCHK_BRCM_TAG_MASK(index));
2210
Florian Fainelli80f8dea2018-11-06 12:58:41 -08002211 priv->filters_loc[index] = nfc->fs.location;
Florian Fainellibb9051a22018-08-07 10:50:23 -07002212 set_bit(index, priv->filters);
2213
2214 return 0;
2215}
2216
2217static int bcm_sysport_rule_del(struct bcm_sysport_priv *priv,
2218 u64 location)
2219{
2220 int index;
2221
2222 /* This is not a rule that we know about */
2223 index = bcm_sysport_rule_find(priv, location);
2224 if (index < 0)
2225 return -EOPNOTSUPP;
2226
2227 /* No need to disable this filter if it was enabled, this will
2228 * be taken care of during suspend time by bcm_sysport_suspend_to_wol
2229 */
2230 clear_bit(index, priv->filters);
Florian Fainelli80f8dea2018-11-06 12:58:41 -08002231 priv->filters_loc[index] = 0;
Florian Fainellibb9051a22018-08-07 10:50:23 -07002232
2233 return 0;
2234}
2235
2236static int bcm_sysport_get_rxnfc(struct net_device *dev,
2237 struct ethtool_rxnfc *nfc, u32 *rule_locs)
2238{
2239 struct bcm_sysport_priv *priv = netdev_priv(dev);
2240 int ret = -EOPNOTSUPP;
2241
2242 switch (nfc->cmd) {
2243 case ETHTOOL_GRXCLSRULE:
2244 ret = bcm_sysport_rule_get(priv, nfc);
2245 break;
2246 default:
2247 break;
2248 }
2249
2250 return ret;
2251}
2252
2253static int bcm_sysport_set_rxnfc(struct net_device *dev,
2254 struct ethtool_rxnfc *nfc)
2255{
2256 struct bcm_sysport_priv *priv = netdev_priv(dev);
2257 int ret = -EOPNOTSUPP;
2258
2259 switch (nfc->cmd) {
2260 case ETHTOOL_SRXCLSRLINS:
2261 ret = bcm_sysport_rule_set(priv, nfc);
2262 break;
2263 case ETHTOOL_SRXCLSRLDEL:
2264 ret = bcm_sysport_rule_del(priv, nfc->fs.location);
2265 break;
2266 default:
2267 break;
2268 }
2269
2270 return ret;
2271}
2272
Julia Lawallc1ab0e92016-08-31 09:30:48 +02002273static const struct ethtool_ops bcm_sysport_ethtool_ops = {
Jakub Kicinskif4a76615f2020-03-09 19:15:00 -07002274 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2275 ETHTOOL_COALESCE_MAX_FRAMES |
2276 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
Florian Fainelli80105be2014-04-24 18:08:57 -07002277 .get_drvinfo = bcm_sysport_get_drvinfo,
2278 .get_msglevel = bcm_sysport_get_msglvl,
2279 .set_msglevel = bcm_sysport_set_msglvl,
2280 .get_link = ethtool_op_get_link,
2281 .get_strings = bcm_sysport_get_strings,
2282 .get_ethtool_stats = bcm_sysport_get_stats,
2283 .get_sset_count = bcm_sysport_get_sset_count,
Florian Fainelli83e82f42014-07-01 21:08:40 -07002284 .get_wol = bcm_sysport_get_wol,
2285 .set_wol = bcm_sysport_set_wol,
Florian Fainellib1a15e82015-05-11 15:12:41 -07002286 .get_coalesce = bcm_sysport_get_coalesce,
2287 .set_coalesce = bcm_sysport_set_coalesce,
Philippe Reynes697666e2016-06-19 20:39:09 +02002288 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2289 .set_link_ksettings = phy_ethtool_set_link_ksettings,
Florian Fainellibb9051a22018-08-07 10:50:23 -07002290 .get_rxnfc = bcm_sysport_get_rxnfc,
2291 .set_rxnfc = bcm_sysport_set_rxnfc,
Florian Fainelli80105be2014-04-24 18:08:57 -07002292};
2293
Florian Fainellid1565762017-10-11 10:57:50 -07002294static u16 bcm_sysport_select_queue(struct net_device *dev, struct sk_buff *skb,
Paolo Abenia350ecc2019-03-20 11:02:06 +01002295 struct net_device *sb_dev)
Florian Fainellid1565762017-10-11 10:57:50 -07002296{
2297 struct bcm_sysport_priv *priv = netdev_priv(dev);
2298 u16 queue = skb_get_queue_mapping(skb);
2299 struct bcm_sysport_tx_ring *tx_ring;
2300 unsigned int q, port;
2301
2302 if (!netdev_uses_dsa(dev))
Paolo Abenia350ecc2019-03-20 11:02:06 +01002303 return netdev_pick_tx(dev, skb, NULL);
Florian Fainellid1565762017-10-11 10:57:50 -07002304
2305 /* DSA tagging layer will have configured the correct queue */
2306 q = BRCM_TAG_GET_QUEUE(queue);
2307 port = BRCM_TAG_GET_PORT(queue);
2308 tx_ring = priv->ring_map[q + port * priv->per_port_num_tx_queues];
2309
Florian Fainellie83b1712017-10-20 15:59:30 -07002310 if (unlikely(!tx_ring))
Paolo Abenia350ecc2019-03-20 11:02:06 +01002311 return netdev_pick_tx(dev, skb, NULL);
Florian Fainellie83b1712017-10-20 15:59:30 -07002312
Florian Fainellid1565762017-10-11 10:57:50 -07002313 return tx_ring->index;
2314}
2315
Florian Fainellic0c21452017-10-25 18:01:05 -07002316static const struct net_device_ops bcm_sysport_netdev_ops = {
2317 .ndo_start_xmit = bcm_sysport_xmit,
2318 .ndo_tx_timeout = bcm_sysport_tx_timeout,
2319 .ndo_open = bcm_sysport_open,
2320 .ndo_stop = bcm_sysport_stop,
2321 .ndo_set_features = bcm_sysport_set_features,
2322 .ndo_set_rx_mode = bcm_sysport_set_rx_mode,
2323 .ndo_set_mac_address = bcm_sysport_change_mac,
2324#ifdef CONFIG_NET_POLL_CONTROLLER
2325 .ndo_poll_controller = bcm_sysport_poll_controller,
2326#endif
2327 .ndo_get_stats64 = bcm_sysport_get_stats64,
2328 .ndo_select_queue = bcm_sysport_select_queue,
2329};
2330
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002331static int bcm_sysport_map_queues(struct net_device *dev,
2332 struct net_device *slave_dev)
Florian Fainellid1565762017-10-11 10:57:50 -07002333{
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002334 struct dsa_port *dp = dsa_port_from_netdev(slave_dev);
2335 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainellid1565762017-10-11 10:57:50 -07002336 struct bcm_sysport_tx_ring *ring;
Florian Fainellid1565762017-10-11 10:57:50 -07002337 unsigned int num_tx_queues;
Florian Fainelli25c44072018-11-06 15:15:17 -08002338 unsigned int q, qp, port;
Florian Fainellid1565762017-10-11 10:57:50 -07002339
2340 /* We can't be setting up queue inspection for non directly attached
2341 * switches
2342 */
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002343 if (dp->ds->index)
Florian Fainellid1565762017-10-11 10:57:50 -07002344 return 0;
2345
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002346 port = dp->index;
Florian Fainellid1565762017-10-11 10:57:50 -07002347
2348 /* On SYSTEMPORT Lite we have twice as less queues, so we cannot do a
2349 * 1:1 mapping, we can only do a 2:1 mapping. By reducing the number of
2350 * per-port (slave_dev) network devices queue, we achieve just that.
2351 * This need to happen now before any slave network device is used such
2352 * it accurately reflects the number of real TX queues.
2353 */
2354 if (priv->is_lite)
2355 netif_set_real_num_tx_queues(slave_dev,
2356 slave_dev->num_tx_queues / 2);
Florian Fainelli1f3ccc3c2018-04-25 16:21:51 -07002357
Florian Fainellid1565762017-10-11 10:57:50 -07002358 num_tx_queues = slave_dev->real_num_tx_queues;
2359
2360 if (priv->per_port_num_tx_queues &&
2361 priv->per_port_num_tx_queues != num_tx_queues)
Colin Ian King14b7dc12018-04-27 20:09:25 +01002362 netdev_warn(slave_dev, "asymmetric number of per-port queues\n");
Florian Fainellid1565762017-10-11 10:57:50 -07002363
2364 priv->per_port_num_tx_queues = num_tx_queues;
2365
Florian Fainelli25c44072018-11-06 15:15:17 -08002366 for (q = 0, qp = 0; q < dev->num_tx_queues && qp < num_tx_queues;
2367 q++) {
2368 ring = &priv->tx_rings[q];
2369
2370 if (ring->inspect)
2371 continue;
Florian Fainellid1565762017-10-11 10:57:50 -07002372
2373 /* Just remember the mapping actual programming done
2374 * during bcm_sysport_init_tx_ring
2375 */
Florian Fainelli25c44072018-11-06 15:15:17 -08002376 ring->switch_queue = qp;
Florian Fainellid1565762017-10-11 10:57:50 -07002377 ring->switch_port = port;
Florian Fainelli3ded76a2017-11-01 11:29:47 -07002378 ring->inspect = true;
Florian Fainelli5a9ef192020-01-16 13:08:58 -08002379 priv->ring_map[qp + port * num_tx_queues] = ring;
Florian Fainelli25c44072018-11-06 15:15:17 -08002380 qp++;
Florian Fainellid1565762017-10-11 10:57:50 -07002381 }
2382
2383 return 0;
2384}
2385
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002386static int bcm_sysport_unmap_queues(struct net_device *dev,
2387 struct net_device *slave_dev)
Florian Fainellida106a12018-11-06 15:15:18 -08002388{
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002389 struct dsa_port *dp = dsa_port_from_netdev(slave_dev);
2390 struct bcm_sysport_priv *priv = netdev_priv(dev);
Florian Fainellida106a12018-11-06 15:15:18 -08002391 struct bcm_sysport_tx_ring *ring;
Florian Fainellida106a12018-11-06 15:15:18 -08002392 unsigned int num_tx_queues;
Florian Fainelli5a9ef192020-01-16 13:08:58 -08002393 unsigned int q, qp, port;
Florian Fainellida106a12018-11-06 15:15:18 -08002394
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002395 port = dp->index;
Florian Fainellida106a12018-11-06 15:15:18 -08002396
2397 num_tx_queues = slave_dev->real_num_tx_queues;
2398
2399 for (q = 0; q < dev->num_tx_queues; q++) {
2400 ring = &priv->tx_rings[q];
2401
2402 if (ring->switch_port != port)
2403 continue;
2404
2405 if (!ring->inspect)
2406 continue;
2407
2408 ring->inspect = false;
Florian Fainelli5a9ef192020-01-16 13:08:58 -08002409 qp = ring->switch_queue;
2410 priv->ring_map[qp + port * num_tx_queues] = NULL;
Florian Fainellida106a12018-11-06 15:15:18 -08002411 }
2412
2413 return 0;
2414}
2415
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002416static int bcm_sysport_netdevice_event(struct notifier_block *nb,
2417 unsigned long event, void *ptr)
Florian Fainellid1565762017-10-11 10:57:50 -07002418{
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002419 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2420 struct netdev_notifier_changeupper_info *info = ptr;
2421 struct bcm_sysport_priv *priv;
2422 int ret = 0;
2423
2424 priv = container_of(nb, struct bcm_sysport_priv, netdev_notifier);
2425 if (priv->netdev != dev)
2426 return NOTIFY_DONE;
Florian Fainellid1565762017-10-11 10:57:50 -07002427
Florian Fainellida106a12018-11-06 15:15:18 -08002428 switch (event) {
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002429 case NETDEV_CHANGEUPPER:
2430 if (dev->netdev_ops != &bcm_sysport_netdev_ops)
2431 return NOTIFY_DONE;
2432
Florian Fainelli6ca80632023-10-23 11:17:28 -07002433 if (!dsa_user_dev_check(info->upper_dev))
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002434 return NOTIFY_DONE;
2435
2436 if (info->linking)
2437 ret = bcm_sysport_map_queues(dev, info->upper_dev);
2438 else
2439 ret = bcm_sysport_unmap_queues(dev, info->upper_dev);
Florian Fainellida106a12018-11-06 15:15:18 -08002440 break;
2441 }
Florian Fainellid1565762017-10-11 10:57:50 -07002442
Florian Fainellida106a12018-11-06 15:15:18 -08002443 return notifier_from_errno(ret);
Florian Fainellid1565762017-10-11 10:57:50 -07002444}
2445
Florian Fainelli80105be2014-04-24 18:08:57 -07002446#define REV_FMT "v%2x.%02x"
2447
Florian Fainelli44a45242017-01-20 11:08:27 -08002448static const struct bcm_sysport_hw_params bcm_sysport_params[] = {
2449 [SYSTEMPORT] = {
2450 .is_lite = false,
2451 .num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS,
2452 },
2453 [SYSTEMPORT_LITE] = {
2454 .is_lite = true,
2455 .num_rx_desc_words = SP_LT_NUM_HW_RX_DESC_WORDS,
2456 },
2457};
2458
2459static const struct of_device_id bcm_sysport_of_match[] = {
2460 { .compatible = "brcm,systemportlite-v1.00",
2461 .data = &bcm_sysport_params[SYSTEMPORT_LITE] },
2462 { .compatible = "brcm,systemport-v1.00",
2463 .data = &bcm_sysport_params[SYSTEMPORT] },
2464 { .compatible = "brcm,systemport",
2465 .data = &bcm_sysport_params[SYSTEMPORT] },
2466 { /* sentinel */ }
2467};
2468MODULE_DEVICE_TABLE(of, bcm_sysport_of_match);
2469
Florian Fainelli80105be2014-04-24 18:08:57 -07002470static int bcm_sysport_probe(struct platform_device *pdev)
2471{
Florian Fainelli44a45242017-01-20 11:08:27 -08002472 const struct bcm_sysport_hw_params *params;
2473 const struct of_device_id *of_id = NULL;
Florian Fainelli80105be2014-04-24 18:08:57 -07002474 struct bcm_sysport_priv *priv;
2475 struct device_node *dn;
2476 struct net_device *dev;
Florian Fainelli80105be2014-04-24 18:08:57 -07002477 u32 txq, rxq;
2478 int ret;
2479
2480 dn = pdev->dev.of_node;
Florian Fainelli44a45242017-01-20 11:08:27 -08002481 of_id = of_match_node(bcm_sysport_of_match, dn);
2482 if (!of_id || !of_id->data)
2483 return -EINVAL;
2484
Florian Fainellid63b5422019-12-17 16:29:50 -08002485 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
2486 if (ret)
2487 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2488 if (ret) {
2489 dev_err(&pdev->dev, "unable to set DMA mask: %d\n", ret);
2490 return ret;
2491 }
2492
Florian Fainelli44a45242017-01-20 11:08:27 -08002493 /* Fairly quickly we need to know the type of adapter we have */
2494 params = of_id->data;
Florian Fainelli80105be2014-04-24 18:08:57 -07002495
2496 /* Read the Transmit/Receive Queue properties */
2497 if (of_property_read_u32(dn, "systemport,num-txq", &txq))
2498 txq = TDMA_NUM_RINGS;
2499 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
2500 rxq = 1;
2501
Florian Fainelli7b78be42017-01-20 11:08:26 -08002502 /* Sanity check the number of transmit queues */
2503 if (!txq || txq > TDMA_NUM_RINGS)
2504 return -EINVAL;
2505
Florian Fainelli80105be2014-04-24 18:08:57 -07002506 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
2507 if (!dev)
2508 return -ENOMEM;
2509
2510 /* Initialize private members */
2511 priv = netdev_priv(dev);
2512
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002513 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_sysport");
Pan Bian0c630a62021-01-19 20:44:23 -08002514 if (IS_ERR(priv->clk)) {
2515 ret = PTR_ERR(priv->clk);
2516 goto err_free_netdev;
2517 }
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002518
Florian Fainelli7b78be42017-01-20 11:08:26 -08002519 /* Allocate number of TX rings */
2520 priv->tx_rings = devm_kcalloc(&pdev->dev, txq,
2521 sizeof(struct bcm_sysport_tx_ring),
2522 GFP_KERNEL);
Dinghao Liu7ef1fc52020-08-24 13:58:31 +08002523 if (!priv->tx_rings) {
2524 ret = -ENOMEM;
2525 goto err_free_netdev;
2526 }
Florian Fainelli7b78be42017-01-20 11:08:26 -08002527
Florian Fainelli44a45242017-01-20 11:08:27 -08002528 priv->is_lite = params->is_lite;
2529 priv->num_rx_desc_words = params->num_rx_desc_words;
2530
Florian Fainelli80105be2014-04-24 18:08:57 -07002531 priv->irq0 = platform_get_irq(pdev, 0);
Florian Fainellid31353c2017-06-01 18:02:39 -07002532 if (!priv->is_lite) {
Florian Fainelli44a45242017-01-20 11:08:27 -08002533 priv->irq1 = platform_get_irq(pdev, 1);
Jiasheng Jiangf93b30e2023-06-01 11:30:02 +08002534 priv->wol_irq = platform_get_irq_optional(pdev, 2);
Florian Fainellid31353c2017-06-01 18:02:39 -07002535 } else {
Jiasheng Jiangf93b30e2023-06-01 11:30:02 +08002536 priv->wol_irq = platform_get_irq_optional(pdev, 1);
Florian Fainellid31353c2017-06-01 18:02:39 -07002537 }
Florian Fainelli44a45242017-01-20 11:08:27 -08002538 if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) {
Florian Fainelli80105be2014-04-24 18:08:57 -07002539 ret = -EINVAL;
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002540 goto err_free_netdev;
Florian Fainelli80105be2014-04-24 18:08:57 -07002541 }
2542
YueHaibing913919e2019-08-21 21:46:13 +08002543 priv->base = devm_platform_ioremap_resource(pdev, 0);
Jingoo Han126e6122014-05-14 12:15:42 +09002544 if (IS_ERR(priv->base)) {
2545 ret = PTR_ERR(priv->base);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002546 goto err_free_netdev;
Florian Fainelli80105be2014-04-24 18:08:57 -07002547 }
2548
2549 priv->netdev = dev;
2550 priv->pdev = pdev;
2551
Andrew Lunn0c65b2b2019-11-04 02:40:33 +01002552 ret = of_get_phy_mode(dn, &priv->phy_interface);
Florian Fainelli80105be2014-04-24 18:08:57 -07002553 /* Default to GMII interface mode */
Andrew Lunn0c65b2b2019-11-04 02:40:33 +01002554 if (ret)
Florian Fainelli80105be2014-04-24 18:08:57 -07002555 priv->phy_interface = PHY_INTERFACE_MODE_GMII;
2556
Florian Fainelli186534a2014-05-22 09:47:46 -07002557 /* In the case of a fixed PHY, the DT node associated
2558 * to the PHY is the Ethernet MAC DT node.
2559 */
2560 if (of_phy_is_fixed_link(dn)) {
2561 ret = of_phy_register_fixed_link(dn);
2562 if (ret) {
2563 dev_err(&pdev->dev, "failed to register fixed PHY\n");
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002564 goto err_free_netdev;
Florian Fainelli186534a2014-05-22 09:47:46 -07002565 }
2566
2567 priv->phy_dn = dn;
2568 }
2569
Florian Fainelli80105be2014-04-24 18:08:57 -07002570 /* Initialize netdevice members */
Jakub Kicinski9ca01b22021-10-06 18:06:56 -07002571 ret = of_get_ethdev_address(dn, dev);
Michael Walle83216e32021-04-12 19:47:17 +02002572 if (ret) {
Florian Fainelli80105be2014-04-24 18:08:57 -07002573 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
Vaishali Thakkaradb35052015-07-08 10:49:30 +05302574 eth_hw_addr_random(dev);
Florian Fainelli80105be2014-04-24 18:08:57 -07002575 }
2576
2577 SET_NETDEV_DEV(dev, &pdev->dev);
2578 dev_set_drvdata(&pdev->dev, dev);
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00002579 dev->ethtool_ops = &bcm_sysport_ethtool_ops;
Florian Fainelli80105be2014-04-24 18:08:57 -07002580 dev->netdev_ops = &bcm_sysport_netdev_ops;
Jakub Kicinskib48b89f2022-09-27 06:27:53 -07002581 netif_napi_add(dev, &priv->napi, bcm_sysport_poll);
Florian Fainelli80105be2014-04-24 18:08:57 -07002582
Florian Fainellib5061772018-09-27 15:36:12 -07002583 dev->features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
Florian Fainelli6e9fdb62020-07-06 14:29:39 -07002584 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2585 NETIF_F_HW_VLAN_CTAG_TX;
Florian Fainellib5061772018-09-27 15:36:12 -07002586 dev->hw_features |= dev->features;
2587 dev->vlan_features |= dev->features;
Florian Fainelli54ddbdb2020-12-18 09:38:43 -08002588 dev->max_mtu = UMAC_MAX_MTU_SIZE;
Florian Fainelli80105be2014-04-24 18:08:57 -07002589
Florian Fainelli83e82f42014-07-01 21:08:40 -07002590 /* Request the WOL interrupt and advertise suspend if available */
2591 priv->wol_irq_disabled = 1;
2592 ret = devm_request_irq(&pdev->dev, priv->wol_irq,
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002593 bcm_sysport_wol_isr, 0, dev->name, priv);
Florian Fainelli83e82f42014-07-01 21:08:40 -07002594 if (!ret)
2595 device_set_wakeup_capable(&pdev->dev, 1);
2596
Florian Fainelli6328a122020-09-01 14:43:48 -07002597 priv->wol_clk = devm_clk_get_optional(&pdev->dev, "sw_sysportwol");
Christophe JAILLETef6b1cd2022-05-15 19:01:56 +02002598 if (IS_ERR(priv->wol_clk)) {
2599 ret = PTR_ERR(priv->wol_clk);
2600 goto err_deregister_fixed_link;
2601 }
Florian Fainelli6328a122020-09-01 14:43:48 -07002602
Florian Fainelli80105be2014-04-24 18:08:57 -07002603 /* Set the needed headroom once and for all */
Paul Gortmaker3afc5572014-05-30 15:39:30 -04002604 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
2605 dev->needed_headroom += sizeof(struct bcm_tsb);
Florian Fainelli80105be2014-04-24 18:08:57 -07002606
Florian Fainellif532e742014-06-05 10:22:18 -07002607 /* libphy will adjust the link state accordingly */
2608 netif_carrier_off(dev);
2609
Florian Fainellia8cdfbdf2018-03-28 15:15:37 -07002610 priv->rx_max_coalesced_frames = 1;
kiki good10377ba2017-08-04 00:07:45 +01002611 u64_stats_init(&priv->syncp);
2612
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002613 priv->netdev_notifier.notifier_call = bcm_sysport_netdevice_event;
Florian Fainellid1565762017-10-11 10:57:50 -07002614
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002615 ret = register_netdevice_notifier(&priv->netdev_notifier);
Florian Fainellid1565762017-10-11 10:57:50 -07002616 if (ret) {
2617 dev_err(&pdev->dev, "failed to register DSA notifier\n");
2618 goto err_deregister_fixed_link;
2619 }
2620
Florian Fainelli80105be2014-04-24 18:08:57 -07002621 ret = register_netdev(dev);
2622 if (ret) {
2623 dev_err(&pdev->dev, "failed to register net_device\n");
Florian Fainellid1565762017-10-11 10:57:50 -07002624 goto err_deregister_notifier;
Florian Fainelli80105be2014-04-24 18:08:57 -07002625 }
2626
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002627 clk_prepare_enable(priv->clk);
2628
Florian Fainelli80105be2014-04-24 18:08:57 -07002629 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
2630 dev_info(&pdev->dev,
Florian Fainelli62be7572019-03-20 09:45:17 -07002631 "Broadcom SYSTEMPORT%s " REV_FMT
2632 " (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
Florian Fainelli44a45242017-01-20 11:08:27 -08002633 priv->is_lite ? " Lite" : "",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002634 (priv->rev >> 8) & 0xff, priv->rev & 0xff,
Florian Fainelli62be7572019-03-20 09:45:17 -07002635 priv->irq0, priv->irq1, txq, rxq);
Florian Fainelli80105be2014-04-24 18:08:57 -07002636
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002637 clk_disable_unprepare(priv->clk);
2638
Florian Fainelli80105be2014-04-24 18:08:57 -07002639 return 0;
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002640
Florian Fainellid1565762017-10-11 10:57:50 -07002641err_deregister_notifier:
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002642 unregister_netdevice_notifier(&priv->netdev_notifier);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002643err_deregister_fixed_link:
2644 if (of_phy_is_fixed_link(dn))
2645 of_phy_deregister_fixed_link(dn);
2646err_free_netdev:
Florian Fainelli80105be2014-04-24 18:08:57 -07002647 free_netdev(dev);
2648 return ret;
2649}
2650
Uwe Kleine-Königd4295df2023-09-18 22:41:43 +02002651static void bcm_sysport_remove(struct platform_device *pdev)
Florian Fainelli80105be2014-04-24 18:08:57 -07002652{
2653 struct net_device *dev = dev_get_drvdata(&pdev->dev);
Florian Fainellid1565762017-10-11 10:57:50 -07002654 struct bcm_sysport_priv *priv = netdev_priv(dev);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002655 struct device_node *dn = pdev->dev.of_node;
Florian Fainelli80105be2014-04-24 18:08:57 -07002656
2657 /* Not much to do, ndo_close has been called
2658 * and we use managed allocations
2659 */
Vladimir Oltean1593cd42021-01-07 03:24:02 +02002660 unregister_netdevice_notifier(&priv->netdev_notifier);
Florian Fainelli80105be2014-04-24 18:08:57 -07002661 unregister_netdev(dev);
Johan Hovold39f8b0d2016-11-28 19:24:58 +01002662 if (of_phy_is_fixed_link(dn))
2663 of_phy_deregister_fixed_link(dn);
Florian Fainelli80105be2014-04-24 18:08:57 -07002664 free_netdev(dev);
2665 dev_set_drvdata(&pdev->dev, NULL);
Florian Fainelli80105be2014-04-24 18:08:57 -07002666}
2667
Florian Fainelli83e82f42014-07-01 21:08:40 -07002668static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
2669{
2670 struct net_device *ndev = priv->netdev;
2671 unsigned int timeout = 1000;
Florian Fainellibb9051a22018-08-07 10:50:23 -07002672 unsigned int index, i = 0;
Florian Fainelli83e82f42014-07-01 21:08:40 -07002673 u32 reg;
2674
Florian Fainelli83e82f42014-07-01 21:08:40 -07002675 reg = umac_readl(priv, UMAC_MPD_CTRL);
Florian Fainellibb9051a22018-08-07 10:50:23 -07002676 if (priv->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE))
2677 reg |= MPD_EN;
Florian Fainelli83e82f42014-07-01 21:08:40 -07002678 reg &= ~PSW_EN;
Florian Fainelli8dfb8d22019-02-01 13:23:38 -08002679 if (priv->wolopts & WAKE_MAGICSECURE) {
2680 /* Program the SecureOn password */
2681 umac_writel(priv, get_unaligned_be16(&priv->sopass[0]),
2682 UMAC_PSW_MS);
2683 umac_writel(priv, get_unaligned_be32(&priv->sopass[2]),
2684 UMAC_PSW_LS);
Florian Fainelli83e82f42014-07-01 21:08:40 -07002685 reg |= PSW_EN;
Florian Fainelli8dfb8d22019-02-01 13:23:38 -08002686 }
Florian Fainelli83e82f42014-07-01 21:08:40 -07002687 umac_writel(priv, reg, UMAC_MPD_CTRL);
2688
Florian Fainellibb9051a22018-08-07 10:50:23 -07002689 if (priv->wolopts & WAKE_FILTER) {
2690 /* Turn on ACPI matching to steal packets from RBUF */
2691 reg = rbuf_readl(priv, RBUF_CONTROL);
2692 if (priv->is_lite)
2693 reg |= RBUF_ACPI_EN_LITE;
2694 else
2695 reg |= RBUF_ACPI_EN;
2696 rbuf_writel(priv, reg, RBUF_CONTROL);
2697
2698 /* Enable RXCHK, active filters and Broadcom tag matching */
2699 reg = rxchk_readl(priv, RXCHK_CONTROL);
2700 reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK <<
2701 RXCHK_BRCM_TAG_MATCH_SHIFT);
2702 for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
2703 reg |= BIT(RXCHK_BRCM_TAG_MATCH_SHIFT + i);
2704 i++;
2705 }
2706 reg |= RXCHK_EN | RXCHK_BRCM_TAG_EN;
2707 rxchk_writel(priv, reg, RXCHK_CONTROL);
2708 }
2709
Florian Fainelli83e82f42014-07-01 21:08:40 -07002710 /* Make sure RBUF entered WoL mode as result */
2711 do {
2712 reg = rbuf_readl(priv, RBUF_STATUS);
2713 if (reg & RBUF_WOL_MODE)
2714 break;
2715
2716 udelay(10);
2717 } while (timeout-- > 0);
2718
2719 /* Do not leave the UniMAC RBUF matching only MPD packets */
2720 if (!timeout) {
Florian Fainelli542261162018-08-03 11:08:44 -07002721 mpd_enable_set(priv, false);
Florian Fainelli83e82f42014-07-01 21:08:40 -07002722 netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
2723 return -ETIMEDOUT;
2724 }
2725
2726 /* UniMAC receive needs to be turned on */
2727 umac_enable_set(priv, CMD_RX_EN, 1);
2728
Florian Fainelli83e82f42014-07-01 21:08:40 -07002729 netif_dbg(priv, wol, ndev, "entered WOL mode\n");
2730
2731 return 0;
2732}
2733
Arnd Bergmanncf876152018-08-14 00:10:34 +02002734static int __maybe_unused bcm_sysport_suspend(struct device *d)
Florian Fainelli40755a02014-07-01 21:08:38 -07002735{
2736 struct net_device *dev = dev_get_drvdata(d);
2737 struct bcm_sysport_priv *priv = netdev_priv(dev);
2738 unsigned int i;
Florian Fainelli83e82f42014-07-01 21:08:40 -07002739 int ret = 0;
Florian Fainelli40755a02014-07-01 21:08:38 -07002740 u32 reg;
2741
2742 if (!netif_running(dev))
2743 return 0;
2744
Florian Fainelli7cb6a2a2018-11-01 15:55:38 -07002745 netif_device_detach(dev);
2746
Florian Fainelli40755a02014-07-01 21:08:38 -07002747 bcm_sysport_netif_stop(dev);
2748
Philippe Reynes715a0222016-06-19 20:39:08 +02002749 phy_suspend(dev->phydev);
Florian Fainelli40755a02014-07-01 21:08:38 -07002750
Florian Fainelli40755a02014-07-01 21:08:38 -07002751 /* Disable UniMAC RX */
2752 umac_enable_set(priv, CMD_RX_EN, 0);
2753
2754 ret = rdma_enable_set(priv, 0);
2755 if (ret) {
2756 netdev_err(dev, "RDMA timeout!\n");
2757 return ret;
2758 }
2759
2760 /* Disable RXCHK if enabled */
Florian Fainelli9d34c1cb2014-07-01 21:08:39 -07002761 if (priv->rx_chk_en) {
Florian Fainelli40755a02014-07-01 21:08:38 -07002762 reg = rxchk_readl(priv, RXCHK_CONTROL);
2763 reg &= ~RXCHK_EN;
2764 rxchk_writel(priv, reg, RXCHK_CONTROL);
2765 }
2766
2767 /* Flush RX pipe */
Florian Fainelli83e82f42014-07-01 21:08:40 -07002768 if (!priv->wolopts)
2769 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
Florian Fainelli40755a02014-07-01 21:08:38 -07002770
2771 ret = tdma_enable_set(priv, 0);
2772 if (ret) {
2773 netdev_err(dev, "TDMA timeout!\n");
2774 return ret;
2775 }
2776
2777 /* Wait for a packet boundary */
2778 usleep_range(2000, 3000);
2779
2780 umac_enable_set(priv, CMD_TX_EN, 0);
2781
2782 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
2783
2784 /* Free RX/TX rings SW structures */
2785 for (i = 0; i < dev->num_tx_queues; i++)
2786 bcm_sysport_fini_tx_ring(priv, i);
2787 bcm_sysport_fini_rx_ring(priv);
2788
Florian Fainelli83e82f42014-07-01 21:08:40 -07002789 /* Get prepared for Wake-on-LAN */
Florian Fainelli6328a122020-09-01 14:43:48 -07002790 if (device_may_wakeup(d) && priv->wolopts) {
2791 clk_prepare_enable(priv->wol_clk);
Florian Fainelli83e82f42014-07-01 21:08:40 -07002792 ret = bcm_sysport_suspend_to_wol(priv);
Florian Fainelli6328a122020-09-01 14:43:48 -07002793 }
Florian Fainelli83e82f42014-07-01 21:08:40 -07002794
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002795 clk_disable_unprepare(priv->clk);
2796
Florian Fainelli83e82f42014-07-01 21:08:40 -07002797 return ret;
Florian Fainelli40755a02014-07-01 21:08:38 -07002798}
2799
Arnd Bergmanncf876152018-08-14 00:10:34 +02002800static int __maybe_unused bcm_sysport_resume(struct device *d)
Florian Fainelli40755a02014-07-01 21:08:38 -07002801{
2802 struct net_device *dev = dev_get_drvdata(d);
2803 struct bcm_sysport_priv *priv = netdev_priv(dev);
2804 unsigned int i;
Florian Fainelli40755a02014-07-01 21:08:38 -07002805 int ret;
2806
2807 if (!netif_running(dev))
2808 return 0;
2809
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002810 clk_prepare_enable(priv->clk);
Florian Fainelli6328a122020-09-01 14:43:48 -07002811 if (priv->wolopts)
2812 clk_disable_unprepare(priv->wol_clk);
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002813
Florian Fainelli704d33e2014-10-28 11:12:01 -07002814 umac_reset(priv);
2815
Florian Fainelli263a4252020-02-05 12:32:04 -08002816 /* Disable the UniMAC RX/TX */
2817 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
2818
Florian Fainelli83e82f42014-07-01 21:08:40 -07002819 /* We may have been suspended and never received a WOL event that
2820 * would turn off MPD detection, take care of that now
2821 */
2822 bcm_sysport_resume_from_wol(priv);
2823
Florian Fainelli40755a02014-07-01 21:08:38 -07002824 /* Initialize both hardware and software ring */
2825 for (i = 0; i < dev->num_tx_queues; i++) {
2826 ret = bcm_sysport_init_tx_ring(priv, i);
2827 if (ret) {
2828 netdev_err(dev, "failed to initialize TX ring %d\n",
Florian Fainelli23acb2f2014-07-09 17:36:46 -07002829 i);
Florian Fainelli40755a02014-07-01 21:08:38 -07002830 goto out_free_tx_rings;
2831 }
2832 }
2833
2834 /* Initialize linked-list */
2835 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
2836
2837 /* Initialize RX ring */
2838 ret = bcm_sysport_init_rx_ring(priv);
2839 if (ret) {
2840 netdev_err(dev, "failed to initialize RX ring\n");
2841 goto out_free_rx_ring;
2842 }
2843
Florian Fainelli40755a02014-07-01 21:08:38 -07002844 /* RX pipe enable */
2845 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
2846
2847 ret = rdma_enable_set(priv, 1);
2848 if (ret) {
2849 netdev_err(dev, "failed to enable RDMA\n");
2850 goto out_free_rx_ring;
2851 }
2852
Florian Fainelli297357d2018-09-27 15:36:11 -07002853 /* Restore enabled features */
2854 bcm_sysport_set_features(dev, dev->features);
Florian Fainelli40755a02014-07-01 21:08:38 -07002855
2856 rbuf_init(priv);
2857
2858 /* Set maximum frame length */
Florian Fainelli44a45242017-01-20 11:08:27 -08002859 if (!priv->is_lite)
2860 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2861 else
2862 gib_set_pad_extension(priv);
Florian Fainelli40755a02014-07-01 21:08:38 -07002863
2864 /* Set MAC address */
2865 umac_set_hw_addr(priv, dev->dev_addr);
2866
2867 umac_enable_set(priv, CMD_RX_EN, 1);
2868
2869 /* TX pipe enable */
2870 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
2871
2872 umac_enable_set(priv, CMD_TX_EN, 1);
2873
2874 ret = tdma_enable_set(priv, 1);
2875 if (ret) {
2876 netdev_err(dev, "TDMA timeout!\n");
2877 goto out_free_rx_ring;
2878 }
2879
Philippe Reynes715a0222016-06-19 20:39:08 +02002880 phy_resume(dev->phydev);
Florian Fainelli40755a02014-07-01 21:08:38 -07002881
2882 bcm_sysport_netif_start(dev);
2883
Florian Fainelli7cb6a2a2018-11-01 15:55:38 -07002884 netif_device_attach(dev);
2885
Florian Fainelli40755a02014-07-01 21:08:38 -07002886 return 0;
2887
2888out_free_rx_ring:
2889 bcm_sysport_fini_rx_ring(priv);
2890out_free_tx_rings:
2891 for (i = 0; i < dev->num_tx_queues; i++)
2892 bcm_sysport_fini_tx_ring(priv, i);
Florian Fainelli31bc72d2020-09-01 14:43:47 -07002893 clk_disable_unprepare(priv->clk);
Florian Fainelli40755a02014-07-01 21:08:38 -07002894 return ret;
2895}
Florian Fainelli40755a02014-07-01 21:08:38 -07002896
2897static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
2898 bcm_sysport_suspend, bcm_sysport_resume);
2899
Florian Fainelli80105be2014-04-24 18:08:57 -07002900static struct platform_driver bcm_sysport_driver = {
2901 .probe = bcm_sysport_probe,
Uwe Kleine-Königd4295df2023-09-18 22:41:43 +02002902 .remove_new = bcm_sysport_remove,
Florian Fainelli80105be2014-04-24 18:08:57 -07002903 .driver = {
2904 .name = "brcm-systemport",
Florian Fainelli80105be2014-04-24 18:08:57 -07002905 .of_match_table = bcm_sysport_of_match,
Florian Fainelli40755a02014-07-01 21:08:38 -07002906 .pm = &bcm_sysport_pm_ops,
Florian Fainelli80105be2014-04-24 18:08:57 -07002907 },
2908};
2909module_platform_driver(bcm_sysport_driver);
2910
2911MODULE_AUTHOR("Broadcom Corporation");
2912MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
2913MODULE_ALIAS("platform:brcm-systemport");
2914MODULE_LICENSE("GPL");