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Neil Armstrong91d59bd2019-05-20 16:00:07 +02001// SPDX-License-Identifier: GPL-2.0
Carlo Caionee4a6b372014-09-29 01:50:05 +02002/*
3 * Amlogic Meson6 SoCs timer handling.
4 *
5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
6 *
7 * Based on code from Amlogic, Inc
Carlo Caionee4a6b372014-09-29 01:50:05 +02008 */
9
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010010#include <linux/bitfield.h>
11#include <linux/bitops.h>
Carlo Caionee4a6b372014-09-29 01:50:05 +020012#include <linux/clk.h>
13#include <linux/clockchips.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/irqreturn.h>
17#include <linux/sched_clock.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21
Martin Blumenstinglfa83c6f2018-11-15 23:46:57 +010022#ifdef CONFIG_ARM
23#include <linux/delay.h>
24#endif
25
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010026#define MESON_ISA_TIMER_MUX 0x00
27#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19)
28#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18)
29#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17)
30#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16)
31#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15)
32#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14)
33#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13)
34#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12)
35#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8)
36#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0
37#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1
38#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2
39#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3
40#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4
41#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6)
42#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4)
43#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2)
44#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0)
45#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0
46#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1
47#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0
48#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3
Carlo Caionee4a6b372014-09-29 01:50:05 +020049
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010050#define MESON_ISA_TIMERA 0x04
51#define MESON_ISA_TIMERB 0x08
52#define MESON_ISA_TIMERC 0x0c
53#define MESON_ISA_TIMERD 0x10
54#define MESON_ISA_TIMERE 0x14
Carlo Caionee4a6b372014-09-29 01:50:05 +020055
56static void __iomem *timer_base;
57
Martin Blumenstinglfa83c6f2018-11-15 23:46:57 +010058#ifdef CONFIG_ARM
59static unsigned long meson6_read_current_timer(void)
60{
61 return readl_relaxed(timer_base + MESON_ISA_TIMERE);
62}
63
64static struct delay_timer meson6_delay_timer = {
65 .read_current_timer = meson6_read_current_timer,
66 .freq = 1000 * 1000,
67};
68#endif
69
Carlo Caionee4a6b372014-09-29 01:50:05 +020070static u64 notrace meson6_timer_sched_read(void)
71{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010072 return (u64)readl(timer_base + MESON_ISA_TIMERE);
Carlo Caionee4a6b372014-09-29 01:50:05 +020073}
74
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010075static void meson6_clkevt_time_stop(void)
Carlo Caionee4a6b372014-09-29 01:50:05 +020076{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010077 u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
Carlo Caionee4a6b372014-09-29 01:50:05 +020078
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010079 writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN,
80 timer_base + MESON_ISA_TIMER_MUX);
Carlo Caionee4a6b372014-09-29 01:50:05 +020081}
82
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010083static void meson6_clkevt_time_setup(unsigned long delay)
Carlo Caionee4a6b372014-09-29 01:50:05 +020084{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010085 writel(delay, timer_base + MESON_ISA_TIMERA);
Carlo Caionee4a6b372014-09-29 01:50:05 +020086}
87
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010088static void meson6_clkevt_time_start(bool periodic)
Carlo Caionee4a6b372014-09-29 01:50:05 +020089{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010090 u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
Carlo Caionee4a6b372014-09-29 01:50:05 +020091
92 if (periodic)
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010093 val |= MESON_ISA_TIMER_MUX_TIMERA_MODE;
Carlo Caionee4a6b372014-09-29 01:50:05 +020094 else
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010095 val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE;
Carlo Caionee4a6b372014-09-29 01:50:05 +020096
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +010097 writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN,
98 timer_base + MESON_ISA_TIMER_MUX);
Carlo Caionee4a6b372014-09-29 01:50:05 +020099}
100
Viresh Kumar40117bd2015-06-18 16:24:23 +0530101static int meson6_shutdown(struct clock_event_device *evt)
Carlo Caionee4a6b372014-09-29 01:50:05 +0200102{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100103 meson6_clkevt_time_stop();
Viresh Kumar40117bd2015-06-18 16:24:23 +0530104 return 0;
105}
106
107static int meson6_set_oneshot(struct clock_event_device *evt)
108{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100109 meson6_clkevt_time_stop();
110 meson6_clkevt_time_start(false);
Viresh Kumar40117bd2015-06-18 16:24:23 +0530111 return 0;
112}
113
114static int meson6_set_periodic(struct clock_event_device *evt)
115{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100116 meson6_clkevt_time_stop();
117 meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1);
118 meson6_clkevt_time_start(true);
Viresh Kumar40117bd2015-06-18 16:24:23 +0530119 return 0;
Carlo Caionee4a6b372014-09-29 01:50:05 +0200120}
121
122static int meson6_clkevt_next_event(unsigned long evt,
123 struct clock_event_device *unused)
124{
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100125 meson6_clkevt_time_stop();
126 meson6_clkevt_time_setup(evt);
127 meson6_clkevt_time_start(false);
Carlo Caionee4a6b372014-09-29 01:50:05 +0200128
129 return 0;
130}
131
132static struct clock_event_device meson6_clockevent = {
Viresh Kumar40117bd2015-06-18 16:24:23 +0530133 .name = "meson6_tick",
134 .rating = 400,
135 .features = CLOCK_EVT_FEAT_PERIODIC |
136 CLOCK_EVT_FEAT_ONESHOT,
137 .set_state_shutdown = meson6_shutdown,
138 .set_state_periodic = meson6_set_periodic,
139 .set_state_oneshot = meson6_set_oneshot,
140 .tick_resume = meson6_shutdown,
141 .set_next_event = meson6_clkevt_next_event,
Carlo Caionee4a6b372014-09-29 01:50:05 +0200142};
143
144static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
145{
146 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
147
148 evt->event_handler(evt);
149
150 return IRQ_HANDLED;
151}
152
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200153static int __init meson6_timer_init(struct device_node *node)
Carlo Caionee4a6b372014-09-29 01:50:05 +0200154{
155 u32 val;
156 int ret, irq;
157
158 timer_base = of_io_request_and_map(node, 0, "meson6-timer");
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200159 if (IS_ERR(timer_base)) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100160 pr_err("Can't map registers\n");
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200161 return -ENXIO;
162 }
Carlo Caionee4a6b372014-09-29 01:50:05 +0200163
164 irq = irq_of_parse_and_map(node, 0);
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200165 if (irq <= 0) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100166 pr_err("Can't parse IRQ\n");
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200167 return -EINVAL;
168 }
Carlo Caionee4a6b372014-09-29 01:50:05 +0200169
170 /* Set 1us for timer E */
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100171 val = readl(timer_base + MESON_ISA_TIMER_MUX);
172 val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK;
173 val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK,
174 MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US);
175 writel(val, timer_base + MESON_ISA_TIMER_MUX);
Carlo Caionee4a6b372014-09-29 01:50:05 +0200176
177 sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100178 clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name,
Carlo Caionee4a6b372014-09-29 01:50:05 +0200179 1000 * 1000, 300, 32, clocksource_mmio_readl_up);
180
181 /* Timer A base 1us */
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100182 val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK;
183 val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK,
184 MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US);
185 writel(val, timer_base + MESON_ISA_TIMER_MUX);
Carlo Caionee4a6b372014-09-29 01:50:05 +0200186
187 /* Stop the timer A */
Martin Blumenstinglbed8fc12018-11-15 23:46:56 +0100188 meson6_clkevt_time_stop();
Carlo Caionee4a6b372014-09-29 01:50:05 +0200189
afzal mohammedcc2550b2020-02-27 16:29:02 +0530190 ret = request_irq(irq, meson6_timer_interrupt,
191 IRQF_TIMER | IRQF_IRQPOLL, "meson6_timer",
192 &meson6_clockevent);
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200193 if (ret) {
Carlo Caionee4a6b372014-09-29 01:50:05 +0200194 pr_warn("failed to setup irq %d\n", irq);
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200195 return ret;
196 }
Carlo Caionee4a6b372014-09-29 01:50:05 +0200197
198 meson6_clockevent.cpumask = cpu_possible_mask;
199 meson6_clockevent.irq = irq;
200
201 clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
202 1, 0xfffe);
Martin Blumenstinglfa83c6f2018-11-15 23:46:57 +0100203
204#ifdef CONFIG_ARM
205 /* Also use MESON_ISA_TIMERE for delays */
206 register_current_timer_delay(&meson6_delay_timer);
207#endif
208
Daniel Lezcanoca46acb2016-06-06 17:57:07 +0200209 return 0;
Carlo Caionee4a6b372014-09-29 01:50:05 +0200210}
Daniel Lezcano17273392017-05-26 16:56:11 +0200211TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",
Carlo Caionee4a6b372014-09-29 01:50:05 +0200212 meson6_timer_init);