Thomas Gleixner | 4fa9c49f | 2019-05-29 07:18:05 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 2 | /******************************************************************************* |
| 3 | STMMAC Common Header File |
| 4 | |
| 5 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
| 6 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 7 | |
| 8 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| 9 | *******************************************************************************/ |
| 10 | |
Rayagond Kokatanur | bd4242d | 2012-08-22 21:28:18 +0000 | [diff] [blame] | 11 | #ifndef __COMMON_H__ |
| 12 | #define __COMMON_H__ |
| 13 | |
Giuseppe CAVALLARO | bfab27a | 2011-12-21 03:58:19 +0000 | [diff] [blame] | 14 | #include <linux/etherdevice.h> |
Giuseppe CAVALLARO | 5e33c791 | 2010-01-06 23:07:21 +0000 | [diff] [blame] | 15 | #include <linux/netdevice.h> |
Giuseppe Cavallaro | afea036 | 2016-02-29 14:27:28 +0100 | [diff] [blame] | 16 | #include <linux/stmmac.h> |
Giuseppe CAVALLARO | bfab27a | 2011-12-21 03:58:19 +0000 | [diff] [blame] | 17 | #include <linux/phy.h> |
Andrew Lunn | 2fa4e4b | 2020-08-27 04:00:28 +0200 | [diff] [blame] | 18 | #include <linux/pcs/pcs-xpcs.h> |
Giuseppe CAVALLARO | bfab27a | 2011-12-21 03:58:19 +0000 | [diff] [blame] | 19 | #include <linux/module.h> |
Javier Martinez Canillas | 12c70f3 | 2016-09-12 10:03:44 -0400 | [diff] [blame] | 20 | #if IS_ENABLED(CONFIG_VLAN_8021Q) |
Giuseppe CAVALLARO | 8f61754 | 2010-04-13 20:21:16 +0000 | [diff] [blame] | 21 | #define STMMAC_VLAN_TAG_USED |
| 22 | #include <linux/if_vlan.h> |
| 23 | #endif |
| 24 | |
Giuseppe CAVALLARO | 56b106a | 2010-04-13 20:21:12 +0000 | [diff] [blame] | 25 | #include "descs.h" |
Jose Abreu | 42de047 | 2018-04-16 16:08:12 +0100 | [diff] [blame] | 26 | #include "hwif.h" |
Giuseppe CAVALLARO | 1c901a4 | 2011-09-01 21:51:38 +0000 | [diff] [blame] | 27 | #include "mmc.h" |
Giuseppe CAVALLARO | 56b106a | 2010-04-13 20:21:12 +0000 | [diff] [blame] | 28 | |
Giuseppe CAVALLARO | 62a2ab9 | 2012-11-25 23:10:43 +0000 | [diff] [blame] | 29 | /* Synopsys Core versions */ |
Jose Abreu | 48ae555 | 2018-08-08 09:04:29 +0100 | [diff] [blame] | 30 | #define DWMAC_CORE_3_40 0x34 |
| 31 | #define DWMAC_CORE_3_50 0x35 |
| 32 | #define DWMAC_CORE_4_00 0x40 |
| 33 | #define DWMAC_CORE_4_10 0x41 |
| 34 | #define DWMAC_CORE_5_00 0x50 |
| 35 | #define DWMAC_CORE_5_10 0x51 |
Mohammad Athari Bin Ismail | 96874c6 | 2021-04-22 15:55:00 +0800 | [diff] [blame] | 36 | #define DWMAC_CORE_5_20 0x52 |
Jose Abreu | 48ae555 | 2018-08-08 09:04:29 +0100 | [diff] [blame] | 37 | #define DWXGMAC_CORE_2_10 0x21 |
Jose Abreu | 4a4ccde | 2020-03-17 10:18:52 +0100 | [diff] [blame] | 38 | #define DWXLGMAC_CORE_2_00 0x20 |
| 39 | |
| 40 | /* Device ID */ |
| 41 | #define DWXGMAC_ID 0x76 |
| 42 | #define DWXLGMAC_ID 0x27 |
Jose Abreu | 48ae555 | 2018-08-08 09:04:29 +0100 | [diff] [blame] | 43 | |
Alexandre TORGUE | 48863ce | 2016-04-01 11:37:30 +0200 | [diff] [blame] | 44 | #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ |
Giuseppe CAVALLARO | 62a2ab9 | 2012-11-25 23:10:43 +0000 | [diff] [blame] | 45 | |
Song, Yoong Siang | aa042f6 | 2020-09-16 15:40:20 +0800 | [diff] [blame] | 46 | /* TX and RX Descriptor Length, these need to be power of two. |
| 47 | * TX descriptor length less than 64 may cause transmit queue timed out error. |
| 48 | * RX descriptor length less than 64 may cause inconsistent Rx chain error. |
| 49 | */ |
| 50 | #define DMA_MIN_TX_SIZE 64 |
| 51 | #define DMA_MAX_TX_SIZE 1024 |
| 52 | #define DMA_DEFAULT_TX_SIZE 512 |
| 53 | #define DMA_MIN_RX_SIZE 64 |
| 54 | #define DMA_MAX_RX_SIZE 1024 |
| 55 | #define DMA_DEFAULT_RX_SIZE 512 |
Giuseppe Cavallaro | e3ad57c | 2016-02-29 14:27:30 +0100 | [diff] [blame] | 56 | #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) |
| 57 | |
Giuseppe CAVALLARO | 56b106a | 2010-04-13 20:21:12 +0000 | [diff] [blame] | 58 | #undef FRAME_FILTER_DEBUG |
| 59 | /* #define FRAME_FILTER_DEBUG */ |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 60 | |
Vijayakannan Ayyathurai | 68e9c5d | 2021-08-16 14:15:59 +0800 | [diff] [blame] | 61 | struct stmmac_txq_stats { |
| 62 | unsigned long tx_pkt_n; |
Vijayakannan Ayyathurai | af9bf70 | 2021-08-16 14:16:00 +0800 | [diff] [blame] | 63 | unsigned long tx_normal_irq_n; |
Vijayakannan Ayyathurai | 68e9c5d | 2021-08-16 14:15:59 +0800 | [diff] [blame] | 64 | }; |
| 65 | |
| 66 | struct stmmac_rxq_stats { |
| 67 | unsigned long rx_pkt_n; |
Vijayakannan Ayyathurai | af9bf70 | 2021-08-16 14:16:00 +0800 | [diff] [blame] | 68 | unsigned long rx_normal_irq_n; |
Vijayakannan Ayyathurai | 68e9c5d | 2021-08-16 14:15:59 +0800 | [diff] [blame] | 69 | }; |
| 70 | |
Giuseppe CAVALLARO | 915c199 | 2014-11-18 09:47:00 +0100 | [diff] [blame] | 71 | /* Extra statistic and debug information exposed by ethtool */ |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 72 | struct stmmac_extra_stats { |
| 73 | /* Transmit errors */ |
| 74 | unsigned long tx_underflow ____cacheline_aligned; |
| 75 | unsigned long tx_carrier; |
| 76 | unsigned long tx_losscarrier; |
Giuseppe CAVALLARO | 3c20f72 | 2011-10-26 19:43:09 +0000 | [diff] [blame] | 77 | unsigned long vlan_tag; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 78 | unsigned long tx_deferred; |
| 79 | unsigned long tx_vlan; |
| 80 | unsigned long tx_jabber; |
| 81 | unsigned long tx_frame_flushed; |
| 82 | unsigned long tx_payload_error; |
| 83 | unsigned long tx_ip_header_error; |
| 84 | /* Receive errors */ |
| 85 | unsigned long rx_desc; |
Giuseppe CAVALLARO | 3c20f72 | 2011-10-26 19:43:09 +0000 | [diff] [blame] | 86 | unsigned long sa_filter_fail; |
| 87 | unsigned long overflow_error; |
| 88 | unsigned long ipc_csum_error; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 89 | unsigned long rx_collision; |
LABBE Corentin | e0a7660 | 2017-02-08 09:31:17 +0100 | [diff] [blame] | 90 | unsigned long rx_crc_errors; |
Giuseppe CAVALLARO | 1cc5a73 | 2012-02-15 00:10:37 +0000 | [diff] [blame] | 91 | unsigned long dribbling_bit; |
Giuseppe Cavallaro | 1b92403 | 2010-02-04 09:33:21 -0800 | [diff] [blame] | 92 | unsigned long rx_length; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 93 | unsigned long rx_mii; |
| 94 | unsigned long rx_multicast; |
| 95 | unsigned long rx_gmac_overflow; |
| 96 | unsigned long rx_watchdog; |
| 97 | unsigned long da_rx_filter_fail; |
| 98 | unsigned long sa_rx_filter_fail; |
| 99 | unsigned long rx_missed_cntr; |
| 100 | unsigned long rx_overflow_cntr; |
| 101 | unsigned long rx_vlan; |
Jose Abreu | b5418e1 | 2019-08-17 20:54:44 +0200 | [diff] [blame] | 102 | unsigned long rx_split_hdr_pkt_n; |
Giuseppe CAVALLARO | 62a2ab9 | 2012-11-25 23:10:43 +0000 | [diff] [blame] | 103 | /* Tx/Rx IRQ error info */ |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 104 | unsigned long tx_undeflow_irq; |
| 105 | unsigned long tx_process_stopped_irq; |
| 106 | unsigned long tx_jabber_irq; |
| 107 | unsigned long rx_overflow_irq; |
| 108 | unsigned long rx_buf_unav_irq; |
| 109 | unsigned long rx_process_stopped_irq; |
| 110 | unsigned long rx_watchdog_irq; |
| 111 | unsigned long tx_early_irq; |
| 112 | unsigned long fatal_bus_error_irq; |
Giuseppe CAVALLARO | 62a2ab9 | 2012-11-25 23:10:43 +0000 | [diff] [blame] | 113 | /* Tx/Rx IRQ Events */ |
| 114 | unsigned long rx_early_irq; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 115 | unsigned long threshold; |
| 116 | unsigned long tx_pkt_n; |
| 117 | unsigned long rx_pkt_n; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 118 | unsigned long normal_irq_n; |
Giuseppe CAVALLARO | 9125cdd | 2012-11-25 23:10:42 +0000 | [diff] [blame] | 119 | unsigned long rx_normal_irq_n; |
| 120 | unsigned long napi_poll; |
| 121 | unsigned long tx_normal_irq_n; |
| 122 | unsigned long tx_clean; |
Giuseppe Cavallaro | 0e80bdc | 2016-02-29 14:27:38 +0100 | [diff] [blame] | 123 | unsigned long tx_set_ic_bit; |
Giuseppe CAVALLARO | 62a2ab9 | 2012-11-25 23:10:43 +0000 | [diff] [blame] | 124 | unsigned long irq_receive_pmt_irq_n; |
| 125 | /* MMC info */ |
Giuseppe CAVALLARO | d765955 | 2012-06-27 21:14:37 +0000 | [diff] [blame] | 126 | unsigned long mmc_tx_irq_n; |
| 127 | unsigned long mmc_rx_irq_n; |
| 128 | unsigned long mmc_rx_csum_offload_irq_n; |
| 129 | /* EEE */ |
Giuseppe CAVALLARO | d765955 | 2012-06-27 21:14:37 +0000 | [diff] [blame] | 130 | unsigned long irq_tx_path_in_lpi_mode_n; |
| 131 | unsigned long irq_tx_path_exit_lpi_mode_n; |
| 132 | unsigned long irq_rx_path_in_lpi_mode_n; |
| 133 | unsigned long irq_rx_path_exit_lpi_mode_n; |
| 134 | unsigned long phy_eee_wakeup_error_n; |
Giuseppe CAVALLARO | c24602e | 2013-03-26 04:43:06 +0000 | [diff] [blame] | 135 | /* Extended RDES status */ |
| 136 | unsigned long ip_hdr_err; |
| 137 | unsigned long ip_payload_err; |
| 138 | unsigned long ip_csum_bypassed; |
| 139 | unsigned long ipv4_pkt_rcvd; |
| 140 | unsigned long ipv6_pkt_rcvd; |
Giuseppe CAVALLARO | ee112c1 | 2016-11-14 09:27:30 +0100 | [diff] [blame] | 141 | unsigned long no_ptp_rx_msg_type_ext; |
| 142 | unsigned long ptp_rx_msg_type_sync; |
| 143 | unsigned long ptp_rx_msg_type_follow_up; |
| 144 | unsigned long ptp_rx_msg_type_delay_req; |
| 145 | unsigned long ptp_rx_msg_type_delay_resp; |
| 146 | unsigned long ptp_rx_msg_type_pdelay_req; |
| 147 | unsigned long ptp_rx_msg_type_pdelay_resp; |
| 148 | unsigned long ptp_rx_msg_type_pdelay_follow_up; |
| 149 | unsigned long ptp_rx_msg_type_announce; |
| 150 | unsigned long ptp_rx_msg_type_management; |
| 151 | unsigned long ptp_rx_msg_pkt_reserved_type; |
Giuseppe CAVALLARO | c24602e | 2013-03-26 04:43:06 +0000 | [diff] [blame] | 152 | unsigned long ptp_frame_type; |
| 153 | unsigned long ptp_ver; |
| 154 | unsigned long timestamp_dropped; |
| 155 | unsigned long av_pkt_rcvd; |
| 156 | unsigned long av_tagged_pkt_rcvd; |
| 157 | unsigned long vlan_tag_priority_val; |
| 158 | unsigned long l3_filter_match; |
| 159 | unsigned long l4_filter_match; |
| 160 | unsigned long l3_l4_filter_no_match; |
Giuseppe CAVALLARO | 0982a0f | 2013-03-26 04:43:07 +0000 | [diff] [blame] | 161 | /* PCS */ |
| 162 | unsigned long irq_pcs_ane_n; |
| 163 | unsigned long irq_pcs_link_n; |
| 164 | unsigned long irq_rgmii_n; |
Giuseppe CAVALLARO | e58bb43 | 2013-03-26 04:43:08 +0000 | [diff] [blame] | 165 | unsigned long pcs_link; |
| 166 | unsigned long pcs_duplex; |
| 167 | unsigned long pcs_speed; |
Giuseppe CAVALLARO | 2f7a791 | 2015-11-30 11:33:10 +0100 | [diff] [blame] | 168 | /* debug register */ |
| 169 | unsigned long mtl_tx_status_fifo_full; |
| 170 | unsigned long mtl_tx_fifo_not_empty; |
| 171 | unsigned long mmtl_fifo_ctrl; |
| 172 | unsigned long mtl_tx_fifo_read_ctrl_write; |
| 173 | unsigned long mtl_tx_fifo_read_ctrl_wait; |
| 174 | unsigned long mtl_tx_fifo_read_ctrl_read; |
| 175 | unsigned long mtl_tx_fifo_read_ctrl_idle; |
| 176 | unsigned long mac_tx_in_pause; |
| 177 | unsigned long mac_tx_frame_ctrl_xfer; |
| 178 | unsigned long mac_tx_frame_ctrl_idle; |
| 179 | unsigned long mac_tx_frame_ctrl_wait; |
| 180 | unsigned long mac_tx_frame_ctrl_pause; |
| 181 | unsigned long mac_gmii_tx_proto_engine; |
| 182 | unsigned long mtl_rx_fifo_fill_level_full; |
| 183 | unsigned long mtl_rx_fifo_fill_above_thresh; |
| 184 | unsigned long mtl_rx_fifo_fill_below_thresh; |
| 185 | unsigned long mtl_rx_fifo_fill_level_empty; |
| 186 | unsigned long mtl_rx_fifo_read_ctrl_flush; |
| 187 | unsigned long mtl_rx_fifo_read_ctrl_read_data; |
| 188 | unsigned long mtl_rx_fifo_read_ctrl_status; |
| 189 | unsigned long mtl_rx_fifo_read_ctrl_idle; |
| 190 | unsigned long mtl_rx_fifo_ctrl_active; |
| 191 | unsigned long mac_rx_frame_ctrl_fifo; |
| 192 | unsigned long mac_gmii_rx_proto_engine; |
Alexandre TORGUE | f748be5 | 2016-04-01 11:37:34 +0200 | [diff] [blame] | 193 | /* TSO */ |
| 194 | unsigned long tx_tso_frames; |
| 195 | unsigned long tx_tso_nfrags; |
Ong Boon Leong | 9f29895 | 2021-03-18 08:50:53 +0800 | [diff] [blame] | 196 | /* EST */ |
| 197 | unsigned long mtl_est_cgce; |
| 198 | unsigned long mtl_est_hlbs; |
| 199 | unsigned long mtl_est_hlbf; |
| 200 | unsigned long mtl_est_btre; |
| 201 | unsigned long mtl_est_btrlm; |
Vijayakannan Ayyathurai | 68e9c5d | 2021-08-16 14:15:59 +0800 | [diff] [blame] | 202 | /* per queue statistics */ |
| 203 | struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES]; |
| 204 | struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES]; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 205 | }; |
| 206 | |
Jose Abreu | 8bf993a | 2018-03-29 10:40:19 +0100 | [diff] [blame] | 207 | /* Safety Feature statistics exposed by ethtool */ |
| 208 | struct stmmac_safety_stats { |
| 209 | unsigned long mac_errors[32]; |
| 210 | unsigned long mtl_errors[32]; |
| 211 | unsigned long dma_errors[32]; |
| 212 | }; |
| 213 | |
| 214 | /* Number of fields in Safety Stats */ |
| 215 | #define STMMAC_SAFETY_FEAT_SIZE \ |
| 216 | (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) |
| 217 | |
Giuseppe CAVALLARO | cd7201f | 2012-04-04 04:33:27 +0000 | [diff] [blame] | 218 | /* CSR Frequency Access Defines*/ |
| 219 | #define CSR_F_35M 35000000 |
| 220 | #define CSR_F_60M 60000000 |
| 221 | #define CSR_F_100M 100000000 |
| 222 | #define CSR_F_150M 150000000 |
| 223 | #define CSR_F_250M 250000000 |
| 224 | #define CSR_F_300M 300000000 |
| 225 | |
| 226 | #define MAC_CSR_H_FRQ_MASK 0x20 |
| 227 | |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 228 | #define HASH_TABLE_SIZE 64 |
Vince Bridgers | f88203a | 2015-04-15 11:17:42 -0500 | [diff] [blame] | 229 | #define PAUSE_TIME 0xffff |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 230 | |
| 231 | /* Flow Control defines */ |
| 232 | #define FLOW_OFF 0 |
| 233 | #define FLOW_RX 1 |
| 234 | #define FLOW_TX 2 |
| 235 | #define FLOW_AUTO (FLOW_TX | FLOW_RX) |
| 236 | |
Giuseppe CAVALLARO | e58bb43 | 2013-03-26 04:43:08 +0000 | [diff] [blame] | 237 | /* PCS defines */ |
| 238 | #define STMMAC_PCS_RGMII (1 << 0) |
| 239 | #define STMMAC_PCS_SGMII (1 << 1) |
| 240 | #define STMMAC_PCS_TBI (1 << 2) |
| 241 | #define STMMAC_PCS_RTBI (1 << 3) |
| 242 | |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 243 | #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 244 | |
Rayagond Kokatanur | 1db123f | 2011-10-18 00:01:22 +0000 | [diff] [blame] | 245 | /* DAM HW feature register fields */ |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 246 | #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ |
| 247 | #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ |
| 248 | #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ |
| 249 | #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ |
| 250 | #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ |
| 251 | #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ |
| 252 | #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ |
| 253 | #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ |
| 254 | #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ |
| 255 | #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ |
| 256 | #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ |
| 257 | #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ |
| 258 | #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ |
| 259 | #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ |
| 260 | #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ |
| 261 | #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ |
| 262 | #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ |
| 263 | #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ |
| 264 | #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ |
| 265 | #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ |
| 266 | #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ |
| 267 | #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ |
| 268 | #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ |
| 269 | /* Timestamping with Internal System Time */ |
| 270 | #define DMA_HW_FEAT_INTTSEN 0x02000000 |
| 271 | #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ |
| 272 | #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ |
| 273 | #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ |
Giuseppe CAVALLARO | 0f1f88a | 2012-04-18 19:48:21 +0000 | [diff] [blame] | 274 | #define DEFAULT_DMA_PBL 8 |
Rayagond Kokatanur | 1db123f | 2011-10-18 00:01:22 +0000 | [diff] [blame] | 275 | |
Ong Boon Leong | 8532f61 | 2021-03-26 01:39:14 +0800 | [diff] [blame] | 276 | /* MSI defines */ |
| 277 | #define STMMAC_MSI_VEC_MAX 32 |
| 278 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 279 | /* PCS status and mask defines */ |
| 280 | #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ |
| 281 | #define PCS_LINK_IRQ BIT(1) /* PCS Link */ |
| 282 | #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ |
| 283 | |
Giuseppe CAVALLARO | 62a2ab9 | 2012-11-25 23:10:43 +0000 | [diff] [blame] | 284 | /* Max/Min RI Watchdog Timer count value */ |
| 285 | #define MAX_DMA_RIWT 0xff |
Jose Abreu | 01d1689 | 2019-06-28 09:29:14 +0200 | [diff] [blame] | 286 | #define MIN_DMA_RIWT 0x10 |
Jose Abreu | 4e4337c | 2019-11-14 12:42:46 +0100 | [diff] [blame] | 287 | #define DEF_DMA_RIWT 0xa0 |
Giuseppe CAVALLARO | 9125cdd | 2012-11-25 23:10:42 +0000 | [diff] [blame] | 288 | /* Tx coalesce parameters */ |
Jose Abreu | 8fce333 | 2018-09-17 09:22:56 +0100 | [diff] [blame] | 289 | #define STMMAC_COAL_TX_TIMER 1000 |
Giuseppe CAVALLARO | 9125cdd | 2012-11-25 23:10:42 +0000 | [diff] [blame] | 290 | #define STMMAC_MAX_COAL_TX_TICK 100000 |
| 291 | #define STMMAC_TX_MAX_FRAMES 256 |
Jose Abreu | da20245 | 2019-11-14 12:42:49 +0100 | [diff] [blame] | 292 | #define STMMAC_TX_FRAMES 25 |
| 293 | #define STMMAC_RX_FRAMES 0 |
Giuseppe CAVALLARO | 9125cdd | 2012-11-25 23:10:42 +0000 | [diff] [blame] | 294 | |
Joao Pinto | abe80fd | 2017-03-17 16:11:07 +0000 | [diff] [blame] | 295 | /* Packets types */ |
| 296 | enum packets_types { |
| 297 | PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ |
| 298 | PACKET_PTPQ = 0x2, /* PTP Packets */ |
| 299 | PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ |
| 300 | PACKET_UPQ = 0x4, /* Untagged Packets */ |
| 301 | PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ |
| 302 | }; |
| 303 | |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 304 | /* Rx IPC status */ |
| 305 | enum rx_frame_status { |
Fabrice Gasnier | c1fa321 | 2016-02-29 14:27:34 +0100 | [diff] [blame] | 306 | good_frame = 0x0, |
| 307 | discard_frame = 0x1, |
| 308 | csum_none = 0x2, |
| 309 | llc_snap = 0x4, |
| 310 | dma_own = 0x8, |
Alexandre TORGUE | 753a710 | 2016-04-01 11:37:28 +0200 | [diff] [blame] | 311 | rx_not_ls = 0x10, |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 312 | }; |
| 313 | |
Fabrice Gasnier | c363b65 | 2016-02-29 14:27:36 +0100 | [diff] [blame] | 314 | /* Tx status */ |
| 315 | enum tx_frame_status { |
| 316 | tx_done = 0x0, |
| 317 | tx_not_ls = 0x1, |
| 318 | tx_err = 0x2, |
| 319 | tx_dma_own = 0x4, |
Xiaoliang Yang | 3a6c12a | 2021-12-08 18:06:51 +0800 | [diff] [blame] | 320 | tx_err_bump_tc = 0x8, |
Fabrice Gasnier | c363b65 | 2016-02-29 14:27:36 +0100 | [diff] [blame] | 321 | }; |
| 322 | |
Giuseppe CAVALLARO | 9125cdd | 2012-11-25 23:10:42 +0000 | [diff] [blame] | 323 | enum dma_irq_status { |
| 324 | tx_hard_error = 0x1, |
| 325 | tx_hard_error_bump_tc = 0x2, |
| 326 | handle_rx = 0x4, |
| 327 | handle_tx = 0x8, |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 328 | }; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 329 | |
Ong Boon Leong | 7e1c520 | 2021-03-26 01:39:12 +0800 | [diff] [blame] | 330 | enum dma_irq_dir { |
| 331 | DMA_DIR_RX = 0x1, |
| 332 | DMA_DIR_TX = 0x2, |
| 333 | DMA_DIR_RXTX = 0x3, |
| 334 | }; |
| 335 | |
Ong Boon Leong | 8532f61 | 2021-03-26 01:39:14 +0800 | [diff] [blame] | 336 | enum request_irq_err { |
| 337 | REQ_IRQ_ERR_ALL, |
| 338 | REQ_IRQ_ERR_TX, |
| 339 | REQ_IRQ_ERR_RX, |
| 340 | REQ_IRQ_ERR_SFTY_UE, |
| 341 | REQ_IRQ_ERR_SFTY_CE, |
| 342 | REQ_IRQ_ERR_LPI, |
| 343 | REQ_IRQ_ERR_WOL, |
| 344 | REQ_IRQ_ERR_MAC, |
| 345 | REQ_IRQ_ERR_NO, |
| 346 | }; |
| 347 | |
Giuseppe CAVALLARO | 915c199 | 2014-11-18 09:47:00 +0100 | [diff] [blame] | 348 | /* EEE and LPI defines */ |
nandini sharma | 162fb1d | 2014-08-28 08:11:41 +0200 | [diff] [blame] | 349 | #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) |
| 350 | #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) |
| 351 | #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) |
| 352 | #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) |
Giuseppe CAVALLARO | 0982a0f | 2013-03-26 04:43:07 +0000 | [diff] [blame] | 353 | |
Ong Boon Leong | 5a55861 | 2021-03-24 17:07:42 +0800 | [diff] [blame] | 354 | /* FPE defines */ |
| 355 | #define FPE_EVENT_UNKNOWN 0 |
| 356 | #define FPE_EVENT_TRSP BIT(0) |
| 357 | #define FPE_EVENT_TVER BIT(1) |
| 358 | #define FPE_EVENT_RRSP BIT(2) |
| 359 | #define FPE_EVENT_RVER BIT(3) |
| 360 | |
Alexandre TORGUE | 48863ce | 2016-04-01 11:37:30 +0200 | [diff] [blame] | 361 | #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) |
Giuseppe CAVALLARO | d765955 | 2012-06-27 21:14:37 +0000 | [diff] [blame] | 362 | |
Giuseppe CAVALLARO | 915c199 | 2014-11-18 09:47:00 +0100 | [diff] [blame] | 363 | /* Physical Coding Sublayer */ |
Giuseppe CAVALLARO | e58bb43 | 2013-03-26 04:43:08 +0000 | [diff] [blame] | 364 | struct rgmii_adv { |
| 365 | unsigned int pause; |
| 366 | unsigned int duplex; |
| 367 | unsigned int lp_pause; |
| 368 | unsigned int lp_duplex; |
| 369 | }; |
| 370 | |
| 371 | #define STMMAC_PCS_PAUSE 1 |
| 372 | #define STMMAC_PCS_ASYM_PAUSE 2 |
| 373 | |
Giuseppe CAVALLARO | e743482 | 2011-09-01 21:51:41 +0000 | [diff] [blame] | 374 | /* DMA HW capabilities */ |
| 375 | struct dma_features { |
| 376 | unsigned int mbps_10_100; |
| 377 | unsigned int mbps_1000; |
| 378 | unsigned int half_duplex; |
| 379 | unsigned int hash_filter; |
| 380 | unsigned int multi_addr; |
| 381 | unsigned int pcs; |
| 382 | unsigned int sma_mdio; |
| 383 | unsigned int pmt_remote_wake_up; |
| 384 | unsigned int pmt_magic_frame; |
| 385 | unsigned int rmon; |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 386 | /* IEEE 1588-2002 */ |
Giuseppe CAVALLARO | e743482 | 2011-09-01 21:51:41 +0000 | [diff] [blame] | 387 | unsigned int time_stamp; |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 388 | /* IEEE 1588-2008 */ |
Giuseppe CAVALLARO | e743482 | 2011-09-01 21:51:41 +0000 | [diff] [blame] | 389 | unsigned int atime_stamp; |
| 390 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
| 391 | unsigned int eee; |
| 392 | unsigned int av; |
Biao Huang | b8ef702 | 2019-07-09 10:36:23 +0800 | [diff] [blame] | 393 | unsigned int hash_tb_sz; |
Alexandre TORGUE | 48863ce | 2016-04-01 11:37:30 +0200 | [diff] [blame] | 394 | unsigned int tsoen; |
Giuseppe CAVALLARO | e743482 | 2011-09-01 21:51:41 +0000 | [diff] [blame] | 395 | /* TX and RX csum */ |
| 396 | unsigned int tx_coe; |
Alexandre TORGUE | 48863ce | 2016-04-01 11:37:30 +0200 | [diff] [blame] | 397 | unsigned int rx_coe; |
Giuseppe CAVALLARO | e743482 | 2011-09-01 21:51:41 +0000 | [diff] [blame] | 398 | unsigned int rx_coe_type1; |
| 399 | unsigned int rx_coe_type2; |
| 400 | unsigned int rxfifo_over_2048; |
| 401 | /* TX and RX number of channels */ |
| 402 | unsigned int number_rx_channel; |
| 403 | unsigned int number_tx_channel; |
jpinto | 9eb1247 | 2016-12-28 12:57:48 +0000 | [diff] [blame] | 404 | /* TX and RX number of queues */ |
| 405 | unsigned int number_rx_queues; |
| 406 | unsigned int number_tx_queues; |
Jose Abreu | 9a8a02c | 2018-05-31 18:01:27 +0100 | [diff] [blame] | 407 | /* PPS output */ |
| 408 | unsigned int pps_out_num; |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 409 | /* Alternate (enhanced) DESC mode */ |
Giuseppe CAVALLARO | e743482 | 2011-09-01 21:51:41 +0000 | [diff] [blame] | 410 | unsigned int enh_desc; |
Thierry Reding | 11fbf81 | 2017-03-10 17:34:58 +0100 | [diff] [blame] | 411 | /* TX and RX FIFO sizes */ |
| 412 | unsigned int tx_fifo_size; |
| 413 | unsigned int rx_fifo_size; |
Jose Abreu | 8bf993a | 2018-03-29 10:40:19 +0100 | [diff] [blame] | 414 | /* Automotive Safety Package */ |
| 415 | unsigned int asp; |
Jose Abreu | 4dbbe8d | 2018-05-04 10:01:38 +0100 | [diff] [blame] | 416 | /* RX Parser */ |
| 417 | unsigned int frpsel; |
| 418 | unsigned int frpbs; |
| 419 | unsigned int frpes; |
Jose Abreu | a993db8 | 2019-06-28 09:29:18 +0200 | [diff] [blame] | 420 | unsigned int addr64; |
Jose Abreu | 7606745 | 2019-08-07 10:03:12 +0200 | [diff] [blame] | 421 | unsigned int rssen; |
Jose Abreu | 3cd1cfc | 2019-08-07 10:03:14 +0200 | [diff] [blame] | 422 | unsigned int vlhash; |
Jose Abreu | 67afd6d | 2019-08-17 20:54:43 +0200 | [diff] [blame] | 423 | unsigned int sphen; |
Jose Abreu | 30d9322 | 2019-08-17 20:54:50 +0200 | [diff] [blame] | 424 | unsigned int vlins; |
| 425 | unsigned int dvlan; |
Jose Abreu | 425eabd | 2019-09-04 15:16:56 +0200 | [diff] [blame] | 426 | unsigned int l3l4fnum; |
Jose Abreu | 5904a980 | 2019-09-04 15:16:58 +0200 | [diff] [blame] | 427 | unsigned int arpoffsel; |
Jose Abreu | 504723a | 2019-12-18 11:33:05 +0100 | [diff] [blame] | 428 | /* TSN Features */ |
| 429 | unsigned int estwid; |
| 430 | unsigned int estdep; |
| 431 | unsigned int estsel; |
Jose Abreu | 1ac1424 | 2019-12-18 11:33:08 +0100 | [diff] [blame] | 432 | unsigned int fpesel; |
Jose Abreu | 430b383 | 2020-01-13 17:24:10 +0100 | [diff] [blame] | 433 | unsigned int tbssel; |
Tan Tee Min | 341f67e | 2021-03-23 19:07:34 +0800 | [diff] [blame] | 434 | /* Numbers of Auxiliary Snapshot Inputs */ |
| 435 | unsigned int aux_snapshot_n; |
Giuseppe CAVALLARO | e743482 | 2011-09-01 21:51:41 +0000 | [diff] [blame] | 436 | }; |
| 437 | |
Jose Abreu | 8605131 | 2019-12-18 11:17:41 +0100 | [diff] [blame] | 438 | /* RX Buffer size must be multiple of 4/8/16 bytes */ |
| 439 | #define BUF_SIZE_16KiB 16368 |
Thor Thayer | 8137b6e | 2018-11-08 11:42:14 -0600 | [diff] [blame] | 440 | #define BUF_SIZE_8KiB 8188 |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 441 | #define BUF_SIZE_4KiB 4096 |
| 442 | #define BUF_SIZE_2KiB 2048 |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 443 | |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 444 | /* Power Down and WOL */ |
| 445 | #define PMT_NOT_SUPPORTED 0 |
| 446 | #define PMT_SUPPORTED 1 |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 447 | |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 448 | /* Common MAC defines */ |
| 449 | #define MAC_CTRL_REG 0x00000000 /* MAC Control */ |
| 450 | #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ |
LABBE Corentin | 2808922 | 2017-02-08 09:31:06 +0100 | [diff] [blame] | 451 | #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 452 | |
Giuseppe CAVALLARO | d765955 | 2012-06-27 21:14:37 +0000 | [diff] [blame] | 453 | /* Default LPI timers */ |
Giuseppe CAVALLARO | f5351ef | 2013-06-18 07:03:23 +0200 | [diff] [blame] | 454 | #define STMMAC_DEFAULT_LIT_LS 0x3E8 |
nandini sharma | 438a62b | 2014-08-28 08:11:42 +0200 | [diff] [blame] | 455 | #define STMMAC_DEFAULT_TWT_LS 0x1E |
Vineetha G. Jaya Kumaran | be1c7ea | 2020-10-28 00:00:51 +0800 | [diff] [blame] | 456 | #define STMMAC_ET_MAX 0xFFFFF |
Giuseppe CAVALLARO | d765955 | 2012-06-27 21:14:37 +0000 | [diff] [blame] | 457 | |
Giuseppe CAVALLARO | 4a7d666 | 2013-03-26 04:43:05 +0000 | [diff] [blame] | 458 | #define STMMAC_CHAIN_MODE 0x1 |
| 459 | #define STMMAC_RING_MODE 0x2 |
| 460 | |
Vince Bridgers | 2618abb | 2014-01-20 05:39:01 -0600 | [diff] [blame] | 461 | #define JUMBO_LEN 9000 |
| 462 | |
Jose Abreu | 7606745 | 2019-08-07 10:03:12 +0200 | [diff] [blame] | 463 | /* Receive Side Scaling */ |
| 464 | #define STMMAC_RSS_HASH_KEY_SIZE 40 |
| 465 | #define STMMAC_RSS_MAX_TABLE_SIZE 256 |
| 466 | |
Jose Abreu | 30d9322 | 2019-08-17 20:54:50 +0200 | [diff] [blame] | 467 | /* VLAN */ |
| 468 | #define STMMAC_VLAN_NONE 0x0 |
| 469 | #define STMMAC_VLAN_REMOVE 0x1 |
| 470 | #define STMMAC_VLAN_INSERT 0x2 |
| 471 | #define STMMAC_VLAN_REPLACE 0x3 |
| 472 | |
Andy Shevchenko | 915af65 | 2014-11-05 11:45:32 +0200 | [diff] [blame] | 473 | extern const struct stmmac_desc_ops enh_desc_ops; |
| 474 | extern const struct stmmac_desc_ops ndesc_ops; |
| 475 | |
Vince Bridgers | 7ed24bb | 2014-07-31 15:49:13 -0500 | [diff] [blame] | 476 | struct mac_device_info; |
| 477 | |
Andy Shevchenko | 915af65 | 2014-11-05 11:45:32 +0200 | [diff] [blame] | 478 | extern const struct stmmac_hwtimestamp stmmac_ptp; |
Alexandre TORGUE | 48863ce | 2016-04-01 11:37:30 +0200 | [diff] [blame] | 479 | extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; |
Andy Shevchenko | 915af65 | 2014-11-05 11:45:32 +0200 | [diff] [blame] | 480 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 481 | struct mac_link { |
LABBE Corentin | ca84dfb | 2017-05-24 09:16:47 +0200 | [diff] [blame] | 482 | u32 speed_mask; |
| 483 | u32 speed10; |
| 484 | u32 speed100; |
| 485 | u32 speed1000; |
Jose Abreu | 2142754 | 2018-08-08 09:04:30 +0100 | [diff] [blame] | 486 | u32 speed2500; |
LABBE Corentin | ca84dfb | 2017-05-24 09:16:47 +0200 | [diff] [blame] | 487 | u32 duplex; |
Jose Abreu | 5b0d7d7d | 2019-06-28 09:29:16 +0200 | [diff] [blame] | 488 | struct { |
| 489 | u32 speed2500; |
| 490 | u32 speed5000; |
| 491 | u32 speed10000; |
| 492 | } xgmii; |
Jose Abreu | 8a88093 | 2020-03-17 10:18:51 +0100 | [diff] [blame] | 493 | struct { |
| 494 | u32 speed25000; |
| 495 | u32 speed40000; |
| 496 | u32 speed50000; |
| 497 | u32 speed100000; |
| 498 | } xlgmii; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 499 | }; |
| 500 | |
| 501 | struct mii_regs { |
| 502 | unsigned int addr; /* MII Address */ |
| 503 | unsigned int data; /* MII Data */ |
LABBE Corentin | b91dce4 | 2016-12-01 16:19:41 +0100 | [diff] [blame] | 504 | unsigned int addr_shift; /* MII address shift */ |
| 505 | unsigned int reg_shift; /* MII reg shift */ |
| 506 | unsigned int addr_mask; /* MII address mask */ |
| 507 | unsigned int reg_mask; /* MII reg mask */ |
| 508 | unsigned int clk_csr_shift; |
| 509 | unsigned int clk_csr_mask; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 510 | }; |
| 511 | |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 512 | struct mac_device_info { |
Giuseppe CAVALLARO | ceb69499 | 2013-04-08 02:10:01 +0000 | [diff] [blame] | 513 | const struct stmmac_ops *mac; |
| 514 | const struct stmmac_desc_ops *desc; |
| 515 | const struct stmmac_dma_ops *dma; |
Giuseppe CAVALLARO | 29896a6 | 2014-03-10 13:40:33 +0100 | [diff] [blame] | 516 | const struct stmmac_mode_ops *mode; |
Rayagond Kokatanur | 891434b | 2013-03-26 04:43:10 +0000 | [diff] [blame] | 517 | const struct stmmac_hwtimestamp *ptp; |
Jose Abreu | 4dbbe8d | 2018-05-04 10:01:38 +0100 | [diff] [blame] | 518 | const struct stmmac_tc_ops *tc; |
Jose Abreu | 3b1dd2c | 2019-05-24 10:20:15 +0200 | [diff] [blame] | 519 | const struct stmmac_mmc_ops *mmc; |
Vladimir Oltean | 5673ef8 | 2021-06-11 23:05:19 +0300 | [diff] [blame] | 520 | struct dw_xpcs *xpcs; |
Giuseppe CAVALLARO | db98a0b | 2010-01-06 23:07:17 +0000 | [diff] [blame] | 521 | struct mii_regs mii; /* MII register Addresses */ |
| 522 | struct mac_link link; |
Vince Bridgers | 7ed24bb | 2014-07-31 15:49:13 -0500 | [diff] [blame] | 523 | void __iomem *pcsr; /* vpointer to device CSRs */ |
Biao Huang | b8ef702 | 2019-07-09 10:36:23 +0800 | [diff] [blame] | 524 | unsigned int multicast_filter_bins; |
| 525 | unsigned int unicast_filter_entries; |
| 526 | unsigned int mcast_bits_log2; |
Giuseppe CAVALLARO | d2afb5b | 2014-09-01 09:17:52 +0200 | [diff] [blame] | 527 | unsigned int rx_csum; |
Giuseppe CAVALLARO | 3fe5cad | 2016-06-24 15:16:25 +0200 | [diff] [blame] | 528 | unsigned int pcs; |
| 529 | unsigned int pmt; |
Giuseppe CAVALLARO | 02e57b9 | 2016-06-24 15:16:26 +0200 | [diff] [blame] | 530 | unsigned int ps; |
Jose Abreu | 4a4ccde | 2020-03-17 10:18:52 +0100 | [diff] [blame] | 531 | unsigned int xlgmac; |
Wong Vee Khee | ed64639 | 2020-03-30 23:53:57 +0800 | [diff] [blame] | 532 | unsigned int num_vlan; |
| 533 | u32 vlan_filter[32]; |
Chuah, Kim Tatt | c89f44f | 2020-04-22 11:31:06 +0800 | [diff] [blame] | 534 | unsigned int promisc; |
Chuah, Kim Tatt | e0f9956 | 2020-09-25 17:40:41 +0800 | [diff] [blame] | 535 | bool vlan_fail_q_en; |
| 536 | u8 vlan_fail_q; |
Giuseppe Cavallaro | 47dd7a5 | 2009-10-14 15:13:45 -0700 | [diff] [blame] | 537 | }; |
| 538 | |
Joao Pinto | abe80fd | 2017-03-17 16:11:07 +0000 | [diff] [blame] | 539 | struct stmmac_rx_routing { |
| 540 | u32 reg_mask; |
| 541 | u32 reg_shift; |
| 542 | }; |
| 543 | |
Jose Abreu | 5f0456b | 2018-04-23 09:05:15 +0100 | [diff] [blame] | 544 | int dwmac100_setup(struct stmmac_priv *priv); |
| 545 | int dwmac1000_setup(struct stmmac_priv *priv); |
| 546 | int dwmac4_setup(struct stmmac_priv *priv); |
Jose Abreu | 2142754 | 2018-08-08 09:04:30 +0100 | [diff] [blame] | 547 | int dwxgmac2_setup(struct stmmac_priv *priv); |
Jose Abreu | 4a4ccde | 2020-03-17 10:18:52 +0100 | [diff] [blame] | 548 | int dwxlgmac2_setup(struct stmmac_priv *priv); |
Giuseppe CAVALLARO | aec7ff2 | 2010-01-06 23:07:18 +0000 | [diff] [blame] | 549 | |
Jakub Kicinski | 7666075 | 2021-10-14 07:24:31 -0700 | [diff] [blame] | 550 | void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], |
Joe Perches | d6cc64e | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 551 | unsigned int high, unsigned int low); |
| 552 | void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
| 553 | unsigned int high, unsigned int low); |
Joe Perches | d6cc64e | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 554 | void stmmac_set_mac(void __iomem *ioaddr, bool enable); |
Giuseppe CAVALLARO | bfab27a | 2011-12-21 03:58:19 +0000 | [diff] [blame] | 555 | |
Jakub Kicinski | 7666075 | 2021-10-14 07:24:31 -0700 | [diff] [blame] | 556 | void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 557 | unsigned int high, unsigned int low); |
| 558 | void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
| 559 | unsigned int high, unsigned int low); |
| 560 | void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); |
| 561 | |
Joe Perches | d6cc64e | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 562 | void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 563 | |
Giuseppe CAVALLARO | 29896a6 | 2014-03-10 13:40:33 +0100 | [diff] [blame] | 564 | extern const struct stmmac_mode_ops ring_mode_ops; |
| 565 | extern const struct stmmac_mode_ops chain_mode_ops; |
Alexandre TORGUE | f748be5 | 2016-04-01 11:37:34 +0200 | [diff] [blame] | 566 | extern const struct stmmac_desc_ops dwmac4_desc_ops; |
Rayagond Kokatanur | bd4242d | 2012-08-22 21:28:18 +0000 | [diff] [blame] | 567 | |
| 568 | #endif /* __COMMON_H__ */ |