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David Howells108b42b2006-03-31 16:00:29 +01001 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
4
5By: David Howells <dhowells@redhat.com>
Paul E. McKenney714b6902019-04-11 07:12:18 -07006 Paul E. McKenney <paulmck@linux.ibm.com>
Peter Zijlstrae7720af52016-04-26 10:22:05 -07007 Will Deacon <will.deacon@arm.com>
8 Peter Zijlstra <peterz@infradead.org>
David Howells108b42b2006-03-31 16:00:29 +01009
Peter Zijlstrae7720af52016-04-26 10:22:05 -070010==========
11DISCLAIMER
12==========
13
14This document is not a specification; it is intentionally (for the sake of
15brevity) and unintentionally (due to being human) incomplete. This document is
16meant as a guide to using the various memory barriers provided by Linux, but
Andrea Parri621df432018-02-20 15:25:07 -080017in case of any doubt (and there are many) please ask. Some doubts may be
18resolved by referring to the formal memory consistency model and related
19documentation at tools/memory-model/. Nevertheless, even this memory
20model should be viewed as the collective opinion of its maintainers rather
21than as an infallible oracle.
Peter Zijlstrae7720af52016-04-26 10:22:05 -070022
23To repeat, this document is not a specification of what Linux expects from
24hardware.
25
David Howells8d4840e2016-04-26 10:22:06 -070026The purpose of this document is twofold:
27
28 (1) to specify the minimum functionality that one can rely on for any
29 particular barrier, and
30
31 (2) to provide a guide as to how to use the barriers that are available.
32
33Note that an architecture can provide more than the minimum requirement
Stan Drozd35bdc722017-04-20 11:03:36 +020034for any particular barrier, but if the architecture provides less than
David Howells8d4840e2016-04-26 10:22:06 -070035that, that architecture is incorrect.
36
37Note also that it is possible that a barrier may be a no-op for an
38architecture because the way that arch works renders an explicit barrier
39unnecessary in that case.
40
41
Peter Zijlstrae7720af52016-04-26 10:22:05 -070042========
43CONTENTS
44========
David Howells108b42b2006-03-31 16:00:29 +010045
46 (*) Abstract memory access model.
47
48 - Device operations.
49 - Guarantees.
50
51 (*) What are memory barriers?
52
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
Paul E. McKenneyf28f0862018-03-07 09:27:37 -080055 - Data dependency barriers (historical).
David Howells108b42b2006-03-31 16:00:29 +010056 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
David Howells670bd952006-06-10 09:54:12 -070059 - Read memory barriers vs load speculation.
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -070060 - Multicopy atomicity.
David Howells108b42b2006-03-31 16:00:29 +010061
62 (*) Explicit kernel barriers.
63
64 - Compiler barrier.
Jarek Poplawski81fc6322007-05-23 13:58:20 -070065 - CPU memory barriers.
David Howells108b42b2006-03-31 16:00:29 +010066
67 (*) Implicit kernel memory barriers.
68
SeongJae Park166bda72016-04-12 08:52:50 -070069 - Lock acquisition functions.
David Howells108b42b2006-03-31 16:00:29 +010070 - Interrupt disabling functions.
David Howells50fa6102009-04-28 15:01:38 +010071 - Sleep and wake-up functions.
David Howells108b42b2006-03-31 16:00:29 +010072 - Miscellaneous functions.
73
SeongJae Park166bda72016-04-12 08:52:50 -070074 (*) Inter-CPU acquiring barrier effects.
David Howells108b42b2006-03-31 16:00:29 +010075
SeongJae Park166bda72016-04-12 08:52:50 -070076 - Acquires vs memory accesses.
David Howells108b42b2006-03-31 16:00:29 +010077
78 (*) Where are memory barriers needed?
79
80 - Interprocessor interaction.
81 - Atomic operations.
82 - Accessing devices.
83 - Interrupts.
84
85 (*) Kernel I/O barrier effects.
86
87 (*) Assumed minimum execution ordering model.
88
89 (*) The effects of the cpu cache.
90
91 - Cache coherency.
92 - Cache coherency vs DMA.
93 - Cache coherency vs MMIO.
94
95 (*) The things CPUs get up to.
96
97 - And then there's the Alpha.
SeongJae Park01e1cd62016-04-12 08:52:51 -070098 - Virtual Machine Guests.
David Howells108b42b2006-03-31 16:00:29 +010099
David Howells90fddab2010-03-24 09:43:00 +0000100 (*) Example uses.
101
102 - Circular buffers.
103
David Howells108b42b2006-03-31 16:00:29 +0100104 (*) References.
105
106
107============================
108ABSTRACT MEMORY ACCESS MODEL
109============================
110
111Consider the following abstract model of the system:
112
113 : :
114 : :
115 : :
116 +-------+ : +--------+ : +-------+
117 | | : | | : | |
118 | | : | | : | |
119 | CPU 1 |<----->| Memory |<----->| CPU 2 |
120 | | : | | : | |
121 | | : | | : | |
122 +-------+ : +--------+ : +-------+
123 ^ : ^ : ^
124 | : | : |
125 | : | : |
126 | : v : |
127 | : +--------+ : |
128 | : | | : |
129 | : | | : |
130 +---------->| Device |<----------+
131 : | | :
132 : | | :
133 : +--------+ :
134 : :
135
136Each CPU executes a program that generates memory access operations. In the
137abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
138perform the memory operations in any order it likes, provided program causality
139appears to be maintained. Similarly, the compiler may also arrange the
140instructions it emits in any order it likes, provided it doesn't affect the
141apparent operation of the program.
142
143So in the above diagram, the effects of the memory operations performed by a
144CPU are perceived by the rest of the system as the operations cross the
145interface between the CPU and rest of the system (the dotted lines).
146
147
148For example, consider the following sequence of events:
149
150 CPU 1 CPU 2
151 =============== ===============
152 { A == 1; B == 2 }
Alexey Dobriyan615cc2c2014-06-06 14:36:41 -0700153 A = 3; x = B;
154 B = 4; y = A;
David Howells108b42b2006-03-31 16:00:29 +0100155
156The set of accesses as seen by the memory system in the middle can be arranged
157in 24 different combinations:
158
Pranith Kumar8ab8b3e2014-09-02 23:34:29 -0400159 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
160 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
161 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
162 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
163 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
164 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
165 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
David Howells108b42b2006-03-31 16:00:29 +0100166 STORE B=4, ...
167 ...
168
169and can thus result in four different combinations of values:
170
Pranith Kumar8ab8b3e2014-09-02 23:34:29 -0400171 x == 2, y == 1
172 x == 2, y == 3
173 x == 4, y == 1
174 x == 4, y == 3
David Howells108b42b2006-03-31 16:00:29 +0100175
176
177Furthermore, the stores committed by a CPU to the memory system may not be
178perceived by the loads made by another CPU in the same order as the stores were
179committed.
180
181
182As a further example, consider this sequence of events:
183
184 CPU 1 CPU 2
185 =============== ===============
SeongJae Park3dbf0912016-04-12 08:52:52 -0700186 { A == 1, B == 2, C == 3, P == &A, Q == &C }
David Howells108b42b2006-03-31 16:00:29 +0100187 B = 4; Q = P;
SeongJae Park8149b5c2020-01-31 21:52:37 +0100188 P = &B; D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100189
190There is an obvious data dependency here, as the value loaded into D depends on
191the address retrieved from P by CPU 2. At the end of the sequence, any of the
192following results are possible:
193
194 (Q == &A) and (D == 1)
195 (Q == &B) and (D == 2)
196 (Q == &B) and (D == 4)
197
198Note that CPU 2 will never try and load C into D because the CPU will load P
199into Q before issuing the load of *Q.
200
201
202DEVICE OPERATIONS
203-----------------
204
205Some devices present their control interfaces as collections of memory
206locations, but the order in which the control registers are accessed is very
207important. For instance, imagine an ethernet card with a set of internal
208registers that are accessed through an address port register (A) and a data
209port register (D). To read internal register 5, the following code might then
210be used:
211
212 *A = 5;
213 x = *D;
214
215but this might show up as either of the following two sequences:
216
217 STORE *A = 5, x = LOAD *D
218 x = LOAD *D, STORE *A = 5
219
220the second of which will almost certainly result in a malfunction, since it set
221the address _after_ attempting to read the register.
222
223
224GUARANTEES
225----------
226
227There are some minimal guarantees that may be expected of a CPU:
228
229 (*) On any given CPU, dependent memory accesses will be issued in order, with
230 respect to itself. This means that for:
231
Paul E. McKenney40555942017-10-09 09:15:21 -0700232 Q = READ_ONCE(P); D = READ_ONCE(*Q);
David Howells108b42b2006-03-31 16:00:29 +0100233
234 the CPU will issue the following memory operations:
235
236 Q = LOAD P, D = LOAD *Q
237
Paul E. McKenney40555942017-10-09 09:15:21 -0700238 and always in that order. However, on DEC Alpha, READ_ONCE() also
239 emits a memory-barrier instruction, so that a DEC Alpha CPU will
240 instead issue the following memory operations:
241
242 Q = LOAD P, MEMORY_BARRIER, D = LOAD *Q, MEMORY_BARRIER
243
244 Whether on DEC Alpha or not, the READ_ONCE() also prevents compiler
245 mischief.
David Howells108b42b2006-03-31 16:00:29 +0100246
247 (*) Overlapping loads and stores within a particular CPU will appear to be
248 ordered within that CPU. This means that for:
249
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700250 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
David Howells108b42b2006-03-31 16:00:29 +0100251
252 the CPU will only issue the following sequence of memory operations:
253
254 a = LOAD *X, STORE *X = b
255
256 And for:
257
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700258 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
David Howells108b42b2006-03-31 16:00:29 +0100259
260 the CPU will only issue:
261
262 STORE *X = c, d = LOAD *X
263
Matt LaPlantefa00e7e2006-11-30 04:55:36 +0100264 (Loads and stores overlap if they are targeted at overlapping pieces of
David Howells108b42b2006-03-31 16:00:29 +0100265 memory).
266
267And there are a number of things that _must_ or _must_not_ be assumed:
268
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700269 (*) It _must_not_ be assumed that the compiler will do what you want
270 with memory references that are not protected by READ_ONCE() and
271 WRITE_ONCE(). Without them, the compiler is within its rights to
272 do all sorts of "creative" transformations, which are covered in
Paul E. McKenney895f5542016-01-06 14:23:03 -0800273 the COMPILER BARRIER section.
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800274
David Howells108b42b2006-03-31 16:00:29 +0100275 (*) It _must_not_ be assumed that independent loads and stores will be issued
276 in the order given. This means that for:
277
278 X = *A; Y = *B; *D = Z;
279
280 we may get any of the following sequences:
281
282 X = LOAD *A, Y = LOAD *B, STORE *D = Z
283 X = LOAD *A, STORE *D = Z, Y = LOAD *B
284 Y = LOAD *B, X = LOAD *A, STORE *D = Z
285 Y = LOAD *B, STORE *D = Z, X = LOAD *A
286 STORE *D = Z, X = LOAD *A, Y = LOAD *B
287 STORE *D = Z, Y = LOAD *B, X = LOAD *A
288
289 (*) It _must_ be assumed that overlapping memory accesses may be merged or
290 discarded. This means that for:
291
292 X = *A; Y = *(A + 4);
293
294 we may get any one of the following sequences:
295
296 X = LOAD *A; Y = LOAD *(A + 4);
297 Y = LOAD *(A + 4); X = LOAD *A;
298 {X, Y} = LOAD {*A, *(A + 4) };
299
300 And for:
301
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700302 *A = X; *(A + 4) = Y;
David Howells108b42b2006-03-31 16:00:29 +0100303
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700304 we may get any of:
David Howells108b42b2006-03-31 16:00:29 +0100305
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700306 STORE *A = X; STORE *(A + 4) = Y;
307 STORE *(A + 4) = Y; STORE *A = X;
308 STORE {*A, *(A + 4) } = {X, Y};
David Howells108b42b2006-03-31 16:00:29 +0100309
Paul E. McKenney432fbf32014-09-04 17:12:49 -0700310And there are anti-guarantees:
311
312 (*) These guarantees do not apply to bitfields, because compilers often
313 generate code to modify these using non-atomic read-modify-write
314 sequences. Do not attempt to use bitfields to synchronize parallel
315 algorithms.
316
317 (*) Even in cases where bitfields are protected by locks, all fields
318 in a given bitfield must be protected by one lock. If two fields
319 in a given bitfield are protected by different locks, the compiler's
320 non-atomic read-modify-write sequences can cause an update to one
321 field to corrupt the value of an adjacent field.
322
323 (*) These guarantees apply only to properly aligned and sized scalar
324 variables. "Properly sized" currently means variables that are
325 the same size as "char", "short", "int" and "long". "Properly
326 aligned" means the natural alignment, thus no constraints for
327 "char", two-byte alignment for "short", four-byte alignment for
328 "int", and either four-byte or eight-byte alignment for "long",
329 on 32-bit and 64-bit systems, respectively. Note that these
330 guarantees were introduced into the C11 standard, so beware when
331 using older pre-C11 compilers (for example, gcc 4.6). The portion
332 of the standard containing this guarantee is Section 3.14, which
333 defines "memory location" as follows:
334
335 memory location
336 either an object of scalar type, or a maximal sequence
337 of adjacent bit-fields all having nonzero width
338
339 NOTE 1: Two threads of execution can update and access
340 separate memory locations without interfering with
341 each other.
342
343 NOTE 2: A bit-field and an adjacent non-bit-field member
344 are in separate memory locations. The same applies
345 to two bit-fields, if one is declared inside a nested
346 structure declaration and the other is not, or if the two
347 are separated by a zero-length bit-field declaration,
348 or if they are separated by a non-bit-field member
349 declaration. It is not safe to concurrently update two
350 bit-fields in the same structure if all members declared
351 between them are also bit-fields, no matter what the
352 sizes of those intervening bit-fields happen to be.
353
David Howells108b42b2006-03-31 16:00:29 +0100354
355=========================
356WHAT ARE MEMORY BARRIERS?
357=========================
358
359As can be seen above, independent memory operations are effectively performed
360in random order, but this can be a problem for CPU-CPU interaction and for I/O.
361What is required is some way of intervening to instruct the compiler and the
362CPU to restrict the order.
363
364Memory barriers are such interventions. They impose a perceived partial
David Howells2b948952006-06-25 05:48:49 -0700365ordering over the memory operations on either side of the barrier.
366
367Such enforcement is important because the CPUs and other devices in a system
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700368can use a variety of tricks to improve performance, including reordering,
David Howells2b948952006-06-25 05:48:49 -0700369deferral and combination of memory operations; speculative loads; speculative
370branch prediction and various types of caching. Memory barriers are used to
371override or suppress these tricks, allowing the code to sanely control the
372interaction of multiple CPUs and/or devices.
David Howells108b42b2006-03-31 16:00:29 +0100373
374
375VARIETIES OF MEMORY BARRIER
376---------------------------
377
378Memory barriers come in four basic varieties:
379
380 (1) Write (or store) memory barriers.
381
382 A write memory barrier gives a guarantee that all the STORE operations
383 specified before the barrier will appear to happen before all the STORE
384 operations specified after the barrier with respect to the other
385 components of the system.
386
387 A write barrier is a partial ordering on stores only; it is not required
388 to have any effect on loads.
389
David Howells6bc39272006-06-25 05:49:22 -0700390 A CPU can be viewed as committing a sequence of store operations to the
Guilherme G. Piccoli5692fcc2017-09-21 16:29:01 -0300391 memory system as time progresses. All stores _before_ a write barrier
392 will occur _before_ all the stores after the write barrier.
David Howells108b42b2006-03-31 16:00:29 +0100393
394 [!] Note that write barriers should normally be paired with read or data
395 dependency barriers; see the "SMP barrier pairing" subsection.
396
397
398 (2) Data dependency barriers.
399
400 A data dependency barrier is a weaker form of read barrier. In the case
401 where two loads are performed such that the second depends on the result
402 of the first (eg: the first load retrieves the address to which the second
403 load will be directed), a data dependency barrier would be required to
Nikolay Borisov51de7882018-02-20 15:25:08 -0800404 make sure that the target of the second load is updated after the address
David Howells108b42b2006-03-31 16:00:29 +0100405 obtained by the first load is accessed.
406
407 A data dependency barrier is a partial ordering on interdependent loads
408 only; it is not required to have any effect on stores, independent loads
409 or overlapping loads.
410
411 As mentioned in (1), the other CPUs in the system can be viewed as
412 committing sequences of stores to the memory system that the CPU being
413 considered can then perceive. A data dependency barrier issued by the CPU
414 under consideration guarantees that for any load preceding it, if that
415 load touches one of a sequence of stores from another CPU, then by the
416 time the barrier completes, the effects of all the stores prior to that
417 touched by the load will be perceptible to any loads issued after the data
418 dependency barrier.
419
420 See the "Examples of memory barrier sequences" subsection for diagrams
421 showing the ordering constraints.
422
423 [!] Note that the first load really has to have a _data_ dependency and
424 not a control dependency. If the address for the second load is dependent
425 on the first load, but the dependency is through a conditional rather than
426 actually loading the address itself, then it's a _control_ dependency and
427 a full read barrier or better is required. See the "Control dependencies"
428 subsection for more information.
429
430 [!] Note that data dependency barriers should normally be paired with
431 write barriers; see the "SMP barrier pairing" subsection.
432
433
434 (3) Read (or load) memory barriers.
435
436 A read barrier is a data dependency barrier plus a guarantee that all the
437 LOAD operations specified before the barrier will appear to happen before
438 all the LOAD operations specified after the barrier with respect to the
439 other components of the system.
440
441 A read barrier is a partial ordering on loads only; it is not required to
442 have any effect on stores.
443
444 Read memory barriers imply data dependency barriers, and so can substitute
445 for them.
446
447 [!] Note that read barriers should normally be paired with write barriers;
448 see the "SMP barrier pairing" subsection.
449
450
451 (4) General memory barriers.
452
David Howells670bd952006-06-10 09:54:12 -0700453 A general memory barrier gives a guarantee that all the LOAD and STORE
454 operations specified before the barrier will appear to happen before all
455 the LOAD and STORE operations specified after the barrier with respect to
456 the other components of the system.
457
458 A general memory barrier is a partial ordering over both loads and stores.
David Howells108b42b2006-03-31 16:00:29 +0100459
460 General memory barriers imply both read and write memory barriers, and so
461 can substitute for either.
462
463
464And a couple of implicit varieties:
465
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100466 (5) ACQUIRE operations.
David Howells108b42b2006-03-31 16:00:29 +0100467
468 This acts as a one-way permeable barrier. It guarantees that all memory
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100469 operations after the ACQUIRE operation will appear to happen after the
470 ACQUIRE operation with respect to the other components of the system.
Davidlohr Bueso787df632016-04-12 08:52:55 -0700471 ACQUIRE operations include LOCK operations and both smp_load_acquire()
Andrea Parri2f359c72018-09-26 11:29:20 -0700472 and smp_cond_load_acquire() operations.
David Howells108b42b2006-03-31 16:00:29 +0100473
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100474 Memory operations that occur before an ACQUIRE operation may appear to
475 happen after it completes.
David Howells108b42b2006-03-31 16:00:29 +0100476
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100477 An ACQUIRE operation should almost always be paired with a RELEASE
478 operation.
David Howells108b42b2006-03-31 16:00:29 +0100479
480
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100481 (6) RELEASE operations.
David Howells108b42b2006-03-31 16:00:29 +0100482
483 This also acts as a one-way permeable barrier. It guarantees that all
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100484 memory operations before the RELEASE operation will appear to happen
485 before the RELEASE operation with respect to the other components of the
486 system. RELEASE operations include UNLOCK operations and
487 smp_store_release() operations.
David Howells108b42b2006-03-31 16:00:29 +0100488
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100489 Memory operations that occur after a RELEASE operation may appear to
David Howells108b42b2006-03-31 16:00:29 +0100490 happen before it completes.
491
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100492 The use of ACQUIRE and RELEASE operations generally precludes the need
SeongJae Parka897b132019-11-22 00:41:23 +0100493 for other sorts of memory barrier. In addition, a RELEASE+ACQUIRE pair is
494 -not- guaranteed to act as a full memory barrier. However, after an
495 ACQUIRE on a given variable, all memory accesses preceding any prior
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100496 RELEASE on that same variable are guaranteed to be visible. In other
497 words, within a given variable's critical section, all accesses of all
498 previous critical sections for that variable are guaranteed to have
499 completed.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -0800500
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100501 This means that ACQUIRE acts as a minimal "acquire" operation and
502 RELEASE acts as a minimal "release" operation.
David Howells108b42b2006-03-31 16:00:29 +0100503
Peter Zijlstra706eeb32017-06-12 14:50:27 +0200504A subset of the atomic operations described in atomic_t.txt have ACQUIRE and
505RELEASE variants in addition to fully-ordered and relaxed (no barrier
506semantics) definitions. For compound atomics performing both a load and a
507store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
508only to the store portion of the operation.
David Howells108b42b2006-03-31 16:00:29 +0100509
510Memory barriers are only required where there's a possibility of interaction
511between two CPUs or between a CPU and a device. If it can be guaranteed that
512there won't be any such interaction in any particular piece of code, then
513memory barriers are unnecessary in that piece of code.
514
515
516Note that these are the _minimum_ guarantees. Different architectures may give
517more substantial guarantees, but they may _not_ be relied upon outside of arch
518specific code.
519
520
521WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
522----------------------------------------------
523
524There are certain things that the Linux kernel memory barriers do not guarantee:
525
526 (*) There is no guarantee that any of the memory accesses specified before a
527 memory barrier will be _complete_ by the completion of a memory barrier
528 instruction; the barrier can be considered to draw a line in that CPU's
529 access queue that accesses of the appropriate type may not cross.
530
531 (*) There is no guarantee that issuing a memory barrier on one CPU will have
532 any direct effect on another CPU or any other hardware in the system. The
533 indirect effect will be the order in which the second CPU sees the effects
534 of the first CPU's accesses occur, but see the next point:
535
David Howells6bc39272006-06-25 05:49:22 -0700536 (*) There is no guarantee that a CPU will see the correct order of effects
David Howells108b42b2006-03-31 16:00:29 +0100537 from a second CPU's accesses, even _if_ the second CPU uses a memory
538 barrier, unless the first CPU _also_ uses a matching memory barrier (see
539 the subsection on "SMP Barrier Pairing").
540
541 (*) There is no guarantee that some intervening piece of off-the-CPU
542 hardware[*] will not reorder the memory accesses. CPU cache coherency
543 mechanisms should propagate the indirect effects of a memory barrier
544 between CPUs, but might not do so in order.
545
546 [*] For information on bus mastering DMA and coherency please read:
547
Mauro Carvalho Chehabbff9e342019-07-15 05:31:06 -0300548 Documentation/driver-api/pci/pci.rst
SeongJae Park537f3a72020-08-29 10:26:05 +0200549 Documentation/core-api/dma-api-howto.rst
550 Documentation/core-api/dma-api.rst
David Howells108b42b2006-03-31 16:00:29 +0100551
552
Paul E. McKenneyf28f0862018-03-07 09:27:37 -0800553DATA DEPENDENCY BARRIERS (HISTORICAL)
554-------------------------------------
555
Will Deacon8ca924a2019-11-07 14:36:37 +0000556As of v4.15 of the Linux kernel, an smp_mb() was added to READ_ONCE() for
557DEC Alpha, which means that about the only people who need to pay attention
558to this section are those working on DEC Alpha architecture-specific code
559and those working on READ_ONCE() itself. For those who need it, and for
560those who are interested in the history, here is the story of
561data-dependency barriers.
David Howells108b42b2006-03-31 16:00:29 +0100562
563The usage requirements of data dependency barriers are a little subtle, and
564it's not always obvious that they're needed. To illustrate, consider the
565following sequence of events:
566
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800567 CPU 1 CPU 2
568 =============== ===============
SeongJae Park3dbf0912016-04-12 08:52:52 -0700569 { A == 1, B == 2, C == 3, P == &A, Q == &C }
David Howells108b42b2006-03-31 16:00:29 +0100570 B = 4;
571 <write barrier>
SeongJae Park8149b5c2020-01-31 21:52:37 +0100572 WRITE_ONCE(P, &B);
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700573 Q = READ_ONCE(P);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800574 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100575
576There's a clear data dependency here, and it would seem that by the end of the
577sequence, Q must be either &A or &B, and that:
578
579 (Q == &A) implies (D == 1)
580 (Q == &B) implies (D == 4)
581
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700582But! CPU 2's perception of P may be updated _before_ its perception of B, thus
David Howells108b42b2006-03-31 16:00:29 +0100583leading to the following situation:
584
585 (Q == &B) and (D == 2) ????
586
Will Deacon806654a2018-11-19 11:02:45 +0000587While this may seem like a failure of coherency or causality maintenance, it
David Howells108b42b2006-03-31 16:00:29 +0100588isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
589Alpha).
590
David Howells2b948952006-06-25 05:48:49 -0700591To deal with this, a data dependency barrier or better must be inserted
592between the address load and the data load:
David Howells108b42b2006-03-31 16:00:29 +0100593
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800594 CPU 1 CPU 2
595 =============== ===============
SeongJae Park3dbf0912016-04-12 08:52:52 -0700596 { A == 1, B == 2, C == 3, P == &A, Q == &C }
David Howells108b42b2006-03-31 16:00:29 +0100597 B = 4;
598 <write barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700599 WRITE_ONCE(P, &B);
600 Q = READ_ONCE(P);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800601 <data dependency barrier>
602 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100603
604This enforces the occurrence of one of the two implications, and prevents the
605third possibility from arising.
606
Paul E. McKenney92a84dd2016-01-14 14:17:04 -0800607
David Howells108b42b2006-03-31 16:00:29 +0100608[!] Note that this extremely counterintuitive situation arises most easily on
609machines with split caches, so that, for example, one cache bank processes
610even-numbered cache lines and the other bank processes odd-numbered cache
611lines. The pointer P might be stored in an odd-numbered cache line, and the
612variable B might be stored in an even-numbered cache line. Then, if the
613even-numbered bank of the reading CPU's cache is extremely busy while the
614odd-numbered bank is idle, one can see the new value of the pointer P (&B),
David Howells6bc39272006-06-25 05:49:22 -0700615but the old value of the variable B (2).
David Howells108b42b2006-03-31 16:00:29 +0100616
617
Paul E. McKenney66ce3a42017-06-30 16:18:28 -0700618A data-dependency barrier is not required to order dependent writes
619because the CPUs that the Linux kernel supports don't do writes
620until they are certain (1) that the write will actually happen, (2)
621of the location of the write, and (3) of the value to be written.
622But please carefully read the "CONTROL DEPENDENCIES" section and the
Mauro Carvalho Chehab72ef5e52020-04-14 18:48:35 +0200623Documentation/RCU/rcu_dereference.rst file: The compiler can and does
Paul E. McKenney66ce3a42017-06-30 16:18:28 -0700624break dependencies in a great many highly creative ways.
625
626 CPU 1 CPU 2
627 =============== ===============
628 { A == 1, B == 2, C = 3, P == &A, Q == &C }
629 B = 4;
630 <write barrier>
631 WRITE_ONCE(P, &B);
632 Q = READ_ONCE(P);
633 WRITE_ONCE(*Q, 5);
634
635Therefore, no data-dependency barrier is required to order the read into
636Q with the store into *Q. In other words, this outcome is prohibited,
637even without a data-dependency barrier:
638
639 (Q == &B) && (B == 4)
640
641Please note that this pattern should be rare. After all, the whole point
642of dependency ordering is to -prevent- writes to the data structure, along
643with the expensive cache misses associated with those writes. This pattern
644can be used to record rare error conditions and the like, and the CPUs'
645naturally occurring ordering prevents such records from being lost.
646
647
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -0700648Note well that the ordering provided by a data dependency is local to
649the CPU containing it. See the section on "Multicopy atomicity" for
650more information.
651
652
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800653The data dependency barrier is very important to the RCU system,
654for example. See rcu_assign_pointer() and rcu_dereference() in
655include/linux/rcupdate.h. This permits the current target of an RCU'd
656pointer to be replaced with a new modified target, without the replacement
657target appearing to be incompletely initialised.
David Howells108b42b2006-03-31 16:00:29 +0100658
659See also the subsection on "Cache Coherency" for a more thorough example.
660
661
662CONTROL DEPENDENCIES
663--------------------
664
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800665Control dependencies can be a bit tricky because current compilers do
666not understand them. The purpose of this section is to help you prevent
667the compiler's ignorance from breaking your code.
668
Paul E. McKenneyff382812015-02-17 10:00:06 -0800669A load-load control dependency requires a full read memory barrier, not
670simply a data dependency barrier to make it work correctly. Consider the
671following bit of code:
David Howells108b42b2006-03-31 16:00:29 +0100672
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700673 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800674 if (q) {
675 <data dependency barrier> /* BUG: No data dependency!!! */
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700676 p = READ_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700677 }
David Howells108b42b2006-03-31 16:00:29 +0100678
679This will not have the desired effect because there is no actual data
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800680dependency, but rather a control dependency that the CPU may short-circuit
681by attempting to predict the outcome in advance, so that other CPUs see
682the load from b as having happened before the load from a. In such a
683case what's actually required is:
David Howells108b42b2006-03-31 16:00:29 +0100684
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700685 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800686 if (q) {
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700687 <read barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700688 p = READ_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700689 }
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800690
691However, stores are not speculated. This means that ordering -is- provided
Paul E. McKenneyff382812015-02-17 10:00:06 -0800692for load-store control dependencies, as in the following example:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800693
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800694 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700695 if (q) {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800696 WRITE_ONCE(b, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800697 }
698
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800699Control dependencies pair normally with other types of barriers.
700That said, please note that neither READ_ONCE() nor WRITE_ONCE()
701are optional! Without the READ_ONCE(), the compiler might combine the
702load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),
703the compiler might combine the store to 'b' with other stores to 'b'.
704Either can result in highly counterintuitive effects on ordering.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800705
706Worse yet, if the compiler is able to prove (say) that the value of
707variable 'a' is always non-zero, it would be well within its rights
708to optimize the original example by eliminating the "if" statement
709as follows:
710
711 q = a;
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800712 b = 1; /* BUG: Compiler and CPU can both reorder!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800713
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800714So don't leave out the READ_ONCE().
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700715
716It is tempting to try to enforce ordering on identical stores on both
717branches of the "if" statement as follows:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800718
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800719 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800720 if (q) {
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800721 barrier();
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800722 WRITE_ONCE(b, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800723 do_something();
724 } else {
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800725 barrier();
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800726 WRITE_ONCE(b, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800727 do_something_else();
728 }
729
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700730Unfortunately, current compilers will transform this as follows at high
731optimization levels:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800732
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800733 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700734 barrier();
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800735 WRITE_ONCE(b, 1); /* BUG: No ordering vs. load from a!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800736 if (q) {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800737 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800738 do_something();
739 } else {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800740 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800741 do_something_else();
742 }
743
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700744Now there is no conditional between the load from 'a' and the store to
745'b', which means that the CPU is within its rights to reorder them:
746The conditional is absolutely required, and must be present in the
747assembly code even after all compiler optimizations have been applied.
748Therefore, if you need ordering in this example, you need explicit
749memory barriers, for example, smp_store_release():
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800750
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700751 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700752 if (q) {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800753 smp_store_release(&b, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800754 do_something();
755 } else {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800756 smp_store_release(&b, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800757 do_something_else();
758 }
759
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700760In contrast, without explicit memory barriers, two-legged-if control
761ordering is guaranteed only when the stores differ, for example:
762
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800763 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700764 if (q) {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800765 WRITE_ONCE(b, 1);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700766 do_something();
767 } else {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800768 WRITE_ONCE(b, 2);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700769 do_something_else();
770 }
771
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800772The initial READ_ONCE() is still required to prevent the compiler from
773proving the value of 'a'.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800774
775In addition, you need to be careful what you do with the local variable 'q',
776otherwise the compiler might be able to guess the value and again remove
777the needed conditional. For example:
778
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800779 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800780 if (q % MAX) {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800781 WRITE_ONCE(b, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800782 do_something();
783 } else {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800784 WRITE_ONCE(b, 2);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800785 do_something_else();
786 }
787
788If MAX is defined to be 1, then the compiler knows that (q % MAX) is
789equal to zero, in which case the compiler is within its rights to
790transform the above code into the following:
791
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800792 q = READ_ONCE(a);
pierre Kuob26cfc42017-04-07 14:37:36 +0800793 WRITE_ONCE(b, 2);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800794 do_something_else();
795
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700796Given this transformation, the CPU is not required to respect the ordering
797between the load from variable 'a' and the store to variable 'b'. It is
798tempting to add a barrier(), but this does not help. The conditional
799is gone, and the barrier won't bring it back. Therefore, if you are
800relying on this ordering, you should make sure that MAX is greater than
801one, perhaps as follows:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800802
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800803 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800804 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
805 if (q % MAX) {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800806 WRITE_ONCE(b, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800807 do_something();
808 } else {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800809 WRITE_ONCE(b, 2);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800810 do_something_else();
811 }
812
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700813Please note once again that the stores to 'b' differ. If they were
814identical, as noted earlier, the compiler could pull this store outside
815of the 'if' statement.
816
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700817You must also be careful not to rely too much on boolean short-circuit
818evaluation. Consider this example:
819
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800820 q = READ_ONCE(a);
Paul E. McKenney57aecae2015-05-18 18:27:42 -0700821 if (q || 1 > 0)
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700822 WRITE_ONCE(b, 1);
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700823
Paul E. McKenney5af46922015-04-25 12:48:29 -0700824Because the first condition cannot fault and the second condition is
825always true, the compiler can transform this example as following,
826defeating control dependency:
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700827
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800828 q = READ_ONCE(a);
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700829 WRITE_ONCE(b, 1);
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700830
831This example underscores the need to ensure that the compiler cannot
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700832out-guess your code. More generally, although READ_ONCE() does force
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700833the compiler to actually emit code for a given load, it does not force
834the compiler to use the results.
835
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700836In addition, control dependencies apply only to the then-clause and
837else-clause of the if-statement in question. In particular, it does
838not necessarily apply to code following the if-statement:
839
840 q = READ_ONCE(a);
841 if (q) {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800842 WRITE_ONCE(b, 1);
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700843 } else {
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800844 WRITE_ONCE(b, 2);
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700845 }
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800846 WRITE_ONCE(c, 1); /* BUG: No ordering against the read from 'a'. */
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700847
848It is tempting to argue that there in fact is ordering because the
849compiler cannot reorder volatile accesses and also cannot reorder
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800850the writes to 'b' with the condition. Unfortunately for this line
851of reasoning, the compiler might compile the two writes to 'b' as
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700852conditional-move instructions, as in this fanciful pseudo-assembly
853language:
854
855 ld r1,a
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700856 cmp r1,$0
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800857 cmov,ne r4,$1
858 cmov,eq r4,$2
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700859 st r4,b
860 st $1,c
861
862A weakly ordered CPU would have no dependency of any sort between the load
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800863from 'a' and the store to 'c'. The control dependencies would extend
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700864only to the pair of cmov instructions and the store depending on them.
865In short, control dependencies apply only to the stores in the then-clause
866and else-clause of the if-statement in question (including functions
867invoked by those two clauses), not to code following that if-statement.
868
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800869
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -0700870Note well that the ordering provided by a control dependency is local
871to the CPU containing it. See the section on "Multicopy atomicity"
872for more information.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800873
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800874
875In summary:
876
877 (*) Control dependencies can order prior loads against later stores.
878 However, they do -not- guarantee any other sort of ordering:
879 Not prior loads against later loads, nor prior stores against
880 later anything. If you need these other forms of ordering,
Davidlohr Buesod87510c2014-12-28 01:11:16 -0800881 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800882 later loads, smp_mb().
883
Paul E. McKenney7817b792015-12-29 16:23:18 -0800884 (*) If both legs of the "if" statement begin with identical stores to
885 the same variable, then those stores must be ordered, either by
886 preceding both of them with smp_mb() or by using smp_store_release()
887 to carry out the stores. Please note that it is -not- sufficient
Paul E. McKenneya5052652016-04-12 08:52:49 -0700888 to use barrier() at beginning of each leg of the "if" statement
889 because, as shown by the example above, optimizing compilers can
890 destroy the control dependency while respecting the letter of the
891 barrier() law.
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800892
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800893 (*) Control dependencies require at least one run-time conditional
Paul E. McKenney586dd562014-02-11 12:28:06 -0800894 between the prior load and the subsequent store, and this
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700895 conditional must involve the prior load. If the compiler is able
896 to optimize the conditional away, it will have also optimized
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800897 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
898 can help to preserve the needed conditional.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800899
900 (*) Control dependencies require that the compiler avoid reordering the
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800901 dependency into nonexistence. Careful use of READ_ONCE() or
902 atomic{,64}_read() can help to preserve your control dependency.
Paul E. McKenney895f5542016-01-06 14:23:03 -0800903 Please see the COMPILER BARRIER section for more information.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800904
Paul E. McKenneyebff09a2016-06-15 16:08:17 -0700905 (*) Control dependencies apply only to the then-clause and else-clause
906 of the if-statement containing the control dependency, including
907 any functions that these two clauses call. Control dependencies
908 do -not- apply to code following the if-statement containing the
909 control dependency.
910
Paul E. McKenneyff382812015-02-17 10:00:06 -0800911 (*) Control dependencies pair normally with other types of barriers.
912
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -0700913 (*) Control dependencies do -not- provide multicopy atomicity. If you
914 need all the CPUs to see a given store at the same time, use smp_mb().
David Howells108b42b2006-03-31 16:00:29 +0100915
Paul E. McKenneyc8241f82016-12-13 16:42:32 -0800916 (*) Compilers do not understand control dependencies. It is therefore
917 your job to ensure that they do not break your code.
918
David Howells108b42b2006-03-31 16:00:29 +0100919
920SMP BARRIER PAIRING
921-------------------
922
923When dealing with CPU-CPU interactions, certain types of memory barrier should
924always be paired. A lack of appropriate pairing is almost certainly an error.
925
Paul E. McKenneyff382812015-02-17 10:00:06 -0800926General barriers pair with each other, though they also pair with most
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -0700927other types of barriers, albeit without multicopy atomicity. An acquire
928barrier pairs with a release barrier, but both may also pair with other
929barriers, including of course general barriers. A write barrier pairs
930with a data dependency barrier, a control dependency, an acquire barrier,
931a release barrier, a read barrier, or a general barrier. Similarly a
932read barrier, control dependency, or a data dependency barrier pairs
933with a write barrier, an acquire barrier, a release barrier, or a
934general barrier:
David Howells108b42b2006-03-31 16:00:29 +0100935
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800936 CPU 1 CPU 2
937 =============== ===============
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700938 WRITE_ONCE(a, 1);
David Howells108b42b2006-03-31 16:00:29 +0100939 <write barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700940 WRITE_ONCE(b, 2); x = READ_ONCE(b);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800941 <read barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700942 y = READ_ONCE(a);
David Howells108b42b2006-03-31 16:00:29 +0100943
944Or:
945
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800946 CPU 1 CPU 2
947 =============== ===============================
David Howells108b42b2006-03-31 16:00:29 +0100948 a = 1;
949 <write barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700950 WRITE_ONCE(b, &a); x = READ_ONCE(b);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800951 <data dependency barrier>
952 y = *x;
David Howells108b42b2006-03-31 16:00:29 +0100953
Paul E. McKenneyff382812015-02-17 10:00:06 -0800954Or even:
955
956 CPU 1 CPU 2
957 =============== ===============================
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700958 r1 = READ_ONCE(y);
Paul E. McKenneyff382812015-02-17 10:00:06 -0800959 <general barrier>
Scott Tsaid92f8422017-09-20 02:16:00 +0800960 WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {
Paul E. McKenneyff382812015-02-17 10:00:06 -0800961 <implicit control dependency>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700962 WRITE_ONCE(y, 1);
Paul E. McKenneyff382812015-02-17 10:00:06 -0800963 }
964
965 assert(r1 == 0 || r2 == 0);
966
David Howells108b42b2006-03-31 16:00:29 +0100967Basically, the read barrier always has to be there, even though it can be of
968the "weaker" type.
969
David Howells670bd952006-06-10 09:54:12 -0700970[!] Note that the stores before the write barrier would normally be expected to
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700971match the loads after the read barrier or the data dependency barrier, and vice
David Howells670bd952006-06-10 09:54:12 -0700972versa:
973
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800974 CPU 1 CPU 2
975 =================== ===================
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700976 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
977 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800978 <write barrier> \ <read barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700979 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
980 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
David Howells670bd952006-06-10 09:54:12 -0700981
David Howells108b42b2006-03-31 16:00:29 +0100982
983EXAMPLES OF MEMORY BARRIER SEQUENCES
984------------------------------------
985
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700986Firstly, write barriers act as partial orderings on store operations.
David Howells108b42b2006-03-31 16:00:29 +0100987Consider the following sequence of events:
988
989 CPU 1
990 =======================
991 STORE A = 1
992 STORE B = 2
993 STORE C = 3
994 <write barrier>
995 STORE D = 4
996 STORE E = 5
997
998This sequence of events is committed to the memory coherence system in an order
999that the rest of the system might perceive as the unordered set of { STORE A,
Adrian Bunk80f72282006-06-30 18:27:16 +02001000STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
David Howells108b42b2006-03-31 16:00:29 +01001001}:
1002
1003 +-------+ : :
1004 | | +------+
1005 | |------>| C=3 | } /\
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001006 | | : +------+ }----- \ -----> Events perceptible to
1007 | | : | A=1 | } \/ the rest of the system
David Howells108b42b2006-03-31 16:00:29 +01001008 | | : +------+ }
1009 | CPU 1 | : | B=2 | }
1010 | | +------+ }
1011 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
1012 | | +------+ } requires all stores prior to the
1013 | | : | E=5 | } barrier to be committed before
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001014 | | : +------+ } further stores may take place
David Howells108b42b2006-03-31 16:00:29 +01001015 | |------>| D=4 | }
1016 | | +------+
1017 +-------+ : :
1018 |
David Howells670bd952006-06-10 09:54:12 -07001019 | Sequence in which stores are committed to the
1020 | memory system by CPU 1
David Howells108b42b2006-03-31 16:00:29 +01001021 V
1022
1023
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001024Secondly, data dependency barriers act as partial orderings on data-dependent
David Howells108b42b2006-03-31 16:00:29 +01001025loads. Consider the following sequence of events:
1026
1027 CPU 1 CPU 2
1028 ======================= =======================
David Howellsc14038c2006-04-10 22:54:24 -07001029 { B = 7; X = 9; Y = 8; C = &Y }
David Howells108b42b2006-03-31 16:00:29 +01001030 STORE A = 1
1031 STORE B = 2
1032 <write barrier>
1033 STORE C = &B LOAD X
1034 STORE D = 4 LOAD C (gets &B)
1035 LOAD *C (reads B)
1036
1037Without intervention, CPU 2 may perceive the events on CPU 1 in some
1038effectively random order, despite the write barrier issued by CPU 1:
1039
1040 +-------+ : : : :
1041 | | +------+ +-------+ | Sequence of update
1042 | |------>| B=2 |----- --->| Y->8 | | of perception on
1043 | | : +------+ \ +-------+ | CPU 2
1044 | CPU 1 | : | A=1 | \ --->| C->&Y | V
1045 | | +------+ | +-------+
1046 | | wwwwwwwwwwwwwwww | : :
1047 | | +------+ | : :
1048 | | : | C=&B |--- | : : +-------+
1049 | | : +------+ \ | +-------+ | |
1050 | |------>| D=4 | ----------->| C->&B |------>| |
1051 | | +------+ | +-------+ | |
1052 +-------+ : : | : : | |
1053 | : : | |
1054 | : : | CPU 2 |
1055 | +-------+ | |
1056 Apparently incorrect ---> | | B->7 |------>| |
1057 perception of B (!) | +-------+ | |
1058 | : : | |
1059 | +-------+ | |
1060 The load of X holds ---> \ | X->9 |------>| |
1061 up the maintenance \ +-------+ | |
1062 of coherence of B ----->| B->2 | +-------+
1063 +-------+
1064 : :
1065
1066
1067In the above example, CPU 2 perceives that B is 7, despite the load of *C
Paolo Ornati670e9f32006-10-03 22:57:56 +02001068(which would be B) coming after the LOAD of C.
David Howells108b42b2006-03-31 16:00:29 +01001069
1070If, however, a data dependency barrier were to be placed between the load of C
David Howellsc14038c2006-04-10 22:54:24 -07001071and the load of *C (ie: B) on CPU 2:
1072
1073 CPU 1 CPU 2
1074 ======================= =======================
1075 { B = 7; X = 9; Y = 8; C = &Y }
1076 STORE A = 1
1077 STORE B = 2
1078 <write barrier>
1079 STORE C = &B LOAD X
1080 STORE D = 4 LOAD C (gets &B)
1081 <data dependency barrier>
1082 LOAD *C (reads B)
1083
1084then the following will occur:
David Howells108b42b2006-03-31 16:00:29 +01001085
1086 +-------+ : : : :
1087 | | +------+ +-------+
1088 | |------>| B=2 |----- --->| Y->8 |
1089 | | : +------+ \ +-------+
1090 | CPU 1 | : | A=1 | \ --->| C->&Y |
1091 | | +------+ | +-------+
1092 | | wwwwwwwwwwwwwwww | : :
1093 | | +------+ | : :
1094 | | : | C=&B |--- | : : +-------+
1095 | | : +------+ \ | +-------+ | |
1096 | |------>| D=4 | ----------->| C->&B |------>| |
1097 | | +------+ | +-------+ | |
1098 +-------+ : : | : : | |
1099 | : : | |
1100 | : : | CPU 2 |
1101 | +-------+ | |
David Howells670bd952006-06-10 09:54:12 -07001102 | | X->9 |------>| |
1103 | +-------+ | |
1104 Makes sure all effects ---> \ ddddddddddddddddd | |
1105 prior to the store of C \ +-------+ | |
1106 are perceptible to ----->| B->2 |------>| |
1107 subsequent loads +-------+ | |
David Howells108b42b2006-03-31 16:00:29 +01001108 : : +-------+
1109
1110
1111And thirdly, a read barrier acts as a partial order on loads. Consider the
1112following sequence of events:
1113
1114 CPU 1 CPU 2
1115 ======================= =======================
David Howells670bd952006-06-10 09:54:12 -07001116 { A = 0, B = 9 }
David Howells108b42b2006-03-31 16:00:29 +01001117 STORE A=1
David Howells108b42b2006-03-31 16:00:29 +01001118 <write barrier>
David Howells670bd952006-06-10 09:54:12 -07001119 STORE B=2
David Howells108b42b2006-03-31 16:00:29 +01001120 LOAD B
David Howells670bd952006-06-10 09:54:12 -07001121 LOAD A
David Howells108b42b2006-03-31 16:00:29 +01001122
1123Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1124some effectively random order, despite the write barrier issued by CPU 1:
1125
David Howells670bd952006-06-10 09:54:12 -07001126 +-------+ : : : :
1127 | | +------+ +-------+
1128 | |------>| A=1 |------ --->| A->0 |
1129 | | +------+ \ +-------+
1130 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1131 | | +------+ | +-------+
1132 | |------>| B=2 |--- | : :
1133 | | +------+ \ | : : +-------+
1134 +-------+ : : \ | +-------+ | |
1135 ---------->| B->2 |------>| |
1136 | +-------+ | CPU 2 |
1137 | | A->0 |------>| |
1138 | +-------+ | |
1139 | : : +-------+
1140 \ : :
1141 \ +-------+
1142 ---->| A->1 |
1143 +-------+
1144 : :
David Howells108b42b2006-03-31 16:00:29 +01001145
1146
David Howells6bc39272006-06-25 05:49:22 -07001147If, however, a read barrier were to be placed between the load of B and the
David Howells670bd952006-06-10 09:54:12 -07001148load of A on CPU 2:
David Howells108b42b2006-03-31 16:00:29 +01001149
David Howells670bd952006-06-10 09:54:12 -07001150 CPU 1 CPU 2
1151 ======================= =======================
1152 { A = 0, B = 9 }
1153 STORE A=1
1154 <write barrier>
1155 STORE B=2
1156 LOAD B
1157 <read barrier>
1158 LOAD A
1159
1160then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
11612:
1162
1163 +-------+ : : : :
1164 | | +------+ +-------+
1165 | |------>| A=1 |------ --->| A->0 |
1166 | | +------+ \ +-------+
1167 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1168 | | +------+ | +-------+
1169 | |------>| B=2 |--- | : :
1170 | | +------+ \ | : : +-------+
1171 +-------+ : : \ | +-------+ | |
1172 ---------->| B->2 |------>| |
1173 | +-------+ | CPU 2 |
1174 | : : | |
1175 | : : | |
1176 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1177 barrier causes all effects \ +-------+ | |
1178 prior to the storage of B ---->| A->1 |------>| |
1179 to be perceptible to CPU 2 +-------+ | |
1180 : : +-------+
1181
1182
1183To illustrate this more completely, consider what could happen if the code
1184contained a load of A either side of the read barrier:
1185
1186 CPU 1 CPU 2
1187 ======================= =======================
1188 { A = 0, B = 9 }
1189 STORE A=1
1190 <write barrier>
1191 STORE B=2
1192 LOAD B
1193 LOAD A [first load of A]
1194 <read barrier>
1195 LOAD A [second load of A]
1196
1197Even though the two loads of A both occur after the load of B, they may both
1198come up with different values:
1199
1200 +-------+ : : : :
1201 | | +------+ +-------+
1202 | |------>| A=1 |------ --->| A->0 |
1203 | | +------+ \ +-------+
1204 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1205 | | +------+ | +-------+
1206 | |------>| B=2 |--- | : :
1207 | | +------+ \ | : : +-------+
1208 +-------+ : : \ | +-------+ | |
1209 ---------->| B->2 |------>| |
1210 | +-------+ | CPU 2 |
1211 | : : | |
1212 | : : | |
1213 | +-------+ | |
1214 | | A->0 |------>| 1st |
1215 | +-------+ | |
1216 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1217 barrier causes all effects \ +-------+ | |
1218 prior to the storage of B ---->| A->1 |------>| 2nd |
1219 to be perceptible to CPU 2 +-------+ | |
1220 : : +-------+
1221
1222
1223But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1224before the read barrier completes anyway:
1225
1226 +-------+ : : : :
1227 | | +------+ +-------+
1228 | |------>| A=1 |------ --->| A->0 |
1229 | | +------+ \ +-------+
1230 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1231 | | +------+ | +-------+
1232 | |------>| B=2 |--- | : :
1233 | | +------+ \ | : : +-------+
1234 +-------+ : : \ | +-------+ | |
1235 ---------->| B->2 |------>| |
1236 | +-------+ | CPU 2 |
1237 | : : | |
1238 \ : : | |
1239 \ +-------+ | |
1240 ---->| A->1 |------>| 1st |
1241 +-------+ | |
1242 rrrrrrrrrrrrrrrrr | |
1243 +-------+ | |
1244 | A->1 |------>| 2nd |
1245 +-------+ | |
1246 : : +-------+
1247
1248
1249The guarantee is that the second load will always come up with A == 1 if the
1250load of B came up with B == 2. No such guarantee exists for the first load of
1251A; that may come up with either A == 0 or A == 1.
1252
1253
1254READ MEMORY BARRIERS VS LOAD SPECULATION
1255----------------------------------------
1256
1257Many CPUs speculate with loads: that is they see that they will need to load an
1258item from memory, and they find a time where they're not using the bus for any
1259other loads, and so do the load in advance - even though they haven't actually
1260got to that point in the instruction execution flow yet. This permits the
1261actual load instruction to potentially complete immediately because the CPU
1262already has the value to hand.
1263
1264It may turn out that the CPU didn't actually need the value - perhaps because a
1265branch circumvented the load - in which case it can discard the value or just
1266cache it for later use.
1267
1268Consider:
1269
Ingo Molnare0edc782013-11-22 11:24:53 +01001270 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001271 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001272 LOAD B
1273 DIVIDE } Divide instructions generally
1274 DIVIDE } take a long time to perform
1275 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001276
1277Which might appear as this:
1278
1279 : : +-------+
1280 +-------+ | |
1281 --->| B->2 |------>| |
1282 +-------+ | CPU 2 |
1283 : :DIVIDE | |
1284 +-------+ | |
1285 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1286 division speculates on the +-------+ ~ | |
1287 LOAD of A : : ~ | |
1288 : :DIVIDE | |
1289 : : ~ | |
1290 Once the divisions are complete --> : : ~-->| |
1291 the CPU can then perform the : : | |
1292 LOAD with immediate effect : : +-------+
1293
1294
1295Placing a read barrier or a data dependency barrier just before the second
1296load:
1297
Ingo Molnare0edc782013-11-22 11:24:53 +01001298 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001299 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001300 LOAD B
1301 DIVIDE
1302 DIVIDE
David Howells670bd952006-06-10 09:54:12 -07001303 <read barrier>
Ingo Molnare0edc782013-11-22 11:24:53 +01001304 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001305
1306will force any value speculatively obtained to be reconsidered to an extent
1307dependent on the type of barrier used. If there was no change made to the
1308speculated memory location, then the speculated value will just be used:
1309
1310 : : +-------+
1311 +-------+ | |
1312 --->| B->2 |------>| |
1313 +-------+ | CPU 2 |
1314 : :DIVIDE | |
1315 +-------+ | |
1316 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1317 division speculates on the +-------+ ~ | |
1318 LOAD of A : : ~ | |
1319 : :DIVIDE | |
1320 : : ~ | |
1321 : : ~ | |
1322 rrrrrrrrrrrrrrrr~ | |
1323 : : ~ | |
1324 : : ~-->| |
1325 : : | |
1326 : : +-------+
1327
1328
1329but if there was an update or an invalidation from another CPU pending, then
1330the speculation will be cancelled and the value reloaded:
1331
1332 : : +-------+
1333 +-------+ | |
1334 --->| B->2 |------>| |
1335 +-------+ | CPU 2 |
1336 : :DIVIDE | |
1337 +-------+ | |
1338 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1339 division speculates on the +-------+ ~ | |
1340 LOAD of A : : ~ | |
1341 : :DIVIDE | |
1342 : : ~ | |
1343 : : ~ | |
1344 rrrrrrrrrrrrrrrrr | |
1345 +-------+ | |
1346 The speculation is discarded ---> --->| A->1 |------>| |
1347 and an updated value is +-------+ | |
1348 retrieved : : +-------+
David Howells108b42b2006-03-31 16:00:29 +01001349
1350
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001351MULTICOPY ATOMICITY
1352--------------------
Paul E. McKenney241e6662011-02-10 16:54:50 -08001353
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001354Multicopy atomicity is a deeply intuitive notion about ordering that is
1355not always provided by real computer systems, namely that a given store
Alan Stern0902b1f2017-09-01 07:53:34 -07001356becomes visible at the same time to all CPUs, or, alternatively, that all
1357CPUs agree on the order in which all stores become visible. However,
1358support of full multicopy atomicity would rule out valuable hardware
1359optimizations, so a weaker form called ``other multicopy atomicity''
1360instead guarantees only that a given store becomes visible at the same
1361time to all -other- CPUs. The remainder of this document discusses this
1362weaker form, but for brevity will call it simply ``multicopy atomicity''.
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001363
1364The following example demonstrates multicopy atomicity:
Paul E. McKenney241e6662011-02-10 16:54:50 -08001365
1366 CPU 1 CPU 2 CPU 3
1367 ======================= ======================= =======================
1368 { X = 0, Y = 0 }
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001369 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)
1370 <general barrier> <read barrier>
1371 STORE Y=r1 LOAD X
Paul E. McKenney241e6662011-02-10 16:54:50 -08001372
Alan Stern0902b1f2017-09-01 07:53:34 -07001373Suppose that CPU 2's load from X returns 1, which it then stores to Y,
1374and CPU 3's load from Y returns 1. This indicates that CPU 1's store
1375to X precedes CPU 2's load from X and that CPU 2's store to Y precedes
1376CPU 3's load from Y. In addition, the memory barriers guarantee that
1377CPU 2 executes its load before its store, and CPU 3 loads from Y before
1378it loads from X. The question is then "Can CPU 3's load from X return 0?"
Paul E. McKenney241e6662011-02-10 16:54:50 -08001379
Alan Stern0902b1f2017-09-01 07:53:34 -07001380Because CPU 3's load from X in some sense comes after CPU 2's load, it
Paul E. McKenney241e6662011-02-10 16:54:50 -08001381is natural to expect that CPU 3's load from X must therefore return 1.
Alan Stern0902b1f2017-09-01 07:53:34 -07001382This expectation follows from multicopy atomicity: if a load executing
1383on CPU B follows a load from the same variable executing on CPU A (and
1384CPU A did not originally store the value which it read), then on
1385multicopy-atomic systems, CPU B's load must return either the same value
1386that CPU A's load did or some later value. However, the Linux kernel
1387does not require systems to be multicopy atomic.
Paul E. McKenney241e6662011-02-10 16:54:50 -08001388
Alan Stern0902b1f2017-09-01 07:53:34 -07001389The use of a general memory barrier in the example above compensates
1390for any lack of multicopy atomicity. In the example, if CPU 2's load
1391from X returns 1 and CPU 3's load from Y returns 1, then CPU 3's load
1392from X must indeed also return 1.
Paul E. McKenney241e6662011-02-10 16:54:50 -08001393
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001394However, dependencies, read barriers, and write barriers are not always
1395able to compensate for non-multicopy atomicity. For example, suppose
1396that CPU 2's general barrier is removed from the above example, leaving
1397only the data dependency shown below:
Paul E. McKenney241e6662011-02-10 16:54:50 -08001398
1399 CPU 1 CPU 2 CPU 3
1400 ======================= ======================= =======================
1401 { X = 0, Y = 0 }
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001402 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)
1403 <data dependency> <read barrier>
1404 STORE Y=r1 LOAD X (reads 0)
Paul E. McKenney241e6662011-02-10 16:54:50 -08001405
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001406This substitution allows non-multicopy atomicity to run rampant: in
1407this example, it is perfectly legal for CPU 2's load from X to return 1,
1408CPU 3's load from Y to return 1, and its load from X to return 0.
Paul E. McKenney241e6662011-02-10 16:54:50 -08001409
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001410The key point is that although CPU 2's data dependency orders its load
Alan Stern0902b1f2017-09-01 07:53:34 -07001411and store, it does not guarantee to order CPU 1's store. Thus, if this
1412example runs on a non-multicopy-atomic system where CPUs 1 and 2 share a
1413store buffer or a level of cache, CPU 2 might have early access to CPU 1's
1414writes. General barriers are therefore required to ensure that all CPUs
1415agree on the combined order of multiple accesses.
Paul E. McKenney241e6662011-02-10 16:54:50 -08001416
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001417General barriers can compensate not only for non-multicopy atomicity,
1418but can also generate additional ordering that can ensure that -all-
1419CPUs will perceive the same order of -all- operations. In contrast, a
1420chain of release-acquire pairs do not provide this additional ordering,
1421which means that only those CPUs on the chain are guaranteed to agree
1422on the combined order of the accesses. For example, switching to C code
1423in deference to the ghost of Herman Hollerith:
Paul E. McKenneyc535cc92016-01-15 09:30:42 -08001424
1425 int u, v, x, y, z;
1426
1427 void cpu0(void)
1428 {
1429 r0 = smp_load_acquire(&x);
1430 WRITE_ONCE(u, 1);
1431 smp_store_release(&y, 1);
1432 }
1433
1434 void cpu1(void)
1435 {
1436 r1 = smp_load_acquire(&y);
1437 r4 = READ_ONCE(v);
1438 r5 = READ_ONCE(u);
1439 smp_store_release(&z, 1);
1440 }
1441
1442 void cpu2(void)
1443 {
1444 r2 = smp_load_acquire(&z);
1445 smp_store_release(&x, 1);
1446 }
1447
1448 void cpu3(void)
1449 {
1450 WRITE_ONCE(v, 1);
1451 smp_mb();
1452 r3 = READ_ONCE(u);
1453 }
1454
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001455Because cpu0(), cpu1(), and cpu2() participate in a chain of
1456smp_store_release()/smp_load_acquire() pairs, the following outcome
1457is prohibited:
Paul E. McKenneyc535cc92016-01-15 09:30:42 -08001458
1459 r0 == 1 && r1 == 1 && r2 == 1
1460
1461Furthermore, because of the release-acquire relationship between cpu0()
1462and cpu1(), cpu1() must see cpu0()'s writes, so that the following
1463outcome is prohibited:
1464
1465 r1 == 1 && r5 == 0
1466
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001467However, the ordering provided by a release-acquire chain is local
1468to the CPUs participating in that chain and does not apply to cpu3(),
1469at least aside from stores. Therefore, the following outcome is possible:
Paul E. McKenneyc535cc92016-01-15 09:30:42 -08001470
1471 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
1472
Paul E. McKenney37ef0342016-01-25 22:12:34 -08001473As an aside, the following outcome is also possible:
1474
1475 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
1476
Paul E. McKenneyc535cc92016-01-15 09:30:42 -08001477Although cpu0(), cpu1(), and cpu2() will see their respective reads and
1478writes in order, CPUs not involved in the release-acquire chain might
1479well disagree on the order. This disagreement stems from the fact that
1480the weak memory-barrier instructions used to implement smp_load_acquire()
1481and smp_store_release() are not required to order prior stores against
1482subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1483store to u as happening -after- cpu1()'s load from v, even though
1484both cpu0() and cpu1() agree that these two operations occurred in the
1485intended order.
1486
1487However, please keep in mind that smp_load_acquire() is not magic.
1488In particular, it simply reads from its argument with ordering. It does
1489-not- ensure that any particular value will be read. Therefore, the
1490following outcome is possible:
1491
1492 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0
1493
1494Note that this outcome can happen even on a mythical sequentially
1495consistent system where nothing is ever reordered.
1496
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07001497To reiterate, if your code requires full ordering of all operations,
1498use general barriers throughout.
Paul E. McKenney241e6662011-02-10 16:54:50 -08001499
1500
David Howells108b42b2006-03-31 16:00:29 +01001501========================
1502EXPLICIT KERNEL BARRIERS
1503========================
1504
1505The Linux kernel has a variety of different barriers that act at different
1506levels:
1507
1508 (*) Compiler barrier.
1509
1510 (*) CPU memory barriers.
1511
David Howells108b42b2006-03-31 16:00:29 +01001512
1513COMPILER BARRIER
1514----------------
1515
1516The Linux kernel has an explicit compiler barrier function that prevents the
1517compiler from moving the memory accesses either side of it to the other side:
1518
1519 barrier();
1520
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001521This is a general barrier -- there are no read-read or write-write
1522variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1523thought of as weak forms of barrier() that affect only the specific
1524accesses flagged by the READ_ONCE() or WRITE_ONCE().
David Howells108b42b2006-03-31 16:00:29 +01001525
Paul E. McKenney692118d2013-12-11 13:59:07 -08001526The barrier() function has the following effects:
1527
1528 (*) Prevents the compiler from reordering accesses following the
1529 barrier() to precede any accesses preceding the barrier().
1530 One example use for this property is to ease communication between
1531 interrupt-handler code and the code that was interrupted.
1532
1533 (*) Within a loop, forces the compiler to load the variables used
1534 in that loop's conditional on each pass through that loop.
1535
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001536The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1537optimizations that, while perfectly safe in single-threaded code, can
1538be fatal in concurrent code. Here are some examples of these sorts
1539of optimizations:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001540
Paul E. McKenney449f7412014-01-02 15:03:50 -08001541 (*) The compiler is within its rights to reorder loads and stores
1542 to the same variable, and in some cases, the CPU is within its
1543 rights to reorder loads to the same variable. This means that
1544 the following code:
1545
1546 a[0] = x;
1547 a[1] = x;
1548
1549 Might result in an older value of x stored in a[1] than in a[0].
1550 Prevent both the compiler and the CPU from doing this as follows:
1551
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001552 a[0] = READ_ONCE(x);
1553 a[1] = READ_ONCE(x);
Paul E. McKenney449f7412014-01-02 15:03:50 -08001554
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001555 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1556 accesses from multiple CPUs to a single variable.
Paul E. McKenney449f7412014-01-02 15:03:50 -08001557
Paul E. McKenney692118d2013-12-11 13:59:07 -08001558 (*) The compiler is within its rights to merge successive loads from
1559 the same variable. Such merging can cause the compiler to "optimize"
1560 the following code:
1561
1562 while (tmp = a)
1563 do_something_with(tmp);
1564
1565 into the following code, which, although in some sense legitimate
1566 for single-threaded code, is almost certainly not what the developer
1567 intended:
1568
1569 if (tmp = a)
1570 for (;;)
1571 do_something_with(tmp);
1572
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001573 Use READ_ONCE() to prevent the compiler from doing this to you:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001574
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001575 while (tmp = READ_ONCE(a))
Paul E. McKenney692118d2013-12-11 13:59:07 -08001576 do_something_with(tmp);
1577
1578 (*) The compiler is within its rights to reload a variable, for example,
1579 in cases where high register pressure prevents the compiler from
1580 keeping all data of interest in registers. The compiler might
1581 therefore optimize the variable 'tmp' out of our previous example:
1582
1583 while (tmp = a)
1584 do_something_with(tmp);
1585
1586 This could result in the following code, which is perfectly safe in
1587 single-threaded code, but can be fatal in concurrent code:
1588
1589 while (a)
1590 do_something_with(a);
1591
1592 For example, the optimized version of this code could result in
1593 passing a zero to do_something_with() in the case where the variable
1594 a was modified by some other CPU between the "while" statement and
1595 the call to do_something_with().
1596
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001597 Again, use READ_ONCE() to prevent the compiler from doing this:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001598
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001599 while (tmp = READ_ONCE(a))
Paul E. McKenney692118d2013-12-11 13:59:07 -08001600 do_something_with(tmp);
1601
1602 Note that if the compiler runs short of registers, it might save
1603 tmp onto the stack. The overhead of this saving and later restoring
1604 is why compilers reload variables. Doing so is perfectly safe for
1605 single-threaded code, so you need to tell the compiler about cases
1606 where it is not safe.
1607
1608 (*) The compiler is within its rights to omit a load entirely if it knows
1609 what the value will be. For example, if the compiler can prove that
1610 the value of variable 'a' is always zero, it can optimize this code:
1611
1612 while (tmp = a)
1613 do_something_with(tmp);
1614
1615 Into this:
1616
1617 do { } while (0);
1618
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001619 This transformation is a win for single-threaded code because it
1620 gets rid of a load and a branch. The problem is that the compiler
1621 will carry out its proof assuming that the current CPU is the only
1622 one updating variable 'a'. If variable 'a' is shared, then the
1623 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1624 compiler that it doesn't know as much as it thinks it does:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001625
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001626 while (tmp = READ_ONCE(a))
Paul E. McKenney692118d2013-12-11 13:59:07 -08001627 do_something_with(tmp);
1628
1629 But please note that the compiler is also closely watching what you
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001630 do with the value after the READ_ONCE(). For example, suppose you
Paul E. McKenney692118d2013-12-11 13:59:07 -08001631 do the following and MAX is a preprocessor macro with the value 1:
1632
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001633 while ((tmp = READ_ONCE(a)) % MAX)
Paul E. McKenney692118d2013-12-11 13:59:07 -08001634 do_something_with(tmp);
1635
1636 Then the compiler knows that the result of the "%" operator applied
1637 to MAX will always be zero, again allowing the compiler to optimize
1638 the code into near-nonexistence. (It will still load from the
1639 variable 'a'.)
1640
1641 (*) Similarly, the compiler is within its rights to omit a store entirely
1642 if it knows that the variable already has the value being stored.
1643 Again, the compiler assumes that the current CPU is the only one
1644 storing into the variable, which can cause the compiler to do the
1645 wrong thing for shared variables. For example, suppose you have
1646 the following:
1647
1648 a = 0;
SeongJae Park65f95ff2016-02-22 08:28:29 -08001649 ... Code that does not store to variable a ...
Paul E. McKenney692118d2013-12-11 13:59:07 -08001650 a = 0;
1651
1652 The compiler sees that the value of variable 'a' is already zero, so
1653 it might well omit the second store. This would come as a fatal
1654 surprise if some other CPU might have stored to variable 'a' in the
1655 meantime.
1656
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001657 Use WRITE_ONCE() to prevent the compiler from making this sort of
Paul E. McKenney692118d2013-12-11 13:59:07 -08001658 wrong guess:
1659
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001660 WRITE_ONCE(a, 0);
SeongJae Park65f95ff2016-02-22 08:28:29 -08001661 ... Code that does not store to variable a ...
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001662 WRITE_ONCE(a, 0);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001663
1664 (*) The compiler is within its rights to reorder memory accesses unless
1665 you tell it not to. For example, consider the following interaction
1666 between process-level code and an interrupt handler:
1667
1668 void process_level(void)
1669 {
1670 msg = get_message();
1671 flag = true;
1672 }
1673
1674 void interrupt_handler(void)
1675 {
1676 if (flag)
1677 process_message(msg);
1678 }
1679
Masanari Iidadf5cbb22014-03-21 10:04:30 +09001680 There is nothing to prevent the compiler from transforming
Paul E. McKenney692118d2013-12-11 13:59:07 -08001681 process_level() to the following, in fact, this might well be a
1682 win for single-threaded code:
1683
1684 void process_level(void)
1685 {
1686 flag = true;
1687 msg = get_message();
1688 }
1689
1690 If the interrupt occurs between these two statement, then
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001691 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
Paul E. McKenney692118d2013-12-11 13:59:07 -08001692 to prevent this as follows:
1693
1694 void process_level(void)
1695 {
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001696 WRITE_ONCE(msg, get_message());
1697 WRITE_ONCE(flag, true);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001698 }
1699
1700 void interrupt_handler(void)
1701 {
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001702 if (READ_ONCE(flag))
1703 process_message(READ_ONCE(msg));
Paul E. McKenney692118d2013-12-11 13:59:07 -08001704 }
1705
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001706 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1707 interrupt_handler() are needed if this interrupt handler can itself
1708 be interrupted by something that also accesses 'flag' and 'msg',
1709 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1710 and WRITE_ONCE() are not needed in interrupt_handler() other than
1711 for documentation purposes. (Note also that nested interrupts
1712 do not typically occur in modern Linux kernels, in fact, if an
1713 interrupt handler returns with interrupts enabled, you will get a
1714 WARN_ONCE() splat.)
Paul E. McKenney692118d2013-12-11 13:59:07 -08001715
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001716 You should assume that the compiler can move READ_ONCE() and
1717 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1718 barrier(), or similar primitives.
Paul E. McKenney692118d2013-12-11 13:59:07 -08001719
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001720 This effect could also be achieved using barrier(), but READ_ONCE()
1721 and WRITE_ONCE() are more selective: With READ_ONCE() and
1722 WRITE_ONCE(), the compiler need only forget the contents of the
1723 indicated memory locations, while with barrier() the compiler must
SeongJae Park8149b5c2020-01-31 21:52:37 +01001724 discard the value of all memory locations that it has currently
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001725 cached in any machine registers. Of course, the compiler must also
1726 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1727 though the CPU of course need not do so.
Paul E. McKenney692118d2013-12-11 13:59:07 -08001728
1729 (*) The compiler is within its rights to invent stores to a variable,
1730 as in the following example:
1731
1732 if (a)
1733 b = a;
1734 else
1735 b = 42;
1736
1737 The compiler might save a branch by optimizing this as follows:
1738
1739 b = 42;
1740 if (a)
1741 b = a;
1742
1743 In single-threaded code, this is not only safe, but also saves
1744 a branch. Unfortunately, in concurrent code, this optimization
1745 could cause some other CPU to see a spurious value of 42 -- even
1746 if variable 'a' was never zero -- when loading variable 'b'.
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001747 Use WRITE_ONCE() to prevent this as follows:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001748
1749 if (a)
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001750 WRITE_ONCE(b, a);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001751 else
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001752 WRITE_ONCE(b, 42);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001753
1754 The compiler can also invent loads. These are usually less
1755 damaging, but they can result in cache-line bouncing and thus in
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001756 poor performance and scalability. Use READ_ONCE() to prevent
Paul E. McKenney692118d2013-12-11 13:59:07 -08001757 invented loads.
1758
1759 (*) For aligned memory locations whose size allows them to be accessed
1760 with a single memory-reference instruction, prevents "load tearing"
1761 and "store tearing," in which a single large access is replaced by
1762 multiple smaller accesses. For example, given an architecture having
1763 16-bit store instructions with 7-bit immediate fields, the compiler
1764 might be tempted to use two 16-bit store-immediate instructions to
1765 implement the following 32-bit store:
1766
1767 p = 0x00010002;
1768
1769 Please note that GCC really does use this sort of optimization,
1770 which is not surprising given that it would likely take more
1771 than two instructions to build the constant and then store it.
1772 This optimization can therefore be a win in single-threaded code.
1773 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1774 this optimization in a volatile store. In the absence of such bugs,
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001775 use of WRITE_ONCE() prevents store tearing in the following example:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001776
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001777 WRITE_ONCE(p, 0x00010002);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001778
1779 Use of packed structures can also result in load and store tearing,
1780 as in this example:
1781
1782 struct __attribute__((__packed__)) foo {
1783 short a;
1784 int b;
1785 short c;
1786 };
1787 struct foo foo1, foo2;
1788 ...
1789
1790 foo2.a = foo1.a;
1791 foo2.b = foo1.b;
1792 foo2.c = foo1.c;
1793
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001794 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1795 volatile markings, the compiler would be well within its rights to
1796 implement these three assignment statements as a pair of 32-bit
1797 loads followed by a pair of 32-bit stores. This would result in
1798 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1799 and WRITE_ONCE() again prevent tearing in this example:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001800
1801 foo2.a = foo1.a;
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001802 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
Paul E. McKenney692118d2013-12-11 13:59:07 -08001803 foo2.c = foo1.c;
1804
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001805All that aside, it is never necessary to use READ_ONCE() and
1806WRITE_ONCE() on a variable that has been marked volatile. For example,
1807because 'jiffies' is marked volatile, it is never necessary to
1808say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1809WRITE_ONCE() are implemented as volatile casts, which has no effect when
1810its argument is already marked volatile.
Paul E. McKenney692118d2013-12-11 13:59:07 -08001811
1812Please note that these compiler barriers have no direct effect on the CPU,
1813which may then reorder things however it wishes.
David Howells108b42b2006-03-31 16:00:29 +01001814
1815
1816CPU MEMORY BARRIERS
1817-------------------
1818
1819The Linux kernel has eight basic CPU memory barriers:
1820
1821 TYPE MANDATORY SMP CONDITIONAL
1822 =============== ======================= ===========================
1823 GENERAL mb() smp_mb()
1824 WRITE wmb() smp_wmb()
1825 READ rmb() smp_rmb()
Paul E. McKenney9ad3c142017-11-27 09:20:40 -08001826 DATA DEPENDENCY READ_ONCE()
David Howells108b42b2006-03-31 16:00:29 +01001827
1828
Nick Piggin73f10282008-05-14 06:35:11 +02001829All memory barriers except the data dependency barriers imply a compiler
SeongJae Park0b6fa342016-04-12 08:52:53 -07001830barrier. Data dependencies do not impose any additional compiler ordering.
Nick Piggin73f10282008-05-14 06:35:11 +02001831
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001832Aside: In the case of data dependencies, the compiler would be expected
1833to issue the loads in the correct order (eg. `a[b]` would have to load
1834the value of b before loading a[b]), however there is no guarantee in
1835the C specification that the compiler may not speculate the value of b
SeongJae Park8149b5c2020-01-31 21:52:37 +01001836(eg. is equal to 1) and load a[b] before b (eg. tmp = a[1]; if (b != 1)
SeongJae Park0b6fa342016-04-12 08:52:53 -07001837tmp = a[b]; ). There is also the problem of a compiler reloading b after
1838having loaded a[b], thus having a newer copy of b than a[b]. A consensus
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001839has not yet been reached about these problems, however the READ_ONCE()
1840macro is a good place to start looking.
David Howells108b42b2006-03-31 16:00:29 +01001841
1842SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001843systems because it is assumed that a CPU will appear to be self-consistent,
David Howells108b42b2006-03-31 16:00:29 +01001844and will order overlapping accesses correctly with respect to itself.
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02001845However, see the subsection on "Virtual Machine Guests" below.
David Howells108b42b2006-03-31 16:00:29 +01001846
1847[!] Note that SMP memory barriers _must_ be used to control the ordering of
1848references to shared memory on SMP systems, though the use of locking instead
1849is sufficient.
1850
1851Mandatory barriers should not be used to control SMP effects, since mandatory
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02001852barriers impose unnecessary overhead on both SMP and UP systems. They may,
1853however, be used to control MMIO effects on accesses through relaxed memory I/O
1854windows. These barriers are required even on non-SMP systems as they affect
1855the order in which memory operations appear to a device by prohibiting both the
1856compiler and the CPU from reordering them.
David Howells108b42b2006-03-31 16:00:29 +01001857
1858
1859There are some more advanced barrier functions:
1860
Peter Zijlstrab92b8b32015-05-12 10:51:55 +02001861 (*) smp_store_mb(var, value)
David Howells108b42b2006-03-31 16:00:29 +01001862
Oleg Nesterov75b2bd52006-11-08 17:44:38 -08001863 This assigns the value to the variable and then inserts a full memory
Davidlohr Bueso2d142e52015-10-27 12:53:51 -07001864 barrier after it. It isn't guaranteed to insert anything more than a
1865 compiler barrier in a UP compilation.
David Howells108b42b2006-03-31 16:00:29 +01001866
1867
Peter Zijlstra1b156112014-03-13 19:00:35 +01001868 (*) smp_mb__before_atomic();
1869 (*) smp_mb__after_atomic();
David Howells108b42b2006-03-31 16:00:29 +01001870
Manfred Spraul39323c62020-02-03 17:34:29 -08001871 These are for use with atomic RMW functions that do not imply memory
1872 barriers, but where the code needs a memory barrier. Examples for atomic
Fox Chend8566f12020-09-09 14:53:40 +08001873 RMW functions that do not imply a memory barrier are e.g. add,
Manfred Spraul39323c62020-02-03 17:34:29 -08001874 subtract, (failed) conditional operations, _relaxed functions,
1875 but not atomic_read or atomic_set. A common example where a memory
1876 barrier may be required is when atomic ops are used for reference
1877 counting.
Peter Zijlstra1b156112014-03-13 19:00:35 +01001878
Manfred Spraul39323c62020-02-03 17:34:29 -08001879 These are also used for atomic RMW bitop functions that do not imply a
1880 memory barrier (such as set_bit and clear_bit).
David Howells108b42b2006-03-31 16:00:29 +01001881
1882 As an example, consider a piece of code that marks an object as being dead
1883 and then decrements the object's reference count:
1884
1885 obj->dead = 1;
Peter Zijlstra1b156112014-03-13 19:00:35 +01001886 smp_mb__before_atomic();
David Howells108b42b2006-03-31 16:00:29 +01001887 atomic_dec(&obj->ref_count);
1888
1889 This makes sure that the death mark on the object is perceived to be set
1890 *before* the reference counter is decremented.
1891
Peter Zijlstra706eeb32017-06-12 14:50:27 +02001892 See Documentation/atomic_{t,bitops}.txt for more information.
David Howells108b42b2006-03-31 16:00:29 +01001893
1894
Alexander Duyck1077fa32014-12-11 15:02:06 -08001895 (*) dma_wmb();
1896 (*) dma_rmb();
1897
1898 These are for use with consistent memory to guarantee the ordering
1899 of writes or reads of shared memory accessible to both the CPU and a
1900 DMA capable device.
1901
1902 For example, consider a device driver that shares memory with a device
1903 and uses a descriptor status value to indicate if the descriptor belongs
1904 to the device or the CPU, and a doorbell to notify it when new
1905 descriptors are available:
1906
1907 if (desc->status != DEVICE_OWN) {
1908 /* do not read data until we own descriptor */
1909 dma_rmb();
1910
1911 /* read/modify data */
1912 read_data = desc->data;
1913 desc->data = write_data;
1914
1915 /* flush modifications before status update */
1916 dma_wmb();
1917
1918 /* assign ownership */
1919 desc->status = DEVICE_OWN;
1920
Alexander Duyck1077fa32014-12-11 15:02:06 -08001921 /* notify device of new descriptors */
1922 writel(DESC_NOTIFY, doorbell);
1923 }
1924
1925 The dma_rmb() allows us guarantee the device has released ownership
Sylvain Trias7a458002015-04-08 10:27:57 +02001926 before we read the data from the descriptor, and the dma_wmb() allows
Alexander Duyck1077fa32014-12-11 15:02:06 -08001927 us to guarantee the data is written to the descriptor before the device
Will Deacon58465812018-05-14 15:55:26 -07001928 can see it now has ownership. Note that, when using writel(), a prior
1929 wmb() is not needed to guarantee that the cache coherent memory writes
1930 have completed before writing to the MMIO region. The cheaper
1931 writel_relaxed() does not provide this guarantee and must not be used
1932 here.
Alexander Duyck1077fa32014-12-11 15:02:06 -08001933
Will Deacon58465812018-05-14 15:55:26 -07001934 See the subsection "Kernel I/O barrier effects" for more information on
SeongJae Park537f3a72020-08-29 10:26:05 +02001935 relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for
1936 more information on consistent memory.
Alexander Duyck1077fa32014-12-11 15:02:06 -08001937
Aneesh Kumar K.V3e79f082020-07-01 12:52:32 +05301938 (*) pmem_wmb();
1939
1940 This is for use with persistent memory to ensure that stores for which
1941 modifications are written to persistent storage reached a platform
1942 durability domain.
1943
1944 For example, after a non-temporal write to pmem region, we use pmem_wmb()
1945 to ensure that stores have reached a platform durability domain. This ensures
1946 that stores have updated persistent storage before any data access or
1947 data transfer caused by subsequent instructions is initiated. This is
1948 in addition to the ordering done by wmb().
1949
1950 For load from persistent memory, existing read memory barriers are sufficient
1951 to ensure read ordering.
SeongJae Parkdfeccea2016-08-11 11:17:40 -07001952
Xiongfeng Wangd5624bb2021-12-21 11:55:56 +08001953 (*) io_stop_wc();
1954
1955 For memory accesses with write-combining attributes (e.g. those returned
1956 by ioremap_wc(), the CPU may wait for prior accesses to be merged with
1957 subsequent ones. io_stop_wc() can be used to prevent the merging of
1958 write-combining memory accesses before this macro with those after it when
1959 such wait has performance implications.
1960
David Howells108b42b2006-03-31 16:00:29 +01001961===============================
1962IMPLICIT KERNEL MEMORY BARRIERS
1963===============================
1964
1965Some of the other functions in the linux kernel imply memory barriers, amongst
David Howells670bd952006-06-10 09:54:12 -07001966which are locking and scheduling functions.
David Howells108b42b2006-03-31 16:00:29 +01001967
1968This specification is a _minimum_ guarantee; any particular architecture may
1969provide more substantial guarantees, but these may not be relied upon outside
1970of arch specific code.
1971
1972
SeongJae Park166bda72016-04-12 08:52:50 -07001973LOCK ACQUISITION FUNCTIONS
1974--------------------------
David Howells108b42b2006-03-31 16:00:29 +01001975
1976The Linux kernel has a number of locking constructs:
1977
1978 (*) spin locks
1979 (*) R/W spin locks
1980 (*) mutexes
1981 (*) semaphores
1982 (*) R/W semaphores
David Howells108b42b2006-03-31 16:00:29 +01001983
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001984In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
David Howells108b42b2006-03-31 16:00:29 +01001985for each construct. These operations all imply certain barriers:
1986
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001987 (1) ACQUIRE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001988
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001989 Memory operations issued after the ACQUIRE will be completed after the
1990 ACQUIRE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001991
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001992 Memory operations issued before the ACQUIRE may be completed after
Peter Zijlstraa9668cd2017-06-07 17:51:27 +02001993 the ACQUIRE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001994
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001995 (2) RELEASE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001996
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001997 Memory operations issued before the RELEASE will be completed before the
1998 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001999
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002000 Memory operations issued after the RELEASE may be completed before the
2001 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01002002
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002003 (3) ACQUIRE vs ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01002004
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002005 All ACQUIRE operations issued before another ACQUIRE operation will be
2006 completed before that ACQUIRE operation.
David Howells108b42b2006-03-31 16:00:29 +01002007
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002008 (4) ACQUIRE vs RELEASE implication:
David Howells108b42b2006-03-31 16:00:29 +01002009
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002010 All ACQUIRE operations issued before a RELEASE operation will be
2011 completed before the RELEASE operation.
David Howells108b42b2006-03-31 16:00:29 +01002012
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002013 (5) Failed conditional ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01002014
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002015 Certain locking variants of the ACQUIRE operation may fail, either due to
2016 being unable to get the lock immediately, or due to receiving an unblocked
Will Deacon806654a2018-11-19 11:02:45 +00002017 signal while asleep waiting for the lock to become available. Failed
David Howells108b42b2006-03-31 16:00:29 +01002018 locks do not imply any sort of barrier.
2019
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002020[!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
2021one-way barriers is that the effects of instructions outside of a critical
2022section may seep into the inside of the critical section.
David Howells108b42b2006-03-31 16:00:29 +01002023
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002024An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
2025because it is possible for an access preceding the ACQUIRE to happen after the
2026ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2027the two accesses can themselves then cross:
David Howells670bd952006-06-10 09:54:12 -07002028
2029 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002030 ACQUIRE M
2031 RELEASE M
David Howells670bd952006-06-10 09:54:12 -07002032 *B = b;
2033
2034may occur as:
2035
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002036 ACQUIRE M, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08002037
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08002038When the ACQUIRE and RELEASE are a lock acquisition and release,
2039respectively, this same reordering can occur if the lock's ACQUIRE and
2040RELEASE are to the same lock variable, but only from the perspective of
2041another CPU not holding that lock. In short, a ACQUIRE followed by an
2042RELEASE may -not- be assumed to be a full memory barrier.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08002043
Paul E. McKenney12d560f2015-07-14 18:35:23 -07002044Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
2045not imply a full memory barrier. Therefore, the CPU's execution of the
2046critical sections corresponding to the RELEASE and the ACQUIRE can cross,
2047so that:
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08002048
2049 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002050 RELEASE M
2051 ACQUIRE N
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08002052 *B = b;
2053
2054could occur as:
2055
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002056 ACQUIRE N, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08002057
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08002058It might appear that this reordering could introduce a deadlock.
2059However, this cannot happen because if such a deadlock threatened,
2060the RELEASE would simply complete, thereby avoiding the deadlock.
2061
2062 Why does this work?
2063
2064 One key point is that we are only talking about the CPU doing
2065 the reordering, not the compiler. If the compiler (or, for
2066 that matter, the developer) switched the operations, deadlock
2067 -could- occur.
2068
2069 But suppose the CPU reordered the operations. In this case,
2070 the unlock precedes the lock in the assembly code. The CPU
2071 simply elected to try executing the later lock operation first.
2072 If there is a deadlock, this lock operation will simply spin (or
2073 try to sleep, but more on that later). The CPU will eventually
2074 execute the unlock operation (which preceded the lock operation
2075 in the assembly code), which will unravel the potential deadlock,
2076 allowing the lock operation to succeed.
2077
2078 But what if the lock is a sleeplock? In that case, the code will
2079 try to enter the scheduler, where it will eventually encounter
2080 a memory barrier, which will force the earlier unlock operation
2081 to complete, again unraveling the deadlock. There might be
2082 a sleep-unlock race, but the locking primitive needs to resolve
2083 such races properly in any case.
2084
David Howells108b42b2006-03-31 16:00:29 +01002085Locks and semaphores may not provide any guarantee of ordering on UP compiled
2086systems, and so cannot be counted on in such a situation to actually achieve
2087anything at all - especially with respect to I/O accesses - unless combined
2088with interrupt disabling operations.
2089
SeongJae Parkd7cab362016-08-11 11:17:41 -07002090See also the section on "Inter-CPU acquiring barrier effects".
David Howells108b42b2006-03-31 16:00:29 +01002091
2092
2093As an example, consider the following:
2094
2095 *A = a;
2096 *B = b;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002097 ACQUIRE
David Howells108b42b2006-03-31 16:00:29 +01002098 *C = c;
2099 *D = d;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002100 RELEASE
David Howells108b42b2006-03-31 16:00:29 +01002101 *E = e;
2102 *F = f;
2103
2104The following sequence of events is acceptable:
2105
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002106 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
David Howells108b42b2006-03-31 16:00:29 +01002107
2108 [+] Note that {*F,*A} indicates a combined access.
2109
2110But none of the following are:
2111
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002112 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2113 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2114 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2115 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
David Howells108b42b2006-03-31 16:00:29 +01002116
2117
2118
2119INTERRUPT DISABLING FUNCTIONS
2120-----------------------------
2121
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002122Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2123(RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
David Howells108b42b2006-03-31 16:00:29 +01002124barriers are required in such a situation, they must be provided from some
2125other means.
2126
2127
David Howells50fa6102009-04-28 15:01:38 +01002128SLEEP AND WAKE-UP FUNCTIONS
2129---------------------------
2130
2131Sleeping and waking on an event flagged in global data can be viewed as an
2132interaction between two pieces of data: the task state of the task waiting for
2133the event and the global data used to indicate the event. To make sure that
2134these appear to happen in the right order, the primitives to begin the process
2135of going to sleep, and the primitives to initiate a wake up imply certain
2136barriers.
2137
2138Firstly, the sleeper normally follows something like this sequence of events:
2139
2140 for (;;) {
2141 set_current_state(TASK_UNINTERRUPTIBLE);
2142 if (event_indicated)
2143 break;
2144 schedule();
2145 }
2146
2147A general memory barrier is interpolated automatically by set_current_state()
2148after it has altered the task state:
2149
2150 CPU 1
2151 ===============================
2152 set_current_state();
Peter Zijlstrab92b8b32015-05-12 10:51:55 +02002153 smp_store_mb();
David Howells50fa6102009-04-28 15:01:38 +01002154 STORE current->state
2155 <general barrier>
2156 LOAD event_indicated
2157
2158set_current_state() may be wrapped by:
2159
2160 prepare_to_wait();
2161 prepare_to_wait_exclusive();
2162
2163which therefore also imply a general memory barrier after setting the state.
2164The whole sequence above is available in various canned forms, all of which
2165interpolate the memory barrier in the right place:
2166
2167 wait_event();
2168 wait_event_interruptible();
2169 wait_event_interruptible_exclusive();
2170 wait_event_interruptible_timeout();
2171 wait_event_killable();
2172 wait_event_timeout();
2173 wait_on_bit();
2174 wait_on_bit_lock();
2175
2176
2177Secondly, code that performs a wake up normally follows something like this:
2178
2179 event_indicated = 1;
2180 wake_up(&event_wait_queue);
2181
2182or:
2183
2184 event_indicated = 1;
2185 wake_up_process(event_daemon);
2186
Andrea Parri7696f992018-07-16 11:06:03 -07002187A general memory barrier is executed by wake_up() if it wakes something up.
2188If it doesn't wake anything up then a memory barrier may or may not be
2189executed; you must not rely on it. The barrier occurs before the task state
2190is accessed, in particular, it sits between the STORE to indicate the event
2191and the STORE to set TASK_RUNNING:
David Howells50fa6102009-04-28 15:01:38 +01002192
Andrea Parri7696f992018-07-16 11:06:03 -07002193 CPU 1 (Sleeper) CPU 2 (Waker)
David Howells50fa6102009-04-28 15:01:38 +01002194 =============================== ===============================
2195 set_current_state(); STORE event_indicated
Peter Zijlstrab92b8b32015-05-12 10:51:55 +02002196 smp_store_mb(); wake_up();
Andrea Parri7696f992018-07-16 11:06:03 -07002197 STORE current->state ...
2198 <general barrier> <general barrier>
2199 LOAD event_indicated if ((LOAD task->state) & TASK_NORMAL)
2200 STORE task->state
David Howells50fa6102009-04-28 15:01:38 +01002201
Andrea Parri7696f992018-07-16 11:06:03 -07002202where "task" is the thread being woken up and it equals CPU 1's "current".
2203
2204To repeat, a general memory barrier is guaranteed to be executed by wake_up()
2205if something is actually awakened, but otherwise there is no such guarantee.
2206To see this, consider the following sequence of events, where X and Y are both
2207initially zero:
Paul E. McKenney5726ce02014-05-13 10:14:51 -07002208
2209 CPU 1 CPU 2
2210 =============================== ===============================
Andrea Parri7696f992018-07-16 11:06:03 -07002211 X = 1; Y = 1;
Paul E. McKenney5726ce02014-05-13 10:14:51 -07002212 smp_mb(); wake_up();
Andrea Parri7696f992018-07-16 11:06:03 -07002213 LOAD Y LOAD X
Paul E. McKenney5726ce02014-05-13 10:14:51 -07002214
Andrea Parri7696f992018-07-16 11:06:03 -07002215If a wakeup does occur, one (at least) of the two loads must see 1. If, on
2216the other hand, a wakeup does not occur, both loads might see 0.
2217
2218wake_up_process() always executes a general memory barrier. The barrier again
2219occurs before the task state is accessed. In particular, if the wake_up() in
2220the previous snippet were replaced by a call to wake_up_process() then one of
2221the two loads would be guaranteed to see 1.
Paul E. McKenney5726ce02014-05-13 10:14:51 -07002222
David Howells50fa6102009-04-28 15:01:38 +01002223The available waker functions include:
2224
2225 complete();
2226 wake_up();
2227 wake_up_all();
2228 wake_up_bit();
2229 wake_up_interruptible();
2230 wake_up_interruptible_all();
2231 wake_up_interruptible_nr();
2232 wake_up_interruptible_poll();
2233 wake_up_interruptible_sync();
2234 wake_up_interruptible_sync_poll();
2235 wake_up_locked();
2236 wake_up_locked_poll();
2237 wake_up_nr();
2238 wake_up_poll();
2239 wake_up_process();
2240
Andrea Parri7696f992018-07-16 11:06:03 -07002241In terms of memory ordering, these functions all provide the same guarantees of
2242a wake_up() (or stronger).
David Howells50fa6102009-04-28 15:01:38 +01002243
2244[!] Note that the memory barriers implied by the sleeper and the waker do _not_
2245order multiple stores before the wake-up with respect to loads of those stored
2246values after the sleeper has called set_current_state(). For instance, if the
2247sleeper does:
2248
2249 set_current_state(TASK_INTERRUPTIBLE);
2250 if (event_indicated)
2251 break;
2252 __set_current_state(TASK_RUNNING);
2253 do_something(my_data);
2254
2255and the waker does:
2256
2257 my_data = value;
2258 event_indicated = 1;
2259 wake_up(&event_wait_queue);
2260
2261there's no guarantee that the change to event_indicated will be perceived by
2262the sleeper as coming after the change to my_data. In such a circumstance, the
2263code on both sides must interpolate its own memory barriers between the
2264separate data accesses. Thus the above sleeper ought to do:
2265
2266 set_current_state(TASK_INTERRUPTIBLE);
2267 if (event_indicated) {
2268 smp_rmb();
2269 do_something(my_data);
2270 }
2271
2272and the waker should do:
2273
2274 my_data = value;
2275 smp_wmb();
2276 event_indicated = 1;
2277 wake_up(&event_wait_queue);
2278
2279
David Howells108b42b2006-03-31 16:00:29 +01002280MISCELLANEOUS FUNCTIONS
2281-----------------------
2282
2283Other functions that imply barriers:
2284
2285 (*) schedule() and similar imply full memory barriers.
2286
David Howells108b42b2006-03-31 16:00:29 +01002287
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002288===================================
2289INTER-CPU ACQUIRING BARRIER EFFECTS
2290===================================
David Howells108b42b2006-03-31 16:00:29 +01002291
2292On SMP systems locking primitives give a more substantial form of barrier: one
2293that does affect memory access ordering on other CPUs, within the context of
2294conflict on any particular lock.
2295
2296
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002297ACQUIRES VS MEMORY ACCESSES
2298---------------------------
David Howells108b42b2006-03-31 16:00:29 +01002299
Aneesh Kumar79afecf2006-05-15 09:44:36 -07002300Consider the following: the system has a pair of spinlocks (M) and (Q), and
David Howells108b42b2006-03-31 16:00:29 +01002301three CPUs; then should the following sequence of events occur:
2302
2303 CPU 1 CPU 2
2304 =============================== ===============================
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002305 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002306 ACQUIRE M ACQUIRE Q
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002307 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2308 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002309 RELEASE M RELEASE Q
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002310 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
David Howells108b42b2006-03-31 16:00:29 +01002311
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002312Then there is no guarantee as to what order CPU 3 will see the accesses to *A
David Howells108b42b2006-03-31 16:00:29 +01002313through *H occur in, other than the constraints imposed by the separate locks
SeongJae Park0b6fa342016-04-12 08:52:53 -07002314on the separate CPUs. It might, for example, see:
David Howells108b42b2006-03-31 16:00:29 +01002315
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002316 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
David Howells108b42b2006-03-31 16:00:29 +01002317
2318But it won't see any of:
2319
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002320 *B, *C or *D preceding ACQUIRE M
2321 *A, *B or *C following RELEASE M
2322 *F, *G or *H preceding ACQUIRE Q
2323 *E, *F or *G following RELEASE Q
David Howells108b42b2006-03-31 16:00:29 +01002324
2325
David Howells108b42b2006-03-31 16:00:29 +01002326=================================
2327WHERE ARE MEMORY BARRIERS NEEDED?
2328=================================
2329
2330Under normal operation, memory operation reordering is generally not going to
2331be a problem as a single-threaded linear piece of code will still appear to
David Howells50fa6102009-04-28 15:01:38 +01002332work correctly, even if it's in an SMP kernel. There are, however, four
David Howells108b42b2006-03-31 16:00:29 +01002333circumstances in which reordering definitely _could_ be a problem:
2334
2335 (*) Interprocessor interaction.
2336
2337 (*) Atomic operations.
2338
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002339 (*) Accessing devices.
David Howells108b42b2006-03-31 16:00:29 +01002340
2341 (*) Interrupts.
2342
2343
2344INTERPROCESSOR INTERACTION
2345--------------------------
2346
2347When there's a system with more than one processor, more than one CPU in the
2348system may be working on the same data set at the same time. This can cause
2349synchronisation problems, and the usual way of dealing with them is to use
2350locks. Locks, however, are quite expensive, and so it may be preferable to
2351operate without the use of a lock if at all possible. In such a case
2352operations that affect both CPUs may have to be carefully ordered to prevent
2353a malfunction.
2354
2355Consider, for example, the R/W semaphore slow path. Here a waiting process is
2356queued on the semaphore, by virtue of it having a piece of its stack linked to
2357the semaphore's list of waiting processes:
2358
2359 struct rw_semaphore {
2360 ...
2361 spinlock_t lock;
2362 struct list_head waiters;
2363 };
2364
2365 struct rwsem_waiter {
2366 struct list_head list;
2367 struct task_struct *task;
2368 };
2369
2370To wake up a particular waiter, the up_read() or up_write() functions have to:
2371
2372 (1) read the next pointer from this waiter's record to know as to where the
2373 next waiter record is;
2374
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002375 (2) read the pointer to the waiter's task structure;
David Howells108b42b2006-03-31 16:00:29 +01002376
2377 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2378
2379 (4) call wake_up_process() on the task; and
2380
2381 (5) release the reference held on the waiter's task struct.
2382
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002383In other words, it has to perform this sequence of events:
David Howells108b42b2006-03-31 16:00:29 +01002384
2385 LOAD waiter->list.next;
2386 LOAD waiter->task;
2387 STORE waiter->task;
2388 CALL wakeup
2389 RELEASE task
2390
2391and if any of these steps occur out of order, then the whole thing may
2392malfunction.
2393
2394Once it has queued itself and dropped the semaphore lock, the waiter does not
2395get the lock again; it instead just waits for its task pointer to be cleared
2396before proceeding. Since the record is on the waiter's stack, this means that
2397if the task pointer is cleared _before_ the next pointer in the list is read,
2398another CPU might start processing the waiter and might clobber the waiter's
2399stack before the up*() function has a chance to read the next pointer.
2400
2401Consider then what might happen to the above sequence of events:
2402
2403 CPU 1 CPU 2
2404 =============================== ===============================
2405 down_xxx()
2406 Queue waiter
2407 Sleep
2408 up_yyy()
2409 LOAD waiter->task;
2410 STORE waiter->task;
2411 Woken up by other event
2412 <preempt>
2413 Resume processing
2414 down_xxx() returns
2415 call foo()
2416 foo() clobbers *waiter
2417 </preempt>
2418 LOAD waiter->list.next;
2419 --- OOPS ---
2420
2421This could be dealt with using the semaphore lock, but then the down_xxx()
2422function has to needlessly get the spinlock again after being woken up.
2423
2424The way to deal with this is to insert a general SMP memory barrier:
2425
2426 LOAD waiter->list.next;
2427 LOAD waiter->task;
2428 smp_mb();
2429 STORE waiter->task;
2430 CALL wakeup
2431 RELEASE task
2432
2433In this case, the barrier makes a guarantee that all memory accesses before the
2434barrier will appear to happen before all the memory accesses after the barrier
2435with respect to the other CPUs on the system. It does _not_ guarantee that all
2436the memory accesses before the barrier will be complete by the time the barrier
2437instruction itself is complete.
2438
2439On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2440compiler barrier, thus making sure the compiler emits the instructions in the
David Howells6bc39272006-06-25 05:49:22 -07002441right order without actually intervening in the CPU. Since there's only one
2442CPU, that CPU's dependency ordering logic will take care of everything else.
David Howells108b42b2006-03-31 16:00:29 +01002443
2444
2445ATOMIC OPERATIONS
2446-----------------
2447
Will Deacon806654a2018-11-19 11:02:45 +00002448While they are technically interprocessor interaction considerations, atomic
David Howellsdbc87002006-04-10 22:54:23 -07002449operations are noted specially as some of them imply full memory barriers and
2450some don't, but they're very heavily relied on as a group throughout the
2451kernel.
2452
Peter Zijlstra706eeb32017-06-12 14:50:27 +02002453See Documentation/atomic_t.txt for more information.
David Howells108b42b2006-03-31 16:00:29 +01002454
2455
2456ACCESSING DEVICES
2457-----------------
2458
2459Many devices can be memory mapped, and so appear to the CPU as if they're just
2460a set of memory locations. To control such a device, the driver usually has to
2461make the right memory accesses in exactly the right order.
2462
2463However, having a clever CPU or a clever compiler creates a potential problem
2464in that the carefully sequenced accesses in the driver code won't reach the
2465device in the requisite order if the CPU or the compiler thinks it is more
2466efficient to reorder, combine or merge accesses - something that would cause
2467the device to malfunction.
2468
2469Inside of the Linux kernel, I/O should be done through the appropriate accessor
2470routines - such as inb() or writel() - which know how to make such accesses
Will Deacon806654a2018-11-19 11:02:45 +00002471appropriately sequential. While this, for the most part, renders the explicit
Will Deacon91553032019-02-22 16:17:54 +00002472use of memory barriers unnecessary, if the accessor functions are used to refer
2473to an I/O memory window with relaxed memory access properties, then _mandatory_
2474memory barriers are required to enforce ordering.
David Howells108b42b2006-03-31 16:00:29 +01002475
Helmut Grohne0fe397f2017-05-03 11:51:46 +02002476See Documentation/driver-api/device-io.rst for more information.
David Howells108b42b2006-03-31 16:00:29 +01002477
2478
2479INTERRUPTS
2480----------
2481
2482A driver may be interrupted by its own interrupt service routine, and thus the
2483two parts of the driver may interfere with each other's attempts to control or
2484access the device.
2485
2486This may be alleviated - at least in part - by disabling local interrupts (a
2487form of locking), such that the critical operations are all contained within
Will Deacon806654a2018-11-19 11:02:45 +00002488the interrupt-disabled section in the driver. While the driver's interrupt
David Howells108b42b2006-03-31 16:00:29 +01002489routine is executing, the driver's core may not run on the same CPU, and its
2490interrupt is not permitted to happen again until the current interrupt has been
2491handled, thus the interrupt handler does not need to lock against that.
2492
2493However, consider a driver that was talking to an ethernet card that sports an
2494address register and a data register. If that driver's core talks to the card
2495under interrupt-disablement and then the driver's interrupt handler is invoked:
2496
2497 LOCAL IRQ DISABLE
2498 writew(ADDR, 3);
2499 writew(DATA, y);
2500 LOCAL IRQ ENABLE
2501 <interrupt>
2502 writew(ADDR, 4);
2503 q = readw(DATA);
2504 </interrupt>
2505
2506The store to the data register might happen after the second store to the
2507address register if ordering rules are sufficiently relaxed:
2508
2509 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2510
2511
2512If ordering rules are relaxed, it must be assumed that accesses done inside an
2513interrupt disabled section may leak outside of it and may interleave with
2514accesses performed in an interrupt - and vice versa - unless implicit or
2515explicit barriers are used.
2516
2517Normally this won't be a problem because the I/O accesses done inside such
2518sections will include synchronous load operations on strictly ordered I/O
Will Deacon91553032019-02-22 16:17:54 +00002519registers that form implicit I/O barriers.
David Howells108b42b2006-03-31 16:00:29 +01002520
2521
2522A similar situation may occur between an interrupt routine and two routines
SeongJae Park0b6fa342016-04-12 08:52:53 -07002523running on separate CPUs that communicate with each other. If such a case is
David Howells108b42b2006-03-31 16:00:29 +01002524likely, then interrupt-disabling locks should be used to guarantee ordering.
2525
2526
2527==========================
2528KERNEL I/O BARRIER EFFECTS
2529==========================
2530
Will Deacon4614bbd2019-02-11 15:24:56 +00002531Interfacing with peripherals via I/O accesses is deeply architecture and device
2532specific. Therefore, drivers which are inherently non-portable may rely on
2533specific behaviours of their target systems in order to achieve synchronization
2534in the most lightweight manner possible. For drivers intending to be portable
2535between multiple architectures and bus implementations, the kernel offers a
2536series of accessor functions that provide various degrees of ordering
2537guarantees:
David Howells108b42b2006-03-31 16:00:29 +01002538
2539 (*) readX(), writeX():
2540
Will Deacon0cde62a2019-04-10 14:01:06 +01002541 The readX() and writeX() MMIO accessors take a pointer to the
2542 peripheral being accessed as an __iomem * parameter. For pointers
2543 mapped with the default I/O attributes (e.g. those returned by
2544 ioremap()), the ordering guarantees are as follows:
David Howells108b42b2006-03-31 16:00:29 +01002545
Will Deacon0cde62a2019-04-10 14:01:06 +01002546 1. All readX() and writeX() accesses to the same peripheral are ordered
Will Deacon97268402019-04-12 13:42:18 +01002547 with respect to each other. This ensures that MMIO register accesses
2548 by the same CPU thread to a particular device will arrive in program
2549 order.
David Howells108b42b2006-03-31 16:00:29 +01002550
Will Deacon97268402019-04-12 13:42:18 +01002551 2. A writeX() issued by a CPU thread holding a spinlock is ordered
2552 before a writeX() to the same peripheral from another CPU thread
2553 issued after a later acquisition of the same spinlock. This ensures
2554 that MMIO register writes to a particular device issued while holding
2555 a spinlock will arrive in an order consistent with acquisitions of
2556 the lock.
David Howells108b42b2006-03-31 16:00:29 +01002557
Will Deacon97268402019-04-12 13:42:18 +01002558 3. A writeX() by a CPU thread to the peripheral will first wait for the
2559 completion of all prior writes to memory either issued by, or
2560 propagated to, the same thread. This ensures that writes by the CPU
2561 to an outbound DMA buffer allocated by dma_alloc_coherent() will be
2562 visible to a DMA engine when the CPU writes to its MMIO control
2563 register to trigger the transfer.
David Howells108b42b2006-03-31 16:00:29 +01002564
Will Deacon97268402019-04-12 13:42:18 +01002565 4. A readX() by a CPU thread from the peripheral will complete before
2566 any subsequent reads from memory by the same thread can begin. This
2567 ensures that reads by the CPU from an incoming DMA buffer allocated
2568 by dma_alloc_coherent() will not see stale data after reading from
2569 the DMA engine's MMIO status register to establish that the DMA
2570 transfer has completed.
2571
2572 5. A readX() by a CPU thread from the peripheral will complete before
2573 any subsequent delay() loop can begin execution on the same thread.
2574 This ensures that two MMIO register writes by the CPU to a peripheral
2575 will arrive at least 1us apart if the first write is immediately read
2576 back with readX() and udelay(1) is called prior to the second
2577 writeX():
David Howells108b42b2006-03-31 16:00:29 +01002578
Will Deacon0cde62a2019-04-10 14:01:06 +01002579 writel(42, DEVICE_REGISTER_0); // Arrives at the device...
2580 readl(DEVICE_REGISTER_0);
2581 udelay(1);
2582 writel(42, DEVICE_REGISTER_1); // ...at least 1us before this.
2583
2584 The ordering properties of __iomem pointers obtained with non-default
2585 attributes (e.g. those returned by ioremap_wc()) are specific to the
2586 underlying architecture and therefore the guarantees listed above cannot
2587 generally be relied upon for accesses to these types of mappings.
David Howells108b42b2006-03-31 16:00:29 +01002588
Will Deacon4614bbd2019-02-11 15:24:56 +00002589 (*) readX_relaxed(), writeX_relaxed():
David Howells108b42b2006-03-31 16:00:29 +01002590
Will Deacon0cde62a2019-04-10 14:01:06 +01002591 These are similar to readX() and writeX(), but provide weaker memory
2592 ordering guarantees. Specifically, they do not guarantee ordering with
Will Deacon97268402019-04-12 13:42:18 +01002593 respect to locking, normal memory accesses or delay() loops (i.e.
2594 bullets 2-5 above) but they are still guaranteed to be ordered with
2595 respect to other accesses from the same CPU thread to the same
2596 peripheral when operating on __iomem pointers mapped with the default
2597 I/O attributes.
Will Deacon4614bbd2019-02-11 15:24:56 +00002598
2599 (*) readsX(), writesX():
2600
Will Deacon0cde62a2019-04-10 14:01:06 +01002601 The readsX() and writesX() MMIO accessors are designed for accessing
2602 register-based, memory-mapped FIFOs residing on peripherals that are not
2603 capable of performing DMA. Consequently, they provide only the ordering
2604 guarantees of readX_relaxed() and writeX_relaxed(), as documented above.
Will Deacon4614bbd2019-02-11 15:24:56 +00002605
2606 (*) inX(), outX():
2607
Will Deacon0cde62a2019-04-10 14:01:06 +01002608 The inX() and outX() accessors are intended to access legacy port-mapped
2609 I/O peripherals, which may require special instructions on some
2610 architectures (notably x86). The port number of the peripheral being
2611 accessed is passed as an argument.
Will Deacon4614bbd2019-02-11 15:24:56 +00002612
Will Deacon0cde62a2019-04-10 14:01:06 +01002613 Since many CPU architectures ultimately access these peripherals via an
2614 internal virtual memory mapping, the portable ordering guarantees
2615 provided by inX() and outX() are the same as those provided by readX()
2616 and writeX() respectively when accessing a mapping with the default I/O
2617 attributes.
Will Deacon4614bbd2019-02-11 15:24:56 +00002618
Will Deacon0cde62a2019-04-10 14:01:06 +01002619 Device drivers may expect outX() to emit a non-posted write transaction
2620 that waits for a completion response from the I/O peripheral before
2621 returning. This is not guaranteed by all architectures and is therefore
2622 not part of the portable ordering semantics.
Will Deacon4614bbd2019-02-11 15:24:56 +00002623
2624 (*) insX(), outsX():
2625
Will Deacon0cde62a2019-04-10 14:01:06 +01002626 As above, the insX() and outsX() accessors provide the same ordering
2627 guarantees as readsX() and writesX() respectively when accessing a
2628 mapping with the default I/O attributes.
David Howells108b42b2006-03-31 16:00:29 +01002629
Will Deacon0cde62a2019-04-10 14:01:06 +01002630 (*) ioreadX(), iowriteX():
David Howells108b42b2006-03-31 16:00:29 +01002631
Will Deacon0cde62a2019-04-10 14:01:06 +01002632 These will perform appropriately for the type of access they're actually
2633 doing, be it inX()/outX() or readX()/writeX().
David Howells108b42b2006-03-31 16:00:29 +01002634
Will Deacon97268402019-04-12 13:42:18 +01002635With the exception of the string accessors (insX(), outsX(), readsX() and
2636writesX()), all of the above assume that the underlying peripheral is
2637little-endian and will therefore perform byte-swapping operations on big-endian
2638architectures.
Will Deacon4614bbd2019-02-11 15:24:56 +00002639
David Howells108b42b2006-03-31 16:00:29 +01002640
2641========================================
2642ASSUMED MINIMUM EXECUTION ORDERING MODEL
2643========================================
2644
2645It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2646maintain the appearance of program causality with respect to itself. Some CPUs
2647(such as i386 or x86_64) are more constrained than others (such as powerpc or
2648frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2649of arch-specific code.
2650
2651This means that it must be considered that the CPU will execute its instruction
2652stream in any order it feels like - or even in parallel - provided that if an
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002653instruction in the stream depends on an earlier instruction, then that
David Howells108b42b2006-03-31 16:00:29 +01002654earlier instruction must be sufficiently complete[*] before the later
2655instruction may proceed; in other words: provided that the appearance of
2656causality is maintained.
2657
2658 [*] Some instructions have more than one effect - such as changing the
2659 condition codes, changing registers or changing memory - and different
2660 instructions may depend on different effects.
2661
2662A CPU may also discard any instruction sequence that winds up having no
2663ultimate effect. For example, if two adjacent instructions both load an
2664immediate value into the same register, the first may be discarded.
2665
2666
2667Similarly, it has to be assumed that compiler might reorder the instruction
2668stream in any way it sees fit, again provided the appearance of causality is
2669maintained.
2670
2671
2672============================
2673THE EFFECTS OF THE CPU CACHE
2674============================
2675
2676The way cached memory operations are perceived across the system is affected to
2677a certain extent by the caches that lie between CPUs and memory, and by the
2678memory coherence system that maintains the consistency of state in the system.
2679
2680As far as the way a CPU interacts with another part of the system through the
2681caches goes, the memory system has to include the CPU's caches, and memory
2682barriers for the most part act at the interface between the CPU and its cache
2683(memory barriers logically act on the dotted line in the following diagram):
2684
2685 <--- CPU ---> : <----------- Memory ----------->
2686 :
2687 +--------+ +--------+ : +--------+ +-----------+
2688 | | | | : | | | | +--------+
Ingo Molnare0edc782013-11-22 11:24:53 +01002689 | CPU | | Memory | : | CPU | | | | |
2690 | Core |--->| Access |----->| Cache |<-->| | | |
David Howells108b42b2006-03-31 16:00:29 +01002691 | | | Queue | : | | | |--->| Memory |
Ingo Molnare0edc782013-11-22 11:24:53 +01002692 | | | | : | | | | | |
2693 +--------+ +--------+ : +--------+ | | | |
David Howells108b42b2006-03-31 16:00:29 +01002694 : | Cache | +--------+
2695 : | Coherency |
2696 : | Mechanism | +--------+
2697 +--------+ +--------+ : +--------+ | | | |
2698 | | | | : | | | | | |
2699 | CPU | | Memory | : | CPU | | |--->| Device |
Ingo Molnare0edc782013-11-22 11:24:53 +01002700 | Core |--->| Access |----->| Cache |<-->| | | |
2701 | | | Queue | : | | | | | |
David Howells108b42b2006-03-31 16:00:29 +01002702 | | | | : | | | | +--------+
2703 +--------+ +--------+ : +--------+ +-----------+
2704 :
2705 :
2706
2707Although any particular load or store may not actually appear outside of the
2708CPU that issued it since it may have been satisfied within the CPU's own cache,
2709it will still appear as if the full memory access had taken place as far as the
2710other CPUs are concerned since the cache coherency mechanisms will migrate the
2711cacheline over to the accessing CPU and propagate the effects upon conflict.
2712
2713The CPU core may execute instructions in any order it deems fit, provided the
2714expected program causality appears to be maintained. Some of the instructions
2715generate load and store operations which then go into the queue of memory
2716accesses to be performed. The core may place these in the queue in any order
2717it wishes, and continue execution until it is forced to wait for an instruction
2718to complete.
2719
2720What memory barriers are concerned with is controlling the order in which
2721accesses cross from the CPU side of things to the memory side of things, and
2722the order in which the effects are perceived to happen by the other observers
2723in the system.
2724
2725[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2726their own loads and stores as if they had happened in program order.
2727
2728[!] MMIO or other device accesses may bypass the cache system. This depends on
2729the properties of the memory window through which devices are accessed and/or
2730the use of any special device communication instructions the CPU may have.
2731
2732
David Howells108b42b2006-03-31 16:00:29 +01002733CACHE COHERENCY VS DMA
2734----------------------
2735
2736Not all systems maintain cache coherency with respect to devices doing DMA. In
2737such cases, a device attempting DMA may obtain stale data from RAM because
2738dirty cache lines may be resident in the caches of various CPUs, and may not
2739have been written back to RAM yet. To deal with this, the appropriate part of
2740the kernel must flush the overlapping bits of cache on each CPU (and maybe
2741invalidate them as well).
2742
2743In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2744cache lines being written back to RAM from a CPU's cache after the device has
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002745installed its own data, or cache lines present in the CPU's cache may simply
2746obscure the fact that RAM has been updated, until at such time as the cacheline
2747is discarded from the CPU's cache and reloaded. To deal with this, the
2748appropriate part of the kernel must invalidate the overlapping bits of the
David Howells108b42b2006-03-31 16:00:29 +01002749cache on each CPU.
2750
Mauro Carvalho Chehabde0f51e2018-05-07 06:35:41 -03002751See Documentation/core-api/cachetlb.rst for more information on cache management.
David Howells108b42b2006-03-31 16:00:29 +01002752
2753
2754CACHE COHERENCY VS MMIO
2755-----------------------
2756
2757Memory mapped I/O usually takes place through memory locations that are part of
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002758a window in the CPU's memory space that has different properties assigned than
David Howells108b42b2006-03-31 16:00:29 +01002759the usual RAM directed window.
2760
2761Amongst these properties is usually the fact that such accesses bypass the
2762caching entirely and go directly to the device buses. This means MMIO accesses
2763may, in effect, overtake accesses to cached memory that were emitted earlier.
2764A memory barrier isn't sufficient in such a case, but rather the cache must be
2765flushed between the cached memory write and the MMIO access if the two are in
2766any way dependent.
2767
2768
2769=========================
2770THE THINGS CPUS GET UP TO
2771=========================
2772
2773A programmer might take it for granted that the CPU will perform memory
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002774operations in exactly the order specified, so that if the CPU is, for example,
David Howells108b42b2006-03-31 16:00:29 +01002775given the following piece of code to execute:
2776
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002777 a = READ_ONCE(*A);
2778 WRITE_ONCE(*B, b);
2779 c = READ_ONCE(*C);
2780 d = READ_ONCE(*D);
2781 WRITE_ONCE(*E, e);
David Howells108b42b2006-03-31 16:00:29 +01002782
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002783they would then expect that the CPU will complete the memory operation for each
David Howells108b42b2006-03-31 16:00:29 +01002784instruction before moving on to the next one, leading to a definite sequence of
2785operations as seen by external observers in the system:
2786
2787 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2788
2789
2790Reality is, of course, much messier. With many CPUs and compilers, the above
2791assumption doesn't hold because:
2792
2793 (*) loads are more likely to need to be completed immediately to permit
2794 execution progress, whereas stores can often be deferred without a
2795 problem;
2796
2797 (*) loads may be done speculatively, and the result discarded should it prove
2798 to have been unnecessary;
2799
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002800 (*) loads may be done speculatively, leading to the result having been fetched
2801 at the wrong time in the expected sequence of events;
David Howells108b42b2006-03-31 16:00:29 +01002802
2803 (*) the order of the memory accesses may be rearranged to promote better use
2804 of the CPU buses and caches;
2805
2806 (*) loads and stores may be combined to improve performance when talking to
2807 memory or I/O hardware that can do batched accesses of adjacent locations,
2808 thus cutting down on transaction setup costs (memory and PCI devices may
2809 both be able to do this); and
2810
Will Deacon806654a2018-11-19 11:02:45 +00002811 (*) the CPU's data cache may affect the ordering, and while cache-coherency
David Howells108b42b2006-03-31 16:00:29 +01002812 mechanisms may alleviate this - once the store has actually hit the cache
2813 - there's no guarantee that the coherency management will be propagated in
2814 order to other CPUs.
2815
2816So what another CPU, say, might actually observe from the above piece of code
2817is:
2818
2819 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2820
2821 (Where "LOAD {*C,*D}" is a combined load)
2822
2823
2824However, it is guaranteed that a CPU will be self-consistent: it will see its
2825_own_ accesses appear to be correctly ordered, without the need for a memory
2826barrier. For instance with the following code:
2827
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002828 U = READ_ONCE(*A);
2829 WRITE_ONCE(*A, V);
2830 WRITE_ONCE(*A, W);
2831 X = READ_ONCE(*A);
2832 WRITE_ONCE(*A, Y);
2833 Z = READ_ONCE(*A);
David Howells108b42b2006-03-31 16:00:29 +01002834
2835and assuming no intervention by an external influence, it can be assumed that
2836the final result will appear to be:
2837
2838 U == the original value of *A
2839 X == W
2840 Z == Y
2841 *A == Y
2842
2843The code above may cause the CPU to generate the full sequence of memory
2844accesses:
2845
2846 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2847
2848in that order, but, without intervention, the sequence may have almost any
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002849combination of elements combined or discarded, provided the program's view
2850of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2851are -not- optional in the above example, as there are architectures
2852where a given CPU might reorder successive loads to the same location.
2853On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
2854necessary to prevent this, for example, on Itanium the volatile casts
2855used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
2856and st.rel instructions (respectively) that prevent such reordering.
David Howells108b42b2006-03-31 16:00:29 +01002857
2858The compiler may also combine, discard or defer elements of the sequence before
2859the CPU even sees them.
2860
2861For instance:
2862
2863 *A = V;
2864 *A = W;
2865
2866may be reduced to:
2867
2868 *A = W;
2869
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002870since, without either a write barrier or an WRITE_ONCE(), it can be
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002871assumed that the effect of the storage of V to *A is lost. Similarly:
David Howells108b42b2006-03-31 16:00:29 +01002872
2873 *A = Y;
2874 Z = *A;
2875
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002876may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
2877reduced to:
David Howells108b42b2006-03-31 16:00:29 +01002878
2879 *A = Y;
2880 Z = Y;
2881
2882and the LOAD operation never appear outside of the CPU.
2883
2884
2885AND THEN THERE'S THE ALPHA
2886--------------------------
2887
2888The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2889some versions of the Alpha CPU have a split data cache, permitting them to have
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002890two semantically-related cache lines updated at separate times. This is where
David Howells108b42b2006-03-31 16:00:29 +01002891the data dependency barrier really becomes necessary as this synchronises both
2892caches with the memory coherence system, thus making it seem like pointer
2893changes vs new data occur in the right order.
2894
Paul E. McKenneyf28f0862018-03-07 09:27:37 -08002895The Alpha defines the Linux kernel's memory model, although as of v4.15
Will Deacon8ca924a2019-11-07 14:36:37 +00002896the Linux kernel's addition of smp_mb() to READ_ONCE() on Alpha greatly
2897reduced its impact on the memory model.
David Howells108b42b2006-03-31 16:00:29 +01002898
SeongJae Park0b6fa342016-04-12 08:52:53 -07002899
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02002900VIRTUAL MACHINE GUESTS
SeongJae Park3dbf0912016-04-12 08:52:52 -07002901----------------------
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02002902
2903Guests running within virtual machines might be affected by SMP effects even if
2904the guest itself is compiled without SMP support. This is an artifact of
2905interfacing with an SMP host while running an UP kernel. Using mandatory
2906barriers for this use-case would be possible but is often suboptimal.
2907
2908To handle this case optimally, low-level virt_mb() etc macros are available.
2909These have the same effect as smp_mb() etc when SMP is enabled, but generate
SeongJae Park0b6fa342016-04-12 08:52:53 -07002910identical code for SMP and non-SMP systems. For example, virtual machine guests
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02002911should use virt_mb() rather than smp_mb() when synchronizing against a
2912(possibly SMP) host.
2913
2914These are equivalent to smp_mb() etc counterparts in all other respects,
2915in particular, they do not control MMIO effects: to control
2916MMIO effects, use mandatory barriers.
David Howells108b42b2006-03-31 16:00:29 +01002917
SeongJae Park0b6fa342016-04-12 08:52:53 -07002918
David Howells90fddab2010-03-24 09:43:00 +00002919============
2920EXAMPLE USES
2921============
2922
2923CIRCULAR BUFFERS
2924----------------
2925
2926Memory barriers can be used to implement circular buffering without the need
2927of a lock to serialise the producer with the consumer. See:
2928
Mauro Carvalho Chehabd8a121e2018-05-07 06:35:43 -03002929 Documentation/core-api/circular-buffers.rst
David Howells90fddab2010-03-24 09:43:00 +00002930
2931for details.
2932
2933
David Howells108b42b2006-03-31 16:00:29 +01002934==========
2935REFERENCES
2936==========
2937
2938Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2939Digital Press)
2940 Chapter 5.2: Physical Address Space Characteristics
2941 Chapter 5.4: Caches and Write Buffers
2942 Chapter 5.5: Data Sharing
2943 Chapter 5.6: Read/Write Ordering
2944
2945AMD64 Architecture Programmer's Manual Volume 2: System Programming
2946 Chapter 7.1: Memory-Access Ordering
2947 Chapter 7.4: Buffering and Combining Memory Writes
2948
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07002949ARM Architecture Reference Manual (ARMv8, for ARMv8-A architecture profile)
2950 Chapter B2: The AArch64 Application Level Memory Model
2951
David Howells108b42b2006-03-31 16:00:29 +01002952IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2953System Programming Guide
2954 Chapter 7.1: Locked Atomic Operations
2955 Chapter 7.2: Memory Ordering
2956 Chapter 7.4: Serializing Instructions
2957
2958The SPARC Architecture Manual, Version 9
2959 Chapter 8: Memory Models
2960 Appendix D: Formal Specification of the Memory Models
2961 Appendix J: Programming with the Memory Models
2962
Paul E. McKenneyf1ab25a2017-08-29 15:49:21 -07002963Storage in the PowerPC (Stone and Fitzgerald)
2964
David Howells108b42b2006-03-31 16:00:29 +01002965UltraSPARC Programmer Reference Manual
2966 Chapter 5: Memory Accesses and Cacheability
2967 Chapter 15: Sparc-V9 Memory Models
2968
2969UltraSPARC III Cu User's Manual
2970 Chapter 9: Memory Models
2971
2972UltraSPARC IIIi Processor User's Manual
2973 Chapter 8: Memory Models
2974
2975UltraSPARC Architecture 2005
2976 Chapter 9: Memory
2977 Appendix D: Formal Specifications of the Memory Models
2978
2979UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2980 Chapter 8: Memory Models
2981 Appendix F: Caches and Cache Coherency
2982
2983Solaris Internals, Core Kernel Architecture, p63-68:
2984 Chapter 3.3: Hardware Considerations for Locks and
2985 Synchronization
2986
2987Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2988for Kernel Programmers:
2989 Chapter 13: Other Memory Models
2990
2991Intel Itanium Architecture Software Developer's Manual: Volume 1:
2992 Section 2.6: Speculation
2993 Section 4.4: Memory Access