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Thomas Gleixnerc456cfc2019-05-28 10:10:14 -07001// SPDX-License-Identifier: GPL-2.0-only
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
3 * arch/sh/mm/tlb-sh4.c
4 *
5 * SH-4 specific TLB operations
6 *
7 * Copyright (C) 1999 Niibe Yutaka
Paul Mundtd04a0f72007-09-21 11:55:03 +09008 * Copyright (C) 2002 - 2007 Paul Mundt
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 */
Paul Mundt39e688a2007-03-05 19:46:47 +090010#include <linux/kernel.h>
Paul Mundt39e688a2007-03-05 19:46:47 +090011#include <linux/mm.h>
Paul Mundtd04a0f72007-09-21 11:55:03 +090012#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <asm/mmu_context.h>
Paul Mundt39e688a2007-03-05 19:46:47 +090014#include <asm/cacheflush.h>
15
Paul Mundt9cef7492009-07-29 00:12:17 +090016void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
Paul Mundt39e688a2007-03-05 19:46:47 +090017{
Paul Mundt9cef7492009-07-29 00:12:17 +090018 unsigned long flags, pteval, vpn;
Paul Mundt39e688a2007-03-05 19:46:47 +090019
Paul Mundt9cef7492009-07-29 00:12:17 +090020 /*
21 * Handle debugger faulting in for debugee.
22 */
Paul Mundt3ed6e122009-07-29 22:06:58 +090023 if (vma && current->active_mm != vma->vm_mm)
Paul Mundt39e688a2007-03-05 19:46:47 +090024 return;
25
Paul Mundt39e688a2007-03-05 19:46:47 +090026 local_irq_save(flags);
27
28 /* Set PTEH register */
29 vpn = (address & MMU_VPN_MASK) | get_asid();
Paul Mundt9d56dd32010-01-26 12:58:40 +090030 __raw_writel(vpn, MMU_PTEH);
Paul Mundt39e688a2007-03-05 19:46:47 +090031
Paul Mundtd04a0f72007-09-21 11:55:03 +090032 pteval = pte.pte_low;
Paul Mundt39e688a2007-03-05 19:46:47 +090033
34 /* Set PTEA register */
Paul Mundtd04a0f72007-09-21 11:55:03 +090035#ifdef CONFIG_X2TLB
36 /*
37 * For the extended mode TLB this is trivial, only the ESZ and
38 * EPR bits need to be written out to PTEA, with the remainder of
39 * the protection bits (with the exception of the compat-mode SZ
40 * and PR bits, which are cleared) being written out in PTEL.
41 */
Paul Mundt9d56dd32010-01-26 12:58:40 +090042 __raw_writel(pte.pte_high, MMU_PTEA);
Paul Mundtd04a0f72007-09-21 11:55:03 +090043#else
Michael Trimarchi6503fe42009-08-20 13:27:44 +090044 if (cpu_data->flags & CPU_HAS_PTEA) {
45 /* The last 3 bits and the first one of pteval contains
46 * the PTEA timing control and space attribute bits
47 */
Paul Mundt9d56dd32010-01-26 12:58:40 +090048 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
Michael Trimarchi6503fe42009-08-20 13:27:44 +090049 }
Paul Mundtd04a0f72007-09-21 11:55:03 +090050#endif
Paul Mundt39e688a2007-03-05 19:46:47 +090051
52 /* Set PTEL register */
53 pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
Paul Mundte7bd34a2007-07-31 17:07:28 +090054#ifdef CONFIG_CACHE_WRITETHROUGH
Paul Mundt39e688a2007-03-05 19:46:47 +090055 pteval |= _PAGE_WT;
56#endif
57 /* conveniently, we want all the software flags to be 0 anyway */
Paul Mundt9d56dd32010-01-26 12:58:40 +090058 __raw_writel(pteval, MMU_PTEL);
Paul Mundt39e688a2007-03-05 19:46:47 +090059
60 /* Load the TLB */
61 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
62 local_irq_restore(flags);
63}
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
Paul Mundt2dc2f8e2010-01-21 16:05:25 +090065void local_flush_tlb_one(unsigned long asid, unsigned long page)
Linus Torvalds1da177e2005-04-16 15:20:36 -070066{
67 unsigned long addr, data;
68
69 /*
70 * NOTE: PTEH.ASID should be set to this MM
71 * _AND_ we need to write ASID to the array.
72 *
73 * It would be simple if we didn't need to set PTEH.ASID...
74 */
75 addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
76 data = page | asid; /* VALID bit is off */
Stuart Menefycbaa1182007-11-30 17:06:36 +090077 jump_to_uncached();
Paul Mundt9d56dd32010-01-26 12:58:40 +090078 __raw_writel(data, addr);
Stuart Menefycbaa1182007-11-30 17:06:36 +090079 back_to_cached();
Linus Torvalds1da177e2005-04-16 15:20:36 -070080}
Paul Mundtbe97d752010-04-02 16:13:27 +090081
82void local_flush_tlb_all(void)
83{
84 unsigned long flags, status;
85 int i;
86
87 /*
88 * Flush all the TLB.
89 */
90 local_irq_save(flags);
91 jump_to_uncached();
92
93 status = __raw_readl(MMUCR);
94 status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
95
96 if (status == 0)
97 status = MMUCR_URB_NENTRIES;
98
99 for (i = 0; i < status; i++)
100 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
101
102 for (i = 0; i < 4; i++)
103 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
104
105 back_to_cached();
106 ctrl_barrier();
107 local_irq_restore(flags);
108}