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Sergio Paracuellos9e2ddbd2019-01-04 08:08:24 +01001Mediatek Mt7621 PCIe PHY
2
3Required properties:
4- compatible: must be "mediatek,mt7621-pci-phy"
5- reg: base address and length of the PCIe PHY block
Sergio Paracuellos200ff802019-03-29 06:52:42 +01006- #phy-cells: must be <1> for pcie0_phy and for pcie1_phy.
Sergio Paracuellos9e2ddbd2019-01-04 08:08:24 +01007
8Example:
Sergio Paracuellos200ff802019-03-29 06:52:42 +01009 pcie0_phy: pcie-phy@1e149000 {
Sergio Paracuellos9e2ddbd2019-01-04 08:08:24 +010010 compatible = "mediatek,mt7621-pci-phy";
Sergio Paracuellos200ff802019-03-29 06:52:42 +010011 reg = <0x1e149000 0x0700>;
12 #phy-cells = <1>;
Sergio Paracuellos9e2ddbd2019-01-04 08:08:24 +010013 };
14
Sergio Paracuellos200ff802019-03-29 06:52:42 +010015 pcie1_phy: pcie-phy@1e14a000 {
Sergio Paracuellos9e2ddbd2019-01-04 08:08:24 +010016 compatible = "mediatek,mt7621-pci-phy";
Sergio Paracuellos200ff802019-03-29 06:52:42 +010017 reg = <0x1e14a000 0x0700>;
18 #phy-cells = <1>;
Sergio Paracuellos9e2ddbd2019-01-04 08:08:24 +010019 };
20
21 /* users of the PCIe phy */
22
23 pcie: pcie@1e140000 {
24 ...
25 ...
Sergio Paracuellos200ff802019-03-29 06:52:42 +010026 phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy 0>;
Sergio Paracuellos9e2ddbd2019-01-04 08:08:24 +010027 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
Sergio Paracuellos200ff802019-03-29 06:52:42 +010028 };