Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * Actions Semiconductor Owl SoC's I2C driver |
| 4 | * |
| 5 | * Copyright (c) 2014 Actions Semi Inc. |
| 6 | * Author: David Liu <liuwei@actions-semi.com> |
| 7 | * |
| 8 | * Copyright (c) 2018 Linaro Ltd. |
| 9 | * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 10 | */ |
| 11 | |
| 12 | #include <linux/clk.h> |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/i2c.h> |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/io.h> |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 17 | #include <linux/iopoll.h> |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 18 | #include <linux/module.h> |
Rob Herring | 59738ab | 2023-07-14 11:46:16 -0600 | [diff] [blame] | 19 | #include <linux/of.h> |
| 20 | #include <linux/platform_device.h> |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 21 | |
| 22 | /* I2C registers */ |
| 23 | #define OWL_I2C_REG_CTL 0x0000 |
| 24 | #define OWL_I2C_REG_CLKDIV 0x0004 |
| 25 | #define OWL_I2C_REG_STAT 0x0008 |
| 26 | #define OWL_I2C_REG_ADDR 0x000C |
| 27 | #define OWL_I2C_REG_TXDAT 0x0010 |
| 28 | #define OWL_I2C_REG_RXDAT 0x0014 |
| 29 | #define OWL_I2C_REG_CMD 0x0018 |
| 30 | #define OWL_I2C_REG_FIFOCTL 0x001C |
| 31 | #define OWL_I2C_REG_FIFOSTAT 0x0020 |
| 32 | #define OWL_I2C_REG_DATCNT 0x0024 |
| 33 | #define OWL_I2C_REG_RCNT 0x0028 |
| 34 | |
| 35 | /* I2Cx_CTL Bit Mask */ |
| 36 | #define OWL_I2C_CTL_RB BIT(1) |
| 37 | #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) |
| 38 | #define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) |
| 39 | #define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) |
| 40 | #define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) |
| 41 | #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) |
| 42 | #define OWL_I2C_CTL_IRQE BIT(5) |
| 43 | #define OWL_I2C_CTL_EN BIT(7) |
| 44 | #define OWL_I2C_CTL_AE BIT(8) |
| 45 | #define OWL_I2C_CTL_SHSM BIT(10) |
| 46 | |
| 47 | #define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) |
| 48 | |
| 49 | /* I2Cx_STAT Bit Mask */ |
| 50 | #define OWL_I2C_STAT_RACK BIT(0) |
| 51 | #define OWL_I2C_STAT_BEB BIT(1) |
| 52 | #define OWL_I2C_STAT_IRQP BIT(2) |
| 53 | #define OWL_I2C_STAT_LAB BIT(3) |
| 54 | #define OWL_I2C_STAT_STPD BIT(4) |
| 55 | #define OWL_I2C_STAT_STAD BIT(5) |
| 56 | #define OWL_I2C_STAT_BBB BIT(6) |
| 57 | #define OWL_I2C_STAT_TCB BIT(7) |
| 58 | #define OWL_I2C_STAT_LBST BIT(8) |
| 59 | #define OWL_I2C_STAT_SAMB BIT(9) |
| 60 | #define OWL_I2C_STAT_SRGC BIT(10) |
| 61 | |
| 62 | /* I2Cx_CMD Bit Mask */ |
| 63 | #define OWL_I2C_CMD_SBE BIT(0) |
| 64 | #define OWL_I2C_CMD_RBE BIT(4) |
| 65 | #define OWL_I2C_CMD_DE BIT(8) |
| 66 | #define OWL_I2C_CMD_NS BIT(9) |
| 67 | #define OWL_I2C_CMD_SE BIT(10) |
| 68 | #define OWL_I2C_CMD_MSS BIT(11) |
| 69 | #define OWL_I2C_CMD_WRS BIT(12) |
| 70 | #define OWL_I2C_CMD_SECL BIT(15) |
| 71 | |
| 72 | #define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) |
| 73 | #define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) |
| 74 | |
| 75 | /* I2Cx_FIFOCTL Bit Mask */ |
| 76 | #define OWL_I2C_FIFOCTL_NIB BIT(0) |
| 77 | #define OWL_I2C_FIFOCTL_RFR BIT(1) |
| 78 | #define OWL_I2C_FIFOCTL_TFR BIT(2) |
| 79 | |
| 80 | /* I2Cc_FIFOSTAT Bit Mask */ |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 81 | #define OWL_I2C_FIFOSTAT_CECB BIT(0) |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 82 | #define OWL_I2C_FIFOSTAT_RNB BIT(1) |
| 83 | #define OWL_I2C_FIFOSTAT_RFE BIT(2) |
| 84 | #define OWL_I2C_FIFOSTAT_TFF BIT(5) |
| 85 | #define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) |
| 86 | #define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) |
| 87 | |
| 88 | /* I2C bus timeout */ |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 89 | #define OWL_I2C_TIMEOUT_MS (4 * 1000) |
| 90 | #define OWL_I2C_TIMEOUT msecs_to_jiffies(OWL_I2C_TIMEOUT_MS) |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 91 | |
| 92 | #define OWL_I2C_MAX_RETRIES 50 |
| 93 | |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 94 | struct owl_i2c_dev { |
| 95 | struct i2c_adapter adap; |
| 96 | struct i2c_msg *msg; |
| 97 | struct completion msg_complete; |
| 98 | struct clk *clk; |
| 99 | spinlock_t lock; |
| 100 | void __iomem *base; |
| 101 | unsigned long clk_rate; |
| 102 | u32 bus_freq; |
| 103 | u32 msg_ptr; |
| 104 | int err; |
| 105 | }; |
| 106 | |
| 107 | static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) |
| 108 | { |
| 109 | unsigned int regval; |
| 110 | |
| 111 | regval = readl(reg); |
| 112 | |
| 113 | if (state) |
| 114 | regval |= val; |
| 115 | else |
| 116 | regval &= ~val; |
| 117 | |
| 118 | writel(regval, reg); |
| 119 | } |
| 120 | |
| 121 | static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) |
| 122 | { |
| 123 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, |
| 124 | OWL_I2C_CTL_EN, false); |
| 125 | mdelay(1); |
| 126 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, |
| 127 | OWL_I2C_CTL_EN, true); |
| 128 | |
| 129 | /* Clear status registers */ |
| 130 | writel(0, i2c_dev->base + OWL_I2C_REG_STAT); |
| 131 | } |
| 132 | |
| 133 | static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev) |
| 134 | { |
| 135 | unsigned int val, timeout = 0; |
| 136 | |
| 137 | /* Reset FIFO */ |
| 138 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, |
| 139 | OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, |
| 140 | true); |
| 141 | |
| 142 | /* Wait 50ms for FIFO reset complete */ |
| 143 | do { |
| 144 | val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); |
| 145 | if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) |
| 146 | break; |
| 147 | usleep_range(500, 1000); |
| 148 | } while (timeout++ < OWL_I2C_MAX_RETRIES); |
| 149 | |
| 150 | if (timeout > OWL_I2C_MAX_RETRIES) { |
| 151 | dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n"); |
| 152 | return -ETIMEDOUT; |
| 153 | } |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) |
| 159 | { |
| 160 | unsigned int val; |
| 161 | |
| 162 | val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); |
| 163 | |
| 164 | /* Set clock divider factor */ |
| 165 | writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); |
| 166 | } |
| 167 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 168 | static void owl_i2c_xfer_data(struct owl_i2c_dev *i2c_dev) |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 169 | { |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 170 | struct i2c_msg *msg = i2c_dev->msg; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 171 | unsigned int stat, fifostat; |
| 172 | |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 173 | i2c_dev->err = 0; |
| 174 | |
Wolfram Sang | b4a0ca1 | 2024-07-06 13:20:36 +0200 | [diff] [blame] | 175 | /* Handle NACK from target */ |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 176 | fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); |
| 177 | if (fifostat & OWL_I2C_FIFOSTAT_RNB) { |
| 178 | i2c_dev->err = -ENXIO; |
Cristian Ciocaltea | f5b3f43 | 2020-10-09 00:44:39 +0300 | [diff] [blame] | 179 | /* Clear NACK error bit by writing "1" */ |
| 180 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, |
| 181 | OWL_I2C_FIFOSTAT_RNB, true); |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 182 | return; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | /* Handle bus error */ |
| 186 | stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); |
| 187 | if (stat & OWL_I2C_STAT_BEB) { |
| 188 | i2c_dev->err = -EIO; |
Cristian Ciocaltea | f5b3f43 | 2020-10-09 00:44:39 +0300 | [diff] [blame] | 189 | /* Clear BUS error bit by writing "1" */ |
| 190 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, |
| 191 | OWL_I2C_STAT_BEB, true); |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 192 | return; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | /* Handle FIFO read */ |
| 196 | if (msg->flags & I2C_M_RD) { |
| 197 | while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & |
| 198 | OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) { |
| 199 | msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + |
| 200 | OWL_I2C_REG_RXDAT); |
| 201 | } |
| 202 | } else { |
| 203 | /* Handle the remaining bytes which were not sent */ |
| 204 | while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & |
| 205 | OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) { |
| 206 | writel(msg->buf[i2c_dev->msg_ptr++], |
| 207 | i2c_dev->base + OWL_I2C_REG_TXDAT); |
| 208 | } |
| 209 | } |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 210 | } |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 211 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 212 | static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) |
| 213 | { |
| 214 | struct owl_i2c_dev *i2c_dev = _dev; |
| 215 | |
| 216 | spin_lock(&i2c_dev->lock); |
| 217 | |
| 218 | owl_i2c_xfer_data(i2c_dev); |
| 219 | |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 220 | /* Clear pending interrupts */ |
| 221 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, |
| 222 | OWL_I2C_STAT_IRQP, true); |
| 223 | |
| 224 | complete_all(&i2c_dev->msg_complete); |
Barry Song | 0685626 | 2020-09-09 16:10:01 +1200 | [diff] [blame] | 225 | spin_unlock(&i2c_dev->lock); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 226 | |
| 227 | return IRQ_HANDLED; |
| 228 | } |
| 229 | |
| 230 | static u32 owl_i2c_func(struct i2c_adapter *adap) |
| 231 | { |
| 232 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
| 233 | } |
| 234 | |
| 235 | static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) |
| 236 | { |
| 237 | struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
| 238 | unsigned long timeout; |
| 239 | |
| 240 | /* Check for Bus busy */ |
| 241 | timeout = jiffies + OWL_I2C_TIMEOUT; |
| 242 | while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { |
| 243 | if (time_after(jiffies, timeout)) { |
| 244 | dev_err(&adap->dev, "Bus busy timeout\n"); |
| 245 | return -ETIMEDOUT; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | return 0; |
| 250 | } |
| 251 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 252 | static int owl_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg *msgs, |
| 253 | int num, bool atomic) |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 254 | { |
| 255 | struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
| 256 | struct i2c_msg *msg; |
| 257 | unsigned long time_left, flags; |
| 258 | unsigned int i2c_cmd, val; |
| 259 | unsigned int addr; |
| 260 | int ret, idx; |
| 261 | |
| 262 | spin_lock_irqsave(&i2c_dev->lock, flags); |
| 263 | |
| 264 | /* Reset I2C controller */ |
| 265 | owl_i2c_reset(i2c_dev); |
| 266 | |
| 267 | /* Set bus frequency */ |
| 268 | owl_i2c_set_freq(i2c_dev); |
| 269 | |
| 270 | /* |
| 271 | * Spinlock should be released before calling reset FIFO and |
| 272 | * bus busy check since those functions may sleep |
| 273 | */ |
| 274 | spin_unlock_irqrestore(&i2c_dev->lock, flags); |
| 275 | |
| 276 | /* Reset FIFO */ |
| 277 | ret = owl_i2c_reset_fifo(i2c_dev); |
| 278 | if (ret) |
| 279 | goto unlocked_err_exit; |
| 280 | |
| 281 | /* Check for bus busy */ |
| 282 | ret = owl_i2c_check_bus_busy(adap); |
| 283 | if (ret) |
| 284 | goto unlocked_err_exit; |
| 285 | |
| 286 | spin_lock_irqsave(&i2c_dev->lock, flags); |
| 287 | |
| 288 | /* Check for Arbitration lost */ |
| 289 | val = readl(i2c_dev->base + OWL_I2C_REG_STAT); |
| 290 | if (val & OWL_I2C_STAT_LAB) { |
| 291 | val &= ~OWL_I2C_STAT_LAB; |
| 292 | writel(val, i2c_dev->base + OWL_I2C_REG_STAT); |
| 293 | ret = -EAGAIN; |
| 294 | goto err_exit; |
| 295 | } |
| 296 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 297 | if (!atomic) |
| 298 | reinit_completion(&i2c_dev->msg_complete); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 299 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 300 | /* Enable/disable I2C controller interrupt */ |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 301 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 302 | OWL_I2C_CTL_IRQE, !atomic); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 303 | |
| 304 | /* |
Wolfram Sang | b4a0ca1 | 2024-07-06 13:20:36 +0200 | [diff] [blame] | 305 | * Select: FIFO enable, controller mode, Stop enable, Data count enable, |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 306 | * Send start bit |
| 307 | */ |
| 308 | i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE | |
| 309 | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE; |
| 310 | |
| 311 | /* Handle repeated start condition */ |
| 312 | if (num > 1) { |
| 313 | /* Set internal address length and enable repeated start */ |
| 314 | i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) | |
| 315 | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE; |
| 316 | |
Wolfram Sang | b4a0ca1 | 2024-07-06 13:20:36 +0200 | [diff] [blame] | 317 | /* Write target address */ |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 318 | addr = i2c_8bit_addr_from_msg(&msgs[0]); |
| 319 | writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); |
| 320 | |
| 321 | /* Write internal register address */ |
| 322 | for (idx = 0; idx < msgs[0].len; idx++) |
| 323 | writel(msgs[0].buf[idx], |
| 324 | i2c_dev->base + OWL_I2C_REG_TXDAT); |
| 325 | |
| 326 | msg = &msgs[1]; |
| 327 | } else { |
| 328 | /* Set address length */ |
| 329 | i2c_cmd |= OWL_I2C_CMD_AS(1); |
| 330 | msg = &msgs[0]; |
| 331 | } |
| 332 | |
| 333 | i2c_dev->msg = msg; |
| 334 | i2c_dev->msg_ptr = 0; |
| 335 | |
| 336 | /* Set data count for the message */ |
| 337 | writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); |
| 338 | |
| 339 | addr = i2c_8bit_addr_from_msg(msg); |
| 340 | writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); |
| 341 | |
| 342 | if (!(msg->flags & I2C_M_RD)) { |
| 343 | /* Write data to FIFO */ |
| 344 | for (idx = 0; idx < msg->len; idx++) { |
| 345 | /* Check for FIFO full */ |
| 346 | if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & |
| 347 | OWL_I2C_FIFOSTAT_TFF) |
| 348 | break; |
| 349 | |
| 350 | writel(msg->buf[idx], |
| 351 | i2c_dev->base + OWL_I2C_REG_TXDAT); |
| 352 | } |
| 353 | |
| 354 | i2c_dev->msg_ptr = idx; |
| 355 | } |
| 356 | |
| 357 | /* Ignore the NACK if needed */ |
| 358 | if (msg->flags & I2C_M_IGNORE_NAK) |
| 359 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, |
| 360 | OWL_I2C_FIFOCTL_NIB, true); |
| 361 | else |
| 362 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, |
| 363 | OWL_I2C_FIFOCTL_NIB, false); |
| 364 | |
| 365 | /* Start the transfer */ |
| 366 | writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); |
| 367 | |
| 368 | spin_unlock_irqrestore(&i2c_dev->lock, flags); |
| 369 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 370 | if (atomic) { |
| 371 | /* Wait for Command Execute Completed or NACK Error bits */ |
| 372 | ret = readl_poll_timeout_atomic(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, |
| 373 | val, val & (OWL_I2C_FIFOSTAT_CECB | |
| 374 | OWL_I2C_FIFOSTAT_RNB), |
| 375 | 10, OWL_I2C_TIMEOUT_MS * 1000); |
| 376 | } else { |
| 377 | time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, |
| 378 | adap->timeout); |
| 379 | if (!time_left) |
| 380 | ret = -ETIMEDOUT; |
| 381 | } |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 382 | |
| 383 | spin_lock_irqsave(&i2c_dev->lock, flags); |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 384 | |
| 385 | if (ret) { |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 386 | dev_err(&adap->dev, "Transaction timed out\n"); |
| 387 | /* Send stop condition and release the bus */ |
| 388 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, |
| 389 | OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, |
| 390 | true); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 391 | goto err_exit; |
| 392 | } |
| 393 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 394 | if (atomic) |
| 395 | owl_i2c_xfer_data(i2c_dev); |
| 396 | |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 397 | ret = i2c_dev->err < 0 ? i2c_dev->err : num; |
| 398 | |
| 399 | err_exit: |
| 400 | spin_unlock_irqrestore(&i2c_dev->lock, flags); |
| 401 | |
| 402 | unlocked_err_exit: |
| 403 | /* Disable I2C controller */ |
| 404 | owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, |
| 405 | OWL_I2C_CTL_EN, false); |
| 406 | |
| 407 | return ret; |
| 408 | } |
| 409 | |
Cristian Ciocaltea | b8be24e | 2020-10-09 00:44:40 +0300 | [diff] [blame] | 410 | static int owl_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, |
| 411 | int num) |
| 412 | { |
| 413 | return owl_i2c_xfer_common(adap, msgs, num, false); |
| 414 | } |
| 415 | |
| 416 | static int owl_i2c_xfer_atomic(struct i2c_adapter *adap, |
| 417 | struct i2c_msg *msgs, int num) |
| 418 | { |
| 419 | return owl_i2c_xfer_common(adap, msgs, num, true); |
| 420 | } |
| 421 | |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 422 | static const struct i2c_algorithm owl_i2c_algorithm = { |
Wolfram Sang | b4a0ca1 | 2024-07-06 13:20:36 +0200 | [diff] [blame] | 423 | .xfer = owl_i2c_xfer, |
| 424 | .xfer_atomic = owl_i2c_xfer_atomic, |
| 425 | .functionality = owl_i2c_func, |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 426 | }; |
| 427 | |
| 428 | static const struct i2c_adapter_quirks owl_i2c_quirks = { |
| 429 | .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, |
| 430 | .max_read_len = 240, |
| 431 | .max_write_len = 240, |
| 432 | .max_comb_1st_msg_len = 6, |
| 433 | .max_comb_2nd_msg_len = 240, |
| 434 | }; |
| 435 | |
| 436 | static int owl_i2c_probe(struct platform_device *pdev) |
| 437 | { |
| 438 | struct device *dev = &pdev->dev; |
| 439 | struct owl_i2c_dev *i2c_dev; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 440 | int ret, irq; |
| 441 | |
| 442 | i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); |
| 443 | if (!i2c_dev) |
| 444 | return -ENOMEM; |
| 445 | |
Dejin Zheng | e0442d76 | 2020-04-09 21:52:24 +0800 | [diff] [blame] | 446 | i2c_dev->base = devm_platform_ioremap_resource(pdev, 0); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 447 | if (IS_ERR(i2c_dev->base)) |
| 448 | return PTR_ERR(i2c_dev->base); |
| 449 | |
| 450 | irq = platform_get_irq(pdev, 0); |
Dejin Zheng | e42688e | 2020-04-16 23:23:45 +0800 | [diff] [blame] | 451 | if (irq < 0) |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 452 | return irq; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 453 | |
| 454 | if (of_property_read_u32(dev->of_node, "clock-frequency", |
| 455 | &i2c_dev->bus_freq)) |
Andy Shevchenko | 90224e6 | 2020-03-24 14:32:16 +0200 | [diff] [blame] | 456 | i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 457 | |
| 458 | /* We support only frequencies of 100k and 400k for now */ |
Andy Shevchenko | 90224e6 | 2020-03-24 14:32:16 +0200 | [diff] [blame] | 459 | if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ && |
| 460 | i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) { |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 461 | dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); |
| 462 | return -EINVAL; |
| 463 | } |
| 464 | |
Andi Shyti | 7e8e667 | 2023-06-12 00:56:56 +0200 | [diff] [blame] | 465 | i2c_dev->clk = devm_clk_get_enabled(dev, NULL); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 466 | if (IS_ERR(i2c_dev->clk)) { |
Andi Shyti | 7e8e667 | 2023-06-12 00:56:56 +0200 | [diff] [blame] | 467 | dev_err(dev, "failed to enable clock\n"); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 468 | return PTR_ERR(i2c_dev->clk); |
| 469 | } |
| 470 | |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 471 | i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); |
| 472 | if (!i2c_dev->clk_rate) { |
| 473 | dev_err(dev, "input clock rate should not be zero\n"); |
Andi Shyti | 7e8e667 | 2023-06-12 00:56:56 +0200 | [diff] [blame] | 474 | return -EINVAL; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 475 | } |
| 476 | |
| 477 | init_completion(&i2c_dev->msg_complete); |
| 478 | spin_lock_init(&i2c_dev->lock); |
| 479 | i2c_dev->adap.owner = THIS_MODULE; |
| 480 | i2c_dev->adap.algo = &owl_i2c_algorithm; |
| 481 | i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; |
| 482 | i2c_dev->adap.quirks = &owl_i2c_quirks; |
| 483 | i2c_dev->adap.dev.parent = dev; |
| 484 | i2c_dev->adap.dev.of_node = dev->of_node; |
| 485 | snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), |
| 486 | "%s", "OWL I2C adapter"); |
| 487 | i2c_set_adapdata(&i2c_dev->adap, i2c_dev); |
| 488 | |
| 489 | platform_set_drvdata(pdev, i2c_dev); |
| 490 | |
| 491 | ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, |
| 492 | i2c_dev); |
| 493 | if (ret) { |
| 494 | dev_err(dev, "failed to request irq %d\n", irq); |
Andi Shyti | 7e8e667 | 2023-06-12 00:56:56 +0200 | [diff] [blame] | 495 | return ret; |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 496 | } |
| 497 | |
| 498 | return i2c_add_adapter(&i2c_dev->adap); |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | static const struct of_device_id owl_i2c_of_match[] = { |
Cristian Ciocaltea | 04fd6f0 | 2020-11-20 01:56:06 +0200 | [diff] [blame] | 502 | { .compatible = "actions,s500-i2c" }, |
Parthiban Nallathambi | 81482d1 | 2018-12-11 09:04:47 +0100 | [diff] [blame] | 503 | { .compatible = "actions,s700-i2c" }, |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 504 | { .compatible = "actions,s900-i2c" }, |
| 505 | { /* sentinel */ } |
| 506 | }; |
| 507 | MODULE_DEVICE_TABLE(of, owl_i2c_of_match); |
| 508 | |
| 509 | static struct platform_driver owl_i2c_driver = { |
| 510 | .probe = owl_i2c_probe, |
| 511 | .driver = { |
| 512 | .name = "owl-i2c", |
Krzysztof Kozlowski | 8759500 | 2023-03-11 12:16:55 +0100 | [diff] [blame] | 513 | .of_match_table = owl_i2c_of_match, |
Cristian Ciocaltea | 46f8bfe | 2020-10-09 00:44:41 +0300 | [diff] [blame] | 514 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
Manivannan Sadhasivam | d211e62 | 2018-08-01 23:32:31 +0530 | [diff] [blame] | 515 | }, |
| 516 | }; |
| 517 | module_platform_driver(owl_i2c_driver); |
| 518 | |
| 519 | MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>"); |
| 520 | MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); |
| 521 | MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver"); |
| 522 | MODULE_LICENSE("GPL"); |