Johan Jonker | 2f8e928 | 2021-02-09 20:23:43 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Rockchip SuperSpeed DWC3 USB SoC controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Heiko Stuebner <heiko@sntech.de> |
| 11 | |
| 12 | description: |
| 13 | The common content of the node is defined in snps,dwc3.yaml. |
| 14 | |
| 15 | Phy documentation is provided in the following places. |
| 16 | |
| 17 | USB2.0 PHY |
| 18 | Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml |
| 19 | |
| 20 | Type-C PHY |
| 21 | Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt |
| 22 | |
| 23 | allOf: |
| 24 | - $ref: snps,dwc3.yaml# |
| 25 | |
| 26 | select: |
| 27 | properties: |
| 28 | compatible: |
| 29 | contains: |
| 30 | enum: |
Johan Jonker | 08f4a6b | 2021-02-09 20:23:48 +0100 | [diff] [blame] | 31 | - rockchip,rk3328-dwc3 |
Johan Jonker | 2f8e928 | 2021-02-09 20:23:43 +0100 | [diff] [blame] | 32 | - rockchip,rk3399-dwc3 |
| 33 | required: |
| 34 | - compatible |
| 35 | |
| 36 | properties: |
| 37 | compatible: |
| 38 | items: |
| 39 | - enum: |
Johan Jonker | 08f4a6b | 2021-02-09 20:23:48 +0100 | [diff] [blame] | 40 | - rockchip,rk3328-dwc3 |
Johan Jonker | 2f8e928 | 2021-02-09 20:23:43 +0100 | [diff] [blame] | 41 | - rockchip,rk3399-dwc3 |
| 42 | - const: snps,dwc3 |
| 43 | |
| 44 | reg: |
| 45 | maxItems: 1 |
| 46 | |
| 47 | interrupts: |
| 48 | maxItems: 1 |
| 49 | |
| 50 | clocks: |
Johan Jonker | 08f4a6b | 2021-02-09 20:23:48 +0100 | [diff] [blame] | 51 | minItems: 3 |
Johan Jonker | 2f8e928 | 2021-02-09 20:23:43 +0100 | [diff] [blame] | 52 | items: |
| 53 | - description: |
| 54 | Controller reference clock, must to be 24 MHz |
| 55 | - description: |
| 56 | Controller suspend clock, must to be 24 MHz or 32 KHz |
| 57 | - description: |
| 58 | Master/Core clock, must to be >= 62.5 MHz for SS |
| 59 | operation and >= 30MHz for HS operation |
| 60 | - description: |
| 61 | Controller grf clock |
| 62 | |
| 63 | clock-names: |
Johan Jonker | 08f4a6b | 2021-02-09 20:23:48 +0100 | [diff] [blame] | 64 | minItems: 3 |
Johan Jonker | 2f8e928 | 2021-02-09 20:23:43 +0100 | [diff] [blame] | 65 | items: |
| 66 | - const: ref_clk |
| 67 | - const: suspend_clk |
| 68 | - const: bus_clk |
| 69 | - const: grf_clk |
| 70 | |
| 71 | power-domains: |
| 72 | maxItems: 1 |
| 73 | |
| 74 | resets: |
| 75 | maxItems: 1 |
| 76 | |
| 77 | reset-names: |
| 78 | const: usb3-otg |
| 79 | |
| 80 | unevaluatedProperties: false |
| 81 | |
| 82 | required: |
| 83 | - compatible |
| 84 | - reg |
| 85 | - interrupts |
| 86 | - clocks |
| 87 | - clock-names |
| 88 | |
| 89 | examples: |
| 90 | - | |
| 91 | #include <dt-bindings/clock/rk3399-cru.h> |
| 92 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 93 | |
| 94 | bus { |
| 95 | #address-cells = <2>; |
| 96 | #size-cells = <2>; |
| 97 | |
| 98 | usbdrd3_0: usb@fe800000 { |
| 99 | compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; |
| 100 | reg = <0x0 0xfe800000 0x0 0x100000>; |
| 101 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 102 | clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, |
| 103 | <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; |
| 104 | clock-names = "ref_clk", "suspend_clk", |
| 105 | "bus_clk", "grf_clk"; |
| 106 | dr_mode = "otg"; |
| 107 | }; |
| 108 | }; |