Greg Kroah-Hartman | 5fd54ac | 2017-11-03 11:28:30 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Renesas USB driver R-Car Gen. 3 initialization and power control |
| 4 | * |
| 5 | * Copyright (C) 2016 Renesas Electronics Corporation |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 6 | */ |
| 7 | |
Yoshihiro Shimoda | b760323 | 2016-10-20 13:19:19 +0900 | [diff] [blame] | 8 | #include <linux/delay.h> |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 9 | #include <linux/io.h> |
| 10 | #include "common.h" |
| 11 | #include "rcar3.h" |
| 12 | |
| 13 | #define LPSTS 0x102 |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 14 | #define UGCTRL 0x180 /* 32-bit register */ |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 15 | #define UGCTRL2 0x184 /* 32-bit register */ |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 16 | #define UGSTS 0x188 /* 32-bit register */ |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 17 | |
| 18 | /* Low Power Status register (LPSTS) */ |
| 19 | #define LPSTS_SUSPM 0x4000 |
| 20 | |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 21 | /* R-Car D3 only: USB General control register (UGCTRL) */ |
| 22 | #define UGCTRL_PLLRESET 0x00000001 |
| 23 | #define UGCTRL_CONNECT 0x00000004 |
| 24 | |
Yoshihiro Shimoda | 2acecd5 | 2017-08-02 13:21:45 +0900 | [diff] [blame] | 25 | /* |
| 26 | * USB General control register 2 (UGCTRL2) |
| 27 | * Remarks: bit[31:11] and bit[9:6] should be 0 |
| 28 | */ |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 29 | #define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */ |
Yoshihiro Shimoda | cd14247 | 2017-12-13 15:46:59 +0900 | [diff] [blame] | 30 | #define UGCTRL2_USB0SEL_EHCI 0x00000010 |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 31 | #define UGCTRL2_USB0SEL_HSUSB 0x00000020 |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 32 | #define UGCTRL2_USB0SEL_OTG 0x00000030 |
Yoshihiro Shimoda | 2acecd5 | 2017-08-02 13:21:45 +0900 | [diff] [blame] | 33 | #define UGCTRL2_VBUSSEL 0x00000400 |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 34 | |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 35 | /* R-Car D3 only: USB General status register (UGSTS) */ |
| 36 | #define UGSTS_LOCK 0x00000100 |
| 37 | |
Ben Dooks | 107a4b5 | 2016-06-21 18:52:54 +0100 | [diff] [blame] | 38 | static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data) |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 39 | { |
| 40 | iowrite32(data, priv->base + reg); |
| 41 | } |
| 42 | |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 43 | static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg) |
| 44 | { |
| 45 | return ioread32(priv->base + reg); |
| 46 | } |
| 47 | |
Yoshihiro Shimoda | 05e37b6 | 2017-12-13 15:46:57 +0900 | [diff] [blame] | 48 | static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val) |
| 49 | { |
| 50 | usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3); |
| 51 | } |
| 52 | |
Yoshihiro Shimoda | cd14247 | 2017-12-13 15:46:59 +0900 | [diff] [blame] | 53 | static void usbhs_rcar3_set_usbsel(struct usbhs_priv *priv, bool ehci) |
| 54 | { |
| 55 | if (ehci) |
| 56 | usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_EHCI); |
| 57 | else |
| 58 | usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB); |
| 59 | } |
| 60 | |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 61 | static int usbhs_rcar3_power_ctrl(struct platform_device *pdev, |
| 62 | void __iomem *base, int enable) |
| 63 | { |
| 64 | struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev); |
| 65 | |
Yoshihiro Shimoda | 05e37b6 | 2017-12-13 15:46:57 +0900 | [diff] [blame] | 66 | usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL); |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 67 | |
Yoshihiro Shimoda | b760323 | 2016-10-20 13:19:19 +0900 | [diff] [blame] | 68 | if (enable) { |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 69 | usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM); |
Yoshihiro Shimoda | b760323 | 2016-10-20 13:19:19 +0900 | [diff] [blame] | 70 | /* The controller on R-Car Gen3 needs to wait up to 45 usec */ |
| 71 | udelay(45); |
| 72 | } else { |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 73 | usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0); |
Yoshihiro Shimoda | b760323 | 2016-10-20 13:19:19 +0900 | [diff] [blame] | 74 | } |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 75 | |
| 76 | return 0; |
| 77 | } |
| 78 | |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 79 | /* R-Car D3 needs to release UGCTRL.PLLRESET */ |
| 80 | static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev, |
| 81 | void __iomem *base, int enable) |
| 82 | { |
| 83 | struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev); |
| 84 | u32 val; |
| 85 | int timeout = 1000; |
Yoshihiro Shimoda | cd14247 | 2017-12-13 15:46:59 +0900 | [diff] [blame] | 86 | bool is_host = false; |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 87 | |
| 88 | if (enable) { |
| 89 | usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */ |
Yoshihiro Shimoda | cd14247 | 2017-12-13 15:46:59 +0900 | [diff] [blame] | 90 | if (priv->edev) |
| 91 | is_host = extcon_get_state(priv->edev, EXTCON_USB_HOST); |
| 92 | |
| 93 | usbhs_rcar3_set_usbsel(priv, is_host); |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 94 | |
| 95 | usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM); |
| 96 | do { |
| 97 | val = usbhs_read32(priv, UGSTS); |
| 98 | udelay(1); |
| 99 | } while (!(val & UGSTS_LOCK) && timeout--); |
| 100 | usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT); |
| 101 | } else { |
| 102 | usbhs_write32(priv, UGCTRL, 0); |
| 103 | usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0); |
| 104 | usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET); |
| 105 | } |
| 106 | |
| 107 | return 0; |
| 108 | } |
| 109 | |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 110 | static int usbhs_rcar3_get_id(struct platform_device *pdev) |
| 111 | { |
| 112 | return USBHS_GADGET; |
| 113 | } |
| 114 | |
Yoshihiro Shimoda | 8ada211 | 2017-12-13 15:47:00 +0900 | [diff] [blame] | 115 | static int usbhs_rcar3_notifier(struct notifier_block *nb, unsigned long event, |
| 116 | void *data) |
| 117 | { |
| 118 | struct usbhs_priv *priv = container_of(nb, struct usbhs_priv, nb); |
| 119 | |
| 120 | usbhs_rcar3_set_usbsel(priv, !!event); |
| 121 | |
| 122 | return NOTIFY_DONE; |
| 123 | } |
| 124 | |
Yoshihiro Shimoda | de18757 | 2016-01-07 18:18:13 +0900 | [diff] [blame] | 125 | const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = { |
| 126 | .power_ctrl = usbhs_rcar3_power_ctrl, |
| 127 | .get_id = usbhs_rcar3_get_id, |
| 128 | }; |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 129 | |
| 130 | const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops = { |
| 131 | .power_ctrl = usbhs_rcar3_power_and_pll_ctrl, |
| 132 | .get_id = usbhs_rcar3_get_id, |
Yoshihiro Shimoda | 8ada211 | 2017-12-13 15:47:00 +0900 | [diff] [blame] | 133 | .notifier = usbhs_rcar3_notifier, |
Yoshihiro Shimoda | 0f38672 | 2017-10-03 20:09:14 +0900 | [diff] [blame] | 134 | }; |