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Greg Kroah-Hartman5fd54ac2017-11-03 11:28:30 +01001// SPDX-License-Identifier: GPL-2.0
Yoshihiro Shimodade187572016-01-07 18:18:13 +09002/*
3 * Renesas USB driver R-Car Gen. 3 initialization and power control
4 *
5 * Copyright (C) 2016 Renesas Electronics Corporation
Yoshihiro Shimodade187572016-01-07 18:18:13 +09006 */
7
Yoshihiro Shimodab7603232016-10-20 13:19:19 +09008#include <linux/delay.h>
Yoshihiro Shimodade187572016-01-07 18:18:13 +09009#include <linux/io.h>
10#include "common.h"
11#include "rcar3.h"
12
13#define LPSTS 0x102
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090014#define UGCTRL 0x180 /* 32-bit register */
Yoshihiro Shimodade187572016-01-07 18:18:13 +090015#define UGCTRL2 0x184 /* 32-bit register */
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090016#define UGSTS 0x188 /* 32-bit register */
Yoshihiro Shimodade187572016-01-07 18:18:13 +090017
18/* Low Power Status register (LPSTS) */
19#define LPSTS_SUSPM 0x4000
20
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090021/* R-Car D3 only: USB General control register (UGCTRL) */
22#define UGCTRL_PLLRESET 0x00000001
23#define UGCTRL_CONNECT 0x00000004
24
Yoshihiro Shimoda2acecd52017-08-02 13:21:45 +090025/*
26 * USB General control register 2 (UGCTRL2)
27 * Remarks: bit[31:11] and bit[9:6] should be 0
28 */
Yoshihiro Shimodade187572016-01-07 18:18:13 +090029#define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
Yoshihiro Shimodacd142472017-12-13 15:46:59 +090030#define UGCTRL2_USB0SEL_EHCI 0x00000010
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090031#define UGCTRL2_USB0SEL_HSUSB 0x00000020
Yoshihiro Shimodade187572016-01-07 18:18:13 +090032#define UGCTRL2_USB0SEL_OTG 0x00000030
Yoshihiro Shimoda2acecd52017-08-02 13:21:45 +090033#define UGCTRL2_VBUSSEL 0x00000400
Yoshihiro Shimodade187572016-01-07 18:18:13 +090034
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090035/* R-Car D3 only: USB General status register (UGSTS) */
36#define UGSTS_LOCK 0x00000100
37
Ben Dooks107a4b52016-06-21 18:52:54 +010038static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
Yoshihiro Shimodade187572016-01-07 18:18:13 +090039{
40 iowrite32(data, priv->base + reg);
41}
42
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090043static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg)
44{
45 return ioread32(priv->base + reg);
46}
47
Yoshihiro Shimoda05e37b62017-12-13 15:46:57 +090048static void usbhs_rcar3_set_ugctrl2(struct usbhs_priv *priv, u32 val)
49{
50 usbhs_write32(priv, UGCTRL2, val | UGCTRL2_RESERVED_3);
51}
52
Yoshihiro Shimodacd142472017-12-13 15:46:59 +090053static void usbhs_rcar3_set_usbsel(struct usbhs_priv *priv, bool ehci)
54{
55 if (ehci)
56 usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_EHCI);
57 else
58 usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_HSUSB);
59}
60
Yoshihiro Shimodade187572016-01-07 18:18:13 +090061static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
62 void __iomem *base, int enable)
63{
64 struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
65
Yoshihiro Shimoda05e37b62017-12-13 15:46:57 +090066 usbhs_rcar3_set_ugctrl2(priv, UGCTRL2_USB0SEL_OTG | UGCTRL2_VBUSSEL);
Yoshihiro Shimodade187572016-01-07 18:18:13 +090067
Yoshihiro Shimodab7603232016-10-20 13:19:19 +090068 if (enable) {
Yoshihiro Shimodade187572016-01-07 18:18:13 +090069 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
Yoshihiro Shimodab7603232016-10-20 13:19:19 +090070 /* The controller on R-Car Gen3 needs to wait up to 45 usec */
71 udelay(45);
72 } else {
Yoshihiro Shimodade187572016-01-07 18:18:13 +090073 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
Yoshihiro Shimodab7603232016-10-20 13:19:19 +090074 }
Yoshihiro Shimodade187572016-01-07 18:18:13 +090075
76 return 0;
77}
78
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090079/* R-Car D3 needs to release UGCTRL.PLLRESET */
80static int usbhs_rcar3_power_and_pll_ctrl(struct platform_device *pdev,
81 void __iomem *base, int enable)
82{
83 struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
84 u32 val;
85 int timeout = 1000;
Yoshihiro Shimodacd142472017-12-13 15:46:59 +090086 bool is_host = false;
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090087
88 if (enable) {
89 usbhs_write32(priv, UGCTRL, 0); /* release PLLRESET */
Yoshihiro Shimodacd142472017-12-13 15:46:59 +090090 if (priv->edev)
91 is_host = extcon_get_state(priv->edev, EXTCON_USB_HOST);
92
93 usbhs_rcar3_set_usbsel(priv, is_host);
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +090094
95 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
96 do {
97 val = usbhs_read32(priv, UGSTS);
98 udelay(1);
99 } while (!(val & UGSTS_LOCK) && timeout--);
100 usbhs_write32(priv, UGCTRL, UGCTRL_CONNECT);
101 } else {
102 usbhs_write32(priv, UGCTRL, 0);
103 usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
104 usbhs_write32(priv, UGCTRL, UGCTRL_PLLRESET);
105 }
106
107 return 0;
108}
109
Yoshihiro Shimodade187572016-01-07 18:18:13 +0900110static int usbhs_rcar3_get_id(struct platform_device *pdev)
111{
112 return USBHS_GADGET;
113}
114
Yoshihiro Shimoda8ada2112017-12-13 15:47:00 +0900115static int usbhs_rcar3_notifier(struct notifier_block *nb, unsigned long event,
116 void *data)
117{
118 struct usbhs_priv *priv = container_of(nb, struct usbhs_priv, nb);
119
120 usbhs_rcar3_set_usbsel(priv, !!event);
121
122 return NOTIFY_DONE;
123}
124
Yoshihiro Shimodade187572016-01-07 18:18:13 +0900125const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
126 .power_ctrl = usbhs_rcar3_power_ctrl,
127 .get_id = usbhs_rcar3_get_id,
128};
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +0900129
130const struct renesas_usbhs_platform_callback usbhs_rcar3_with_pll_ops = {
131 .power_ctrl = usbhs_rcar3_power_and_pll_ctrl,
132 .get_id = usbhs_rcar3_get_id,
Yoshihiro Shimoda8ada2112017-12-13 15:47:00 +0900133 .notifier = usbhs_rcar3_notifier,
Yoshihiro Shimoda0f386722017-10-03 20:09:14 +0900134};