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Thomas Gleixnera912e802019-05-27 08:55:00 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Thierry Redingf6b8a572012-08-22 10:01:24 +02002/*
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
Uwe Kleine-König3b442c62019-07-30 14:32:29 +02005 *
6 * Limitations:
7 * - The .apply callback doesn't complete the currently running period before
8 * reconfiguring the hardware.
Thierry Redingf6b8a572012-08-22 10:01:24 +02009 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/gpio.h>
14#include <linux/kernel.h>
Paul Cercueilc2693512020-03-23 15:24:20 +010015#include <linux/mfd/ingenic-tcu.h>
16#include <linux/mfd/syscon.h>
Thierry Redingf6b8a572012-08-22 10:01:24 +020017#include <linux/module.h>
Paul Cercueilcc201732018-01-06 17:58:42 +010018#include <linux/of_device.h>
Thierry Redingf6b8a572012-08-22 10:01:24 +020019#include <linux/platform_device.h>
20#include <linux/pwm.h>
Paul Cercueilc2693512020-03-23 15:24:20 +010021#include <linux/regmap.h>
Thierry Redingf6b8a572012-08-22 10:01:24 +020022
Paul Cercueil74db7282020-05-27 13:52:25 +020023struct soc_info {
24 unsigned int num_pwms;
25};
Thierry Redingf6b8a572012-08-22 10:01:24 +020026
Thierry Redingf6b8a572012-08-22 10:01:24 +020027struct jz4740_pwm_chip {
28 struct pwm_chip chip;
Paul Cercueilc2693512020-03-23 15:24:20 +010029 struct regmap *map;
Thierry Redingf6b8a572012-08-22 10:01:24 +020030};
31
32static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
33{
34 return container_of(chip, struct jz4740_pwm_chip, chip);
35}
36
Paul Cercueila2005fc2020-03-23 15:24:21 +010037static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
38 unsigned int channel)
39{
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */
Paul Cercueil74db7282020-05-27 13:52:25 +020041 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
Paul Cercueila2005fc2020-03-23 15:24:21 +010042
43 device_property_read_u32(jz->chip.dev->parent,
44 "ingenic,pwm-channels-mask",
45 &pwm_channels_mask);
46
47 return !!(pwm_channels_mask & BIT(channel));
48}
49
Thierry Redingf6b8a572012-08-22 10:01:24 +020050static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
51{
Paul Cercueilce1f9ce2020-03-23 15:24:18 +010052 struct jz4740_pwm_chip *jz = to_jz4740(chip);
53 struct clk *clk;
54 char name[16];
55 int err;
56
Paul Cercueila2005fc2020-03-23 15:24:21 +010057 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
Thierry Redingf6b8a572012-08-22 10:01:24 +020058 return -EBUSY;
59
Paul Cercueilce1f9ce2020-03-23 15:24:18 +010060 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
61
62 clk = clk_get(chip->dev, name);
63 if (IS_ERR(clk)) {
64 if (PTR_ERR(clk) != -EPROBE_DEFER)
65 dev_err(chip->dev, "Failed to get clock: %pe", clk);
66
67 return PTR_ERR(clk);
68 }
69
70 err = clk_prepare_enable(clk);
71 if (err < 0) {
72 clk_put(clk);
73 return err;
74 }
75
76 pwm_set_chip_data(pwm, clk);
Thierry Redingf6b8a572012-08-22 10:01:24 +020077
78 return 0;
79}
80
81static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
82{
Paul Cercueilce1f9ce2020-03-23 15:24:18 +010083 struct clk *clk = pwm_get_chip_data(pwm);
Thierry Redingf6b8a572012-08-22 10:01:24 +020084
Paul Cercueilce1f9ce2020-03-23 15:24:18 +010085 clk_disable_unprepare(clk);
86 clk_put(clk);
Thierry Redingf6b8a572012-08-22 10:01:24 +020087}
88
89static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
90{
Paul Cercueilc2693512020-03-23 15:24:20 +010091 struct jz4740_pwm_chip *jz = to_jz4740(chip);
Thierry Redingf6b8a572012-08-22 10:01:24 +020092
Paul Cercueilc2693512020-03-23 15:24:20 +010093 /* Enable PWM output */
94 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
95 TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN);
96
97 /* Start counter */
98 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
Thierry Redingf6b8a572012-08-22 10:01:24 +020099
100 return 0;
101}
102
103static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
104{
Paul Cercueilc2693512020-03-23 15:24:20 +0100105 struct jz4740_pwm_chip *jz = to_jz4740(chip);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200106
Paul Cercueil6580fd12019-06-07 17:44:09 +0200107 /*
108 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
109 * properly return to their init level.
110 */
Paul Cercueilc2693512020-03-23 15:24:20 +0100111 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
112 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
Paul Cercueil6580fd12019-06-07 17:44:09 +0200113
114 /*
115 * Disable PWM output.
Maarten ter Huurnedf56b172018-01-06 17:58:40 +0100116 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
117 * counter is stopped, while in TCU1 mode the order does not matter.
118 */
Paul Cercueilc2693512020-03-23 15:24:20 +0100119 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
120 TCU_TCSR_PWM_EN, 0);
Maarten ter Huurnedf56b172018-01-06 17:58:40 +0100121
122 /* Stop counter */
Paul Cercueilc2693512020-03-23 15:24:20 +0100123 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
Thierry Redingf6b8a572012-08-22 10:01:24 +0200124}
125
Paul Cercueil1ac99c52019-06-07 17:44:07 +0200126static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
Uwe Kleine-König71523d12019-08-24 17:37:07 +0200127 const struct pwm_state *state)
Thierry Redingf6b8a572012-08-22 10:01:24 +0200128{
129 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
Paul Cercueil485b56f2020-03-23 15:24:19 +0100130 unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
131 struct clk *clk = pwm_get_chip_data(pwm);
132 unsigned long period, duty;
Paul Cercueil485b56f2020-03-23 15:24:19 +0100133 long rate;
Paul Cercueilce1f9ce2020-03-23 15:24:18 +0100134 int err;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200135
Paul Cercueil485b56f2020-03-23 15:24:19 +0100136 /*
137 * Limit the clock to a maximum rate that still gives us a period value
138 * which fits in 16 bits.
139 */
140 do_div(tmp, state->period);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200141
Paul Cercueil485b56f2020-03-23 15:24:19 +0100142 /*
143 * /!\ IMPORTANT NOTE:
144 * -------------------
145 * This code relies on the fact that clk_round_rate() will always round
146 * down, which is not a valid assumption given by the clk API, but only
147 * happens to be true with the clk drivers used for Ingenic SoCs.
148 *
149 * Right now, there is no alternative as the clk API does not have a
150 * round-down function (and won't have one for a while), but if it ever
151 * comes to light, a round-down function should be used instead.
152 */
153 rate = clk_round_rate(clk, tmp);
154 if (rate < 0) {
155 dev_err(chip->dev, "Unable to round rate: %ld", rate);
156 return rate;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200157 }
158
Paul Cercueil485b56f2020-03-23 15:24:19 +0100159 /* Calculate period value */
160 tmp = (unsigned long long)rate * state->period;
161 do_div(tmp, NSEC_PER_SEC);
Paul Cercueil9017dc42020-05-27 13:52:23 +0200162 period = tmp;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200163
Paul Cercueil485b56f2020-03-23 15:24:19 +0100164 /* Calculate duty value */
Paul Cercueil9017dc42020-05-27 13:52:23 +0200165 tmp = (unsigned long long)rate * state->duty_cycle;
166 do_div(tmp, NSEC_PER_SEC);
Paul Cercueila020f222020-05-27 13:52:24 +0200167 duty = tmp;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200168
169 if (duty >= period)
170 duty = period - 1;
171
Paul Cercueil1ac99c52019-06-07 17:44:07 +0200172 jz4740_pwm_disable(chip, pwm);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200173
Paul Cercueilce1f9ce2020-03-23 15:24:18 +0100174 err = clk_set_rate(clk, rate);
175 if (err) {
176 dev_err(chip->dev, "Unable to set rate: %d", err);
177 return err;
178 }
179
Paul Cercueilc2693512020-03-23 15:24:20 +0100180 /* Reset counter to 0 */
181 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200182
Paul Cercueilc2693512020-03-23 15:24:20 +0100183 /* Set duty */
184 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200185
Paul Cercueilc2693512020-03-23 15:24:20 +0100186 /* Set period */
187 regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period);
188
189 /* Set abrupt shutdown */
190 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
191 TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
192
Paul Cercueila020f222020-05-27 13:52:24 +0200193 /*
194 * Set polarity.
195 *
196 * The PWM starts in inactive state until the internal timer reaches the
197 * duty value, then becomes active until the timer reaches the period
198 * value. In theory, we should then use (period - duty) as the real duty
199 * value, as a high duty value would otherwise result in the PWM pin
200 * being inactive most of the time.
201 *
202 * Here, we don't do that, and instead invert the polarity of the PWM
203 * when it is active. This trick makes the PWM start with its active
204 * state instead of its inactive state.
205 */
206 if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
Paul Cercueilc2693512020-03-23 15:24:20 +0100207 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
208 TCU_TCSR_PWM_INITL_HIGH, 0);
Paul Cercueila020f222020-05-27 13:52:24 +0200209 else
Paul Cercueilc2693512020-03-23 15:24:20 +0100210 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
211 TCU_TCSR_PWM_INITL_HIGH,
212 TCU_TCSR_PWM_INITL_HIGH);
Paul Cercueil174dcc82018-01-06 17:58:41 +0100213
Paul Cercueil1ac99c52019-06-07 17:44:07 +0200214 if (state->enabled)
215 jz4740_pwm_enable(chip, pwm);
216
Paul Cercueil174dcc82018-01-06 17:58:41 +0100217 return 0;
218}
219
Thierry Redingf6b8a572012-08-22 10:01:24 +0200220static const struct pwm_ops jz4740_pwm_ops = {
221 .request = jz4740_pwm_request,
222 .free = jz4740_pwm_free,
Paul Cercueil1ac99c52019-06-07 17:44:07 +0200223 .apply = jz4740_pwm_apply,
Thierry Redingf6b8a572012-08-22 10:01:24 +0200224 .owner = THIS_MODULE,
225};
226
Bill Pemberton3e9fe832012-11-19 13:23:14 -0500227static int jz4740_pwm_probe(struct platform_device *pdev)
Thierry Redingf6b8a572012-08-22 10:01:24 +0200228{
Paul Cercueilc2693512020-03-23 15:24:20 +0100229 struct device *dev = &pdev->dev;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200230 struct jz4740_pwm_chip *jz4740;
Paul Cercueil74db7282020-05-27 13:52:25 +0200231 const struct soc_info *info;
232
233 info = device_get_match_data(dev);
234 if (!info)
235 return -EINVAL;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200236
Paul Cercueilc2693512020-03-23 15:24:20 +0100237 jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200238 if (!jz4740)
239 return -ENOMEM;
240
Paul Cercueilc2693512020-03-23 15:24:20 +0100241 jz4740->map = device_node_to_regmap(dev->parent->of_node);
242 if (IS_ERR(jz4740->map)) {
243 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map));
244 return PTR_ERR(jz4740->map);
245 }
246
247 jz4740->chip.dev = dev;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200248 jz4740->chip.ops = &jz4740_pwm_ops;
Paul Cercueil74db7282020-05-27 13:52:25 +0200249 jz4740->chip.npwm = info->num_pwms;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200250 jz4740->chip.base = -1;
Paul Cercueilcc201732018-01-06 17:58:42 +0100251 jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
252 jz4740->chip.of_pwm_n_cells = 3;
Thierry Redingf6b8a572012-08-22 10:01:24 +0200253
Thierry Redingf6b8a572012-08-22 10:01:24 +0200254 platform_set_drvdata(pdev, jz4740);
255
Lars-Peter Clausen0dc11352013-12-07 18:13:16 +0100256 return pwmchip_add(&jz4740->chip);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200257}
258
Bill Pemberton77f37912012-11-19 13:26:09 -0500259static int jz4740_pwm_remove(struct platform_device *pdev)
Thierry Redingf6b8a572012-08-22 10:01:24 +0200260{
261 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200262
Lars-Peter Clausen0dc11352013-12-07 18:13:16 +0100263 return pwmchip_remove(&jz4740->chip);
Thierry Redingf6b8a572012-08-22 10:01:24 +0200264}
265
Paul Cercueil74db7282020-05-27 13:52:25 +0200266static const struct soc_info __maybe_unused jz4740_soc_info = {
267 .num_pwms = 8,
268};
269
270static const struct soc_info __maybe_unused jz4725b_soc_info = {
271 .num_pwms = 6,
272};
273
Paul Cercueilcc201732018-01-06 17:58:42 +0100274#ifdef CONFIG_OF
275static const struct of_device_id jz4740_pwm_dt_ids[] = {
Paul Cercueil74db7282020-05-27 13:52:25 +0200276 { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
277 { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
Paul Cercueilcc201732018-01-06 17:58:42 +0100278 {},
279};
280MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
281#endif
282
Thierry Redingf6b8a572012-08-22 10:01:24 +0200283static struct platform_driver jz4740_pwm_driver = {
284 .driver = {
285 .name = "jz4740-pwm",
Paul Cercueilcc201732018-01-06 17:58:42 +0100286 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
Thierry Redingf6b8a572012-08-22 10:01:24 +0200287 },
288 .probe = jz4740_pwm_probe,
Bill Pembertonfd109112012-11-19 13:21:28 -0500289 .remove = jz4740_pwm_remove,
Thierry Redingf6b8a572012-08-22 10:01:24 +0200290};
291module_platform_driver(jz4740_pwm_driver);
292
293MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
294MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
295MODULE_ALIAS("platform:jz4740-pwm");
296MODULE_LICENSE("GPL");