Thomas Gleixner | a912e80 | 2019-05-27 08:55:00 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> |
| 4 | * JZ4740 platform PWM support |
Uwe Kleine-König | 3b442c6 | 2019-07-30 14:32:29 +0200 | [diff] [blame] | 5 | * |
| 6 | * Limitations: |
| 7 | * - The .apply callback doesn't complete the currently running period before |
| 8 | * reconfiguring the hardware. |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <linux/clk.h> |
| 12 | #include <linux/err.h> |
| 13 | #include <linux/gpio.h> |
| 14 | #include <linux/kernel.h> |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 15 | #include <linux/mfd/ingenic-tcu.h> |
| 16 | #include <linux/mfd/syscon.h> |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 17 | #include <linux/module.h> |
Paul Cercueil | cc20173 | 2018-01-06 17:58:42 +0100 | [diff] [blame] | 18 | #include <linux/of_device.h> |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/pwm.h> |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 21 | #include <linux/regmap.h> |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 22 | |
Paul Cercueil | 74db728 | 2020-05-27 13:52:25 +0200 | [diff] [blame] | 23 | struct soc_info { |
| 24 | unsigned int num_pwms; |
| 25 | }; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 26 | |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 27 | struct jz4740_pwm_chip { |
| 28 | struct pwm_chip chip; |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 29 | struct regmap *map; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 30 | }; |
| 31 | |
| 32 | static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) |
| 33 | { |
| 34 | return container_of(chip, struct jz4740_pwm_chip, chip); |
| 35 | } |
| 36 | |
Paul Cercueil | a2005fc | 2020-03-23 15:24:21 +0100 | [diff] [blame] | 37 | static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz, |
| 38 | unsigned int channel) |
| 39 | { |
| 40 | /* Enable all TCU channels for PWM use by default except channels 0/1 */ |
Paul Cercueil | 74db728 | 2020-05-27 13:52:25 +0200 | [diff] [blame] | 41 | u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2); |
Paul Cercueil | a2005fc | 2020-03-23 15:24:21 +0100 | [diff] [blame] | 42 | |
| 43 | device_property_read_u32(jz->chip.dev->parent, |
| 44 | "ingenic,pwm-channels-mask", |
| 45 | &pwm_channels_mask); |
| 46 | |
| 47 | return !!(pwm_channels_mask & BIT(channel)); |
| 48 | } |
| 49 | |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 50 | static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
| 51 | { |
Paul Cercueil | ce1f9ce | 2020-03-23 15:24:18 +0100 | [diff] [blame] | 52 | struct jz4740_pwm_chip *jz = to_jz4740(chip); |
| 53 | struct clk *clk; |
| 54 | char name[16]; |
| 55 | int err; |
| 56 | |
Paul Cercueil | a2005fc | 2020-03-23 15:24:21 +0100 | [diff] [blame] | 57 | if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm)) |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 58 | return -EBUSY; |
| 59 | |
Paul Cercueil | ce1f9ce | 2020-03-23 15:24:18 +0100 | [diff] [blame] | 60 | snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); |
| 61 | |
| 62 | clk = clk_get(chip->dev, name); |
| 63 | if (IS_ERR(clk)) { |
| 64 | if (PTR_ERR(clk) != -EPROBE_DEFER) |
| 65 | dev_err(chip->dev, "Failed to get clock: %pe", clk); |
| 66 | |
| 67 | return PTR_ERR(clk); |
| 68 | } |
| 69 | |
| 70 | err = clk_prepare_enable(clk); |
| 71 | if (err < 0) { |
| 72 | clk_put(clk); |
| 73 | return err; |
| 74 | } |
| 75 | |
| 76 | pwm_set_chip_data(pwm, clk); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
| 82 | { |
Paul Cercueil | ce1f9ce | 2020-03-23 15:24:18 +0100 | [diff] [blame] | 83 | struct clk *clk = pwm_get_chip_data(pwm); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 84 | |
Paul Cercueil | ce1f9ce | 2020-03-23 15:24:18 +0100 | [diff] [blame] | 85 | clk_disable_unprepare(clk); |
| 86 | clk_put(clk); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 90 | { |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 91 | struct jz4740_pwm_chip *jz = to_jz4740(chip); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 92 | |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 93 | /* Enable PWM output */ |
| 94 | regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), |
| 95 | TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN); |
| 96 | |
| 97 | /* Start counter */ |
| 98 | regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 99 | |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 104 | { |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 105 | struct jz4740_pwm_chip *jz = to_jz4740(chip); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 106 | |
Paul Cercueil | 6580fd1 | 2019-06-07 17:44:09 +0200 | [diff] [blame] | 107 | /* |
| 108 | * Set duty > period. This trick allows the TCU channels in TCU2 mode to |
| 109 | * properly return to their init level. |
| 110 | */ |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 111 | regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff); |
| 112 | regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0); |
Paul Cercueil | 6580fd1 | 2019-06-07 17:44:09 +0200 | [diff] [blame] | 113 | |
| 114 | /* |
| 115 | * Disable PWM output. |
Maarten ter Huurne | df56b17 | 2018-01-06 17:58:40 +0100 | [diff] [blame] | 116 | * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the |
| 117 | * counter is stopped, while in TCU1 mode the order does not matter. |
| 118 | */ |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 119 | regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), |
| 120 | TCU_TCSR_PWM_EN, 0); |
Maarten ter Huurne | df56b17 | 2018-01-06 17:58:40 +0100 | [diff] [blame] | 121 | |
| 122 | /* Stop counter */ |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 123 | regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 124 | } |
| 125 | |
Paul Cercueil | 1ac99c5 | 2019-06-07 17:44:07 +0200 | [diff] [blame] | 126 | static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
Uwe Kleine-König | 71523d1 | 2019-08-24 17:37:07 +0200 | [diff] [blame] | 127 | const struct pwm_state *state) |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 128 | { |
| 129 | struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); |
Paul Cercueil | 485b56f | 2020-03-23 15:24:19 +0100 | [diff] [blame] | 130 | unsigned long long tmp = 0xffffull * NSEC_PER_SEC; |
| 131 | struct clk *clk = pwm_get_chip_data(pwm); |
| 132 | unsigned long period, duty; |
Paul Cercueil | 485b56f | 2020-03-23 15:24:19 +0100 | [diff] [blame] | 133 | long rate; |
Paul Cercueil | ce1f9ce | 2020-03-23 15:24:18 +0100 | [diff] [blame] | 134 | int err; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 135 | |
Paul Cercueil | 485b56f | 2020-03-23 15:24:19 +0100 | [diff] [blame] | 136 | /* |
| 137 | * Limit the clock to a maximum rate that still gives us a period value |
| 138 | * which fits in 16 bits. |
| 139 | */ |
| 140 | do_div(tmp, state->period); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 141 | |
Paul Cercueil | 485b56f | 2020-03-23 15:24:19 +0100 | [diff] [blame] | 142 | /* |
| 143 | * /!\ IMPORTANT NOTE: |
| 144 | * ------------------- |
| 145 | * This code relies on the fact that clk_round_rate() will always round |
| 146 | * down, which is not a valid assumption given by the clk API, but only |
| 147 | * happens to be true with the clk drivers used for Ingenic SoCs. |
| 148 | * |
| 149 | * Right now, there is no alternative as the clk API does not have a |
| 150 | * round-down function (and won't have one for a while), but if it ever |
| 151 | * comes to light, a round-down function should be used instead. |
| 152 | */ |
| 153 | rate = clk_round_rate(clk, tmp); |
| 154 | if (rate < 0) { |
| 155 | dev_err(chip->dev, "Unable to round rate: %ld", rate); |
| 156 | return rate; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 157 | } |
| 158 | |
Paul Cercueil | 485b56f | 2020-03-23 15:24:19 +0100 | [diff] [blame] | 159 | /* Calculate period value */ |
| 160 | tmp = (unsigned long long)rate * state->period; |
| 161 | do_div(tmp, NSEC_PER_SEC); |
Paul Cercueil | 9017dc4 | 2020-05-27 13:52:23 +0200 | [diff] [blame] | 162 | period = tmp; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 163 | |
Paul Cercueil | 485b56f | 2020-03-23 15:24:19 +0100 | [diff] [blame] | 164 | /* Calculate duty value */ |
Paul Cercueil | 9017dc4 | 2020-05-27 13:52:23 +0200 | [diff] [blame] | 165 | tmp = (unsigned long long)rate * state->duty_cycle; |
| 166 | do_div(tmp, NSEC_PER_SEC); |
Paul Cercueil | a020f22 | 2020-05-27 13:52:24 +0200 | [diff] [blame] | 167 | duty = tmp; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 168 | |
| 169 | if (duty >= period) |
| 170 | duty = period - 1; |
| 171 | |
Paul Cercueil | 1ac99c5 | 2019-06-07 17:44:07 +0200 | [diff] [blame] | 172 | jz4740_pwm_disable(chip, pwm); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 173 | |
Paul Cercueil | ce1f9ce | 2020-03-23 15:24:18 +0100 | [diff] [blame] | 174 | err = clk_set_rate(clk, rate); |
| 175 | if (err) { |
| 176 | dev_err(chip->dev, "Unable to set rate: %d", err); |
| 177 | return err; |
| 178 | } |
| 179 | |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 180 | /* Reset counter to 0 */ |
| 181 | regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 182 | |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 183 | /* Set duty */ |
| 184 | regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 185 | |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 186 | /* Set period */ |
| 187 | regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period); |
| 188 | |
| 189 | /* Set abrupt shutdown */ |
| 190 | regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), |
| 191 | TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD); |
| 192 | |
Paul Cercueil | a020f22 | 2020-05-27 13:52:24 +0200 | [diff] [blame] | 193 | /* |
| 194 | * Set polarity. |
| 195 | * |
| 196 | * The PWM starts in inactive state until the internal timer reaches the |
| 197 | * duty value, then becomes active until the timer reaches the period |
| 198 | * value. In theory, we should then use (period - duty) as the real duty |
| 199 | * value, as a high duty value would otherwise result in the PWM pin |
| 200 | * being inactive most of the time. |
| 201 | * |
| 202 | * Here, we don't do that, and instead invert the polarity of the PWM |
| 203 | * when it is active. This trick makes the PWM start with its active |
| 204 | * state instead of its inactive state. |
| 205 | */ |
| 206 | if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled) |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 207 | regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), |
| 208 | TCU_TCSR_PWM_INITL_HIGH, 0); |
Paul Cercueil | a020f22 | 2020-05-27 13:52:24 +0200 | [diff] [blame] | 209 | else |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 210 | regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), |
| 211 | TCU_TCSR_PWM_INITL_HIGH, |
| 212 | TCU_TCSR_PWM_INITL_HIGH); |
Paul Cercueil | 174dcc8 | 2018-01-06 17:58:41 +0100 | [diff] [blame] | 213 | |
Paul Cercueil | 1ac99c5 | 2019-06-07 17:44:07 +0200 | [diff] [blame] | 214 | if (state->enabled) |
| 215 | jz4740_pwm_enable(chip, pwm); |
| 216 | |
Paul Cercueil | 174dcc8 | 2018-01-06 17:58:41 +0100 | [diff] [blame] | 217 | return 0; |
| 218 | } |
| 219 | |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 220 | static const struct pwm_ops jz4740_pwm_ops = { |
| 221 | .request = jz4740_pwm_request, |
| 222 | .free = jz4740_pwm_free, |
Paul Cercueil | 1ac99c5 | 2019-06-07 17:44:07 +0200 | [diff] [blame] | 223 | .apply = jz4740_pwm_apply, |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 224 | .owner = THIS_MODULE, |
| 225 | }; |
| 226 | |
Bill Pemberton | 3e9fe83 | 2012-11-19 13:23:14 -0500 | [diff] [blame] | 227 | static int jz4740_pwm_probe(struct platform_device *pdev) |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 228 | { |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 229 | struct device *dev = &pdev->dev; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 230 | struct jz4740_pwm_chip *jz4740; |
Paul Cercueil | 74db728 | 2020-05-27 13:52:25 +0200 | [diff] [blame] | 231 | const struct soc_info *info; |
| 232 | |
| 233 | info = device_get_match_data(dev); |
| 234 | if (!info) |
| 235 | return -EINVAL; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 236 | |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 237 | jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 238 | if (!jz4740) |
| 239 | return -ENOMEM; |
| 240 | |
Paul Cercueil | c269351 | 2020-03-23 15:24:20 +0100 | [diff] [blame] | 241 | jz4740->map = device_node_to_regmap(dev->parent->of_node); |
| 242 | if (IS_ERR(jz4740->map)) { |
| 243 | dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map)); |
| 244 | return PTR_ERR(jz4740->map); |
| 245 | } |
| 246 | |
| 247 | jz4740->chip.dev = dev; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 248 | jz4740->chip.ops = &jz4740_pwm_ops; |
Paul Cercueil | 74db728 | 2020-05-27 13:52:25 +0200 | [diff] [blame] | 249 | jz4740->chip.npwm = info->num_pwms; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 250 | jz4740->chip.base = -1; |
Paul Cercueil | cc20173 | 2018-01-06 17:58:42 +0100 | [diff] [blame] | 251 | jz4740->chip.of_xlate = of_pwm_xlate_with_flags; |
| 252 | jz4740->chip.of_pwm_n_cells = 3; |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 253 | |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 254 | platform_set_drvdata(pdev, jz4740); |
| 255 | |
Lars-Peter Clausen | 0dc1135 | 2013-12-07 18:13:16 +0100 | [diff] [blame] | 256 | return pwmchip_add(&jz4740->chip); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 257 | } |
| 258 | |
Bill Pemberton | 77f3791 | 2012-11-19 13:26:09 -0500 | [diff] [blame] | 259 | static int jz4740_pwm_remove(struct platform_device *pdev) |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 260 | { |
| 261 | struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 262 | |
Lars-Peter Clausen | 0dc1135 | 2013-12-07 18:13:16 +0100 | [diff] [blame] | 263 | return pwmchip_remove(&jz4740->chip); |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 264 | } |
| 265 | |
Paul Cercueil | 74db728 | 2020-05-27 13:52:25 +0200 | [diff] [blame] | 266 | static const struct soc_info __maybe_unused jz4740_soc_info = { |
| 267 | .num_pwms = 8, |
| 268 | }; |
| 269 | |
| 270 | static const struct soc_info __maybe_unused jz4725b_soc_info = { |
| 271 | .num_pwms = 6, |
| 272 | }; |
| 273 | |
Paul Cercueil | cc20173 | 2018-01-06 17:58:42 +0100 | [diff] [blame] | 274 | #ifdef CONFIG_OF |
| 275 | static const struct of_device_id jz4740_pwm_dt_ids[] = { |
Paul Cercueil | 74db728 | 2020-05-27 13:52:25 +0200 | [diff] [blame] | 276 | { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info }, |
| 277 | { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info }, |
Paul Cercueil | cc20173 | 2018-01-06 17:58:42 +0100 | [diff] [blame] | 278 | {}, |
| 279 | }; |
| 280 | MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids); |
| 281 | #endif |
| 282 | |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 283 | static struct platform_driver jz4740_pwm_driver = { |
| 284 | .driver = { |
| 285 | .name = "jz4740-pwm", |
Paul Cercueil | cc20173 | 2018-01-06 17:58:42 +0100 | [diff] [blame] | 286 | .of_match_table = of_match_ptr(jz4740_pwm_dt_ids), |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 287 | }, |
| 288 | .probe = jz4740_pwm_probe, |
Bill Pemberton | fd10911 | 2012-11-19 13:21:28 -0500 | [diff] [blame] | 289 | .remove = jz4740_pwm_remove, |
Thierry Reding | f6b8a57 | 2012-08-22 10:01:24 +0200 | [diff] [blame] | 290 | }; |
| 291 | module_platform_driver(jz4740_pwm_driver); |
| 292 | |
| 293 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |
| 294 | MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver"); |
| 295 | MODULE_ALIAS("platform:jz4740-pwm"); |
| 296 | MODULE_LICENSE("GPL"); |