Dan Williams | 06737cd | 2021-08-02 10:29:49 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* Copyright(c) 2020 Intel Corporation. */ |
| 3 | |
| 4 | #ifndef __CXL_CORE_H__ |
| 5 | #define __CXL_CORE_H__ |
| 6 | |
| 7 | extern const struct device_type cxl_nvdimm_bridge_type; |
| 8 | extern const struct device_type cxl_nvdimm_type; |
Jonathan Cameron | 1ad3f70 | 2023-05-26 10:58:22 +0100 | [diff] [blame] | 9 | extern const struct device_type cxl_pmu_type; |
Dan Williams | 06737cd | 2021-08-02 10:29:49 -0700 | [diff] [blame] | 10 | |
| 11 | extern struct attribute_group cxl_base_attribute_group; |
| 12 | |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 13 | #ifdef CONFIG_CXL_REGION |
| 14 | extern struct device_attribute dev_attr_create_pmem_region; |
Dan Williams | 6e09926 | 2023-02-10 01:05:57 -0800 | [diff] [blame] | 15 | extern struct device_attribute dev_attr_create_ram_region; |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 16 | extern struct device_attribute dev_attr_delete_region; |
Dan Williams | b9686e8 | 2022-06-04 15:49:53 -0700 | [diff] [blame] | 17 | extern struct device_attribute dev_attr_region; |
Dan Williams | 04ad63f | 2022-01-11 08:06:40 -0800 | [diff] [blame] | 18 | extern const struct device_type cxl_pmem_region_type; |
Dan Williams | 09d09e0 | 2023-02-10 01:07:19 -0800 | [diff] [blame] | 19 | extern const struct device_type cxl_dax_region_type; |
Dan Williams | 8d48817 | 2021-06-15 14:00:40 -0700 | [diff] [blame] | 20 | extern const struct device_type cxl_region_type; |
Dan Williams | b9686e8 | 2022-06-04 15:49:53 -0700 | [diff] [blame] | 21 | void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled); |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 22 | #define CXL_REGION_ATTR(x) (&dev_attr_##x.attr) |
Dan Williams | 8d48817 | 2021-06-15 14:00:40 -0700 | [diff] [blame] | 23 | #define CXL_REGION_TYPE(x) (&cxl_region_type) |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 24 | #define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr), |
Dan Williams | 04ad63f | 2022-01-11 08:06:40 -0800 | [diff] [blame] | 25 | #define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type) |
Dan Williams | 09d09e0 | 2023-02-10 01:07:19 -0800 | [diff] [blame] | 26 | #define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type) |
Dan Williams | 8d48817 | 2021-06-15 14:00:40 -0700 | [diff] [blame] | 27 | int cxl_region_init(void); |
| 28 | void cxl_region_exit(void); |
Alison Schofield | f0832a5 | 2023-04-18 10:39:07 -0700 | [diff] [blame] | 29 | int cxl_get_poison_by_endpoint(struct cxl_port *port); |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 30 | #else |
Alison Schofield | f0832a5 | 2023-04-18 10:39:07 -0700 | [diff] [blame] | 31 | static inline int cxl_get_poison_by_endpoint(struct cxl_port *port) |
| 32 | { |
| 33 | return 0; |
| 34 | } |
Dan Williams | b9686e8 | 2022-06-04 15:49:53 -0700 | [diff] [blame] | 35 | static inline void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled) |
| 36 | { |
| 37 | } |
Dan Williams | 8d48817 | 2021-06-15 14:00:40 -0700 | [diff] [blame] | 38 | static inline int cxl_region_init(void) |
| 39 | { |
| 40 | return 0; |
| 41 | } |
| 42 | static inline void cxl_region_exit(void) |
| 43 | { |
| 44 | } |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 45 | #define CXL_REGION_ATTR(x) NULL |
Dan Williams | 8d48817 | 2021-06-15 14:00:40 -0700 | [diff] [blame] | 46 | #define CXL_REGION_TYPE(x) NULL |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 47 | #define SET_CXL_REGION_ATTR(x) |
Dan Williams | 04ad63f | 2022-01-11 08:06:40 -0800 | [diff] [blame] | 48 | #define CXL_PMEM_REGION_TYPE(x) NULL |
Dan Williams | 09d09e0 | 2023-02-10 01:07:19 -0800 | [diff] [blame] | 49 | #define CXL_DAX_REGION_TYPE(x) NULL |
Ben Widawsky | 779dd20 | 2021-06-08 10:28:34 -0700 | [diff] [blame] | 50 | #endif |
| 51 | |
Dan Williams | 4faf31b | 2021-09-08 22:12:32 -0700 | [diff] [blame] | 52 | struct cxl_send_command; |
| 53 | struct cxl_mem_query_commands; |
| 54 | int cxl_query_cmd(struct cxl_memdev *cxlmd, |
| 55 | struct cxl_mem_query_commands __user *q); |
| 56 | int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s); |
Dan Williams | d17d054 | 2022-02-01 12:24:30 -0800 | [diff] [blame] | 57 | void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, |
| 58 | resource_size_t length); |
Dan Williams | 4faf31b | 2021-09-08 22:12:32 -0700 | [diff] [blame] | 59 | |
Dan Williams | 9b99ecf | 2022-07-10 09:57:28 -0700 | [diff] [blame] | 60 | struct dentry *cxl_debugfs_create_dir(const char *dir); |
Dan Williams | cf88042 | 2022-05-23 18:02:30 -0700 | [diff] [blame] | 61 | int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, |
| 62 | enum cxl_decoder_mode mode); |
| 63 | int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size); |
| 64 | int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); |
| 65 | resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled); |
| 66 | resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled); |
Robert Richter | eb4663b | 2023-06-25 11:35:20 -0700 | [diff] [blame] | 67 | |
| 68 | enum cxl_rcrb { |
| 69 | CXL_RCRB_DOWNSTREAM, |
| 70 | CXL_RCRB_UPSTREAM, |
| 71 | }; |
Dan Williams | 0619337 | 2023-06-22 15:54:59 -0500 | [diff] [blame] | 72 | struct cxl_rcrb_info; |
| 73 | resource_size_t __rcrb_to_component(struct device *dev, |
| 74 | struct cxl_rcrb_info *ri, |
Robert Richter | eb4663b | 2023-06-25 11:35:20 -0700 | [diff] [blame] | 75 | enum cxl_rcrb which); |
Robert Richter | f05fd10 | 2023-10-27 15:08:06 -0700 | [diff] [blame] | 76 | u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb); |
Robert Richter | eb4663b | 2023-06-25 11:35:20 -0700 | [diff] [blame] | 77 | |
Dan Williams | b9686e8 | 2022-06-04 15:49:53 -0700 | [diff] [blame] | 78 | extern struct rw_semaphore cxl_dpa_rwsem; |
Dan Williams | 3398183 | 2023-10-04 18:35:01 -0700 | [diff] [blame] | 79 | extern struct rw_semaphore cxl_region_rwsem; |
Dan Williams | cf88042 | 2022-05-23 18:02:30 -0700 | [diff] [blame] | 80 | |
Ben Widawsky | 3d135db | 2021-08-02 10:30:05 -0700 | [diff] [blame] | 81 | int cxl_memdev_init(void); |
| 82 | void cxl_memdev_exit(void); |
Dan Williams | 4faf31b | 2021-09-08 22:12:32 -0700 | [diff] [blame] | 83 | void cxl_mbox_init(void); |
Ben Widawsky | 3d135db | 2021-08-02 10:30:05 -0700 | [diff] [blame] | 84 | |
Alison Schofield | ddf49d5 | 2023-04-18 10:39:05 -0700 | [diff] [blame] | 85 | enum cxl_poison_trace_type { |
| 86 | CXL_POISON_TRACE_LIST, |
Alison Schofield | 98b6926 | 2023-04-18 20:26:28 -0700 | [diff] [blame] | 87 | CXL_POISON_TRACE_INJECT, |
| 88 | CXL_POISON_TRACE_CLEAR, |
Alison Schofield | ddf49d5 | 2023-04-18 10:39:05 -0700 | [diff] [blame] | 89 | }; |
| 90 | |
Dan Williams | 06737cd | 2021-08-02 10:29:49 -0700 | [diff] [blame] | 91 | #endif /* __CXL_CORE_H__ */ |