blob: 86d7ba23235e3bdefb567e3dc3cb656b4f9593c0 [file] [log] [blame]
Dan Williams06737cd2021-08-02 10:29:49 -07001/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2020 Intel Corporation. */
3
4#ifndef __CXL_CORE_H__
5#define __CXL_CORE_H__
6
7extern const struct device_type cxl_nvdimm_bridge_type;
8extern const struct device_type cxl_nvdimm_type;
Jonathan Cameron1ad3f702023-05-26 10:58:22 +01009extern const struct device_type cxl_pmu_type;
Dan Williams06737cd2021-08-02 10:29:49 -070010
11extern struct attribute_group cxl_base_attribute_group;
12
Ben Widawsky779dd202021-06-08 10:28:34 -070013#ifdef CONFIG_CXL_REGION
14extern struct device_attribute dev_attr_create_pmem_region;
Dan Williams6e099262023-02-10 01:05:57 -080015extern struct device_attribute dev_attr_create_ram_region;
Ben Widawsky779dd202021-06-08 10:28:34 -070016extern struct device_attribute dev_attr_delete_region;
Dan Williamsb9686e82022-06-04 15:49:53 -070017extern struct device_attribute dev_attr_region;
Dan Williams04ad63f2022-01-11 08:06:40 -080018extern const struct device_type cxl_pmem_region_type;
Dan Williams09d09e02023-02-10 01:07:19 -080019extern const struct device_type cxl_dax_region_type;
Dan Williams8d488172021-06-15 14:00:40 -070020extern const struct device_type cxl_region_type;
Dan Williamsb9686e82022-06-04 15:49:53 -070021void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
Ben Widawsky779dd202021-06-08 10:28:34 -070022#define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
Dan Williams8d488172021-06-15 14:00:40 -070023#define CXL_REGION_TYPE(x) (&cxl_region_type)
Ben Widawsky779dd202021-06-08 10:28:34 -070024#define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
Dan Williams04ad63f2022-01-11 08:06:40 -080025#define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
Dan Williams09d09e02023-02-10 01:07:19 -080026#define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)
Dan Williams8d488172021-06-15 14:00:40 -070027int cxl_region_init(void);
28void cxl_region_exit(void);
Alison Schofieldf0832a52023-04-18 10:39:07 -070029int cxl_get_poison_by_endpoint(struct cxl_port *port);
Ben Widawsky779dd202021-06-08 10:28:34 -070030#else
Alison Schofieldf0832a52023-04-18 10:39:07 -070031static inline int cxl_get_poison_by_endpoint(struct cxl_port *port)
32{
33 return 0;
34}
Dan Williamsb9686e82022-06-04 15:49:53 -070035static inline void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
36{
37}
Dan Williams8d488172021-06-15 14:00:40 -070038static inline int cxl_region_init(void)
39{
40 return 0;
41}
42static inline void cxl_region_exit(void)
43{
44}
Ben Widawsky779dd202021-06-08 10:28:34 -070045#define CXL_REGION_ATTR(x) NULL
Dan Williams8d488172021-06-15 14:00:40 -070046#define CXL_REGION_TYPE(x) NULL
Ben Widawsky779dd202021-06-08 10:28:34 -070047#define SET_CXL_REGION_ATTR(x)
Dan Williams04ad63f2022-01-11 08:06:40 -080048#define CXL_PMEM_REGION_TYPE(x) NULL
Dan Williams09d09e02023-02-10 01:07:19 -080049#define CXL_DAX_REGION_TYPE(x) NULL
Ben Widawsky779dd202021-06-08 10:28:34 -070050#endif
51
Dan Williams4faf31b2021-09-08 22:12:32 -070052struct cxl_send_command;
53struct cxl_mem_query_commands;
54int cxl_query_cmd(struct cxl_memdev *cxlmd,
55 struct cxl_mem_query_commands __user *q);
56int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s);
Dan Williamsd17d0542022-02-01 12:24:30 -080057void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
58 resource_size_t length);
Dan Williams4faf31b2021-09-08 22:12:32 -070059
Dan Williams9b99ecf2022-07-10 09:57:28 -070060struct dentry *cxl_debugfs_create_dir(const char *dir);
Dan Williamscf880422022-05-23 18:02:30 -070061int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
62 enum cxl_decoder_mode mode);
63int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size);
64int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
65resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
66resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled);
Robert Richtereb4663b2023-06-25 11:35:20 -070067
68enum cxl_rcrb {
69 CXL_RCRB_DOWNSTREAM,
70 CXL_RCRB_UPSTREAM,
71};
Dan Williams06193372023-06-22 15:54:59 -050072struct cxl_rcrb_info;
73resource_size_t __rcrb_to_component(struct device *dev,
74 struct cxl_rcrb_info *ri,
Robert Richtereb4663b2023-06-25 11:35:20 -070075 enum cxl_rcrb which);
Robert Richterf05fd102023-10-27 15:08:06 -070076u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
Robert Richtereb4663b2023-06-25 11:35:20 -070077
Dan Williamsb9686e82022-06-04 15:49:53 -070078extern struct rw_semaphore cxl_dpa_rwsem;
Dan Williams33981832023-10-04 18:35:01 -070079extern struct rw_semaphore cxl_region_rwsem;
Dan Williamscf880422022-05-23 18:02:30 -070080
Ben Widawsky3d135db2021-08-02 10:30:05 -070081int cxl_memdev_init(void);
82void cxl_memdev_exit(void);
Dan Williams4faf31b2021-09-08 22:12:32 -070083void cxl_mbox_init(void);
Ben Widawsky3d135db2021-08-02 10:30:05 -070084
Alison Schofieldddf49d52023-04-18 10:39:05 -070085enum cxl_poison_trace_type {
86 CXL_POISON_TRACE_LIST,
Alison Schofield98b69262023-04-18 20:26:28 -070087 CXL_POISON_TRACE_INJECT,
88 CXL_POISON_TRACE_CLEAR,
Alison Schofieldddf49d52023-04-18 10:39:05 -070089};
90
Dan Williams06737cd2021-08-02 10:29:49 -070091#endif /* __CXL_CORE_H__ */