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Shuming Fan6ad73a22022-11-08 17:27:27 +08001// SPDX-License-Identifier: GPL-2.0-only
2//
3// rt1318-sdw.c -- rt1318 SDCA ALSA SoC amplifier audio driver
4//
5// Copyright(c) 2022 Realtek Semiconductor Corp.
6//
7//
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/pm_runtime.h>
11#include <linux/mod_devicetable.h>
12#include <linux/module.h>
13#include <linux/regmap.h>
14#include <linux/dmi.h>
15#include <linux/firmware.h>
16#include <sound/core.h>
17#include <sound/pcm.h>
18#include <sound/pcm_params.h>
19#include <sound/soc-dapm.h>
20#include <sound/initval.h>
21#include "rt1318-sdw.h"
22
23static const struct reg_sequence rt1318_blind_write[] = {
24 { 0xc001, 0x43 },
25 { 0xc003, 0xa2 },
26 { 0xc004, 0x44 },
27 { 0xc005, 0x44 },
28 { 0xc006, 0x33 },
29 { 0xc007, 0x64 },
30 { 0xc320, 0x20 },
31 { 0xf203, 0x18 },
32 { 0xf211, 0x00 },
33 { 0xf212, 0x26 },
34 { 0xf20d, 0x17 },
35 { 0xf214, 0x06 },
36 { 0xf20e, 0x00 },
37 { 0xf223, 0x7f },
38 { 0xf224, 0xdb },
39 { 0xf225, 0xee },
40 { 0xf226, 0x3f },
41 { 0xf227, 0x0f },
42 { 0xf21a, 0x78 },
43 { 0xf242, 0x3c },
44 { 0xc321, 0x0b },
45 { 0xc200, 0xd8 },
46 { 0xc201, 0x27 },
47 { 0xc202, 0x0f },
48 { 0xf800, 0x20 },
49 { 0xdf00, 0x10 },
50 { 0xdf5f, 0x01 },
51 { 0xdf60, 0xa7 },
52 { 0xc400, 0x0e },
53 { 0xc401, 0x43 },
54 { 0xc402, 0xe0 },
55 { 0xc403, 0x00 },
56 { 0xc404, 0x4c },
57 { 0xc407, 0x02 },
58 { 0xc408, 0x3f },
59 { 0xc300, 0x01 },
60 { 0xc206, 0x78 },
61 { 0xc203, 0x84 },
62 { 0xc120, 0xc0 },
63 { 0xc121, 0x03 },
64 { 0xe000, 0x88 },
65 { 0xc321, 0x09 },
66 { 0xc322, 0x01 },
67 { 0xe706, 0x0f },
68 { 0xe707, 0x30 },
69 { 0xe806, 0x0f },
70 { 0xe807, 0x30 },
71 { 0xed00, 0xb0 },
72 { 0xce04, 0x02 },
73 { 0xce05, 0x63 },
74 { 0xce06, 0x68 },
75 { 0xce07, 0x07 },
76 { 0xcf04, 0x02 },
77 { 0xcf05, 0x63 },
78 { 0xcf06, 0x68 },
79 { 0xcf07, 0x07 },
80 { 0xce60, 0xe3 },
81 { 0xc130, 0x51 },
82 { 0xf102, 0x00 },
83 { 0xf103, 0x00 },
84 { 0xf104, 0xf5 },
85 { 0xf105, 0x06 },
86 { 0xf109, 0x9b },
87 { 0xf10a, 0x0b },
88 { 0xf10b, 0x4c },
89 { 0xf10b, 0x5c },
90 { 0xf102, 0x00 },
91 { 0xf103, 0x00 },
92 { 0xf104, 0xf5 },
93 { 0xf105, 0x0b },
94 { 0xf109, 0x03 },
95 { 0xf10a, 0x0b },
96 { 0xf10b, 0x4c },
97 { 0xf10b, 0x5c },
98 { 0xf102, 0x00 },
99 { 0xf103, 0x00 },
100 { 0xf104, 0xf5 },
101 { 0xf105, 0x0c },
102 { 0xf109, 0x7f },
103 { 0xf10a, 0x0b },
104 { 0xf10b, 0x4c },
105 { 0xf10b, 0x5c },
106
107 { 0xe604, 0x00 },
108 { 0xdb00, 0x0c },
109 { 0xdd00, 0x0c },
110 { 0xdc19, 0x00 },
111 { 0xdc1a, 0xff },
112 { 0xdc1b, 0xff },
113 { 0xdc1c, 0xff },
114 { 0xdc1d, 0x00 },
115 { 0xdc1e, 0x00 },
116 { 0xdc1f, 0x00 },
117 { 0xdc20, 0xff },
118 { 0xde19, 0x00 },
119 { 0xde1a, 0xff },
120 { 0xde1b, 0xff },
121 { 0xde1c, 0xff },
122 { 0xde1d, 0x00 },
123 { 0xde1e, 0x00 },
124 { 0xde1f, 0x00 },
125 { 0xde20, 0xff },
126 { 0xdb32, 0x00 },
127 { 0xdd32, 0x00 },
128 { 0xdb33, 0x0a },
129 { 0xdd33, 0x0a },
130 { 0xdb34, 0x1a },
131 { 0xdd34, 0x1a },
132 { 0xdb17, 0xef },
133 { 0xdd17, 0xef },
134 { 0xdba7, 0x00 },
135 { 0xdba8, 0x64 },
136 { 0xdda7, 0x00 },
137 { 0xdda8, 0x64 },
138 { 0xdb19, 0x40 },
139 { 0xdd19, 0x40 },
140 { 0xdb00, 0x4c },
141 { 0xdb01, 0x79 },
142 { 0xdd01, 0x79 },
143 { 0xdb04, 0x05 },
144 { 0xdb05, 0x03 },
145 { 0xdd04, 0x05 },
146 { 0xdd05, 0x03 },
147 { 0xdbbb, 0x09 },
148 { 0xdbbc, 0x30 },
149 { 0xdbbd, 0xf0 },
150 { 0xdbbe, 0xf1 },
151 { 0xddbb, 0x09 },
152 { 0xddbc, 0x30 },
153 { 0xddbd, 0xf0 },
154 { 0xddbe, 0xf1 },
155 { 0xdb01, 0x79 },
156 { 0xdd01, 0x79 },
157 { 0xdc52, 0xef },
158 { 0xde52, 0xef },
159 { 0x2f55, 0x22 },
160};
161
162static const struct reg_default rt1318_reg_defaults[] = {
163 { 0x3000, 0x00 },
164 { 0x3004, 0x01 },
165 { 0x3005, 0x23 },
166 { 0x3202, 0x00 },
167 { 0x3203, 0x01 },
168 { 0x3206, 0x00 },
169 { 0xc000, 0x00 },
170 { 0xc001, 0x43 },
171 { 0xc003, 0x22 },
172 { 0xc004, 0x44 },
173 { 0xc005, 0x44 },
174 { 0xc006, 0x33 },
175 { 0xc007, 0x64 },
176 { 0xc008, 0x05 },
177 { 0xc00a, 0xfc },
178 { 0xc00b, 0x0f },
179 { 0xc00c, 0x0e },
180 { 0xc00d, 0xef },
181 { 0xc00e, 0xe5 },
182 { 0xc00f, 0xff },
183 { 0xc120, 0xc0 },
184 { 0xc121, 0x00 },
185 { 0xc122, 0x00 },
186 { 0xc123, 0x14 },
187 { 0xc125, 0x00 },
188 { 0xc200, 0x00 },
189 { 0xc201, 0x00 },
190 { 0xc202, 0x00 },
191 { 0xc203, 0x04 },
192 { 0xc204, 0x00 },
193 { 0xc205, 0x00 },
194 { 0xc206, 0x68 },
195 { 0xc207, 0x70 },
196 { 0xc208, 0x00 },
197 { 0xc20a, 0x00 },
198 { 0xc20b, 0x01 },
199 { 0xc20c, 0x7f },
200 { 0xc20d, 0x01 },
201 { 0xc20e, 0x7f },
202 { 0xc300, 0x00 },
203 { 0xc301, 0x00 },
204 { 0xc303, 0x80 },
205 { 0xc320, 0x00 },
206 { 0xc321, 0x09 },
207 { 0xc322, 0x02 },
208 { 0xc410, 0x04 },
209 { 0xc430, 0x00 },
210 { 0xc431, 0x00 },
211 { 0xca00, 0x10 },
212 { 0xca01, 0x00 },
213 { 0xca02, 0x0b },
214 { 0xca10, 0x10 },
215 { 0xca11, 0x00 },
216 { 0xca12, 0x0b },
217 { 0xdd93, 0x00 },
218 { 0xdd94, 0x64 },
219 { 0xe300, 0xa0 },
220 { 0xed00, 0x80 },
221 { 0xed01, 0x0f },
222 { 0xed02, 0xff },
223 { 0xed03, 0x00 },
224 { 0xed04, 0x00 },
225 { 0xed05, 0x0f },
226 { 0xed06, 0xff },
227 { 0xf010, 0x10 },
228 { 0xf011, 0xec },
229 { 0xf012, 0x68 },
230 { 0xf013, 0x21 },
231 { 0xf800, 0x00 },
232 { 0xf801, 0x12 },
233 { 0xf802, 0xe0 },
234 { 0xf803, 0x2f },
235 { 0xf804, 0x00 },
236 { 0xf805, 0x00 },
237 { 0xf806, 0x07 },
238 { 0xf807, 0xff },
239 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
240 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
241 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
242 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
243 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
244};
245
246static bool rt1318_readable_register(struct device *dev, unsigned int reg)
247{
248 switch (reg) {
249 case 0x2f55:
250 case 0x3000:
251 case 0x3004 ... 0x3005:
252 case 0x3202 ... 0x3203:
253 case 0x3206:
254 case 0xc000 ... 0xc00f:
255 case 0xc120 ... 0xc125:
256 case 0xc200 ... 0xc20e:
257 case 0xc300 ... 0xc303:
258 case 0xc320 ... 0xc322:
259 case 0xc410:
260 case 0xc430 ... 0xc431:
261 case 0xca00 ... 0xca02:
262 case 0xca10 ... 0xca12:
263 case 0xcb00 ... 0xcb0b:
264 case 0xcc00 ... 0xcce5:
265 case 0xcd00 ... 0xcde5:
266 case 0xce00 ... 0xce6a:
267 case 0xcf00 ... 0xcf53:
268 case 0xd000 ... 0xd0cc:
269 case 0xd100 ... 0xd1b9:
270 case 0xdb00 ... 0xdc53:
271 case 0xdd00 ... 0xde53:
272 case 0xdf00 ... 0xdf6b:
273 case 0xe300:
274 case 0xeb00 ... 0xebcc:
275 case 0xec00 ... 0xecb9:
276 case 0xed00 ... 0xed06:
277 case 0xf010 ... 0xf014:
278 case 0xf800 ... 0xf807:
279 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0):
280 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L):
281 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R):
282 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0):
283 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
284 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
285 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
286 return true;
287 default:
288 return false;
289 }
290}
291
292static bool rt1318_volatile_register(struct device *dev, unsigned int reg)
293{
294 switch (reg) {
295 case 0x2f55:
296 case 0x3000 ... 0x3001:
297 case 0xc000:
298 case 0xc301:
299 case 0xc410:
300 case 0xc430 ... 0xc431:
301 case 0xdb06:
302 case 0xdb12:
303 case 0xdb1d ... 0xdb1f:
304 case 0xdb35:
305 case 0xdb37:
306 case 0xdb8a ... 0xdb92:
307 case 0xdbc5 ... 0xdbc8:
308 case 0xdc2b ... 0xdc49:
309 case 0xdd0b:
310 case 0xdd12:
311 case 0xdd1d ... 0xdd1f:
312 case 0xdd35:
313 case 0xdd8a ... 0xdd92:
314 case 0xddc5 ... 0xddc8:
315 case 0xde2b ... 0xde44:
316 case 0xdf4a ... 0xdf55:
317 case 0xe224 ... 0xe23b:
318 case 0xea01:
319 case 0xebc5:
320 case 0xebc8:
321 case 0xebcb ... 0xebcc:
322 case 0xed03 ... 0xed06:
323 case 0xf010 ... 0xf014:
324 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
325 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
326 return true;
327 default:
328 return false;
329 }
330}
331
332static const struct regmap_config rt1318_sdw_regmap = {
333 .reg_bits = 32,
334 .val_bits = 8,
335 .readable_reg = rt1318_readable_register,
336 .volatile_reg = rt1318_volatile_register,
337 .max_register = 0x41081488,
338 .reg_defaults = rt1318_reg_defaults,
339 .num_reg_defaults = ARRAY_SIZE(rt1318_reg_defaults),
Mark Brown22691a02023-06-10 15:27:19 +0100340 .cache_type = REGCACHE_MAPLE,
Shuming Fan6ad73a22022-11-08 17:27:27 +0800341 .use_single_read = true,
342 .use_single_write = true,
343};
344
345static int rt1318_read_prop(struct sdw_slave *slave)
346{
347 struct sdw_slave_prop *prop = &slave->prop;
348 int nval;
349 int i, j;
350 u32 bit;
351 unsigned long addr;
352 struct sdw_dpn_prop *dpn;
353
354 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
355 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
Shuming Fan6ad73a22022-11-08 17:27:27 +0800356
357 prop->paging_support = true;
358
359 /* first we need to allocate memory for set bits in port lists */
360 prop->source_ports = BIT(2);
361 prop->sink_ports = BIT(1);
362
363 nval = hweight32(prop->source_ports);
364 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
365 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
366 if (!prop->src_dpn_prop)
367 return -ENOMEM;
368
369 i = 0;
370 dpn = prop->src_dpn_prop;
371 addr = prop->source_ports;
372 for_each_set_bit(bit, &addr, 32) {
373 dpn[i].num = bit;
374 dpn[i].type = SDW_DPN_FULL;
375 dpn[i].simple_ch_prep_sm = true;
376 dpn[i].ch_prep_timeout = 10;
377 i++;
378 }
379
380 /* do this again for sink now */
381 nval = hweight32(prop->sink_ports);
382 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
383 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
384 if (!prop->sink_dpn_prop)
385 return -ENOMEM;
386
387 j = 0;
388 dpn = prop->sink_dpn_prop;
389 addr = prop->sink_ports;
390 for_each_set_bit(bit, &addr, 32) {
391 dpn[j].num = bit;
392 dpn[j].type = SDW_DPN_FULL;
393 dpn[j].simple_ch_prep_sm = true;
394 dpn[j].ch_prep_timeout = 10;
395 j++;
396 }
397
398 /* set the timeout values */
399 prop->clk_stop_timeout = 20;
400
401 return 0;
402}
403
404static int rt1318_io_init(struct device *dev, struct sdw_slave *slave)
405{
406 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
407
408 if (rt1318->hw_init)
409 return 0;
410
411 if (rt1318->first_hw_init) {
412 regcache_cache_only(rt1318->regmap, false);
413 regcache_cache_bypass(rt1318->regmap, true);
414 } else {
415 /*
416 * PM runtime is only enabled when a Slave reports as Attached
417 */
418
419 /* set autosuspend parameters */
420 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
421 pm_runtime_use_autosuspend(&slave->dev);
422
423 /* update count of parent 'active' children */
424 pm_runtime_set_active(&slave->dev);
425
426 /* make sure the device does not suspend immediately */
427 pm_runtime_mark_last_busy(&slave->dev);
428
429 pm_runtime_enable(&slave->dev);
430 }
431
432 pm_runtime_get_noresume(&slave->dev);
433
434 /* blind write */
435 regmap_multi_reg_write(rt1318->regmap, rt1318_blind_write,
436 ARRAY_SIZE(rt1318_blind_write));
437
438 if (rt1318->first_hw_init) {
439 regcache_cache_bypass(rt1318->regmap, false);
440 regcache_mark_dirty(rt1318->regmap);
441 }
442
443 /* Mark Slave initialization complete */
444 rt1318->first_hw_init = true;
445 rt1318->hw_init = true;
446
447 pm_runtime_mark_last_busy(&slave->dev);
448 pm_runtime_put_autosuspend(&slave->dev);
449
450 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
451 return 0;
452}
453
454static int rt1318_update_status(struct sdw_slave *slave,
455 enum sdw_slave_status status)
456{
457 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(&slave->dev);
458
Shuming Fan6ad73a22022-11-08 17:27:27 +0800459 if (status == SDW_SLAVE_UNATTACHED)
460 rt1318->hw_init = false;
461
462 /*
463 * Perform initialization only if slave status is present and
464 * hw_init flag is false
465 */
Krzysztof Kozlowski28eb1e42023-05-18 09:27:44 +0200466 if (rt1318->hw_init || status != SDW_SLAVE_ATTACHED)
Shuming Fan6ad73a22022-11-08 17:27:27 +0800467 return 0;
468
469 /* perform I/O transfers required for Slave initialization */
470 return rt1318_io_init(&slave->dev, slave);
471}
472
473static int rt1318_classd_event(struct snd_soc_dapm_widget *w,
474 struct snd_kcontrol *kcontrol, int event)
475{
476 struct snd_soc_component *component =
477 snd_soc_dapm_to_component(w->dapm);
478 struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component);
479 unsigned char ps0 = 0x0, ps3 = 0x3;
480
481 switch (event) {
482 case SND_SOC_DAPM_POST_PMU:
483 regmap_write(rt1318->regmap,
484 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23,
485 RT1318_SDCA_CTL_REQ_POWER_STATE, 0),
486 ps0);
487 break;
488 case SND_SOC_DAPM_PRE_PMD:
489 regmap_write(rt1318->regmap,
490 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23,
491 RT1318_SDCA_CTL_REQ_POWER_STATE, 0),
492 ps3);
493 break;
494
495 default:
496 break;
497 }
498
499 return 0;
500}
501
502static const char * const rt1318_rx_data_ch_select[] = {
503 "L,R",
504 "L,L",
505 "L,R",
506 "L,L+R",
507 "R,L",
508 "R,R",
509 "R,L+R",
510 "L+R,L",
511 "L+R,R",
512 "L+R,L+R",
513};
514
515static SOC_ENUM_SINGLE_DECL(rt1318_rx_data_ch_enum,
516 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
517 rt1318_rx_data_ch_select);
518
519static const struct snd_kcontrol_new rt1318_snd_controls[] = {
520
521 /* UDMPU Cluster Selection */
522 SOC_ENUM("RX Channel Select", rt1318_rx_data_ch_enum),
523};
524
525static const struct snd_kcontrol_new rt1318_sto_dac =
526 SOC_DAPM_DOUBLE_R("Switch",
527 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L),
528 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R),
529 0, 1, 1);
530
531static const struct snd_soc_dapm_widget rt1318_dapm_widgets[] = {
532 /* Audio Interface */
533 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
534 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
535
536 /* Digital Interface */
537 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1318_sto_dac),
538
539 /* Output */
540 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
541 rt1318_classd_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
542 SND_SOC_DAPM_OUTPUT("SPOL"),
543 SND_SOC_DAPM_OUTPUT("SPOR"),
544 /* Input */
545 SND_SOC_DAPM_PGA("FB Data", SND_SOC_NOPM, 0, 0, NULL, 0),
546 SND_SOC_DAPM_SIGGEN("FB Gen"),
547};
548
549static const struct snd_soc_dapm_route rt1318_dapm_routes[] = {
550 { "DAC", "Switch", "DP1RX" },
551 { "CLASS D", NULL, "DAC" },
552 { "SPOL", NULL, "CLASS D" },
553 { "SPOR", NULL, "CLASS D" },
554
555 { "FB Data", NULL, "FB Gen" },
556 { "DP2TX", NULL, "FB Data" },
557};
558
559static int rt1318_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
560 int direction)
561{
Pierre-Louis Bossartbe8e5a82023-03-24 09:44:01 +0800562 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
Shuming Fan6ad73a22022-11-08 17:27:27 +0800563
564 return 0;
565}
566
567static void rt1318_sdw_shutdown(struct snd_pcm_substream *substream,
568 struct snd_soc_dai *dai)
569{
Shuming Fan6ad73a22022-11-08 17:27:27 +0800570 snd_soc_dai_set_dma_data(dai, substream, NULL);
Shuming Fan6ad73a22022-11-08 17:27:27 +0800571}
572
573static int rt1318_sdw_hw_params(struct snd_pcm_substream *substream,
574 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
575{
576 struct snd_soc_component *component = dai->component;
577 struct rt1318_sdw_priv *rt1318 =
578 snd_soc_component_get_drvdata(component);
579 struct sdw_stream_config stream_config;
580 struct sdw_port_config port_config;
581 enum sdw_data_direction direction;
Pierre-Louis Bossartbe8e5a82023-03-24 09:44:01 +0800582 struct sdw_stream_runtime *sdw_stream;
Shuming Fan6ad73a22022-11-08 17:27:27 +0800583 int retval, port, num_channels, ch_mask;
584 unsigned int sampling_rate;
585
586 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
Pierre-Louis Bossartbe8e5a82023-03-24 09:44:01 +0800587 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
Shuming Fan6ad73a22022-11-08 17:27:27 +0800588
Pierre-Louis Bossartbe8e5a82023-03-24 09:44:01 +0800589 if (!sdw_stream)
Shuming Fan6ad73a22022-11-08 17:27:27 +0800590 return -EINVAL;
591
592 if (!rt1318->sdw_slave)
593 return -EINVAL;
594
595 /* SoundWire specific configuration */
596 /* port 1 for playback */
597 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
598 direction = SDW_DATA_DIR_RX;
599 port = 1;
600 } else {
601 direction = SDW_DATA_DIR_TX;
602 port = 2;
603 }
604
605 num_channels = params_channels(params);
606 ch_mask = (1 << num_channels) - 1;
607
608 stream_config.frame_rate = params_rate(params);
609 stream_config.ch_count = num_channels;
610 stream_config.bps = snd_pcm_format_width(params_format(params));
611 stream_config.direction = direction;
612
613 port_config.ch_mask = ch_mask;
614 port_config.num = port;
615
616 retval = sdw_stream_add_slave(rt1318->sdw_slave, &stream_config,
Pierre-Louis Bossartbe8e5a82023-03-24 09:44:01 +0800617 &port_config, 1, sdw_stream);
Shuming Fan6ad73a22022-11-08 17:27:27 +0800618 if (retval) {
619 dev_err(dai->dev, "Unable to configure port\n");
620 return retval;
621 }
622
623 /* sampling rate configuration */
624 switch (params_rate(params)) {
625 case 16000:
626 sampling_rate = RT1318_SDCA_RATE_16000HZ;
627 break;
628 case 32000:
629 sampling_rate = RT1318_SDCA_RATE_32000HZ;
630 break;
631 case 44100:
632 sampling_rate = RT1318_SDCA_RATE_44100HZ;
633 break;
634 case 48000:
635 sampling_rate = RT1318_SDCA_RATE_48000HZ;
636 break;
637 case 96000:
638 sampling_rate = RT1318_SDCA_RATE_96000HZ;
639 break;
640 case 192000:
641 sampling_rate = RT1318_SDCA_RATE_192000HZ;
642 break;
643 default:
644 dev_err(component->dev, "Rate %d is not supported\n",
645 params_rate(params));
646 return -EINVAL;
647 }
648
649 /* set sampling frequency */
650 regmap_write(rt1318->regmap,
651 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
652 sampling_rate);
653
654 return 0;
655}
656
657static int rt1318_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
658 struct snd_soc_dai *dai)
659{
660 struct snd_soc_component *component = dai->component;
661 struct rt1318_sdw_priv *rt1318 =
662 snd_soc_component_get_drvdata(component);
Pierre-Louis Bossartbe8e5a82023-03-24 09:44:01 +0800663 struct sdw_stream_runtime *sdw_stream =
Shuming Fan6ad73a22022-11-08 17:27:27 +0800664 snd_soc_dai_get_dma_data(dai, substream);
665
666 if (!rt1318->sdw_slave)
667 return -EINVAL;
668
Pierre-Louis Bossartbe8e5a82023-03-24 09:44:01 +0800669 sdw_stream_remove_slave(rt1318->sdw_slave, sdw_stream);
Shuming Fan6ad73a22022-11-08 17:27:27 +0800670 return 0;
671}
672
673/*
674 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
675 * port_prep are not defined for now
676 */
Krzysztof Kozlowski65b7b862023-01-24 17:39:51 +0100677static const struct sdw_slave_ops rt1318_slave_ops = {
Shuming Fan6ad73a22022-11-08 17:27:27 +0800678 .read_prop = rt1318_read_prop,
679 .update_status = rt1318_update_status,
680};
681
682static int rt1318_sdw_component_probe(struct snd_soc_component *component)
683{
684 int ret;
685 struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component);
686
687 rt1318->component = component;
688
689 ret = pm_runtime_resume(component->dev);
690 dev_dbg(&rt1318->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
691 if (ret < 0 && ret != -EACCES)
692 return ret;
693
694 return 0;
695}
696
697static const struct snd_soc_component_driver soc_component_sdw_rt1318 = {
698 .probe = rt1318_sdw_component_probe,
699 .controls = rt1318_snd_controls,
700 .num_controls = ARRAY_SIZE(rt1318_snd_controls),
701 .dapm_widgets = rt1318_dapm_widgets,
702 .num_dapm_widgets = ARRAY_SIZE(rt1318_dapm_widgets),
703 .dapm_routes = rt1318_dapm_routes,
704 .num_dapm_routes = ARRAY_SIZE(rt1318_dapm_routes),
705 .endianness = 1,
706};
707
708static const struct snd_soc_dai_ops rt1318_aif_dai_ops = {
709 .hw_params = rt1318_sdw_hw_params,
710 .hw_free = rt1318_sdw_pcm_hw_free,
711 .set_stream = rt1318_set_sdw_stream,
712 .shutdown = rt1318_sdw_shutdown,
713};
714
715#define RT1318_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
716 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
717#define RT1318_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
718 SNDRV_PCM_FMTBIT_S32_LE)
719
720static struct snd_soc_dai_driver rt1318_sdw_dai[] = {
721 {
722 .name = "rt1318-aif",
723 .playback = {
724 .stream_name = "DP1 Playback",
725 .channels_min = 1,
726 .channels_max = 2,
727 .rates = RT1318_STEREO_RATES,
728 .formats = RT1318_FORMATS,
729 },
730 .capture = {
731 .stream_name = "DP2 Capture",
732 .channels_min = 1,
733 .channels_max = 2,
734 .rates = RT1318_STEREO_RATES,
735 .formats = RT1318_FORMATS,
736 },
737 .ops = &rt1318_aif_dai_ops,
738 },
739};
740
741static int rt1318_sdw_init(struct device *dev, struct regmap *regmap,
742 struct sdw_slave *slave)
743{
744 struct rt1318_sdw_priv *rt1318;
745 int ret;
746
747 rt1318 = devm_kzalloc(dev, sizeof(*rt1318), GFP_KERNEL);
748 if (!rt1318)
749 return -ENOMEM;
750
751 dev_set_drvdata(dev, rt1318);
752 rt1318->sdw_slave = slave;
753 rt1318->regmap = regmap;
754
755 /*
756 * Mark hw_init to false
757 * HW init will be performed when device reports present
758 */
759 rt1318->hw_init = false;
760 rt1318->first_hw_init = false;
761
762 ret = devm_snd_soc_register_component(dev,
763 &soc_component_sdw_rt1318,
764 rt1318_sdw_dai,
765 ARRAY_SIZE(rt1318_sdw_dai));
766
767 dev_dbg(&slave->dev, "%s\n", __func__);
768
769 return ret;
770}
771
772static int rt1318_sdw_probe(struct sdw_slave *slave,
773 const struct sdw_device_id *id)
774{
775 struct regmap *regmap;
776
777 /* Regmap Initialization */
778 regmap = devm_regmap_init_sdw(slave, &rt1318_sdw_regmap);
779 if (IS_ERR(regmap))
780 return PTR_ERR(regmap);
781
782 return rt1318_sdw_init(&slave->dev, regmap, slave);
783}
784
785static int rt1318_sdw_remove(struct sdw_slave *slave)
786{
787 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(&slave->dev);
788
789 if (rt1318->first_hw_init)
790 pm_runtime_disable(&slave->dev);
791
792 return 0;
793}
794
795static const struct sdw_device_id rt1318_id[] = {
796 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1318, 0x3, 0x1, 0),
797 {},
798};
799MODULE_DEVICE_TABLE(sdw, rt1318_id);
800
801static int __maybe_unused rt1318_dev_suspend(struct device *dev)
802{
803 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
804
805 if (!rt1318->hw_init)
806 return 0;
807
808 regcache_cache_only(rt1318->regmap, true);
809 return 0;
810}
811
812#define RT1318_PROBE_TIMEOUT 5000
813
814static int __maybe_unused rt1318_dev_resume(struct device *dev)
815{
816 struct sdw_slave *slave = dev_to_sdw_dev(dev);
817 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev);
818 unsigned long time;
819
820 if (!rt1318->first_hw_init)
821 return 0;
822
823 if (!slave->unattach_request)
824 goto regmap_sync;
825
826 time = wait_for_completion_timeout(&slave->initialization_complete,
827 msecs_to_jiffies(RT1318_PROBE_TIMEOUT));
828 if (!time) {
829 dev_err(&slave->dev, "Initialization not complete, timed out\n");
830 return -ETIMEDOUT;
831 }
832
833regmap_sync:
834 slave->unattach_request = 0;
835 regcache_cache_only(rt1318->regmap, false);
836 regcache_sync(rt1318->regmap);
837
838 return 0;
839}
840
841static const struct dev_pm_ops rt1318_pm = {
842 SET_SYSTEM_SLEEP_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume)
843 SET_RUNTIME_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume, NULL)
844};
845
846static struct sdw_driver rt1318_sdw_driver = {
847 .driver = {
848 .name = "rt1318-sdca",
849 .owner = THIS_MODULE,
850 .pm = &rt1318_pm,
851 },
852 .probe = rt1318_sdw_probe,
853 .remove = rt1318_sdw_remove,
854 .ops = &rt1318_slave_ops,
855 .id_table = rt1318_id,
856};
857module_sdw_driver(rt1318_sdw_driver);
858
859MODULE_DESCRIPTION("ASoC RT1318 driver SDCA SDW");
860MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
861MODULE_LICENSE("GPL");