blob: b7efa70c2d6c271c4fb57819a8b20fa6dbe2925c [file] [log] [blame]
Sam Shihb4966a72022-01-19 20:36:58 +08001// SPDX-License-Identifier: GPL-2.0
Sam Shihec97d232021-12-17 20:11:48 +08002/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include "clk-mtk.h"
14#include "clk-gate.h"
15#include "clk-mux.h"
16
17#include <dt-bindings/clock/mt7986-clk.h>
18#include <linux/clk.h>
19
20static DEFINE_SPINLOCK(mt7986_clk_lock);
21
22static const struct mtk_fixed_factor infra_divs[] = {
23 FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
24};
25
26static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
27 "uart_sel" };
28
29static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
30 "spi_sel" };
31
32static const char *const infra_pwm_bsel_parents[] __initconst = {
33 "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
34};
35
36static const char *const infra_pcie_parents[] __initconst = {
37 "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
38};
39
40static const struct mtk_mux infra_muxes[] = {
41 /* MODULE_CLK_SEL_0 */
42 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
43 infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
44 -1, -1, -1),
45 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
46 infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
47 -1, -1, -1),
48 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
49 infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
50 -1, -1, -1),
51 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
52 infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
53 -1, -1, -1),
54 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
55 infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
56 -1, -1, -1),
57 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
58 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
59 2, -1, -1, -1),
60 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
61 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
62 2, -1, -1, -1),
63 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
64 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
65 2, -1, -1, -1),
66 /* MODULE_CLK_SEL_1 */
67 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
68 infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
69 -1, -1, -1),
70};
71
72static const struct mtk_gate_regs infra0_cg_regs = {
73 .set_ofs = 0x40,
74 .clr_ofs = 0x44,
75 .sta_ofs = 0x48,
76};
77
78static const struct mtk_gate_regs infra1_cg_regs = {
79 .set_ofs = 0x50,
80 .clr_ofs = 0x54,
81 .sta_ofs = 0x58,
82};
83
84static const struct mtk_gate_regs infra2_cg_regs = {
85 .set_ofs = 0x60,
86 .clr_ofs = 0x64,
87 .sta_ofs = 0x68,
88};
89
AngeloGioacchino Del Regno4c85e202023-03-06 15:05:11 +010090#define GATE_INFRA0(_id, _name, _parent, _shift) \
91 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
Sam Shihec97d232021-12-17 20:11:48 +080092
AngeloGioacchino Del Regno4c85e202023-03-06 15:05:11 +010093#define GATE_INFRA1(_id, _name, _parent, _shift) \
94 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
Sam Shihec97d232021-12-17 20:11:48 +080095
AngeloGioacchino Del Regno4c85e202023-03-06 15:05:11 +010096#define GATE_INFRA2(_id, _name, _parent, _shift) \
97 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
Sam Shihec97d232021-12-17 20:11:48 +080098
99static const struct mtk_gate infra_clks[] = {
100 /* INFRA0 */
101 GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
102 GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
103 GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
104 GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
105 GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
106 GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
107 GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
108 GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
109 GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
110 GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
111 GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
112 GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
113 GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
114 14),
115 GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
116 GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
117 GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
118 GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
119 GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
120 /* INFRA1 */
121 GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
122 GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
123 GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
124 GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
125 GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
126 GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
127 GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
128 GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
129 10),
130 GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
131 GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
132 GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
133 13),
134 GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
135 14),
136 GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
137 GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
138 GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
139 17),
140 GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
141 18),
142 GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
143 19),
Daniel Gollea4631522022-10-26 17:18:07 +0100144 GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
Sam Shihec97d232021-12-17 20:11:48 +0800145 GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
146 GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
147 /* INFRA2 */
148 GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
149 GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
150 1),
151 GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
152 GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
153 GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
154 GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
155 13),
156 GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
157 GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
158};
159
AngeloGioacchino Del Regno148a3952023-03-06 15:05:22 +0100160static const struct mtk_clk_desc infra_desc = {
161 .clks = infra_clks,
162 .num_clks = ARRAY_SIZE(infra_clks),
163 .factor_clks = infra_divs,
164 .num_factor_clks = ARRAY_SIZE(infra_divs),
165 .mux_clks = infra_muxes,
166 .num_mux_clks = ARRAY_SIZE(infra_muxes),
167 .clk_lock = &mt7986_clk_lock,
168};
Sam Shihec97d232021-12-17 20:11:48 +0800169
170static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
AngeloGioacchino Del Regno148a3952023-03-06 15:05:22 +0100171 { .compatible = "mediatek,mt7986-infracfg", .data = &infra_desc },
172 { /* sentinel */ }
Sam Shihec97d232021-12-17 20:11:48 +0800173};
AngeloGioacchino Del Regno65c9ad72023-03-06 15:05:38 +0100174MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_infracfg);
Sam Shihec97d232021-12-17 20:11:48 +0800175
176static struct platform_driver clk_mt7986_infracfg_drv = {
Sam Shihec97d232021-12-17 20:11:48 +0800177 .driver = {
178 .name = "clk-mt7986-infracfg",
179 .of_match_table = of_match_clk_mt7986_infracfg,
180 },
AngeloGioacchino Del Regno148a3952023-03-06 15:05:22 +0100181 .probe = mtk_clk_simple_probe,
182 .remove = mtk_clk_simple_remove,
Sam Shihec97d232021-12-17 20:11:48 +0800183};
AngeloGioacchino Del Regno148a3952023-03-06 15:05:22 +0100184module_platform_driver(clk_mt7986_infracfg_drv);
185
186MODULE_DESCRIPTION("MediaTek MT7986 infracfg clocks driver");
187MODULE_LICENSE("GPL");