blob: eb1ba6319fdaf3f57eb4ba9215297ae098b77cec [file] [log] [blame]
Thomas Gleixner5a729242022-06-07 16:11:32 +02001// SPDX-License-Identifier: GPL-2.0-only
Santosh Shilimkar2722e562011-03-07 20:53:10 +05302/*
Sricharan Rc10d5c92014-04-11 13:09:36 -05003 * OMAP L3 Interconnect error handling driver
sricharaned0e3522011-08-24 20:07:45 +05304 *
Suman Annae7309c22015-04-24 12:54:20 -05005 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
sricharaned0e3522011-08-24 20:07:45 +05306 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
sricharaned0e3522011-08-24 20:07:45 +05308 */
Santosh Shilimkar2722e562011-03-07 20:53:10 +05309#include <linux/init.h>
Santosh Shilimkar2722e562011-03-07 20:53:10 +053010#include <linux/interrupt.h>
Sricharan R06594522013-11-26 07:38:23 -060011#include <linux/io.h>
Santosh Shilimkar2722e562011-03-07 20:53:10 +053012#include <linux/kernel.h>
Sricharan R06594522013-11-26 07:38:23 -060013#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
Santosh Shilimkar2722e562011-03-07 20:53:10 +053017#include <linux/slab.h>
18
19#include "omap_l3_noc.h"
20
Nishanth Menone4be3f32014-04-17 12:33:50 -050021/**
22 * l3_handle_target() - Handle Target specific parse and reporting
23 * @l3: pointer to l3 struct
24 * @base: base address of clkdm
25 * @flag_mux: flagmux corresponding to the event
26 * @err_src: error source index of the slave (target)
Santosh Shilimkar2722e562011-03-07 20:53:10 +053027 *
Nishanth Menone4be3f32014-04-17 12:33:50 -050028 * This does the second part of the error interrupt handling:
29 * 3) Parse in the slave information
30 * 4) Print the logged information.
31 * 5) Add dump stack to provide kernel trace.
32 * 6) Clear the source if known.
33 *
34 * This handles two types of errors:
Santosh Shilimkar2722e562011-03-07 20:53:10 +053035 * 1) Custom errors in L3 :
36 * Target like DMM/FW/EMIF generates SRESP=ERR error
37 * 2) Standard L3 error:
38 * - Unsupported CMD.
39 * L3 tries to access target while it is idle
40 * - OCP disconnect.
41 * - Address hole error:
42 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
43 * do not have connectivity, the error is logged in
44 * their default target which is DMM2.
45 *
46 * On High Secure devices, firewall errors are possible and those
47 * can be trapped as well. But the trapping is implemented as part
48 * secure software and hence need not be implemented here.
49 */
Nishanth Menone4be3f32014-04-17 12:33:50 -050050static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
51 struct l3_flagmux_data *flag_mux, int err_src)
Santosh Shilimkar2722e562011-03-07 20:53:10 +053052{
Nishanth Menone4be3f32014-04-17 12:33:50 -050053 int k;
54 u32 std_err_main, clear, masterid;
Nishanth Menoncf52b2e2014-04-16 17:23:33 -050055 u8 op_code, m_req_info;
Nishanth Menone4be3f32014-04-17 12:33:50 -050056 void __iomem *l3_targ_base;
Nishanth Menon9e224c82014-04-11 11:21:47 -050057 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
Nishanth Menoncf52b2e2014-04-16 17:23:33 -050058 void __iomem *l3_targ_hdr, *l3_targ_info;
Nishanth Menon3ae9af72014-04-11 11:38:10 -050059 struct l3_target_data *l3_targ_inst;
Sricharan R06594522013-11-26 07:38:23 -060060 struct l3_masters_data *master;
Nishanth Menone4be3f32014-04-17 12:33:50 -050061 char *target_name, *master_name = "UN IDENTIFIED";
Nishanth Menonc98aa7a2014-04-11 12:24:56 -050062 char *err_description;
63 char err_string[30] = { 0 };
Nishanth Menoncf52b2e2014-04-16 17:23:33 -050064 char info_string[60] = { 0 };
Santosh Shilimkar2722e562011-03-07 20:53:10 +053065
Nishanth Menone4be3f32014-04-17 12:33:50 -050066 /* We DONOT expect err_src to go out of bounds */
67 BUG_ON(err_src > MAX_CLKDM_TARGETS);
68
69 if (err_src < flag_mux->num_targ_data) {
70 l3_targ_inst = &flag_mux->l3_targ[err_src];
71 target_name = l3_targ_inst->name;
72 l3_targ_base = base + l3_targ_inst->offset;
73 } else {
74 target_name = L3_TARGET_NOT_SUPPORTED;
75 }
76
77 if (target_name == L3_TARGET_NOT_SUPPORTED)
78 return -ENODEV;
79
80 /* Read the stderrlog_main_source from clk domain */
81 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
82 l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
83
84 std_err_main = readl_relaxed(l3_targ_stderr);
85
86 switch (std_err_main & CUSTOM_ERROR) {
87 case STANDARD_ERROR:
88 err_description = "Standard";
89 snprintf(err_string, sizeof(err_string),
90 ": At Address: 0x%08X ",
91 readl_relaxed(l3_targ_slvofslsb));
92
93 l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
Nishanth Menon7f9de022014-04-16 15:47:28 -050094 l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_HDR;
Nishanth Menoncf52b2e2014-04-16 17:23:33 -050095 l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_INFO;
Nishanth Menone4be3f32014-04-17 12:33:50 -050096 break;
97
98 case CUSTOM_ERROR:
99 err_description = "Custom";
100
101 l3_targ_mstaddr = l3_targ_base +
102 L3_TARG_STDERRLOG_CINFO_MSTADDR;
Nishanth Menon7f9de022014-04-16 15:47:28 -0500103 l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_CINFO_OPCODE;
Nishanth Menoncf52b2e2014-04-16 17:23:33 -0500104 l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_CINFO_INFO;
Nishanth Menone4be3f32014-04-17 12:33:50 -0500105 break;
106
107 default:
108 /* Nothing to be handled here as of now */
109 return 0;
110 }
111
112 /* STDERRLOG_MSTADDR Stores the NTTP master address. */
113 masterid = (readl_relaxed(l3_targ_mstaddr) &
114 l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
115
116 for (k = 0, master = l3->l3_masters; k < l3->num_masters;
117 k++, master++) {
118 if (masterid == master->id) {
119 master_name = master->name;
120 break;
121 }
122 }
123
Nishanth Menon7f9de022014-04-16 15:47:28 -0500124 op_code = readl_relaxed(l3_targ_hdr) & 0x7;
125
Nishanth Menoncf52b2e2014-04-16 17:23:33 -0500126 m_req_info = readl_relaxed(l3_targ_info) & 0xF;
127 snprintf(info_string, sizeof(info_string),
128 ": %s in %s mode during %s access",
129 (m_req_info & BIT(0)) ? "Opcode Fetch" : "Data Access",
130 (m_req_info & BIT(1)) ? "Supervisor" : "User",
131 (m_req_info & BIT(3)) ? "Debug" : "Functional");
132
Nishanth Menone4be3f32014-04-17 12:33:50 -0500133 WARN(true,
Nishanth Menoncf52b2e2014-04-16 17:23:33 -0500134 "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n",
Nishanth Menone4be3f32014-04-17 12:33:50 -0500135 dev_name(l3->dev),
136 err_description,
137 master_name, target_name,
Nishanth Menon7f9de022014-04-16 15:47:28 -0500138 l3_transaction_type[op_code],
Nishanth Menoncf52b2e2014-04-16 17:23:33 -0500139 err_string, info_string);
Nishanth Menone4be3f32014-04-17 12:33:50 -0500140
141 /* clear the std error log*/
142 clear = std_err_main | CLEAR_STDERR_LOG;
143 writel_relaxed(clear, l3_targ_stderr);
144
145 return 0;
146}
147
148/**
149 * l3_interrupt_handler() - interrupt handler for l3 events
150 * @irq: irq number
151 * @_l3: pointer to l3 structure
152 *
153 * Interrupt Handler for L3 error detection.
154 * 1) Identify the L3 clockdomain partition to which the error belongs to.
155 * 2) Identify the slave where the error information is logged
156 * ... handle the slave event..
157 * 7) if the slave is unknown, mask out the slave.
158 */
159static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
160{
161 struct omap_l3 *l3 = _l3;
162 int inttype, i, ret;
163 int err_src = 0;
164 u32 err_reg, mask_val;
165 void __iomem *base, *mask_reg;
166 struct l3_flagmux_data *flag_mux;
167
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530168 /* Get the Type of interrupt */
omar ramirez35f7b962011-04-18 16:39:42 +0000169 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530170
Sricharan R06594522013-11-26 07:38:23 -0600171 for (i = 0; i < l3->num_modules; i++) {
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530172 /*
173 * Read the regerr register of the clock domain
174 * to determine the source
175 */
sricharan6616aac2011-08-23 12:58:48 +0530176 base = l3->l3_base[i];
Nishanth Menon97708c02014-04-14 09:57:50 -0500177 flag_mux = l3->l3_flagmux[i];
178 err_reg = readl_relaxed(base + flag_mux->offset +
Nishanth Menon9e224c82014-04-11 11:21:47 -0500179 L3_FLAGMUX_REGERR0 + (inttype << 3));
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530180
Afzal Mohammed2100b592014-04-25 17:38:11 -0500181 err_reg &= ~(inttype ? flag_mux->mask_app_bits :
182 flag_mux->mask_dbg_bits);
183
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530184 /* Get the corresponding error and analyse */
185 if (err_reg) {
186 /* Identify the source from control status register */
Todd Poynor342fd142011-08-24 19:11:39 +0530187 err_src = __ffs(err_reg);
Rajendra Nayak3340d732014-04-10 11:31:33 -0500188
Nishanth Menone4be3f32014-04-17 12:33:50 -0500189 ret = l3_handle_target(l3, base, flag_mux, err_src);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530190
Rajendra Nayak3340d732014-04-10 11:31:33 -0500191 /*
Nishanth Menone4be3f32014-04-17 12:33:50 -0500192 * Certain plaforms may have "undocumented" status
193 * pending on boot. So dont generate a severe warning
194 * here. Just mask it off to prevent the error from
195 * reoccuring and locking up the system.
Rajendra Nayak3340d732014-04-10 11:31:33 -0500196 */
Nishanth Menone4be3f32014-04-17 12:33:50 -0500197 if (ret) {
Rajendra Nayak3340d732014-04-10 11:31:33 -0500198 dev_err(l3->dev,
199 "L3 %s error: target %d mod:%d %s\n",
200 inttype ? "debug" : "application",
201 err_src, i, "(unclearable)");
202
Nishanth Menon97708c02014-04-14 09:57:50 -0500203 mask_reg = base + flag_mux->offset +
Rajendra Nayak3340d732014-04-10 11:31:33 -0500204 L3_FLAGMUX_MASK0 + (inttype << 3);
205 mask_val = readl_relaxed(mask_reg);
206 mask_val &= ~(1 << err_src);
207 writel_relaxed(mask_val, mask_reg);
Afzal Mohammed2100b592014-04-25 17:38:11 -0500208
209 /* Mark these bits as to be ignored */
210 if (inttype)
211 flag_mux->mask_app_bits |= 1 << err_src;
212 else
213 flag_mux->mask_dbg_bits |= 1 << err_src;
Rajendra Nayak3340d732014-04-10 11:31:33 -0500214 }
215
Nishanth Menonc98aa7a2014-04-11 12:24:56 -0500216 /* Error found so break the for loop */
Keerthyc4cf0932014-11-10 23:49:48 +0530217 return IRQ_HANDLED;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530218 }
219 }
Keerthyc4cf0932014-11-10 23:49:48 +0530220
221 dev_err(l3->dev, "L3 %s IRQ not handled!!\n",
222 inttype ? "debug" : "application");
223
224 return IRQ_NONE;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530225}
226
Sricharan R06594522013-11-26 07:38:23 -0600227static const struct of_device_id l3_noc_match[] = {
Suman Annae7309c22015-04-24 12:54:20 -0500228 {.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
229 {.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
Rajendra Nayak53a848b2014-04-10 11:33:13 -0500230 {.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
Afzal Mohammed27b7d5f2013-12-02 17:48:57 +0530231 {.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
Sricharan R06594522013-11-26 07:38:23 -0600232 {},
233};
234MODULE_DEVICE_TABLE(of, l3_noc_match);
235
Sricharan Rc10d5c92014-04-11 13:09:36 -0500236static int omap_l3_probe(struct platform_device *pdev)
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530237{
Sricharan R06594522013-11-26 07:38:23 -0600238 const struct of_device_id *of_id;
Sricharan Rc10d5c92014-04-11 13:09:36 -0500239 static struct omap_l3 *l3;
Nishanth Menonf33ddf72014-04-11 14:37:03 -0500240 int ret, i, res_idx;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530241
Sricharan R06594522013-11-26 07:38:23 -0600242 of_id = of_match_device(l3_noc_match, &pdev->dev);
243 if (!of_id) {
244 dev_err(&pdev->dev, "OF data missing\n");
245 return -EINVAL;
246 }
247
Peter Ujfalusibae74512014-04-01 16:23:46 +0300248 l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530249 if (!l3)
omar ramirez7529b702011-04-18 16:39:41 +0000250 return -ENOMEM;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530251
Sricharan R06594522013-11-26 07:38:23 -0600252 memcpy(l3, of_id->data, sizeof(*l3));
Nishanth Menonca6a3492014-04-11 12:04:01 -0500253 l3->dev = &pdev->dev;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530254 platform_set_drvdata(pdev, l3);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530255
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300256 /* Get mem resources */
Nishanth Menonf33ddf72014-04-11 14:37:03 -0500257 for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
258 struct resource *res;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530259
Nishanth Menonf33ddf72014-04-11 14:37:03 -0500260 if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
261 /* First entry cannot be submodule */
262 BUG_ON(i == 0);
263 l3->l3_base[i] = l3->l3_base[i - 1];
264 continue;
265 }
266 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300267 l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
268 if (IS_ERR(l3->l3_base[i])) {
Nishanth Menonca6a3492014-04-11 12:04:01 -0500269 dev_err(l3->dev, "ioremap %d failed\n", i);
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300270 return PTR_ERR(l3->l3_base[i]);
271 }
Nishanth Menonf33ddf72014-04-11 14:37:03 -0500272 res_idx++;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530273 }
274
275 /*
276 * Setup interrupt Handlers
277 */
Todd Poynorc1df2dc2011-08-29 17:42:23 +0530278 l3->debug_irq = platform_get_irq(pdev, 0);
Nishanth Menonca6a3492014-04-11 12:04:01 -0500279 ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
Grygorii Strashko7d7275b2021-01-28 21:15:48 +0200280 IRQF_NO_THREAD, "l3-dbg-irq", l3);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530281 if (ret) {
Nishanth Menonca6a3492014-04-11 12:04:01 -0500282 dev_err(l3->dev, "request_irq failed for %d\n",
Peter Ujfalusiae225982014-04-01 16:23:50 +0300283 l3->debug_irq);
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300284 return ret;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530285 }
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530286
Todd Poynorc1df2dc2011-08-29 17:42:23 +0530287 l3->app_irq = platform_get_irq(pdev, 1);
Nishanth Menonca6a3492014-04-11 12:04:01 -0500288 ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
Grygorii Strashko7d7275b2021-01-28 21:15:48 +0200289 IRQF_NO_THREAD, "l3-app-irq", l3);
Peter Ujfalusia0ef78f32014-04-01 16:23:48 +0300290 if (ret)
Nishanth Menonca6a3492014-04-11 12:04:01 -0500291 dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530292
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530293 return ret;
294}
295
Grygorii Strashko258d2a12015-04-27 21:24:31 +0300296#ifdef CONFIG_PM_SLEEP
Keerthy61b43d42014-11-10 23:49:47 +0530297
298/**
299 * l3_resume_noirq() - resume function for l3_noc
300 * @dev: pointer to l3_noc device structure
301 *
302 * We only have the resume handler only since we
303 * have already maintained the delta register
304 * configuration as part of configuring the system
305 */
306static int l3_resume_noirq(struct device *dev)
307{
308 struct omap_l3 *l3 = dev_get_drvdata(dev);
309 int i;
310 struct l3_flagmux_data *flag_mux;
311 void __iomem *base, *mask_regx = NULL;
312 u32 mask_val;
313
314 for (i = 0; i < l3->num_modules; i++) {
315 base = l3->l3_base[i];
316 flag_mux = l3->l3_flagmux[i];
317 if (!flag_mux->mask_app_bits && !flag_mux->mask_dbg_bits)
318 continue;
319
320 mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
321 (L3_APPLICATION_ERROR << 3);
322 mask_val = readl_relaxed(mask_regx);
323 mask_val &= ~(flag_mux->mask_app_bits);
324
325 writel_relaxed(mask_val, mask_regx);
326 mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
327 (L3_DEBUG_ERROR << 3);
328 mask_val = readl_relaxed(mask_regx);
329 mask_val &= ~(flag_mux->mask_dbg_bits);
330
331 writel_relaxed(mask_val, mask_regx);
332 }
333
334 /* Dummy read to force OCP barrier */
335 if (mask_regx)
336 (void)readl(mask_regx);
337
338 return 0;
339}
340
341static const struct dev_pm_ops l3_dev_pm_ops = {
Grygorii Strashko258d2a12015-04-27 21:24:31 +0300342 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, l3_resume_noirq)
Keerthy61b43d42014-11-10 23:49:47 +0530343};
344
345#define L3_DEV_PM_OPS (&l3_dev_pm_ops)
346#else
347#define L3_DEV_PM_OPS NULL
348#endif
349
Sricharan Rc10d5c92014-04-11 13:09:36 -0500350static struct platform_driver omap_l3_driver = {
351 .probe = omap_l3_probe,
Benoit Coussond039c5b2011-08-12 13:52:50 +0200352 .driver = {
353 .name = "omap_l3_noc",
Keerthy61b43d42014-11-10 23:49:47 +0530354 .pm = L3_DEV_PM_OPS,
Sricharan R06594522013-11-26 07:38:23 -0600355 .of_match_table = of_match_ptr(l3_noc_match),
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530356 },
357};
358
Sricharan Rc10d5c92014-04-11 13:09:36 -0500359static int __init omap_l3_init(void)
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530360{
Sricharan Rc10d5c92014-04-11 13:09:36 -0500361 return platform_driver_register(&omap_l3_driver);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530362}
Sricharan Rc10d5c92014-04-11 13:09:36 -0500363postcore_initcall_sync(omap_l3_init);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530364
Sricharan Rc10d5c92014-04-11 13:09:36 -0500365static void __exit omap_l3_exit(void)
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530366{
Sricharan Rc10d5c92014-04-11 13:09:36 -0500367 platform_driver_unregister(&omap_l3_driver);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530368}
Sricharan Rc10d5c92014-04-11 13:09:36 -0500369module_exit(omap_l3_exit);
Arnd Bergmannbe605662018-01-11 10:36:51 +0100370
371MODULE_AUTHOR("Santosh Shilimkar");
372MODULE_AUTHOR("Sricharan R");
373MODULE_DESCRIPTION("OMAP L3 Interconnect error handling driver");
374MODULE_LICENSE("GPL v2");