blob: b5b060adce8a60dbde7778f0765720bd4617e724 [file] [log] [blame]
Mischa Jonkera92a5d02013-04-18 11:40:39 +02001/*
2 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "skeleton.dtsi"
11
12/ {
13 compatible = "snps,nsimosci";
Mischa Jonker6eda4772013-05-16 19:36:08 +020014 clock-frequency = <20000000>; /* 20 MHZ */
Mischa Jonkera92a5d02013-04-18 11:40:39 +020015 #address-cells = <1>;
16 #size-cells = <1>;
Vineet Gupta9ba76482016-01-28 09:57:12 +053017 interrupt-parent = <&core_intc>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020018
19 chosen {
Vineet Gupta61fb4bf2014-04-05 15:30:22 +053020 /* this is for console on PGU */
21 /* bootargs = "console=tty0 consoleblank=0"; */
22 /* this is for console on serial */
Vineet Guptae8ef0602014-10-01 14:28:36 +053023 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug";
Mischa Jonkera92a5d02013-04-18 11:40:39 +020024 };
25
26 aliases {
27 serial0 = &uart0;
28 };
29
Mischa Jonkera92a5d02013-04-18 11:40:39 +020030 fpga {
31 compatible = "simple-bus";
32 #address-cells = <1>;
33 #size-cells = <1>;
34
35 /* child and parent address space 1:1 mapped */
36 ranges;
37
Vineet Guptab3d6aba2016-01-01 18:48:40 +053038 core_clk: core_clk {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <20000000>;
42 };
43
Vineet Gupta9ba76482016-01-28 09:57:12 +053044 core_intc: interrupt-controller {
Mischa Jonkera92a5d02013-04-18 11:40:39 +020045 compatible = "snps,arc700-intc";
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 };
49
Vineet Guptae8ef0602014-10-01 14:28:36 +053050 uart0: serial@f0000000 {
Mischa Jonker6eda4772013-05-16 19:36:08 +020051 compatible = "ns8250";
Vineet Guptae8ef0602014-10-01 14:28:36 +053052 reg = <0xf0000000 0x2000>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020053 interrupts = <11>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020054 clock-frequency = <3686400>;
55 baud = <115200>;
56 reg-shift = <2>;
57 reg-io-width = <4>;
Mischa Jonker6eda4772013-05-16 19:36:08 +020058 no-loopback-test = <1>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020059 };
60
Vineet Guptae8ef0602014-10-01 14:28:36 +053061 pgu0: pgu@f9000000 {
Mischa Jonkera92a5d02013-04-18 11:40:39 +020062 compatible = "snps,arcpgufb";
Vineet Guptae8ef0602014-10-01 14:28:36 +053063 reg = <0xf9000000 0x400>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020064 };
65
Vineet Guptae8ef0602014-10-01 14:28:36 +053066 ps2: ps2@f9001000 {
Mischa Jonkera92a5d02013-04-18 11:40:39 +020067 compatible = "snps,arc_ps2";
Vineet Guptae8ef0602014-10-01 14:28:36 +053068 reg = <0xf9000400 0x14>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020069 interrupts = <13>;
70 interrupt-names = "arc_ps2_irq";
71 };
72
Vineet Guptae8ef0602014-10-01 14:28:36 +053073 eth0: ethernet@f0003000 {
Lada Trimasovadf420fd2016-03-14 17:11:57 +030074 compatible = "ezchip,nps-mgt-enet";
Vineet Guptae8ef0602014-10-01 14:28:36 +053075 reg = <0xf0003000 0x44>;
Lada Trimasovadf420fd2016-03-14 17:11:57 +030076 interrupts = <7>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020077 };
78 };
79};