blob: 3ba843f5cdc0f91a789e536b876a0b4bb292e645 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov8e834c22010-12-25 22:44:01 +030011 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 * TODO
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
Joe Perches8d7b1c72011-01-31 08:39:24 -080017#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
Jeff Garzik669a5db2006-08-29 18:12:40 -040019#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
Jeff Garzik669a5db2006-08-29 18:12:40 -040022#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt37x"
Joe Perches8d7b1c72011-01-31 08:39:24 -080028#define DRV_VERSION "0.6.23"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30struct hpt_clock {
31 u8 xfer_speed;
32 u32 timing;
33};
34
35struct hpt_chip {
36 const char *name;
37 unsigned int base;
38 struct hpt_clock const *clocks[4];
39};
40
41/* key for bus clock timings
42 * bit
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040043 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
44 * cycles = value + 1
45 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
46 * cycles = value + 1
47 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040048 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040049 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040050 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040051 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
52 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
53 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
54 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040055 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040056 * 28 UDMA enable.
57 * 29 DMA enable.
58 * 30 PIO_MST enable. If set, the chip is in bus master mode during
59 * PIO xfer.
60 * 31 FIFO enable. Only for PIO.
Jeff Garzik669a5db2006-08-29 18:12:40 -040061 */
62
Alan Coxfcc2f692007-03-08 23:28:52 +000063static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040071
Alan Coxfcc2f692007-03-08 23:28:52 +000072 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040075
Alan Coxfcc2f692007-03-08 23:28:52 +000076 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
Jeff Garzik669a5db2006-08-29 18:12:40 -040081};
82
Alan Coxfcc2f692007-03-08 23:28:52 +000083static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040091
Alan Coxfcc2f692007-03-08 23:28:52 +000092 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040095
Alan Coxfcc2f692007-03-08 23:28:52 +000096 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101};
102
Alan Coxfcc2f692007-03-08 23:28:52 +0000103static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400111
Alan Coxfcc2f692007-03-08 23:28:52 +0000112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400115
Alan Coxfcc2f692007-03-08 23:28:52 +0000116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400121};
122
Jeff Garzik669a5db2006-08-29 18:12:40 -0400123
124static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000128 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129 NULL,
130 NULL,
Alan Coxa4734462007-04-26 00:19:25 -0700131 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132 }
133};
134
135static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000139 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000141 hpt37x_timings_50,
Alan Coxa4734462007-04-26 00:19:25 -0700142 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400143 }
144};
145
146static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000150 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400151 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000152 hpt37x_timings_50,
153 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154 }
155};
156
157static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000161 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000163 hpt37x_timings_50,
164 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165 }
166};
167
168static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000172 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400173 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000174 hpt37x_timings_50,
175 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400176 }
177};
178
179static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000183 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000185 hpt37x_timings_50,
186 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400187 }
188};
189
190static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000194 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195 NULL,
196 NULL,
197 NULL
198 }
199};
200
201/**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400209
Jeff Garzik669a5db2006-08-29 18:12:40 -0400210static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300214 while (clocks->xfer_speed) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221}
222
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300223static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
224 const char * const list[])
Jeff Garzik669a5db2006-08-29 18:12:40 -0400225{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900226 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400227 int i = 0;
228
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900229 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400230
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900231 while (list[i] != NULL) {
232 if (!strcmp(list[i], model_num)) {
Joe Perches8d7b1c72011-01-31 08:39:24 -0800233 pr_warn("%s is not supported for %s\n",
234 modestr, list[i]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400235 return 1;
236 }
237 i++;
238 }
239 return 0;
240}
241
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300242static const char * const bad_ata33[] = {
243 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
244 "Maxtor 90845U3", "Maxtor 90650U2",
245 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
246 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
247 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
248 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400249 "Maxtor 90510D4",
250 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300251 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
252 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
253 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
254 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400255 NULL
256};
257
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300258static const char * const bad_ata100_5[] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400259 "IBM-DTLA-307075",
260 "IBM-DTLA-307060",
261 "IBM-DTLA-307045",
262 "IBM-DTLA-307030",
263 "IBM-DTLA-307020",
264 "IBM-DTLA-307015",
265 "IBM-DTLA-305040",
266 "IBM-DTLA-305030",
267 "IBM-DTLA-305020",
268 "IC35L010AVER07-0",
269 "IC35L020AVER07-0",
270 "IC35L030AVER07-0",
271 "IC35L040AVER07-0",
272 "IC35L060AVER07-0",
273 "WDC AC310200R",
274 NULL
275};
276
277/**
278 * hpt370_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279 * @adev: ATA device
280 *
281 * Block UDMA on devices that cause trouble with this controller.
282 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400283
Alan Coxa76b62ca2007-03-09 09:34:07 -0500284static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400285{
Alan6929da442007-01-05 16:37:01 -0800286 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
288 mask &= ~ATA_MASK_UDMA;
289 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800290 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400291 }
Tejun Heoc7087652010-05-10 21:41:34 +0200292 return mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400293}
294
295/**
296 * hpt370a_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297 * @adev: ATA device
298 *
299 * Block UDMA on devices that cause trouble with this controller.
300 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400301
Alan Coxa76b62ca2007-03-09 09:34:07 -0500302static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400303{
Alan Cox73946f92007-11-05 22:53:38 +0000304 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400305 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800306 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400307 }
Tejun Heoc7087652010-05-10 21:41:34 +0200308 return mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400310
Jeff Garzik669a5db2006-08-29 18:12:40 -0400311/**
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300312 * hpt372_filter - mode selection filter
313 * @adev: ATA device
314 * @mask: mode mask
315 *
316 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
317 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
318 */
319static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
320{
321 if (ata_id_is_sata(adev->id))
322 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
323
324 return mask;
325}
326
327/**
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100328 * hpt37x_cable_detect - Detect the cable type
329 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400330 *
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100331 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400332 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400333
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100334static int hpt37x_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400335{
Jeff Garzik669a5db2006-08-29 18:12:40 -0400336 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100337 u8 scr2, ata66;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500338
Jeff Garzik669a5db2006-08-29 18:12:40 -0400339 pci_read_config_byte(pdev, 0x5B, &scr2);
340 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
Bartlomiej Zolnierkiewicz10a9c9692009-11-19 20:31:31 +0100341
342 udelay(10); /* debounce */
343
Jeff Garzik669a5db2006-08-29 18:12:40 -0400344 /* Cable register now active */
345 pci_read_config_byte(pdev, 0x5A, &ata66);
346 /* Restore state */
347 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400348
Alan Cox22d5c762007-11-19 14:39:13 +0000349 if (ata66 & (2 >> ap->port_no))
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100350 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400351 else
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100352 return ATA_CBL_PATA80;
353}
354
355/**
356 * hpt374_fn1_cable_detect - Detect the cable type
357 * @ap: ATA port to detect on
358 *
359 * Return the cable type attached to this port
360 */
361
362static int hpt374_fn1_cable_detect(struct ata_port *ap)
363{
364 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
365 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
366 u16 mcr3;
367 u8 ata66;
368
369 /* Do the extra channel work */
370 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
371 /* Set bit 15 of 0x52 to enable TCBLID as input */
372 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
373 pci_read_config_byte(pdev, 0x5A, &ata66);
374 /* Reset TCBLID/FCBLID to output */
375 pci_write_config_word(pdev, mcrbase + 2, mcr3);
376
377 if (ata66 & (2 >> ap->port_no))
378 return ATA_CBL_PATA40;
379 else
380 return ATA_CBL_PATA80;
381}
382
383/**
384 * hpt37x_pre_reset - reset the hpt37x bus
385 * @link: ATA link to reset
386 * @deadline: deadline jiffies for the operation
387 *
Bartlomiej Zolnierkiewiczab81a502009-11-19 19:12:24 +0100388 * Perform the initial reset handling for the HPT37x.
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100389 */
390
391static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
392{
393 struct ata_port *ap = link->ap;
394 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
395 static const struct pci_bits hpt37x_enable_bits[] = {
396 { 0x50, 1, 0x04, 0x04 },
397 { 0x54, 1, 0x04, 0x04 }
398 };
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300399
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100400 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
401 return -ENOENT;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400402
403 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000404 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400405 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400406
Tejun Heo9363c382008-04-07 22:47:16 +0900407 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400408}
409
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400410static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
411 u8 mode)
412{
413 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
414 u32 addr1, addr2;
415 u32 reg, timing, mask;
416 u8 fast;
417
418 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
419 addr2 = 0x51 + 4 * ap->port_no;
420
421 /* Fast interrupt prediction disable, hold off interrupt disable */
422 pci_read_config_byte(pdev, addr2, &fast);
423 fast &= ~0x02;
424 fast |= 0x01;
425 pci_write_config_byte(pdev, addr2, fast);
426
427 /* Determine timing mask and find matching mode entry */
428 if (mode < XFER_MW_DMA_0)
429 mask = 0xcfc3ffff;
430 else if (mode < XFER_UDMA_0)
431 mask = 0x31c001ff;
432 else
433 mask = 0x303c0000;
434
435 timing = hpt37x_find_mode(ap, mode);
436
437 pci_read_config_dword(pdev, addr1, &reg);
438 reg = (reg & ~mask) | (timing & mask);
439 pci_write_config_dword(pdev, addr1, reg);
440}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400441/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400442 * hpt370_set_piomode - PIO setup
443 * @ap: ATA interface
444 * @adev: device on the interface
445 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400446 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400447 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400448
Jeff Garzik669a5db2006-08-29 18:12:40 -0400449static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
450{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400451 hpt370_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400452}
453
454/**
455 * hpt370_set_dmamode - DMA timing setup
456 * @ap: ATA interface
457 * @adev: Device being configured
458 *
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400459 * Set up the channel for MWDMA or UDMA modes.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400460 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400461
Jeff Garzik669a5db2006-08-29 18:12:40 -0400462static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
463{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400464 hpt370_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400465}
466
467/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400468 * hpt370_bmdma_end - DMA engine stop
469 * @qc: ATA command
470 *
471 * Work around the HPT370 DMA engine.
472 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400473
Jeff Garzik669a5db2006-08-29 18:12:40 -0400474static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
475{
476 struct ata_port *ap = qc->ap;
477 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900478 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400479 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
480 u8 dma_cmd;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400481
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400482 if (dma_stat & ATA_DMA_ACTIVE) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400483 udelay(20);
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400484 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400485 }
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400486 if (dma_stat & ATA_DMA_ACTIVE) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400487 /* Clear the engine */
488 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
489 udelay(10);
490 /* Stop DMA */
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400491 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
492 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400493 /* Clear Error */
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400494 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
495 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
496 bmdma + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400497 /* Clear the engine */
498 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
499 udelay(10);
500 }
501 ata_bmdma_stop(qc);
502}
503
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400504static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
505 u8 mode)
506{
507 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
508 u32 addr1, addr2;
509 u32 reg, timing, mask;
510 u8 fast;
511
512 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
513 addr2 = 0x51 + 4 * ap->port_no;
514
515 /* Fast interrupt prediction disable, hold off interrupt disable */
516 pci_read_config_byte(pdev, addr2, &fast);
517 fast &= ~0x07;
518 pci_write_config_byte(pdev, addr2, fast);
519
520 /* Determine timing mask and find matching mode entry */
521 if (mode < XFER_MW_DMA_0)
522 mask = 0xcfc3ffff;
523 else if (mode < XFER_UDMA_0)
524 mask = 0x31c001ff;
525 else
526 mask = 0x303c0000;
527
528 timing = hpt37x_find_mode(ap, mode);
529
530 pci_read_config_dword(pdev, addr1, &reg);
531 reg = (reg & ~mask) | (timing & mask);
532 pci_write_config_dword(pdev, addr1, reg);
533}
534
Jeff Garzik669a5db2006-08-29 18:12:40 -0400535/**
536 * hpt372_set_piomode - PIO setup
537 * @ap: ATA interface
538 * @adev: device on the interface
539 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400540 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400541 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400542
Jeff Garzik669a5db2006-08-29 18:12:40 -0400543static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
544{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400545 hpt372_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400546}
547
548/**
549 * hpt372_set_dmamode - DMA timing setup
550 * @ap: ATA interface
551 * @adev: Device being configured
552 *
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400553 * Set up the channel for MWDMA or UDMA modes.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400554 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400555
Jeff Garzik669a5db2006-08-29 18:12:40 -0400556static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
557{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400558 hpt372_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400559}
560
561/**
562 * hpt37x_bmdma_end - DMA engine stop
563 * @qc: ATA command
564 *
565 * Clean up after the HPT372 and later DMA engine
566 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400567
Jeff Garzik669a5db2006-08-29 18:12:40 -0400568static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
569{
570 struct ata_port *ap = qc->ap;
571 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan6929da442007-01-05 16:37:01 -0800572 int mscreg = 0x50 + 4 * ap->port_no;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400573 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400574
Jeff Garzik669a5db2006-08-29 18:12:40 -0400575 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
576 pci_read_config_byte(pdev, mscreg, &msc_stat);
577 if (bwsr_stat & (1 << ap->port_no))
578 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
579 ata_bmdma_stop(qc);
580}
581
582
583static struct scsi_host_template hpt37x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900584 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400585};
586
587/*
588 * Configuration for HPT370
589 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400590
Jeff Garzik669a5db2006-08-29 18:12:40 -0400591static struct ata_port_operations hpt370_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900592 .inherits = &ata_bmdma_port_ops,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400593
Jeff Garzik669a5db2006-08-29 18:12:40 -0400594 .bmdma_stop = hpt370_bmdma_stop,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400595
Tejun Heo029cfd62008-03-25 12:22:49 +0900596 .mode_filter = hpt370_filter,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100597 .cable_detect = hpt37x_cable_detect,
Tejun Heo029cfd62008-03-25 12:22:49 +0900598 .set_piomode = hpt370_set_piomode,
599 .set_dmamode = hpt370_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900600 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400601};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400602
603/*
604 * Configuration for HPT370A. Close to 370 but less filters
605 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400606
Jeff Garzik669a5db2006-08-29 18:12:40 -0400607static struct ata_port_operations hpt370a_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900608 .inherits = &hpt370_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400609 .mode_filter = hpt370a_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400610};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400611
612/*
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300613 * Configuration for HPT371 and HPT302. Slightly different PIO and DMA
614 * mode setting functionality.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400615 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400616
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300617static struct ata_port_operations hpt302_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900618 .inherits = &ata_bmdma_port_ops,
619
620 .bmdma_stop = hpt37x_bmdma_stop,
621
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100622 .cable_detect = hpt37x_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400623 .set_piomode = hpt372_set_piomode,
624 .set_dmamode = hpt372_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900625 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400626};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400627
628/*
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300629 * Configuration for HPT372. Mode setting works like 371 and 302
630 * but we have a mode filter.
631 */
632
633static struct ata_port_operations hpt372_port_ops = {
634 .inherits = &hpt302_port_ops,
635 .mode_filter = hpt372_filter,
636};
637
638/*
639 * Configuration for HPT374. Mode setting and filtering works like 372
Tejun Heoa1efdab2008-03-25 12:22:50 +0900640 * but we have a different cable detection procedure for function 1.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400641 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400642
Tejun Heoa1efdab2008-03-25 12:22:50 +0900643static struct ata_port_operations hpt374_fn1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900644 .inherits = &hpt372_port_ops,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100645 .cable_detect = hpt374_fn1_cable_detect,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400646};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400647
648/**
Krzysztof Halasaad452d62009-09-20 16:22:51 +0200649 * hpt37x_clock_slot - Turn timing to PC clock entry
Jeff Garzik669a5db2006-08-29 18:12:40 -0400650 * @freq: Reported frequency timing
651 * @base: Base timing
652 *
653 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
654 * and 3 for 66Mhz)
655 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400656
Jeff Garzik669a5db2006-08-29 18:12:40 -0400657static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
658{
659 unsigned int f = (base * freq) / 192; /* Mhz */
660 if (f < 40)
661 return 0; /* 33Mhz slot */
662 if (f < 45)
663 return 1; /* 40Mhz slot */
664 if (f < 55)
665 return 2; /* 50Mhz slot */
666 return 3; /* 60Mhz slot */
667}
668
669/**
670 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400671 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400672 *
673 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
674 * succeeds
675 */
676
677static int hpt37x_calibrate_dpll(struct pci_dev *dev)
678{
679 u8 reg5b;
680 u32 reg5c;
681 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400682
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300683 for (tries = 0; tries < 0x5000; tries++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400684 udelay(50);
685 pci_read_config_byte(dev, 0x5b, &reg5b);
686 if (reg5b & 0x80) {
687 /* See if it stays set */
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300688 for (tries = 0; tries < 0x1000; tries++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400689 pci_read_config_byte(dev, 0x5b, &reg5b);
690 /* Failed ? */
691 if ((reg5b & 0x80) == 0)
692 return 0;
693 }
694 /* Turn off tuning, we have the DPLL set */
695 pci_read_config_dword(dev, 0x5c, &reg5c);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300696 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400697 return 1;
698 }
699 }
700 /* Never went stable */
701 return 0;
702}
Alan Cox73946f92007-11-05 22:53:38 +0000703
704static u32 hpt374_read_freq(struct pci_dev *pdev)
705{
706 u32 freq;
707 unsigned long io_base = pci_resource_start(pdev, 4);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300708
Alan Cox73946f92007-11-05 22:53:38 +0000709 if (PCI_FUNC(pdev->devfn) & 1) {
Andrew Morton40f46f12007-12-13 16:01:38 -0800710 struct pci_dev *pdev_0;
711
712 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
Alan Cox73946f92007-11-05 22:53:38 +0000713 /* Someone hot plugged the controller on us ? */
714 if (pdev_0 == NULL)
715 return 0;
716 io_base = pci_resource_start(pdev_0, 4);
717 freq = inl(io_base + 0x90);
718 pci_dev_put(pdev_0);
Andrew Morton40f46f12007-12-13 16:01:38 -0800719 } else
Alan Cox73946f92007-11-05 22:53:38 +0000720 freq = inl(io_base + 0x90);
721 return freq;
722}
723
Jeff Garzik669a5db2006-08-29 18:12:40 -0400724/**
725 * hpt37x_init_one - Initialise an HPT37X/302
726 * @dev: PCI device
727 * @id: Entry in match table
728 *
729 * Initialise an HPT37x device. There are some interesting complications
730 * here. Firstly the chip may report 366 and be one of several variants.
731 * Secondly all the timings depend on the clock for the chip which we must
732 * detect and look up
733 *
734 * This is the known chip mappings. It may be missing a couple of later
735 * releases.
736 *
737 * Chip version PCI Rev Notes
738 * HPT366 4 (HPT366) 0 Other driver
739 * HPT366 4 (HPT366) 1 Other driver
740 * HPT368 4 (HPT366) 2 Other driver
741 * HPT370 4 (HPT366) 3 UDMA100
742 * HPT370A 4 (HPT366) 4 UDMA100
743 * HPT372 4 (HPT366) 5 UDMA133 (1)
744 * HPT372N 4 (HPT366) 6 Other driver
745 * HPT372A 5 (HPT372) 1 UDMA133 (1)
746 * HPT372N 5 (HPT372) 2 Other driver
747 * HPT302 6 (HPT302) 1 UDMA133
748 * HPT302N 6 (HPT302) 2 Other driver
749 * HPT371 7 (HPT371) * UDMA133
750 * HPT374 8 (HPT374) * UDMA133 4 channel
751 * HPT372N 9 (HPT372N) * Other driver
752 *
753 * (1) UDMA133 support depends on the bus clock
754 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400755
Jeff Garzik669a5db2006-08-29 18:12:40 -0400756static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
757{
758 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200759 static const struct ata_port_info info_hpt370 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400760 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100761 .pio_mask = ATA_PIO4,
762 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400763 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400764 .port_ops = &hpt370_port_ops
765 };
766 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200767 static const struct ata_port_info info_hpt370a = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400768 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100769 .pio_mask = ATA_PIO4,
770 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400771 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400772 .port_ops = &hpt370a_port_ops
773 };
Sergei Shtylyovfc2698d52011-01-05 21:59:49 +0300774 /* HPT370 - UDMA66 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200775 static const struct ata_port_info info_hpt370_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400776 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100777 .pio_mask = ATA_PIO4,
778 .mwdma_mask = ATA_MWDMA2,
Sergei Shtylyovfc2698d52011-01-05 21:59:49 +0300779 .udma_mask = ATA_UDMA4,
Alan Coxfcc2f692007-03-08 23:28:52 +0000780 .port_ops = &hpt370_port_ops
781 };
Sergei Shtylyovfc2698d52011-01-05 21:59:49 +0300782 /* HPT370A - UDMA66 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200783 static const struct ata_port_info info_hpt370a_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400784 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100785 .pio_mask = ATA_PIO4,
786 .mwdma_mask = ATA_MWDMA2,
Sergei Shtylyovfc2698d52011-01-05 21:59:49 +0300787 .udma_mask = ATA_UDMA4,
Alan Coxfcc2f692007-03-08 23:28:52 +0000788 .port_ops = &hpt370a_port_ops
789 };
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300790 /* HPT372 - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200791 static const struct ata_port_info info_hpt372 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400792 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100793 .pio_mask = ATA_PIO4,
794 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400795 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400796 .port_ops = &hpt372_port_ops
797 };
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300798 /* HPT371, 302 - UDMA133 */
799 static const struct ata_port_info info_hpt302 = {
800 .flags = ATA_FLAG_SLAVE_POSS,
801 .pio_mask = ATA_PIO4,
802 .mwdma_mask = ATA_MWDMA2,
803 .udma_mask = ATA_UDMA6,
804 .port_ops = &hpt302_port_ops
805 };
Sergei Shtylyovdefed552011-01-11 21:01:23 +0300806 /* HPT374 - UDMA100, function 1 uses different cable_detect method */
Tejun Heoa1efdab2008-03-25 12:22:50 +0900807 static const struct ata_port_info info_hpt374_fn0 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400808 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100809 .pio_mask = ATA_PIO4,
810 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400811 .udma_mask = ATA_UDMA5,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900812 .port_ops = &hpt372_port_ops
813 };
814 static const struct ata_port_info info_hpt374_fn1 = {
815 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100816 .pio_mask = ATA_PIO4,
817 .mwdma_mask = ATA_MWDMA2,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900818 .udma_mask = ATA_UDMA5,
819 .port_ops = &hpt374_fn1_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400820 };
821
822 static const int MHz[4] = { 33, 40, 50, 66 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200823 void *private_data = NULL;
Tejun Heo887125e2008-03-25 12:22:49 +0900824 const struct ata_port_info *ppi[] = { NULL, NULL };
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400825 u8 rev = dev->revision;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400826 u8 irqmask;
Alan Coxfcc2f692007-03-08 23:28:52 +0000827 u8 mcr1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400828 u32 freq;
Alan Coxfcc2f692007-03-08 23:28:52 +0000829 int prefer_dpll = 1;
Jeff Garzika617c092007-05-21 20:14:23 -0400830
Alan Coxfcc2f692007-03-08 23:28:52 +0000831 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400832
833 const struct hpt_chip *chip_table;
834 int clock_slot;
Tejun Heof08048e2008-03-25 12:22:47 +0900835 int rc;
836
837 rc = pcim_enable_device(dev);
838 if (rc)
839 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400840
Sergei Shtylyov910f7bb2011-01-10 22:31:13 +0300841 switch (dev->device) {
842 case PCI_DEVICE_ID_TTI_HPT366:
Jeff Garzik669a5db2006-08-29 18:12:40 -0400843 /* May be a later chip in disguise. Check */
844 /* Older chips are in the HPT366 driver. Ignore them */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400845 if (rev < 3)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400846 return -ENODEV;
847 /* N series chips have their own driver. Ignore */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400848 if (rev == 6)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400849 return -ENODEV;
850
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300851 switch (rev) {
852 case 3:
853 ppi[0] = &info_hpt370;
854 chip_table = &hpt370;
855 prefer_dpll = 0;
856 break;
857 case 4:
858 ppi[0] = &info_hpt370a;
859 chip_table = &hpt370a;
860 prefer_dpll = 0;
861 break;
862 case 5:
863 ppi[0] = &info_hpt372;
864 chip_table = &hpt372;
865 break;
866 default:
Joe Perches8d7b1c72011-01-31 08:39:24 -0800867 pr_err("Unknown HPT366 subtype, please report (%d)\n",
868 rev);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300869 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400870 }
Sergei Shtylyov910f7bb2011-01-10 22:31:13 +0300871 break;
872 case PCI_DEVICE_ID_TTI_HPT372:
873 /* 372N if rev >= 2 */
874 if (rev >= 2)
875 return -ENODEV;
876 ppi[0] = &info_hpt372;
877 chip_table = &hpt372a;
878 break;
879 case PCI_DEVICE_ID_TTI_HPT302:
880 /* 302N if rev > 1 */
881 if (rev > 1)
882 return -ENODEV;
883 ppi[0] = &info_hpt302;
884 /* Check this */
885 chip_table = &hpt302;
886 break;
887 case PCI_DEVICE_ID_TTI_HPT371:
888 if (rev > 1)
889 return -ENODEV;
890 ppi[0] = &info_hpt302;
891 chip_table = &hpt371;
892 /*
893 * Single channel device, master is not present but the BIOS
894 * (or us for non x86) must mark it absent
895 */
896 pci_read_config_byte(dev, 0x50, &mcr1);
897 mcr1 &= ~0x04;
898 pci_write_config_byte(dev, 0x50, mcr1);
899 break;
900 case PCI_DEVICE_ID_TTI_HPT374:
901 chip_table = &hpt374;
902 if (!(PCI_FUNC(dev->devfn) & 1))
903 *ppi = &info_hpt374_fn0;
904 else
905 *ppi = &info_hpt374_fn1;
906 break;
907 default:
Joe Perches8d7b1c72011-01-31 08:39:24 -0800908 pr_err("PCI table is bogus, please report (%d)\n", dev->device);
Sergei Shtylyov910f7bb2011-01-10 22:31:13 +0300909 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400910 }
911 /* Ok so this is a chip we support */
912
913 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
914 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
915 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
916 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
917
918 pci_read_config_byte(dev, 0x5A, &irqmask);
919 irqmask &= ~0x10;
920 pci_write_config_byte(dev, 0x5a, irqmask);
921
922 /*
923 * default to pci clock. make sure MA15/16 are set to output
924 * to prevent drives having problems with 40-pin cables. Needed
925 * for some drives such as IBM-DTLA which will not enter ready
926 * state on reset when PDIAG is a input.
927 */
928
Jeff Garzik85cd7252006-08-31 00:03:49 -0400929 pci_write_config_byte(dev, 0x5b, 0x23);
Jeff Garzika617c092007-05-21 20:14:23 -0400930
Alan Coxfcc2f692007-03-08 23:28:52 +0000931 /*
932 * HighPoint does this for HPT372A.
933 * NOTE: This register is only writeable via I/O space.
934 */
935 if (chip_table == &hpt372a)
936 outb(0x0e, iobase + 0x9c);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400937
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300938 /*
939 * Some devices do not let this value be accessed via PCI space
940 * according to the old driver. In addition we must use the value
941 * from FN 0 on the HPT374.
942 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000943
Alan Cox73946f92007-11-05 22:53:38 +0000944 if (chip_table == &hpt374) {
945 freq = hpt374_read_freq(dev);
946 if (freq == 0)
947 return -ENODEV;
948 } else
949 freq = inl(iobase + 0x90);
950
Jeff Garzik669a5db2006-08-29 18:12:40 -0400951 if ((freq >> 12) != 0xABCDE) {
952 int i;
953 u8 sr;
954 u32 total = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400955
Joe Perches8d7b1c72011-01-31 08:39:24 -0800956 pr_warn("BIOS has not set timing clocks\n");
Jeff Garzik85cd7252006-08-31 00:03:49 -0400957
Jeff Garzik669a5db2006-08-29 18:12:40 -0400958 /* This is the process the HPT371 BIOS is reported to use */
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300959 for (i = 0; i < 128; i++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400960 pci_read_config_byte(dev, 0x78, &sr);
Alan Coxfcc2f692007-03-08 23:28:52 +0000961 total += sr & 0x1FF;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400962 udelay(15);
963 }
964 freq = total / 128;
965 }
966 freq &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400967
Jeff Garzik669a5db2006-08-29 18:12:40 -0400968 /*
969 * Turn the frequency check into a band and then find a timing
970 * table to match it.
971 */
Jeff Garzika617c092007-05-21 20:14:23 -0400972
Jeff Garzik669a5db2006-08-29 18:12:40 -0400973 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
Alan Coxfcc2f692007-03-08 23:28:52 +0000974 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400975 /*
976 * We need to try PLL mode instead
Alan Coxfcc2f692007-03-08 23:28:52 +0000977 *
978 * For non UDMA133 capable devices we should
979 * use a 50MHz DPLL by choice
Jeff Garzik669a5db2006-08-29 18:12:40 -0400980 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000981 unsigned int f_low, f_high;
Alan Cox960c8a12007-05-25 20:48:55 +0100982 int dpll, adjust;
Jeff Garzika617c092007-05-21 20:14:23 -0400983
Alan Cox960c8a12007-05-25 20:48:55 +0100984 /* Compute DPLL */
Tejun Heo887125e2008-03-25 12:22:49 +0900985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
Jeff Garzika617c092007-05-21 20:14:23 -0400986
Alan Cox960c8a12007-05-25 20:48:55 +0100987 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
Alan Coxfcc2f692007-03-08 23:28:52 +0000988 f_high = f_low + 2;
Alan Cox960c8a12007-05-25 20:48:55 +0100989 if (clock_slot > 1)
990 f_high += 2;
Alan Coxfcc2f692007-03-08 23:28:52 +0000991
992 /* Select the DPLL clock. */
993 pci_write_config_byte(dev, 0x5b, 0x21);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300994 pci_write_config_dword(dev, 0x5C,
995 (f_high << 16) | f_low | 0x100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400996
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300997 for (adjust = 0; adjust < 8; adjust++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400998 if (hpt37x_calibrate_dpll(dev))
999 break;
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001000 /*
1001 * See if it'll settle at a fractionally
1002 * different clock
1003 */
Alan Cox64a81702007-07-24 15:17:48 +01001004 if (adjust & 1)
1005 f_low -= adjust >> 1;
1006 else
1007 f_high += adjust >> 1;
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001008 pci_write_config_dword(dev, 0x5C,
1009 (f_high << 16) | f_low | 0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001010 }
1011 if (adjust == 8) {
Joe Perches8d7b1c72011-01-31 08:39:24 -08001012 pr_err("DPLL did not stabilize!\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -04001013 return -ENODEV;
1014 }
Alan Cox960c8a12007-05-25 20:48:55 +01001015 if (dpll == 3)
Tejun Heo1626aeb2007-05-04 12:43:58 +02001016 private_data = (void *)hpt37x_timings_66;
Alan Coxfcc2f692007-03-08 23:28:52 +00001017 else
Tejun Heo1626aeb2007-05-04 12:43:58 +02001018 private_data = (void *)hpt37x_timings_50;
Jeff Garzik85cd7252006-08-31 00:03:49 -04001019
Joe Perches8d7b1c72011-01-31 08:39:24 -08001020 pr_info("bus clock %dMHz, using %dMHz DPLL\n",
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +03001021 MHz[clock_slot], MHz[dpll]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001022 } else {
Tejun Heo1626aeb2007-05-04 12:43:58 +02001023 private_data = (void *)chip_table->clocks[clock_slot];
Jeff Garzik669a5db2006-08-29 18:12:40 -04001024 /*
Alan Coxa4734462007-04-26 00:19:25 -07001025 * Perform a final fixup. Note that we will have used the
1026 * DPLL on the HPT372 which means we don't have to worry
1027 * about lack of UDMA133 support on lower clocks
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001028 */
Jeff Garzik85cd7252006-08-31 00:03:49 -04001029
Tejun Heo887125e2008-03-25 12:22:49 +09001030 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1031 ppi[0] = &info_hpt370_33;
1032 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1033 ppi[0] = &info_hpt370a_33;
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +03001034
Joe Perches8d7b1c72011-01-31 08:39:24 -08001035 pr_info("%s using %dMHz bus clock\n",
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +03001036 chip_table->name, MHz[clock_slot]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001037 }
Alan Coxfcc2f692007-03-08 23:28:52 +00001038
Jeff Garzik669a5db2006-08-29 18:12:40 -04001039 /* Now kick off ATA set up */
Tejun Heo1c5afdf2010-05-19 22:10:22 +02001040 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001041}
1042
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001043static const struct pci_device_id hpt37x[] = {
1044 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1045 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1046 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1047 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1048 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1049
1050 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -04001051};
1052
1053static struct pci_driver hpt37x_pci_driver = {
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001054 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001055 .id_table = hpt37x,
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001056 .probe = hpt37x_init_one,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001057 .remove = ata_pci_remove_one
1058};
1059
Axel Lin2fc75da2012-04-19 13:43:05 +08001060module_pci_driver(hpt37x_pci_driver);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001061
Jeff Garzik669a5db2006-08-29 18:12:40 -04001062MODULE_AUTHOR("Alan Cox");
1063MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1064MODULE_LICENSE("GPL");
1065MODULE_DEVICE_TABLE(pci, hpt37x);
1066MODULE_VERSION(DRV_VERSION);