Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | // Copyright IBM Corp |
| 3 | // Copyright ASPEED Technology |
| 4 | |
| 5 | #define pr_fmt(fmt) "clk-ast2600: " fmt |
| 6 | |
| 7 | #include <linux/mfd/syscon.h> |
| 8 | #include <linux/of_address.h> |
| 9 | #include <linux/of_device.h> |
| 10 | #include <linux/platform_device.h> |
| 11 | #include <linux/regmap.h> |
| 12 | #include <linux/slab.h> |
| 13 | |
| 14 | #include <dt-bindings/clock/ast2600-clock.h> |
| 15 | |
| 16 | #include "clk-aspeed.h" |
| 17 | |
Andrew Jeffery | 3696eeb | 2019-10-10 12:37:25 +1030 | [diff] [blame] | 18 | #define ASPEED_G6_NUM_CLKS 71 |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 19 | |
Ryan Chen | 6286ce1 | 2021-01-19 14:17:15 +0800 | [diff] [blame] | 20 | #define ASPEED_G6_SILICON_REV 0x014 |
| 21 | #define CHIP_REVISION_ID GENMASK(23, 16) |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 22 | |
| 23 | #define ASPEED_G6_RESET_CTRL 0x040 |
| 24 | #define ASPEED_G6_RESET_CTRL2 0x050 |
| 25 | |
| 26 | #define ASPEED_G6_CLK_STOP_CTRL 0x080 |
| 27 | #define ASPEED_G6_CLK_STOP_CTRL2 0x090 |
| 28 | |
| 29 | #define ASPEED_G6_MISC_CTRL 0x0C0 |
| 30 | #define UART_DIV13_EN BIT(12) |
| 31 | |
| 32 | #define ASPEED_G6_CLK_SELECTION1 0x300 |
| 33 | #define ASPEED_G6_CLK_SELECTION2 0x304 |
| 34 | #define ASPEED_G6_CLK_SELECTION4 0x310 |
| 35 | |
| 36 | #define ASPEED_HPLL_PARAM 0x200 |
| 37 | #define ASPEED_APLL_PARAM 0x210 |
| 38 | #define ASPEED_MPLL_PARAM 0x220 |
| 39 | #define ASPEED_EPLL_PARAM 0x240 |
| 40 | #define ASPEED_DPLL_PARAM 0x260 |
| 41 | |
| 42 | #define ASPEED_G6_STRAP1 0x500 |
| 43 | |
Andrew Jeffery | 3696eeb | 2019-10-10 12:37:25 +1030 | [diff] [blame] | 44 | #define ASPEED_MAC12_CLK_DLY 0x340 |
| 45 | #define ASPEED_MAC34_CLK_DLY 0x350 |
| 46 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 47 | /* Globally visible clocks */ |
| 48 | static DEFINE_SPINLOCK(aspeed_g6_clk_lock); |
| 49 | |
| 50 | /* Keeps track of all clocks */ |
| 51 | static struct clk_hw_onecell_data *aspeed_g6_clk_data; |
| 52 | |
| 53 | static void __iomem *scu_g6_base; |
Joel Stanley | f45c5b1 | 2021-09-23 09:24:49 +0930 | [diff] [blame] | 54 | /* AST2600 revision: A0, A1, A2, etc */ |
| 55 | static u8 soc_rev; |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 56 | |
| 57 | /* |
| 58 | * Clocks marked with CLK_IS_CRITICAL: |
| 59 | * |
| 60 | * ref0 and ref1 are essential for the SoC to operate |
| 61 | * mpll is required if SDRAM is used |
| 62 | */ |
| 63 | static const struct aspeed_gate_data aspeed_g6_gates[] = { |
| 64 | /* clk rst name parent flags */ |
| 65 | [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ |
Jae Hyun Yoo | 3536169 | 2020-12-21 23:32:25 +0100 | [diff] [blame] | 66 | [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */ |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 67 | [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ |
| 68 | /* vclk parent - dclk/d1clk/hclk/mclk */ |
Jae Hyun Yoo | 3536169 | 2020-12-21 23:32:25 +0100 | [diff] [blame] | 69 | [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */ |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 70 | [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ |
| 71 | /* From dpll */ |
| 72 | [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ |
| 73 | [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL }, |
| 74 | [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ |
| 75 | /* Reserved 8 */ |
| 76 | [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ |
| 77 | /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */ |
| 78 | [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */ |
| 79 | /* Reserved 11/12 */ |
| 80 | [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ |
| 81 | [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ |
| 82 | [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ |
| 83 | /* Reserved 16/19 */ |
| 84 | [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */ |
| 85 | [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */ |
| 86 | /* Reserved 22/23 */ |
| 87 | [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */ |
| 88 | [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */ |
| 89 | /* Reserved 26 */ |
| 90 | [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */ |
| 91 | /* Reserved 28/29/30 */ |
| 92 | [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */ |
| 93 | [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ |
| 94 | [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL }, |
| 95 | /* Reserved 35 */ |
| 96 | [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ |
| 97 | [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ |
| 98 | /* Reserved 38 RSA: no longer used */ |
| 99 | /* Reserved 39 */ |
| 100 | [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */ |
| 101 | [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */ |
| 102 | [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */ |
| 103 | [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */ |
| 104 | [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */ |
| 105 | [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */ |
| 106 | [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */ |
| 107 | [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */ |
| 108 | [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ |
| 109 | [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ |
| 110 | [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ |
| 111 | [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ |
| 112 | [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */ |
| 113 | [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */ |
| 114 | [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */ |
| 115 | [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */ |
| 116 | [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */ |
| 117 | [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */ |
| 118 | [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */ |
| 119 | [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */ |
| 120 | [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */ |
| 121 | [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */ |
| 122 | [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */ |
| 123 | }; |
| 124 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 125 | static const struct clk_div_table ast2600_eclk_div_table[] = { |
| 126 | { 0x0, 2 }, |
| 127 | { 0x1, 2 }, |
| 128 | { 0x2, 3 }, |
| 129 | { 0x3, 4 }, |
| 130 | { 0x4, 5 }, |
| 131 | { 0x5, 6 }, |
| 132 | { 0x6, 7 }, |
| 133 | { 0x7, 8 }, |
| 134 | { 0 } |
| 135 | }; |
| 136 | |
Eddie James | c2407ab | 2020-07-09 14:57:05 -0500 | [diff] [blame] | 137 | static const struct clk_div_table ast2600_emmc_extclk_div_table[] = { |
| 138 | { 0x0, 2 }, |
| 139 | { 0x1, 4 }, |
| 140 | { 0x2, 6 }, |
| 141 | { 0x3, 8 }, |
| 142 | { 0x4, 10 }, |
| 143 | { 0x5, 12 }, |
| 144 | { 0x6, 14 }, |
| 145 | { 0x7, 16 }, |
| 146 | { 0 } |
| 147 | }; |
| 148 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 149 | static const struct clk_div_table ast2600_mac_div_table[] = { |
| 150 | { 0x0, 4 }, |
| 151 | { 0x1, 4 }, |
| 152 | { 0x2, 6 }, |
| 153 | { 0x3, 8 }, |
| 154 | { 0x4, 10 }, |
| 155 | { 0x5, 12 }, |
| 156 | { 0x6, 14 }, |
| 157 | { 0x7, 16 }, |
| 158 | { 0 } |
| 159 | }; |
| 160 | |
| 161 | static const struct clk_div_table ast2600_div_table[] = { |
| 162 | { 0x0, 4 }, |
| 163 | { 0x1, 8 }, |
| 164 | { 0x2, 12 }, |
| 165 | { 0x3, 16 }, |
| 166 | { 0x4, 20 }, |
| 167 | { 0x5, 24 }, |
| 168 | { 0x6, 28 }, |
| 169 | { 0x7, 32 }, |
| 170 | { 0 } |
| 171 | }; |
| 172 | |
| 173 | /* For hpll/dpll/epll/mpll */ |
| 174 | static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) |
| 175 | { |
| 176 | unsigned int mult, div; |
| 177 | |
| 178 | if (val & BIT(24)) { |
| 179 | /* Pass through mode */ |
| 180 | mult = div = 1; |
| 181 | } else { |
| 182 | /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ |
| 183 | u32 m = val & 0x1fff; |
| 184 | u32 n = (val >> 13) & 0x3f; |
| 185 | u32 p = (val >> 19) & 0xf; |
| 186 | mult = (m + 1) / (n + 1); |
| 187 | div = (p + 1); |
| 188 | } |
| 189 | return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, |
| 190 | mult, div); |
| 191 | }; |
| 192 | |
| 193 | static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) |
| 194 | { |
| 195 | unsigned int mult, div; |
| 196 | |
Joel Stanley | f45c5b1 | 2021-09-23 09:24:49 +0930 | [diff] [blame] | 197 | if (soc_rev >= 2) { |
Ryan Chen | 6286ce1 | 2021-01-19 14:17:15 +0800 | [diff] [blame] | 198 | if (val & BIT(24)) { |
| 199 | /* Pass through mode */ |
| 200 | mult = div = 1; |
| 201 | } else { |
| 202 | /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ |
| 203 | u32 m = val & 0x1fff; |
| 204 | u32 n = (val >> 13) & 0x3f; |
| 205 | u32 p = (val >> 19) & 0xf; |
| 206 | |
| 207 | mult = (m + 1); |
| 208 | div = (n + 1) * (p + 1); |
| 209 | } |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 210 | } else { |
Ryan Chen | 6286ce1 | 2021-01-19 14:17:15 +0800 | [diff] [blame] | 211 | if (val & BIT(20)) { |
| 212 | /* Pass through mode */ |
| 213 | mult = div = 1; |
| 214 | } else { |
| 215 | /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ |
| 216 | u32 m = (val >> 5) & 0x3f; |
| 217 | u32 od = (val >> 4) & 0x1; |
| 218 | u32 n = val & 0xf; |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 219 | |
Ryan Chen | 6286ce1 | 2021-01-19 14:17:15 +0800 | [diff] [blame] | 220 | mult = (2 - od) * (m + 2); |
| 221 | div = n + 1; |
| 222 | } |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 223 | } |
| 224 | return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, |
| 225 | mult, div); |
| 226 | }; |
| 227 | |
| 228 | static u32 get_bit(u8 idx) |
| 229 | { |
| 230 | return BIT(idx % 32); |
| 231 | } |
| 232 | |
| 233 | static u32 get_reset_reg(struct aspeed_clk_gate *gate) |
| 234 | { |
| 235 | if (gate->reset_idx < 32) |
| 236 | return ASPEED_G6_RESET_CTRL; |
| 237 | |
| 238 | return ASPEED_G6_RESET_CTRL2; |
| 239 | } |
| 240 | |
| 241 | static u32 get_clock_reg(struct aspeed_clk_gate *gate) |
| 242 | { |
| 243 | if (gate->clock_idx < 32) |
| 244 | return ASPEED_G6_CLK_STOP_CTRL; |
| 245 | |
| 246 | return ASPEED_G6_CLK_STOP_CTRL2; |
| 247 | } |
| 248 | |
| 249 | static int aspeed_g6_clk_is_enabled(struct clk_hw *hw) |
| 250 | { |
| 251 | struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); |
| 252 | u32 clk = get_bit(gate->clock_idx); |
| 253 | u32 rst = get_bit(gate->reset_idx); |
| 254 | u32 reg; |
| 255 | u32 enval; |
| 256 | |
| 257 | /* |
| 258 | * If the IP is in reset, treat the clock as not enabled, |
| 259 | * this happens with some clocks such as the USB one when |
| 260 | * coming from cold reset. Without this, aspeed_clk_enable() |
| 261 | * will fail to lift the reset. |
| 262 | */ |
| 263 | if (gate->reset_idx >= 0) { |
| 264 | regmap_read(gate->map, get_reset_reg(gate), ®); |
| 265 | |
| 266 | if (reg & rst) |
| 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | regmap_read(gate->map, get_clock_reg(gate), ®); |
| 271 | |
| 272 | enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; |
| 273 | |
| 274 | return ((reg & clk) == enval) ? 1 : 0; |
| 275 | } |
| 276 | |
| 277 | static int aspeed_g6_clk_enable(struct clk_hw *hw) |
| 278 | { |
| 279 | struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); |
| 280 | unsigned long flags; |
| 281 | u32 clk = get_bit(gate->clock_idx); |
| 282 | u32 rst = get_bit(gate->reset_idx); |
| 283 | |
| 284 | spin_lock_irqsave(gate->lock, flags); |
| 285 | |
| 286 | if (aspeed_g6_clk_is_enabled(hw)) { |
| 287 | spin_unlock_irqrestore(gate->lock, flags); |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | if (gate->reset_idx >= 0) { |
| 292 | /* Put IP in reset */ |
| 293 | regmap_write(gate->map, get_reset_reg(gate), rst); |
| 294 | /* Delay 100us */ |
| 295 | udelay(100); |
| 296 | } |
| 297 | |
| 298 | /* Enable clock */ |
| 299 | if (gate->flags & CLK_GATE_SET_TO_DISABLE) { |
Joel Stanley | 427400f | 2019-10-16 23:43:19 +1030 | [diff] [blame] | 300 | /* Clock is clear to enable, so use set to clear register */ |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 301 | regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); |
Joel Stanley | 427400f | 2019-10-16 23:43:19 +1030 | [diff] [blame] | 302 | } else { |
| 303 | /* Clock is set to enable, so use write to set register */ |
| 304 | regmap_write(gate->map, get_clock_reg(gate), clk); |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | if (gate->reset_idx >= 0) { |
| 308 | /* A delay of 10ms is specified by the ASPEED docs */ |
| 309 | mdelay(10); |
| 310 | /* Take IP out of reset */ |
| 311 | regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); |
| 312 | } |
| 313 | |
| 314 | spin_unlock_irqrestore(gate->lock, flags); |
| 315 | |
| 316 | return 0; |
| 317 | } |
| 318 | |
| 319 | static void aspeed_g6_clk_disable(struct clk_hw *hw) |
| 320 | { |
| 321 | struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); |
| 322 | unsigned long flags; |
| 323 | u32 clk = get_bit(gate->clock_idx); |
| 324 | |
| 325 | spin_lock_irqsave(gate->lock, flags); |
| 326 | |
| 327 | if (gate->flags & CLK_GATE_SET_TO_DISABLE) { |
| 328 | regmap_write(gate->map, get_clock_reg(gate), clk); |
| 329 | } else { |
| 330 | /* Use set to clear register */ |
| 331 | regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); |
| 332 | } |
| 333 | |
| 334 | spin_unlock_irqrestore(gate->lock, flags); |
| 335 | } |
| 336 | |
| 337 | static const struct clk_ops aspeed_g6_clk_gate_ops = { |
| 338 | .enable = aspeed_g6_clk_enable, |
| 339 | .disable = aspeed_g6_clk_disable, |
| 340 | .is_enabled = aspeed_g6_clk_is_enabled, |
| 341 | }; |
| 342 | |
| 343 | static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev, |
| 344 | unsigned long id) |
| 345 | { |
| 346 | struct aspeed_reset *ar = to_aspeed_reset(rcdev); |
| 347 | u32 rst = get_bit(id); |
| 348 | u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; |
| 349 | |
| 350 | /* Use set to clear register */ |
| 351 | return regmap_write(ar->map, reg + 0x04, rst); |
| 352 | } |
| 353 | |
| 354 | static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev, |
| 355 | unsigned long id) |
| 356 | { |
| 357 | struct aspeed_reset *ar = to_aspeed_reset(rcdev); |
| 358 | u32 rst = get_bit(id); |
| 359 | u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; |
| 360 | |
| 361 | return regmap_write(ar->map, reg, rst); |
| 362 | } |
| 363 | |
| 364 | static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev, |
| 365 | unsigned long id) |
| 366 | { |
| 367 | struct aspeed_reset *ar = to_aspeed_reset(rcdev); |
| 368 | int ret; |
| 369 | u32 val; |
| 370 | u32 rst = get_bit(id); |
| 371 | u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; |
| 372 | |
| 373 | ret = regmap_read(ar->map, reg, &val); |
| 374 | if (ret) |
| 375 | return ret; |
| 376 | |
| 377 | return !!(val & rst); |
| 378 | } |
| 379 | |
| 380 | static const struct reset_control_ops aspeed_g6_reset_ops = { |
| 381 | .assert = aspeed_g6_reset_assert, |
| 382 | .deassert = aspeed_g6_reset_deassert, |
| 383 | .status = aspeed_g6_reset_status, |
| 384 | }; |
| 385 | |
| 386 | static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev, |
| 387 | const char *name, const char *parent_name, unsigned long flags, |
| 388 | struct regmap *map, u8 clock_idx, u8 reset_idx, |
| 389 | u8 clk_gate_flags, spinlock_t *lock) |
| 390 | { |
| 391 | struct aspeed_clk_gate *gate; |
| 392 | struct clk_init_data init; |
| 393 | struct clk_hw *hw; |
| 394 | int ret; |
| 395 | |
| 396 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
| 397 | if (!gate) |
| 398 | return ERR_PTR(-ENOMEM); |
| 399 | |
| 400 | init.name = name; |
| 401 | init.ops = &aspeed_g6_clk_gate_ops; |
| 402 | init.flags = flags; |
| 403 | init.parent_names = parent_name ? &parent_name : NULL; |
| 404 | init.num_parents = parent_name ? 1 : 0; |
| 405 | |
| 406 | gate->map = map; |
| 407 | gate->clock_idx = clock_idx; |
| 408 | gate->reset_idx = reset_idx; |
| 409 | gate->flags = clk_gate_flags; |
| 410 | gate->lock = lock; |
| 411 | gate->hw.init = &init; |
| 412 | |
| 413 | hw = &gate->hw; |
| 414 | ret = clk_hw_register(dev, hw); |
| 415 | if (ret) { |
| 416 | kfree(gate); |
| 417 | hw = ERR_PTR(ret); |
| 418 | } |
| 419 | |
| 420 | return hw; |
| 421 | } |
| 422 | |
Eddie James | c2407ab | 2020-07-09 14:57:05 -0500 | [diff] [blame] | 423 | static const char *const emmc_extclk_parent_names[] = { |
| 424 | "emmc_extclk_hpll_in", |
| 425 | "mpll", |
| 426 | }; |
| 427 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 428 | static const char * const vclk_parent_names[] = { |
| 429 | "dpll", |
| 430 | "d1pll", |
| 431 | "hclk", |
| 432 | "mclk", |
| 433 | }; |
| 434 | |
| 435 | static const char * const d1clk_parent_names[] = { |
| 436 | "dpll", |
| 437 | "epll", |
| 438 | "usb-phy-40m", |
| 439 | "gpioc6_clkin", |
| 440 | "dp_phy_pll", |
| 441 | }; |
| 442 | |
| 443 | static int aspeed_g6_clk_probe(struct platform_device *pdev) |
| 444 | { |
| 445 | struct device *dev = &pdev->dev; |
| 446 | struct aspeed_reset *ar; |
| 447 | struct regmap *map; |
| 448 | struct clk_hw *hw; |
| 449 | u32 val, rate; |
| 450 | int i, ret; |
| 451 | |
| 452 | map = syscon_node_to_regmap(dev->of_node); |
| 453 | if (IS_ERR(map)) { |
| 454 | dev_err(dev, "no syscon regmap\n"); |
| 455 | return PTR_ERR(map); |
| 456 | } |
| 457 | |
| 458 | ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); |
| 459 | if (!ar) |
| 460 | return -ENOMEM; |
| 461 | |
| 462 | ar->map = map; |
| 463 | |
| 464 | ar->rcdev.owner = THIS_MODULE; |
| 465 | ar->rcdev.nr_resets = 64; |
| 466 | ar->rcdev.ops = &aspeed_g6_reset_ops; |
| 467 | ar->rcdev.of_node = dev->of_node; |
| 468 | |
| 469 | ret = devm_reset_controller_register(dev, &ar->rcdev); |
| 470 | if (ret) { |
| 471 | dev_err(dev, "could not register reset controller\n"); |
| 472 | return ret; |
| 473 | } |
| 474 | |
| 475 | /* UART clock div13 setting */ |
| 476 | regmap_read(map, ASPEED_G6_MISC_CTRL, &val); |
| 477 | if (val & UART_DIV13_EN) |
| 478 | rate = 24000000 / 13; |
| 479 | else |
| 480 | rate = 24000000; |
| 481 | hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); |
| 482 | if (IS_ERR(hw)) |
| 483 | return PTR_ERR(hw); |
| 484 | aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; |
| 485 | |
| 486 | /* UART6~13 clock div13 setting */ |
| 487 | regmap_read(map, 0x80, &val); |
| 488 | if (val & BIT(31)) |
| 489 | rate = 24000000 / 13; |
| 490 | else |
| 491 | rate = 24000000; |
| 492 | hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate); |
| 493 | if (IS_ERR(hw)) |
| 494 | return PTR_ERR(hw); |
| 495 | aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; |
| 496 | |
Eddie James | c2407ab | 2020-07-09 14:57:05 -0500 | [diff] [blame] | 497 | /* EMMC ext clock */ |
| 498 | hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll", |
| 499 | 0, 1, 2); |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 500 | if (IS_ERR(hw)) |
| 501 | return PTR_ERR(hw); |
Eddie James | c2407ab | 2020-07-09 14:57:05 -0500 | [diff] [blame] | 502 | |
| 503 | hw = clk_hw_register_mux(dev, "emmc_extclk_mux", |
| 504 | emmc_extclk_parent_names, |
| 505 | ARRAY_SIZE(emmc_extclk_parent_names), 0, |
| 506 | scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1, |
| 507 | 0, &aspeed_g6_clk_lock); |
| 508 | if (IS_ERR(hw)) |
| 509 | return PTR_ERR(hw); |
| 510 | |
| 511 | hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux", |
| 512 | 0, scu_g6_base + ASPEED_G6_CLK_SELECTION1, |
| 513 | 15, 0, &aspeed_g6_clk_lock); |
| 514 | if (IS_ERR(hw)) |
| 515 | return PTR_ERR(hw); |
| 516 | |
| 517 | hw = clk_hw_register_divider_table(dev, "emmc_extclk", |
| 518 | "emmc_extclk_gate", 0, |
| 519 | scu_g6_base + |
| 520 | ASPEED_G6_CLK_SELECTION1, 12, |
| 521 | 3, 0, ast2600_emmc_extclk_div_table, |
| 522 | &aspeed_g6_clk_lock); |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 523 | if (IS_ERR(hw)) |
| 524 | return PTR_ERR(hw); |
| 525 | aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; |
| 526 | |
| 527 | /* SD/SDIO clock divider and gate */ |
| 528 | hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, |
| 529 | scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, |
| 530 | &aspeed_g6_clk_lock); |
| 531 | if (IS_ERR(hw)) |
| 532 | return PTR_ERR(hw); |
| 533 | hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", |
| 534 | 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, |
| 535 | ast2600_div_table, |
| 536 | &aspeed_g6_clk_lock); |
| 537 | if (IS_ERR(hw)) |
| 538 | return PTR_ERR(hw); |
| 539 | aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; |
| 540 | |
Andrew Jeffery | 3696eeb | 2019-10-10 12:37:25 +1030 | [diff] [blame] | 541 | /* MAC1/2 RMII 50MHz RCLK */ |
| 542 | hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000); |
| 543 | if (IS_ERR(hw)) |
| 544 | return PTR_ERR(hw); |
| 545 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 546 | /* MAC1/2 AHB bus clock divider */ |
| 547 | hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0, |
| 548 | scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0, |
| 549 | ast2600_mac_div_table, |
| 550 | &aspeed_g6_clk_lock); |
| 551 | if (IS_ERR(hw)) |
| 552 | return PTR_ERR(hw); |
| 553 | aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw; |
| 554 | |
Andrew Jeffery | 3696eeb | 2019-10-10 12:37:25 +1030 | [diff] [blame] | 555 | /* RMII1 50MHz (RCLK) output enable */ |
| 556 | hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, |
| 557 | scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0, |
| 558 | &aspeed_g6_clk_lock); |
| 559 | if (IS_ERR(hw)) |
| 560 | return PTR_ERR(hw); |
| 561 | aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; |
| 562 | |
| 563 | /* RMII2 50MHz (RCLK) output enable */ |
| 564 | hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, |
| 565 | scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0, |
| 566 | &aspeed_g6_clk_lock); |
| 567 | if (IS_ERR(hw)) |
| 568 | return PTR_ERR(hw); |
| 569 | aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; |
| 570 | |
| 571 | /* MAC1/2 RMII 50MHz RCLK */ |
| 572 | hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000); |
| 573 | if (IS_ERR(hw)) |
| 574 | return PTR_ERR(hw); |
| 575 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 576 | /* MAC3/4 AHB bus clock divider */ |
| 577 | hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0, |
| 578 | scu_g6_base + 0x310, 24, 3, 0, |
| 579 | ast2600_mac_div_table, |
| 580 | &aspeed_g6_clk_lock); |
| 581 | if (IS_ERR(hw)) |
| 582 | return PTR_ERR(hw); |
| 583 | aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw; |
| 584 | |
Andrew Jeffery | 3696eeb | 2019-10-10 12:37:25 +1030 | [diff] [blame] | 585 | /* RMII3 50MHz (RCLK) output enable */ |
| 586 | hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0, |
| 587 | scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0, |
| 588 | &aspeed_g6_clk_lock); |
| 589 | if (IS_ERR(hw)) |
| 590 | return PTR_ERR(hw); |
| 591 | aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw; |
| 592 | |
| 593 | /* RMII4 50MHz (RCLK) output enable */ |
| 594 | hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0, |
| 595 | scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0, |
| 596 | &aspeed_g6_clk_lock); |
| 597 | if (IS_ERR(hw)) |
| 598 | return PTR_ERR(hw); |
| 599 | aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw; |
| 600 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 601 | /* LPC Host (LHCLK) clock divider */ |
| 602 | hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, |
| 603 | scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, |
| 604 | ast2600_div_table, |
| 605 | &aspeed_g6_clk_lock); |
| 606 | if (IS_ERR(hw)) |
| 607 | return PTR_ERR(hw); |
| 608 | aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw; |
| 609 | |
| 610 | /* gfx d1clk : use dp clk */ |
| 611 | regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10)); |
| 612 | /* SoC Display clock selection */ |
| 613 | hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names, |
| 614 | ARRAY_SIZE(d1clk_parent_names), 0, |
| 615 | scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0, |
| 616 | &aspeed_g6_clk_lock); |
| 617 | if (IS_ERR(hw)) |
| 618 | return PTR_ERR(hw); |
| 619 | aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw; |
| 620 | |
| 621 | /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */ |
| 622 | regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */ |
| 623 | |
| 624 | /* P-Bus (BCLK) clock divider */ |
Joel Stanley | b8c1dc9c | 2022-04-21 13:34:26 +0930 | [diff] [blame] | 625 | hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0, |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 626 | scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, |
| 627 | ast2600_div_table, |
| 628 | &aspeed_g6_clk_lock); |
| 629 | if (IS_ERR(hw)) |
| 630 | return PTR_ERR(hw); |
| 631 | aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw; |
| 632 | |
| 633 | /* Video Capture clock selection */ |
| 634 | hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names, |
| 635 | ARRAY_SIZE(vclk_parent_names), 0, |
| 636 | scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0, |
| 637 | &aspeed_g6_clk_lock); |
| 638 | if (IS_ERR(hw)) |
| 639 | return PTR_ERR(hw); |
| 640 | aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw; |
| 641 | |
| 642 | /* Video Engine clock divider */ |
| 643 | hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0, |
| 644 | scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0, |
| 645 | ast2600_eclk_div_table, |
| 646 | &aspeed_g6_clk_lock); |
| 647 | if (IS_ERR(hw)) |
| 648 | return PTR_ERR(hw); |
| 649 | aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw; |
| 650 | |
| 651 | for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) { |
| 652 | const struct aspeed_gate_data *gd = &aspeed_g6_gates[i]; |
| 653 | u32 gate_flags; |
| 654 | |
| 655 | /* |
| 656 | * Special case: the USB port 1 clock (bit 14) is always |
| 657 | * working the opposite way from the other ones. |
| 658 | */ |
| 659 | gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; |
| 660 | hw = aspeed_g6_clk_hw_register_gate(dev, |
| 661 | gd->name, |
| 662 | gd->parent_name, |
| 663 | gd->flags, |
| 664 | map, |
| 665 | gd->clock_idx, |
| 666 | gd->reset_idx, |
| 667 | gate_flags, |
| 668 | &aspeed_g6_clk_lock); |
| 669 | if (IS_ERR(hw)) |
| 670 | return PTR_ERR(hw); |
| 671 | aspeed_g6_clk_data->hws[i] = hw; |
| 672 | } |
| 673 | |
| 674 | return 0; |
| 675 | }; |
| 676 | |
| 677 | static const struct of_device_id aspeed_g6_clk_dt_ids[] = { |
| 678 | { .compatible = "aspeed,ast2600-scu" }, |
| 679 | { } |
| 680 | }; |
| 681 | |
| 682 | static struct platform_driver aspeed_g6_clk_driver = { |
| 683 | .probe = aspeed_g6_clk_probe, |
| 684 | .driver = { |
| 685 | .name = "ast2600-clk", |
| 686 | .of_match_table = aspeed_g6_clk_dt_ids, |
| 687 | .suppress_bind_attrs = true, |
| 688 | }, |
| 689 | }; |
| 690 | builtin_platform_driver(aspeed_g6_clk_driver); |
| 691 | |
| 692 | static const u32 ast2600_a0_axi_ahb_div_table[] = { |
| 693 | 2, 2, 3, 5, |
| 694 | }; |
| 695 | |
Eddie James | 2d49106 | 2020-04-08 15:36:16 -0500 | [diff] [blame] | 696 | static const u32 ast2600_a1_axi_ahb_div0_tbl[] = { |
| 697 | 3, 2, 3, 4, |
| 698 | }; |
| 699 | |
| 700 | static const u32 ast2600_a1_axi_ahb_div1_tbl[] = { |
| 701 | 3, 4, 6, 8, |
| 702 | }; |
| 703 | |
| 704 | static const u32 ast2600_a1_axi_ahb200_tbl[] = { |
| 705 | 3, 4, 3, 4, 2, 2, 2, 2, |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 706 | }; |
| 707 | |
| 708 | static void __init aspeed_g6_cc(struct regmap *map) |
| 709 | { |
| 710 | struct clk_hw *hw; |
Joel Stanley | f45c5b1 | 2021-09-23 09:24:49 +0930 | [diff] [blame] | 711 | u32 val, div, divbits, axi_div, ahb_div; |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 712 | |
| 713 | clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000); |
| 714 | |
| 715 | /* |
| 716 | * High-speed PLL clock derived from the crystal. This the CPU clock, |
| 717 | * and we assume that it is enabled |
| 718 | */ |
| 719 | regmap_read(map, ASPEED_HPLL_PARAM, &val); |
| 720 | aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val); |
| 721 | |
| 722 | regmap_read(map, ASPEED_MPLL_PARAM, &val); |
| 723 | aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val); |
| 724 | |
| 725 | regmap_read(map, ASPEED_DPLL_PARAM, &val); |
| 726 | aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val); |
| 727 | |
| 728 | regmap_read(map, ASPEED_EPLL_PARAM, &val); |
| 729 | aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); |
| 730 | |
| 731 | regmap_read(map, ASPEED_APLL_PARAM, &val); |
| 732 | aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val); |
| 733 | |
| 734 | /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/ |
| 735 | regmap_read(map, ASPEED_G6_STRAP1, &val); |
| 736 | if (val & BIT(16)) |
| 737 | axi_div = 1; |
| 738 | else |
| 739 | axi_div = 2; |
| 740 | |
Eddie James | 2d49106 | 2020-04-08 15:36:16 -0500 | [diff] [blame] | 741 | divbits = (val >> 11) & 0x3; |
Joel Stanley | f45c5b1 | 2021-09-23 09:24:49 +0930 | [diff] [blame] | 742 | if (soc_rev >= 1) { |
Eddie James | 2d49106 | 2020-04-08 15:36:16 -0500 | [diff] [blame] | 743 | if (!divbits) { |
| 744 | ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3]; |
| 745 | if (val & BIT(16)) |
| 746 | ahb_div *= 2; |
| 747 | } else { |
| 748 | if (val & BIT(16)) |
| 749 | ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits]; |
| 750 | else |
| 751 | ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits]; |
| 752 | } |
| 753 | } else { |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 754 | ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3]; |
Eddie James | 2d49106 | 2020-04-08 15:36:16 -0500 | [diff] [blame] | 755 | } |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 756 | |
| 757 | hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div); |
| 758 | aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw; |
| 759 | |
| 760 | regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val); |
| 761 | val = (val >> 23) & 0x7; |
| 762 | div = 4 * (val + 1); |
| 763 | hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div); |
| 764 | aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw; |
| 765 | |
| 766 | regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val); |
| 767 | val = (val >> 9) & 0x7; |
| 768 | div = 2 * (val + 1); |
| 769 | hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div); |
| 770 | aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw; |
| 771 | |
| 772 | /* USB 2.0 port1 phy 40MHz clock */ |
| 773 | hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000); |
| 774 | aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw; |
| 775 | }; |
| 776 | |
| 777 | static void __init aspeed_g6_cc_init(struct device_node *np) |
| 778 | { |
| 779 | struct regmap *map; |
| 780 | int ret; |
| 781 | int i; |
| 782 | |
| 783 | scu_g6_base = of_iomap(np, 0); |
| 784 | if (!scu_g6_base) |
| 785 | return; |
| 786 | |
Joel Stanley | f45c5b1 | 2021-09-23 09:24:49 +0930 | [diff] [blame] | 787 | soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16; |
| 788 | |
Joel Stanley | d3d04f6 | 2019-08-25 23:48:48 +0930 | [diff] [blame] | 789 | aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws, |
| 790 | ASPEED_G6_NUM_CLKS), GFP_KERNEL); |
| 791 | if (!aspeed_g6_clk_data) |
| 792 | return; |
| 793 | |
| 794 | /* |
| 795 | * This way all clocks fetched before the platform device probes, |
| 796 | * except those we assign here for early use, will be deferred. |
| 797 | */ |
| 798 | for (i = 0; i < ASPEED_G6_NUM_CLKS; i++) |
| 799 | aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); |
| 800 | |
| 801 | /* |
| 802 | * We check that the regmap works on this very first access, |
| 803 | * but as this is an MMIO-backed regmap, subsequent regmap |
| 804 | * access is not going to fail and we skip error checks from |
| 805 | * this point. |
| 806 | */ |
| 807 | map = syscon_node_to_regmap(np); |
| 808 | if (IS_ERR(map)) { |
| 809 | pr_err("no syscon regmap\n"); |
| 810 | return; |
| 811 | } |
| 812 | |
| 813 | aspeed_g6_cc(map); |
| 814 | aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; |
| 815 | ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data); |
| 816 | if (ret) |
| 817 | pr_err("failed to add DT provider: %d\n", ret); |
| 818 | }; |
| 819 | CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init); |