Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | /* |
Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 3 | * arch/powerpc/sysdev/ipic.c |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
| 5 | * IPIC routines implementations. |
| 6 | * |
| 7 | * Copyright 2005 Freescale Semiconductor, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | */ |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/init.h> |
| 11 | #include <linux/errno.h> |
| 12 | #include <linux/reboot.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/stddef.h> |
| 15 | #include <linux/sched.h> |
| 16 | #include <linux/signal.h> |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 17 | #include <linux/syscore_ops.h> |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 18 | #include <linux/device.h> |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 19 | #include <linux/spinlock.h> |
Scott Wood | d49747b | 2007-10-09 12:37:13 -0500 | [diff] [blame] | 20 | #include <linux/fsl_devices.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <asm/irq.h> |
| 22 | #include <asm/io.h> |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 23 | #include <asm/prom.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <asm/ipic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
| 26 | #include "ipic.h" |
| 27 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | static struct ipic * primary_ipic; |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 29 | static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip; |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 30 | static DEFINE_RAW_SPINLOCK(ipic_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
| 32 | static struct ipic_info ipic_info[] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 33 | [1] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 34 | .mask = IPIC_SIMSR_H, |
| 35 | .prio = IPIC_SIPRR_C, |
| 36 | .force = IPIC_SIFCR_H, |
| 37 | .bit = 16, |
| 38 | .prio_mask = 0, |
| 39 | }, |
| 40 | [2] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 41 | .mask = IPIC_SIMSR_H, |
| 42 | .prio = IPIC_SIPRR_C, |
| 43 | .force = IPIC_SIFCR_H, |
| 44 | .bit = 17, |
| 45 | .prio_mask = 1, |
| 46 | }, |
John Rigby | a7267d6 | 2008-01-17 17:05:32 -0700 | [diff] [blame] | 47 | [3] = { |
| 48 | .mask = IPIC_SIMSR_H, |
| 49 | .prio = IPIC_SIPRR_C, |
| 50 | .force = IPIC_SIFCR_H, |
| 51 | .bit = 18, |
| 52 | .prio_mask = 2, |
| 53 | }, |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 54 | [4] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 55 | .mask = IPIC_SIMSR_H, |
| 56 | .prio = IPIC_SIPRR_C, |
| 57 | .force = IPIC_SIFCR_H, |
| 58 | .bit = 19, |
| 59 | .prio_mask = 3, |
| 60 | }, |
John Rigby | a7267d6 | 2008-01-17 17:05:32 -0700 | [diff] [blame] | 61 | [5] = { |
| 62 | .mask = IPIC_SIMSR_H, |
| 63 | .prio = IPIC_SIPRR_C, |
| 64 | .force = IPIC_SIFCR_H, |
| 65 | .bit = 20, |
| 66 | .prio_mask = 4, |
| 67 | }, |
| 68 | [6] = { |
| 69 | .mask = IPIC_SIMSR_H, |
| 70 | .prio = IPIC_SIPRR_C, |
| 71 | .force = IPIC_SIFCR_H, |
| 72 | .bit = 21, |
| 73 | .prio_mask = 5, |
| 74 | }, |
| 75 | [7] = { |
| 76 | .mask = IPIC_SIMSR_H, |
| 77 | .prio = IPIC_SIPRR_C, |
| 78 | .force = IPIC_SIFCR_H, |
| 79 | .bit = 22, |
| 80 | .prio_mask = 6, |
| 81 | }, |
| 82 | [8] = { |
| 83 | .mask = IPIC_SIMSR_H, |
| 84 | .prio = IPIC_SIPRR_C, |
| 85 | .force = IPIC_SIFCR_H, |
| 86 | .bit = 23, |
| 87 | .prio_mask = 7, |
| 88 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | [9] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | .mask = IPIC_SIMSR_H, |
| 91 | .prio = IPIC_SIPRR_D, |
| 92 | .force = IPIC_SIFCR_H, |
| 93 | .bit = 24, |
| 94 | .prio_mask = 0, |
| 95 | }, |
| 96 | [10] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | .mask = IPIC_SIMSR_H, |
| 98 | .prio = IPIC_SIPRR_D, |
| 99 | .force = IPIC_SIFCR_H, |
| 100 | .bit = 25, |
| 101 | .prio_mask = 1, |
| 102 | }, |
| 103 | [11] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | .mask = IPIC_SIMSR_H, |
| 105 | .prio = IPIC_SIPRR_D, |
| 106 | .force = IPIC_SIFCR_H, |
| 107 | .bit = 26, |
| 108 | .prio_mask = 2, |
| 109 | }, |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 110 | [12] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 111 | .mask = IPIC_SIMSR_H, |
| 112 | .prio = IPIC_SIPRR_D, |
| 113 | .force = IPIC_SIFCR_H, |
| 114 | .bit = 27, |
| 115 | .prio_mask = 3, |
| 116 | }, |
| 117 | [13] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 118 | .mask = IPIC_SIMSR_H, |
| 119 | .prio = IPIC_SIPRR_D, |
| 120 | .force = IPIC_SIFCR_H, |
| 121 | .bit = 28, |
| 122 | .prio_mask = 4, |
| 123 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | [14] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | .mask = IPIC_SIMSR_H, |
| 126 | .prio = IPIC_SIPRR_D, |
| 127 | .force = IPIC_SIFCR_H, |
| 128 | .bit = 29, |
| 129 | .prio_mask = 5, |
| 130 | }, |
| 131 | [15] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | .mask = IPIC_SIMSR_H, |
| 133 | .prio = IPIC_SIPRR_D, |
| 134 | .force = IPIC_SIFCR_H, |
| 135 | .bit = 30, |
| 136 | .prio_mask = 6, |
| 137 | }, |
| 138 | [16] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | .mask = IPIC_SIMSR_H, |
| 140 | .prio = IPIC_SIPRR_D, |
| 141 | .force = IPIC_SIFCR_H, |
| 142 | .bit = 31, |
| 143 | .prio_mask = 7, |
| 144 | }, |
| 145 | [17] = { |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 146 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | .mask = IPIC_SEMSR, |
| 148 | .prio = IPIC_SMPRR_A, |
| 149 | .force = IPIC_SEFCR, |
| 150 | .bit = 1, |
| 151 | .prio_mask = 5, |
| 152 | }, |
| 153 | [18] = { |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 154 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | .mask = IPIC_SEMSR, |
| 156 | .prio = IPIC_SMPRR_A, |
| 157 | .force = IPIC_SEFCR, |
| 158 | .bit = 2, |
| 159 | .prio_mask = 6, |
| 160 | }, |
| 161 | [19] = { |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 162 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | .mask = IPIC_SEMSR, |
| 164 | .prio = IPIC_SMPRR_A, |
| 165 | .force = IPIC_SEFCR, |
| 166 | .bit = 3, |
| 167 | .prio_mask = 7, |
| 168 | }, |
| 169 | [20] = { |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 170 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | .mask = IPIC_SEMSR, |
| 172 | .prio = IPIC_SMPRR_B, |
| 173 | .force = IPIC_SEFCR, |
| 174 | .bit = 4, |
| 175 | .prio_mask = 4, |
| 176 | }, |
| 177 | [21] = { |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 178 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | .mask = IPIC_SEMSR, |
| 180 | .prio = IPIC_SMPRR_B, |
| 181 | .force = IPIC_SEFCR, |
| 182 | .bit = 5, |
| 183 | .prio_mask = 5, |
| 184 | }, |
| 185 | [22] = { |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 186 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | .mask = IPIC_SEMSR, |
| 188 | .prio = IPIC_SMPRR_B, |
| 189 | .force = IPIC_SEFCR, |
| 190 | .bit = 6, |
| 191 | .prio_mask = 6, |
| 192 | }, |
| 193 | [23] = { |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 194 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | .mask = IPIC_SEMSR, |
| 196 | .prio = IPIC_SMPRR_B, |
| 197 | .force = IPIC_SEFCR, |
| 198 | .bit = 7, |
| 199 | .prio_mask = 7, |
| 200 | }, |
| 201 | [32] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | .mask = IPIC_SIMSR_H, |
| 203 | .prio = IPIC_SIPRR_A, |
| 204 | .force = IPIC_SIFCR_H, |
| 205 | .bit = 0, |
| 206 | .prio_mask = 0, |
| 207 | }, |
| 208 | [33] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | .mask = IPIC_SIMSR_H, |
| 210 | .prio = IPIC_SIPRR_A, |
| 211 | .force = IPIC_SIFCR_H, |
| 212 | .bit = 1, |
| 213 | .prio_mask = 1, |
| 214 | }, |
| 215 | [34] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | .mask = IPIC_SIMSR_H, |
| 217 | .prio = IPIC_SIPRR_A, |
| 218 | .force = IPIC_SIFCR_H, |
| 219 | .bit = 2, |
| 220 | .prio_mask = 2, |
| 221 | }, |
| 222 | [35] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | .mask = IPIC_SIMSR_H, |
| 224 | .prio = IPIC_SIPRR_A, |
| 225 | .force = IPIC_SIFCR_H, |
| 226 | .bit = 3, |
| 227 | .prio_mask = 3, |
| 228 | }, |
| 229 | [36] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | .mask = IPIC_SIMSR_H, |
| 231 | .prio = IPIC_SIPRR_A, |
| 232 | .force = IPIC_SIFCR_H, |
| 233 | .bit = 4, |
| 234 | .prio_mask = 4, |
| 235 | }, |
| 236 | [37] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | .mask = IPIC_SIMSR_H, |
| 238 | .prio = IPIC_SIPRR_A, |
| 239 | .force = IPIC_SIFCR_H, |
| 240 | .bit = 5, |
| 241 | .prio_mask = 5, |
| 242 | }, |
| 243 | [38] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 244 | .mask = IPIC_SIMSR_H, |
| 245 | .prio = IPIC_SIPRR_A, |
| 246 | .force = IPIC_SIFCR_H, |
| 247 | .bit = 6, |
| 248 | .prio_mask = 6, |
| 249 | }, |
| 250 | [39] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | .mask = IPIC_SIMSR_H, |
| 252 | .prio = IPIC_SIPRR_A, |
| 253 | .force = IPIC_SIFCR_H, |
| 254 | .bit = 7, |
| 255 | .prio_mask = 7, |
| 256 | }, |
John Rigby | a7267d6 | 2008-01-17 17:05:32 -0700 | [diff] [blame] | 257 | [40] = { |
| 258 | .mask = IPIC_SIMSR_H, |
| 259 | .prio = IPIC_SIPRR_B, |
| 260 | .force = IPIC_SIFCR_H, |
| 261 | .bit = 8, |
| 262 | .prio_mask = 0, |
| 263 | }, |
| 264 | [41] = { |
| 265 | .mask = IPIC_SIMSR_H, |
| 266 | .prio = IPIC_SIPRR_B, |
| 267 | .force = IPIC_SIFCR_H, |
| 268 | .bit = 9, |
| 269 | .prio_mask = 1, |
| 270 | }, |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 271 | [42] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 272 | .mask = IPIC_SIMSR_H, |
| 273 | .prio = IPIC_SIPRR_B, |
| 274 | .force = IPIC_SIFCR_H, |
| 275 | .bit = 10, |
| 276 | .prio_mask = 2, |
| 277 | }, |
John Rigby | a7267d6 | 2008-01-17 17:05:32 -0700 | [diff] [blame] | 278 | [43] = { |
| 279 | .mask = IPIC_SIMSR_H, |
| 280 | .prio = IPIC_SIPRR_B, |
| 281 | .force = IPIC_SIFCR_H, |
| 282 | .bit = 11, |
| 283 | .prio_mask = 3, |
| 284 | }, |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 285 | [44] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 286 | .mask = IPIC_SIMSR_H, |
| 287 | .prio = IPIC_SIPRR_B, |
| 288 | .force = IPIC_SIFCR_H, |
| 289 | .bit = 12, |
| 290 | .prio_mask = 4, |
| 291 | }, |
| 292 | [45] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 293 | .mask = IPIC_SIMSR_H, |
| 294 | .prio = IPIC_SIPRR_B, |
| 295 | .force = IPIC_SIFCR_H, |
| 296 | .bit = 13, |
| 297 | .prio_mask = 5, |
| 298 | }, |
| 299 | [46] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 300 | .mask = IPIC_SIMSR_H, |
| 301 | .prio = IPIC_SIPRR_B, |
| 302 | .force = IPIC_SIFCR_H, |
| 303 | .bit = 14, |
| 304 | .prio_mask = 6, |
| 305 | }, |
| 306 | [47] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 307 | .mask = IPIC_SIMSR_H, |
| 308 | .prio = IPIC_SIPRR_B, |
| 309 | .force = IPIC_SIFCR_H, |
| 310 | .bit = 15, |
| 311 | .prio_mask = 7, |
| 312 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | [48] = { |
Scott Wood | 446183e | 2017-06-24 21:39:05 -0500 | [diff] [blame] | 314 | .ack = IPIC_SEPNR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | .mask = IPIC_SEMSR, |
| 316 | .prio = IPIC_SMPRR_A, |
| 317 | .force = IPIC_SEFCR, |
| 318 | .bit = 0, |
| 319 | .prio_mask = 4, |
| 320 | }, |
| 321 | [64] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 322 | .mask = IPIC_SIMSR_L, |
| 323 | .prio = IPIC_SMPRR_A, |
| 324 | .force = IPIC_SIFCR_L, |
| 325 | .bit = 0, |
| 326 | .prio_mask = 0, |
| 327 | }, |
| 328 | [65] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | .mask = IPIC_SIMSR_L, |
| 330 | .prio = IPIC_SMPRR_A, |
| 331 | .force = IPIC_SIFCR_L, |
| 332 | .bit = 1, |
| 333 | .prio_mask = 1, |
| 334 | }, |
| 335 | [66] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | .mask = IPIC_SIMSR_L, |
| 337 | .prio = IPIC_SMPRR_A, |
| 338 | .force = IPIC_SIFCR_L, |
| 339 | .bit = 2, |
| 340 | .prio_mask = 2, |
| 341 | }, |
| 342 | [67] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | .mask = IPIC_SIMSR_L, |
| 344 | .prio = IPIC_SMPRR_A, |
| 345 | .force = IPIC_SIFCR_L, |
| 346 | .bit = 3, |
| 347 | .prio_mask = 3, |
| 348 | }, |
| 349 | [68] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | .mask = IPIC_SIMSR_L, |
| 351 | .prio = IPIC_SMPRR_B, |
| 352 | .force = IPIC_SIFCR_L, |
| 353 | .bit = 4, |
| 354 | .prio_mask = 0, |
| 355 | }, |
| 356 | [69] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | .mask = IPIC_SIMSR_L, |
| 358 | .prio = IPIC_SMPRR_B, |
| 359 | .force = IPIC_SIFCR_L, |
| 360 | .bit = 5, |
| 361 | .prio_mask = 1, |
| 362 | }, |
| 363 | [70] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 364 | .mask = IPIC_SIMSR_L, |
| 365 | .prio = IPIC_SMPRR_B, |
| 366 | .force = IPIC_SIFCR_L, |
| 367 | .bit = 6, |
| 368 | .prio_mask = 2, |
| 369 | }, |
| 370 | [71] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | .mask = IPIC_SIMSR_L, |
| 372 | .prio = IPIC_SMPRR_B, |
| 373 | .force = IPIC_SIFCR_L, |
| 374 | .bit = 7, |
| 375 | .prio_mask = 3, |
| 376 | }, |
| 377 | [72] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | .mask = IPIC_SIMSR_L, |
| 379 | .prio = 0, |
| 380 | .force = IPIC_SIFCR_L, |
| 381 | .bit = 8, |
| 382 | }, |
| 383 | [73] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | .mask = IPIC_SIMSR_L, |
| 385 | .prio = 0, |
| 386 | .force = IPIC_SIFCR_L, |
| 387 | .bit = 9, |
| 388 | }, |
| 389 | [74] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | .mask = IPIC_SIMSR_L, |
| 391 | .prio = 0, |
| 392 | .force = IPIC_SIFCR_L, |
| 393 | .bit = 10, |
| 394 | }, |
| 395 | [75] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | .mask = IPIC_SIMSR_L, |
| 397 | .prio = 0, |
| 398 | .force = IPIC_SIFCR_L, |
| 399 | .bit = 11, |
| 400 | }, |
| 401 | [76] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | .mask = IPIC_SIMSR_L, |
| 403 | .prio = 0, |
| 404 | .force = IPIC_SIFCR_L, |
| 405 | .bit = 12, |
| 406 | }, |
| 407 | [77] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 408 | .mask = IPIC_SIMSR_L, |
| 409 | .prio = 0, |
| 410 | .force = IPIC_SIFCR_L, |
| 411 | .bit = 13, |
| 412 | }, |
| 413 | [78] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | .mask = IPIC_SIMSR_L, |
| 415 | .prio = 0, |
| 416 | .force = IPIC_SIFCR_L, |
| 417 | .bit = 14, |
| 418 | }, |
| 419 | [79] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | .mask = IPIC_SIMSR_L, |
| 421 | .prio = 0, |
| 422 | .force = IPIC_SIFCR_L, |
| 423 | .bit = 15, |
| 424 | }, |
| 425 | [80] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 426 | .mask = IPIC_SIMSR_L, |
| 427 | .prio = 0, |
| 428 | .force = IPIC_SIFCR_L, |
| 429 | .bit = 16, |
| 430 | }, |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 431 | [81] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 432 | .mask = IPIC_SIMSR_L, |
| 433 | .prio = 0, |
| 434 | .force = IPIC_SIFCR_L, |
| 435 | .bit = 17, |
| 436 | }, |
| 437 | [82] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 438 | .mask = IPIC_SIMSR_L, |
| 439 | .prio = 0, |
| 440 | .force = IPIC_SIFCR_L, |
| 441 | .bit = 18, |
| 442 | }, |
John Rigby | a7267d6 | 2008-01-17 17:05:32 -0700 | [diff] [blame] | 443 | [83] = { |
| 444 | .mask = IPIC_SIMSR_L, |
| 445 | .prio = 0, |
| 446 | .force = IPIC_SIFCR_L, |
| 447 | .bit = 19, |
| 448 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | [84] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | .mask = IPIC_SIMSR_L, |
| 451 | .prio = 0, |
| 452 | .force = IPIC_SIFCR_L, |
| 453 | .bit = 20, |
| 454 | }, |
| 455 | [85] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | .mask = IPIC_SIMSR_L, |
| 457 | .prio = 0, |
| 458 | .force = IPIC_SIFCR_L, |
| 459 | .bit = 21, |
| 460 | }, |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 461 | [86] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 462 | .mask = IPIC_SIMSR_L, |
| 463 | .prio = 0, |
| 464 | .force = IPIC_SIFCR_L, |
| 465 | .bit = 22, |
| 466 | }, |
| 467 | [87] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 468 | .mask = IPIC_SIMSR_L, |
| 469 | .prio = 0, |
| 470 | .force = IPIC_SIFCR_L, |
| 471 | .bit = 23, |
| 472 | }, |
| 473 | [88] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 474 | .mask = IPIC_SIMSR_L, |
| 475 | .prio = 0, |
| 476 | .force = IPIC_SIFCR_L, |
| 477 | .bit = 24, |
| 478 | }, |
| 479 | [89] = { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 480 | .mask = IPIC_SIMSR_L, |
| 481 | .prio = 0, |
| 482 | .force = IPIC_SIFCR_L, |
| 483 | .bit = 25, |
| 484 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | [90] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 486 | .mask = IPIC_SIMSR_L, |
| 487 | .prio = 0, |
| 488 | .force = IPIC_SIFCR_L, |
| 489 | .bit = 26, |
| 490 | }, |
| 491 | [91] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 492 | .mask = IPIC_SIMSR_L, |
| 493 | .prio = 0, |
| 494 | .force = IPIC_SIFCR_L, |
| 495 | .bit = 27, |
| 496 | }, |
Kim Phillips | 8cf6b195 | 2008-01-24 20:46:50 -0600 | [diff] [blame] | 497 | [94] = { |
| 498 | .mask = IPIC_SIMSR_L, |
| 499 | .prio = 0, |
| 500 | .force = IPIC_SIFCR_L, |
| 501 | .bit = 30, |
| 502 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | }; |
| 504 | |
| 505 | static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg) |
| 506 | { |
| 507 | return in_be32(base + (reg >> 2)); |
| 508 | } |
| 509 | |
| 510 | static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value) |
| 511 | { |
| 512 | out_be32(base + (reg >> 2), value); |
| 513 | } |
| 514 | |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 515 | static inline struct ipic * ipic_from_irq(unsigned int virq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | { |
| 517 | return primary_ipic; |
| 518 | } |
| 519 | |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 520 | static void ipic_unmask_irq(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | { |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 522 | struct ipic *ipic = ipic_from_irq(d->irq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 523 | unsigned int src = irqd_to_hwirq(d); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 524 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | u32 temp; |
| 526 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 527 | raw_spin_lock_irqsave(&ipic_lock, flags); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 528 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | temp = ipic_read(ipic->regs, ipic_info[src].mask); |
| 530 | temp |= (1 << (31 - ipic_info[src].bit)); |
| 531 | ipic_write(ipic->regs, ipic_info[src].mask, temp); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 532 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 533 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | } |
| 535 | |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 536 | static void ipic_mask_irq(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 537 | { |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 538 | struct ipic *ipic = ipic_from_irq(d->irq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 539 | unsigned int src = irqd_to_hwirq(d); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 540 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | u32 temp; |
| 542 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 543 | raw_spin_lock_irqsave(&ipic_lock, flags); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 544 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | temp = ipic_read(ipic->regs, ipic_info[src].mask); |
| 546 | temp &= ~(1 << (31 - ipic_info[src].bit)); |
| 547 | ipic_write(ipic->regs, ipic_info[src].mask, temp); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 548 | |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 549 | /* mb() can't guarantee that masking is finished. But it does finish |
| 550 | * for nearly all cases. */ |
| 551 | mb(); |
| 552 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 553 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 554 | } |
| 555 | |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 556 | static void ipic_ack_irq(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | { |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 558 | struct ipic *ipic = ipic_from_irq(d->irq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 559 | unsigned int src = irqd_to_hwirq(d); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 560 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 561 | u32 temp; |
| 562 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 563 | raw_spin_lock_irqsave(&ipic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 564 | |
dayu@datangmobile.cn | 30c4046 | 2009-02-18 13:47:42 +0800 | [diff] [blame] | 565 | temp = 1 << (31 - ipic_info[src].bit); |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 566 | ipic_write(ipic->regs, ipic_info[src].ack, temp); |
| 567 | |
| 568 | /* mb() can't guarantee that ack is finished. But it does finish |
| 569 | * for nearly all cases. */ |
| 570 | mb(); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 571 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 572 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | } |
| 574 | |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 575 | static void ipic_mask_irq_and_ack(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 576 | { |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 577 | struct ipic *ipic = ipic_from_irq(d->irq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 578 | unsigned int src = irqd_to_hwirq(d); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 579 | unsigned long flags; |
| 580 | u32 temp; |
| 581 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 582 | raw_spin_lock_irqsave(&ipic_lock, flags); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 583 | |
| 584 | temp = ipic_read(ipic->regs, ipic_info[src].mask); |
| 585 | temp &= ~(1 << (31 - ipic_info[src].bit)); |
| 586 | ipic_write(ipic->regs, ipic_info[src].mask, temp); |
| 587 | |
dayu@datangmobile.cn | 30c4046 | 2009-02-18 13:47:42 +0800 | [diff] [blame] | 588 | temp = 1 << (31 - ipic_info[src].bit); |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 589 | ipic_write(ipic->regs, ipic_info[src].ack, temp); |
| 590 | |
| 591 | /* mb() can't guarantee that ack is finished. But it does finish |
| 592 | * for nearly all cases. */ |
| 593 | mb(); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 594 | |
Thomas Gleixner | a9e8bf2 | 2010-02-18 02:23:14 +0000 | [diff] [blame] | 595 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 596 | } |
| 597 | |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 598 | static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 599 | { |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 600 | struct ipic *ipic = ipic_from_irq(d->irq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 601 | unsigned int src = irqd_to_hwirq(d); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 602 | unsigned int vold, vnew, edibit; |
| 603 | |
| 604 | if (flow_type == IRQ_TYPE_NONE) |
| 605 | flow_type = IRQ_TYPE_LEVEL_LOW; |
| 606 | |
| 607 | /* ipic supports only low assertion and high-to-low change senses |
| 608 | */ |
| 609 | if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) { |
| 610 | printk(KERN_ERR "ipic: sense type 0x%x not supported\n", |
| 611 | flow_type); |
| 612 | return -EINVAL; |
| 613 | } |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 614 | /* ipic supports only edge mode on external interrupts */ |
| 615 | if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) { |
| 616 | printk(KERN_ERR "ipic: edge sense not supported on internal " |
| 617 | "interrupts\n"); |
| 618 | return -EINVAL; |
Thomas Gleixner | ecf4b19 | 2011-03-25 16:16:30 +0100 | [diff] [blame] | 619 | |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 620 | } |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 621 | |
Thomas Gleixner | ecf4b19 | 2011-03-25 16:16:30 +0100 | [diff] [blame] | 622 | irqd_set_trigger_type(d, flow_type); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 623 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { |
Thomas Gleixner | 9758a7b | 2015-06-23 15:52:34 +0200 | [diff] [blame] | 624 | irq_set_handler_locked(d, handle_level_irq); |
Thomas Gleixner | ecf4b19 | 2011-03-25 16:16:30 +0100 | [diff] [blame] | 625 | d->chip = &ipic_level_irq_chip; |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 626 | } else { |
Thomas Gleixner | 9758a7b | 2015-06-23 15:52:34 +0200 | [diff] [blame] | 627 | irq_set_handler_locked(d, handle_edge_irq); |
Thomas Gleixner | ecf4b19 | 2011-03-25 16:16:30 +0100 | [diff] [blame] | 628 | d->chip = &ipic_edge_irq_chip; |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | /* only EXT IRQ senses are programmable on ipic |
| 632 | * internal IRQ senses are LEVEL_LOW |
| 633 | */ |
| 634 | if (src == IPIC_IRQ_EXT0) |
| 635 | edibit = 15; |
| 636 | else |
| 637 | if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7) |
| 638 | edibit = (14 - (src - IPIC_IRQ_EXT1)); |
| 639 | else |
| 640 | return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; |
| 641 | |
| 642 | vold = ipic_read(ipic->regs, IPIC_SECNR); |
| 643 | if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) { |
| 644 | vnew = vold | (1 << edibit); |
| 645 | } else { |
| 646 | vnew = vold & ~(1 << edibit); |
| 647 | } |
| 648 | if (vold != vnew) |
| 649 | ipic_write(ipic->regs, IPIC_SECNR, vnew); |
Thomas Gleixner | ecf4b19 | 2011-03-25 16:16:30 +0100 | [diff] [blame] | 650 | return IRQ_SET_MASK_OK_NOCOPY; |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 651 | } |
| 652 | |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 653 | /* level interrupts and edge interrupts have different ack operations */ |
| 654 | static struct irq_chip ipic_level_irq_chip = { |
Anton Blanchard | fc380c0 | 2010-01-31 20:33:41 +0000 | [diff] [blame] | 655 | .name = "IPIC", |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 656 | .irq_unmask = ipic_unmask_irq, |
| 657 | .irq_mask = ipic_mask_irq, |
| 658 | .irq_mask_ack = ipic_mask_irq, |
| 659 | .irq_set_type = ipic_set_irq_type, |
Li Yang | 77d4309 | 2007-12-04 19:01:40 +0800 | [diff] [blame] | 660 | }; |
| 661 | |
| 662 | static struct irq_chip ipic_edge_irq_chip = { |
Anton Blanchard | fc380c0 | 2010-01-31 20:33:41 +0000 | [diff] [blame] | 663 | .name = "IPIC", |
Lennert Buytenhek | 687228a | 2011-03-07 13:59:58 +0000 | [diff] [blame] | 664 | .irq_unmask = ipic_unmask_irq, |
| 665 | .irq_mask = ipic_mask_irq, |
| 666 | .irq_mask_ack = ipic_mask_irq_and_ack, |
| 667 | .irq_ack = ipic_ack_irq, |
| 668 | .irq_set_type = ipic_set_irq_type, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | }; |
| 670 | |
Marc Zyngier | ad3aedf | 2015-07-28 14:46:08 +0100 | [diff] [blame] | 671 | static int ipic_host_match(struct irq_domain *h, struct device_node *node, |
| 672 | enum irq_domain_bus_token bus_token) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 673 | { |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 674 | /* Exact match, unless ipic node is NULL */ |
Marc Zyngier | 5d4c9bc | 2015-10-13 12:51:29 +0100 | [diff] [blame] | 675 | struct device_node *of_node = irq_domain_get_of_node(h); |
| 676 | return of_node == NULL || of_node == node; |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 677 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 678 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 679 | static int ipic_host_map(struct irq_domain *h, unsigned int virq, |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 680 | irq_hw_number_t hw) |
| 681 | { |
| 682 | struct ipic *ipic = h->host_data; |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 683 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 684 | irq_set_chip_data(virq, ipic); |
| 685 | irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 686 | |
| 687 | /* Set default irq type */ |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 688 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 689 | |
| 690 | return 0; |
| 691 | } |
| 692 | |
Krzysztof Kozlowski | 202648a | 2015-04-27 21:48:47 +0900 | [diff] [blame] | 693 | static const struct irq_domain_ops ipic_host_ops = { |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 694 | .match = ipic_host_match, |
| 695 | .map = ipic_host_map, |
Grant Likely | ff8c3ab | 2012-01-24 17:09:13 -0700 | [diff] [blame] | 696 | .xlate = irq_domain_xlate_onetwocell, |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 697 | }; |
| 698 | |
Kumar Gala | 126186a | 2007-01-26 01:45:32 -0600 | [diff] [blame] | 699 | struct ipic * __init ipic_init(struct device_node *node, unsigned int flags) |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 700 | { |
| 701 | struct ipic *ipic; |
| 702 | struct resource res; |
| 703 | u32 temp = 0, ret; |
| 704 | |
Michael Ellerman | 84f1c1e | 2008-05-26 12:12:30 +1000 | [diff] [blame] | 705 | ret = of_address_to_resource(node, 0, &res); |
| 706 | if (ret) |
| 707 | return NULL; |
| 708 | |
Anton Vorontsov | ea96025 | 2009-07-01 10:59:57 +0000 | [diff] [blame] | 709 | ipic = kzalloc(sizeof(*ipic), GFP_KERNEL); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 710 | if (ipic == NULL) |
Kumar Gala | 126186a | 2007-01-26 01:45:32 -0600 | [diff] [blame] | 711 | return NULL; |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 712 | |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 713 | ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS, |
| 714 | &ipic_host_ops, ipic); |
Julia Lawall | 7a626b6 | 2009-08-02 10:44:53 +0200 | [diff] [blame] | 715 | if (ipic->irqhost == NULL) { |
| 716 | kfree(ipic); |
Kumar Gala | 126186a | 2007-01-26 01:45:32 -0600 | [diff] [blame] | 717 | return NULL; |
Julia Lawall | 7a626b6 | 2009-08-02 10:44:53 +0200 | [diff] [blame] | 718 | } |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 719 | |
Joe Perches | 28f65c11 | 2011-06-09 09:13:32 -0700 | [diff] [blame] | 720 | ipic->regs = ioremap(res.start, resource_size(&res)); |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 721 | |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 722 | /* init hw */ |
| 723 | ipic_write(ipic->regs, IPIC_SICNR, 0x0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | |
| 725 | /* default priority scheme is grouped. If spread mode is required |
| 726 | * configure SICFR accordingly */ |
| 727 | if (flags & IPIC_SPREADMODE_GRP_A) |
| 728 | temp |= SICFR_IPSA; |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 729 | if (flags & IPIC_SPREADMODE_GRP_B) |
| 730 | temp |= SICFR_IPSB; |
| 731 | if (flags & IPIC_SPREADMODE_GRP_C) |
| 732 | temp |= SICFR_IPSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | if (flags & IPIC_SPREADMODE_GRP_D) |
| 734 | temp |= SICFR_IPSD; |
| 735 | if (flags & IPIC_SPREADMODE_MIX_A) |
| 736 | temp |= SICFR_MPSA; |
| 737 | if (flags & IPIC_SPREADMODE_MIX_B) |
| 738 | temp |= SICFR_MPSB; |
| 739 | |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 740 | ipic_write(ipic->regs, IPIC_SICFR, temp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 741 | |
| 742 | /* handle MCP route */ |
| 743 | temp = 0; |
| 744 | if (flags & IPIC_DISABLE_MCP_OUT) |
| 745 | temp = SERCR_MCPR; |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 746 | ipic_write(ipic->regs, IPIC_SERCR, temp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | |
| 748 | /* handle routing of IRQ0 to MCP */ |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 749 | temp = ipic_read(ipic->regs, IPIC_SEMSR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 750 | |
| 751 | if (flags & IPIC_IRQ0_MCP) |
| 752 | temp |= SEMSR_SIRQ0; |
| 753 | else |
| 754 | temp &= ~SEMSR_SIRQ0; |
| 755 | |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 756 | ipic_write(ipic->regs, IPIC_SEMSR, temp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 757 | |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 758 | primary_ipic = ipic; |
| 759 | irq_set_default_host(primary_ipic->irqhost); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | |
Sebastian Andrzej Siewior | 8640d3b | 2009-08-05 21:41:12 +0200 | [diff] [blame] | 761 | ipic_write(ipic->regs, IPIC_SIMSR_H, 0); |
| 762 | ipic_write(ipic->regs, IPIC_SIMSR_L, 0); |
| 763 | |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 764 | printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS, |
| 765 | primary_ipic->regs); |
Kumar Gala | 126186a | 2007-01-26 01:45:32 -0600 | [diff] [blame] | 766 | |
| 767 | return ipic; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 768 | } |
| 769 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 770 | void ipic_set_default_priority(void) |
| 771 | { |
Li Yang | f03ca95 | 2007-10-19 19:38:43 +0800 | [diff] [blame] | 772 | ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT); |
| 773 | ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT); |
| 774 | ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT); |
| 775 | ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT); |
| 776 | ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT); |
| 777 | ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | } |
| 779 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | u32 ipic_get_mcp_status(void) |
| 781 | { |
Christophe Leroy | 6beb338 | 2018-08-27 08:27:27 +0000 | [diff] [blame] | 782 | return primary_ipic ? ipic_read(primary_ipic->regs, IPIC_SERSR) : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | } |
| 784 | |
| 785 | void ipic_clear_mcp_status(u32 mask) |
| 786 | { |
Christophe Leroy | 6b148a7 | 2017-10-18 11:16:47 +0200 | [diff] [blame] | 787 | ipic_write(primary_ipic->regs, IPIC_SERSR, mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 788 | } |
| 789 | |
Michael Ellerman | ef24ba7 | 2016-09-06 21:53:24 +1000 | [diff] [blame] | 790 | /* Return an interrupt vector or 0 if no interrupt is pending. */ |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 791 | unsigned int ipic_get_irq(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | { |
| 793 | int irq; |
| 794 | |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 795 | BUG_ON(primary_ipic == NULL); |
| 796 | |
| 797 | #define IPIC_SIVCR_VECTOR_MASK 0x7f |
| 798 | irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | |
| 800 | if (irq == 0) /* 0 --> no irq is pending */ |
Michael Ellerman | ef24ba7 | 2016-09-06 21:53:24 +1000 | [diff] [blame] | 801 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | |
Kim Phillips | b9f0f1b | 2006-08-25 11:59:07 -0500 | [diff] [blame] | 803 | return irq_linear_revmap(primary_ipic->irqhost, irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 804 | } |
| 805 | |
Michael Neuling | e2a02ba | 2009-02-06 11:10:27 +1100 | [diff] [blame] | 806 | #ifdef CONFIG_SUSPEND |
Scott Wood | d49747b | 2007-10-09 12:37:13 -0500 | [diff] [blame] | 807 | static struct { |
| 808 | u32 sicfr; |
| 809 | u32 siprr[2]; |
| 810 | u32 simsr[2]; |
| 811 | u32 sicnr; |
| 812 | u32 smprr[2]; |
| 813 | u32 semsr; |
| 814 | u32 secnr; |
| 815 | u32 sermr; |
| 816 | u32 sercr; |
| 817 | } ipic_saved_state; |
| 818 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 819 | static int ipic_suspend(void) |
Scott Wood | d49747b | 2007-10-09 12:37:13 -0500 | [diff] [blame] | 820 | { |
| 821 | struct ipic *ipic = primary_ipic; |
| 822 | |
| 823 | ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR); |
| 824 | ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A); |
| 825 | ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D); |
| 826 | ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H); |
| 827 | ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L); |
| 828 | ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR); |
| 829 | ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A); |
| 830 | ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B); |
| 831 | ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR); |
| 832 | ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR); |
| 833 | ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR); |
| 834 | ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR); |
| 835 | |
| 836 | if (fsl_deep_sleep()) { |
| 837 | /* In deep sleep, make sure there can be no |
| 838 | * pending interrupts, as this can cause |
| 839 | * problems on 831x. |
| 840 | */ |
| 841 | ipic_write(ipic->regs, IPIC_SIMSR_H, 0); |
| 842 | ipic_write(ipic->regs, IPIC_SIMSR_L, 0); |
| 843 | ipic_write(ipic->regs, IPIC_SEMSR, 0); |
| 844 | ipic_write(ipic->regs, IPIC_SERMR, 0); |
| 845 | } |
| 846 | |
| 847 | return 0; |
| 848 | } |
| 849 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 850 | static void ipic_resume(void) |
Scott Wood | d49747b | 2007-10-09 12:37:13 -0500 | [diff] [blame] | 851 | { |
| 852 | struct ipic *ipic = primary_ipic; |
| 853 | |
| 854 | ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr); |
| 855 | ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]); |
| 856 | ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]); |
| 857 | ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]); |
| 858 | ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]); |
| 859 | ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr); |
| 860 | ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]); |
| 861 | ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]); |
| 862 | ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr); |
| 863 | ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr); |
| 864 | ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr); |
| 865 | ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr); |
Scott Wood | d49747b | 2007-10-09 12:37:13 -0500 | [diff] [blame] | 866 | } |
| 867 | #else |
| 868 | #define ipic_suspend NULL |
| 869 | #define ipic_resume NULL |
| 870 | #endif |
| 871 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 872 | static struct syscore_ops ipic_syscore_ops = { |
Scott Wood | d49747b | 2007-10-09 12:37:13 -0500 | [diff] [blame] | 873 | .suspend = ipic_suspend, |
| 874 | .resume = ipic_resume, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 875 | }; |
| 876 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 877 | static int __init init_ipic_syscore(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | { |
Olaf Hering | 1428a9f | 2008-03-18 06:53:05 +1100 | [diff] [blame] | 879 | if (!primary_ipic || !primary_ipic->regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 880 | return -ENODEV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 882 | printk(KERN_DEBUG "Registering ipic system core operations\n"); |
| 883 | register_syscore_ops(&ipic_syscore_ops); |
| 884 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 885 | return 0; |
| 886 | } |
| 887 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 888 | subsys_initcall(init_ipic_syscore); |