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Aisheng Dongfe37b482018-12-13 15:42:54 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Dong Aisheng59640122021-04-23 11:33:33 +08003 * Copyright 2018-2021 NXP
Aisheng Dongfe37b482018-12-13 15:42:54 +00004 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#ifndef __IMX_CLK_SCU_H
8#define __IMX_CLK_SCU_H
9
10#include <linux/firmware/imx/sci.h>
Dong Aisheng77d8f302020-07-29 16:00:10 +080011#include <linux/of.h>
Aisheng Dongfe37b482018-12-13 15:42:54 +000012
Dong Aisheng5392c5d2021-04-23 11:33:32 +080013#define IMX_SCU_GPR_CLK_GATE BIT(0)
14#define IMX_SCU_GPR_CLK_DIV BIT(1)
15#define IMX_SCU_GPR_CLK_MUX BIT(2)
16
Dong Aisheng59640122021-04-23 11:33:33 +080017struct imx_clk_scu_rsrc_table {
18 const u32 *rsrc;
19 u8 num;
20};
21
Dong Aisheng77d8f302020-07-29 16:00:10 +080022extern struct list_head imx_scu_clks[];
Dong Aishengea0c5cb2020-07-29 16:00:18 +080023extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
Jacky Bai036a4b42021-12-17 15:25:33 +020024extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl;
Dong Aisheng59640122021-04-23 11:33:33 +080025extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
Dong Aishengafd04062021-04-23 11:33:34 +080026extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
Dong Aisheng77d8f302020-07-29 16:00:10 +080027
Dong Aisheng59640122021-04-23 11:33:33 +080028int imx_clk_scu_init(struct device_node *np,
29 const struct imx_clk_scu_rsrc_table *data);
Dong Aisheng77d8f302020-07-29 16:00:10 +080030struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
31 void *data);
32struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
33 const char * const *parents,
34 int num_parents, u32 rsrc_id, u8 clk_type);
Aisheng Dong666aed22019-01-30 13:39:15 +000035
Dong Aisheng2f1a2c12020-07-29 16:00:12 +080036struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
37 const char * const *parents, int num_parents,
38 u32 rsrc_id, u8 clk_type);
Aisheng Dong666aed22019-01-30 13:39:15 +000039
Dong Aisheng77d8f302020-07-29 16:00:10 +080040void imx_clk_scu_unregister(void);
41
Dong Aishenga4bfc852020-07-29 16:00:16 +080042struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
43 const char *parent_name, unsigned long flags,
44 void __iomem *reg, u8 bit_idx, bool hw_gate);
45void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
46
Dong Aisheng5392c5d2021-04-23 11:33:32 +080047struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
48 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
49 bool invert);
50
Aisheng Dong666aed22019-01-30 13:39:15 +000051static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
Dong Aisheng91e91672021-04-23 11:33:31 +080052 u8 clk_type)
Aisheng Dong666aed22019-01-30 13:39:15 +000053{
Dong Aisheng91e91672021-04-23 11:33:31 +080054 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
Aisheng Dong666aed22019-01-30 13:39:15 +000055}
56
57static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
Dong Aisheng91e91672021-04-23 11:33:31 +080058 int num_parents, u32 rsrc_id, u8 clk_type)
Aisheng Dong666aed22019-01-30 13:39:15 +000059{
Dong Aisheng91e91672021-04-23 11:33:31 +080060 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
Aisheng Dong666aed22019-01-30 13:39:15 +000061}
Aisheng Dongfe37b482018-12-13 15:42:54 +000062
Dong Aishenga4bfc852020-07-29 16:00:16 +080063static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
64 const char *parent_name, unsigned long flags,
65 void __iomem *reg, u8 bit_idx, bool hw_gate)
66{
67 return __imx_clk_lpcg_scu(dev, name, parent_name, flags, reg,
68 bit_idx, hw_gate);
69}
70
71static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
72 unsigned long flags, void __iomem *reg,
73 u8 bit_idx, bool hw_gate)
74{
75 return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
76 bit_idx, hw_gate);
77}
Dong Aisheng5392c5d2021-04-23 11:33:32 +080078
79static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
80 u32 rsrc_id, u8 gpr_id, bool invert)
81{
82 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
83 IMX_SCU_GPR_CLK_GATE, invert);
84}
85
86static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
87 u32 rsrc_id, u8 gpr_id)
88{
89 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
90 IMX_SCU_GPR_CLK_DIV, 0);
91}
92
93static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
94 int num_parents, u32 rsrc_id, u8 gpr_id)
95{
96 return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
97 gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
98}
Aisheng Dongfe37b482018-12-13 15:42:54 +000099#endif