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Nick Milner2d2894c2018-05-09 14:57:43 +02001* Rockchip rk3399 DMC (Dynamic Memory Controller) device
Lin Huangc1ceb8f72016-09-05 13:06:09 +08002
3Required properties:
4- compatible: Must be "rockchip,rk3399-dmc".
5- devfreq-events: Node to get DDR loading, Refer to
Nick Milner2d2894c2018-05-09 14:57:43 +02006 Documentation/devicetree/bindings/devfreq/event/
Lin Huangc1ceb8f72016-09-05 13:06:09 +08007 rockchip-dfi.txt
Lin Huangc1ceb8f72016-09-05 13:06:09 +08008- clocks: Phandles for clock specified in "clock-names" property
9- clock-names : The name of clock used by the DFI, must be
10 "pclk_ddr_mon";
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -030011- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
Lin Huangc1ceb8f72016-09-05 13:06:09 +080012 for details.
13- center-supply: DMC supply node.
14- status: Marks the node enabled/disabled.
15
Enric Balletbo i Serra77f2c232018-05-09 14:57:46 +020016Optional properties:
17- interrupts: The CPU interrupt number. The interrupt specifier
18 format depends on the interrupt controller.
19 It should be a DCF interrupt. When DDR DVFS finishes
20 a DCF interrupt is triggered.
Enric Balletbo i Serraed279522020-07-09 11:05:29 +020021- rockchip,pmu: Phandle to the syscon managing the "PMU general register
22 files".
Enric Balletbo i Serra77f2c232018-05-09 14:57:46 +020023
Nick Milner2d2894c2018-05-09 14:57:43 +020024Following properties relate to DDR timing:
Lin Huangc1ceb8f72016-09-05 13:06:09 +080025
Enric Balletbo i Serra49502b22018-05-09 14:57:44 +020026- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
Nick Milner2d2894c2018-05-09 14:57:43 +020027 it selects the DDR3 cl-trp-trcd type. It must be
28 set according to "Speed Bin" in DDR3 datasheet,
29 DO NOT use a smaller "Speed Bin" than specified
30 for the DDR3 being used.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080031
Nick Milner2d2894c2018-05-09 14:57:43 +020032- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
33 power-down idle period in which memories are
34 placed into power-down mode if bus is idle
35 for PD_IDLE DFI clock cycles.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080036
Nick Milner2d2894c2018-05-09 14:57:43 +020037- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
38 self-refresh idle period in which memories are
39 placed into self-refresh mode if bus is idle
40 for SR_IDLE * 1024 DFI clock cycles (DFI
41 clocks freq is half of DRAM clock), default
42 value is "0".
Lin Huangc1ceb8f72016-09-05 13:06:09 +080043
Nick Milner2d2894c2018-05-09 14:57:43 +020044- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
45 clock gating idle period. Memories are placed
46 into self-refresh mode and memory controller
47 clock arg gating started if bus is idle for
48 sr_mc_gate_idle*1024 DFI clock cycles.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080049
Nick Milner2d2894c2018-05-09 14:57:43 +020050- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
51 period in which memories are placed into
52 self-refresh power down mode if bus is idle
53 for srpd_lite_idle * 1024 DFI clock cycles.
54 This parameter is for LPDDR4 only.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080055
Nick Milner2d2894c2018-05-09 14:57:43 +020056- rockchip,standby_idle : Defines the standby idle period in which
57 memories are placed into self-refresh mode.
58 The controller, pi, PHY and DRAM clock will
59 be gated if bus is idle for standby_idle * DFI
60 clock cycles.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080061
Nick Milner2d2894c2018-05-09 14:57:43 +020062- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
63 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
64 DDR3 DLL will be bypassed. Note: if DLL was bypassed,
65 the odt will also stop working.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080066
Nick Milner2d2894c2018-05-09 14:57:43 +020067- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
68 MHz (Mega Hz). When DDR frequency is less than
69 DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
70 Note: PHY DLL and PHY ODT are independent.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080071
Nick Milner2d2894c2018-05-09 14:57:43 +020072- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
73 the ODT disable frequency in MHz (Mega Hz).
74 when the DDR frequency is less then ddr3_odt_dis_freq,
75 the ODT on the DRAM side and controller side are
Lin Huangc1ceb8f72016-09-05 13:06:09 +080076 both disabled.
77
Nick Milner2d2894c2018-05-09 14:57:43 +020078- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
79 the DRAM side driver strength in ohms. Default
Lin Huangc1ceb8f72016-09-05 13:06:09 +080080 value is DDR3_DS_40ohm.
81
Nick Milner2d2894c2018-05-09 14:57:43 +020082- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
83 the DRAM side ODT strength in ohms. Default value
Lin Huangc1ceb8f72016-09-05 13:06:09 +080084 is DDR3_ODT_120ohm.
85
Nick Milner2d2894c2018-05-09 14:57:43 +020086- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
87 the phy side CA line (incluing command line,
Lin Huangc1ceb8f72016-09-05 13:06:09 +080088 address line and clock line) driver strength.
89 Default value is PHY_DRV_ODT_40.
90
Nick Milner2d2894c2018-05-09 14:57:43 +020091- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
92 the PHY side DQ line (including DQS/DQ/DM line)
93 driver strength. Default value is PHY_DRV_ODT_40.
Lin Huangc1ceb8f72016-09-05 13:06:09 +080094
Nick Milner2d2894c2018-05-09 14:57:43 +020095- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
96 the PHY side ODT strength. Default value is
Lin Huangc1ceb8f72016-09-05 13:06:09 +080097 PHY_DRV_ODT_240.
98
Nick Milner2d2894c2018-05-09 14:57:43 +020099- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
100 then ODT disable frequency in MHz (Mega Hz).
101 When DDR frequency is less then ddr3_odt_dis_freq,
102 the ODT on the DRAM side and controller side are
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800103 both disabled.
104
Nick Milner2d2894c2018-05-09 14:57:43 +0200105- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
106 the DRAM side driver strength in ohms. Default
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800107 value is LP3_DS_34ohm.
108
Nick Milner2d2894c2018-05-09 14:57:43 +0200109- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
110 the DRAM side ODT strength in ohms. Default value
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800111 is LP3_ODT_240ohm.
112
Nick Milner2d2894c2018-05-09 14:57:43 +0200113- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
114 the PHY side CA line (including command line,
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800115 address line and clock line) driver strength.
Nick Milner2d2894c2018-05-09 14:57:43 +0200116 Default value is PHY_DRV_ODT_40.
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800117
Nick Milner2d2894c2018-05-09 14:57:43 +0200118- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
119 the PHY side DQ line (including DQS/DQ/DM line)
120 driver strength. Default value is
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800121 PHY_DRV_ODT_40.
122
123- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
124 the phy side odt strength, default value is
125 PHY_DRV_ODT_240.
126
Nick Milner2d2894c2018-05-09 14:57:43 +0200127- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
128 defines the ODT disable frequency in
129 MHz (Mega Hz). When the DDR frequency is less then
130 ddr3_odt_dis_freq, the ODT on the DRAM side and
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800131 controller side are both disabled.
132
Nick Milner2d2894c2018-05-09 14:57:43 +0200133- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
134 the DRAM side driver strength in ohms. Default
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800135 value is LP4_PDDS_60ohm.
136
Nick Milner2d2894c2018-05-09 14:57:43 +0200137- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
138 the DRAM side ODT on DQS/DQ line strength in ohms.
139 Default value is LP4_DQ_ODT_40ohm.
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800140
Nick Milner2d2894c2018-05-09 14:57:43 +0200141- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
142 the DRAM side ODT on CA line strength in ohms.
143 Default value is LP4_CA_ODT_40ohm.
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800144
Nick Milner2d2894c2018-05-09 14:57:43 +0200145- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
146 the PHY side CA line (including command address
147 line) driver strength. Default value is
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800148 PHY_DRV_ODT_40.
149
Nick Milner2d2894c2018-05-09 14:57:43 +0200150- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
151 the PHY side clock line and CS line driver
152 strength. Default value is PHY_DRV_ODT_80.
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800153
Nick Milner2d2894c2018-05-09 14:57:43 +0200154- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
155 the PHY side DQ line (including DQS/DQ/DM line)
156 driver strength. Default value is PHY_DRV_ODT_80.
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800157
Nick Milner2d2894c2018-05-09 14:57:43 +0200158- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
159 the PHY side ODT strength. Default value is
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800160 PHY_DRV_ODT_60.
161
162Example:
163 dmc_opp_table: dmc_opp_table {
164 compatible = "operating-points-v2";
165
166 opp00 {
167 opp-hz = /bits/ 64 <300000000>;
168 opp-microvolt = <900000>;
169 };
170 opp01 {
171 opp-hz = /bits/ 64 <666000000>;
172 opp-microvolt = <900000>;
173 };
174 };
175
176 dmc: dmc {
177 compatible = "rockchip,rk3399-dmc";
178 devfreq-events = <&dfi>;
179 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&cru SCLK_DDRCLK>;
181 clock-names = "dmc_clk";
182 operating-points-v2 = <&dmc_opp_table>;
183 center-supply = <&ppvar_centerlogic>;
184 upthreshold = <15>;
185 downdifferential = <10>;
186 rockchip,ddr3_speed_bin = <21>;
187 rockchip,pd_idle = <0x40>;
188 rockchip,sr_idle = <0x2>;
189 rockchip,sr_mc_gate_idle = <0x3>;
190 rockchip,srpd_lite_idle = <0x4>;
191 rockchip,standby_idle = <0x2000>;
192 rockchip,dram_dll_dis_freq = <300>;
193 rockchip,phy_dll_dis_freq = <125>;
194 rockchip,auto_pd_dis_freq = <666>;
195 rockchip,ddr3_odt_dis_freq = <333>;
196 rockchip,ddr3_drv = <DDR3_DS_40ohm>;
197 rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
198 rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
199 rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
200 rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
201 rockchip,lpddr3_odt_dis_freq = <333>;
202 rockchip,lpddr3_drv = <LP3_DS_34ohm>;
203 rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
204 rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
205 rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
206 rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
207 rockchip,lpddr4_odt_dis_freq = <333>;
208 rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
209 rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
210 rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
211 rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
212 rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
213 rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
214 rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
Lin Huangc1ceb8f72016-09-05 13:06:09 +0800215 };